--- BasiliskII/src/Unix/sigsegv.cpp 2004/01/12 15:29:25 1.41 +++ BasiliskII/src/Unix/sigsegv.cpp 2008/01/19 22:25:27 1.81 @@ -10,7 +10,7 @@ * tjw@omnigroup.com Sun, 4 Jun 2000 * www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html * - * Basilisk II (C) 1997-2004 Christian Bauer + * Basilisk II (C) 1997-2008 Christian Bauer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -49,6 +49,17 @@ using std::list; #define RETSIGTYPE void #endif +// Size of an unsigned integer large enough to hold all bits of a pointer +// NOTE: this can be different than SIGSEGV_REGISTER_TYPE. In +// particular, on ILP32 systems with a 64-bit kernel (HP-UX/ia64?) +#ifdef HAVE_WIN32_VM +// Windows is either ILP32 or LLP64 +typedef UINT_PTR sigsegv_uintptr_t; +#else +// Other systems are sane enough to follow ILP32 or LP64 models +typedef unsigned long sigsegv_uintptr_t; +#endif + // Type of the system signal handler typedef RETSIGTYPE (*signal_handler)(int); @@ -66,19 +77,23 @@ static bool sigsegv_do_install_handler(i * Instruction decoding aids */ +// Transfer type +enum transfer_type_t { + SIGSEGV_TRANSFER_UNKNOWN = 0, + SIGSEGV_TRANSFER_LOAD = 1, + SIGSEGV_TRANSFER_STORE = 2 +}; + // Transfer size enum transfer_size_t { SIZE_UNKNOWN, SIZE_BYTE, SIZE_WORD, // 2 bytes SIZE_LONG, // 4 bytes - SIZE_QUAD, // 8 bytes + SIZE_QUAD // 8 bytes }; -// Transfer type -typedef sigsegv_transfer_type_t transfer_type_t; - -#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__)) +#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__)) // Addressing mode enum addressing_mode_t { MODE_UNKNOWN, @@ -97,10 +112,10 @@ struct instruction_t { char ra, rd; }; -static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned int * gpr) +static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned long * gpr) { // Get opcode and divide into fields - unsigned int opcode = *((unsigned int *)nip); + unsigned int opcode = *((unsigned int *)(unsigned long)nip); unsigned int primop = opcode >> 26; unsigned int exop = (opcode >> 1) & 0x3ff; unsigned int ra = (opcode >> 16) & 0x1f; @@ -174,6 +189,18 @@ static void powerpc_decode_instruction(i transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break; case 45: // sthu transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break; + case 58: // ld, ldu, lwa + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_QUAD; + addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM; + imm &= ~3; + break; + case 62: // std, stdu, stq + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_QUAD; + addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM; + imm &= ~3; + break; } // Calculate effective address @@ -214,7 +241,7 @@ static void powerpc_decode_instruction(i #if HAVE_SIGINFO_T // Generic extended signal handler -#if defined(__NetBSD__) || defined(__FreeBSD__) +#if defined(__FreeBSD__) #define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS) #else #define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) @@ -228,7 +255,7 @@ static void powerpc_decode_instruction(i #define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) #define SIGSEGV_FAULT_INSTRUCTION (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC] #if (defined(mips) || defined(__mips)) -#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS +#define SIGSEGV_REGISTER_FILE &SIGSEGV_CONTEXT_REGS[CTX_EPC], &SIGSEGV_CONTEXT_REGS[CTX_R0] #define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction #endif #endif @@ -244,43 +271,83 @@ static void powerpc_decode_instruction(i #define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW #define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction #endif +#if defined(__i386__) +#include +#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[EIP] +#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction #endif -#if defined(__FreeBSD__) +#endif +#if defined(__FreeBSD__) || defined(__OpenBSD__) #if (defined(i386) || defined(__i386__)) #define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip) -#define SIGSEGV_REGISTER_FILE ((unsigned long *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */ +#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */ +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction +#endif +#endif +#if defined(__NetBSD__) +#if (defined(i386) || defined(__i386__)) +#include +#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs) +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP] +#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS #define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction #endif +#if (defined(powerpc) || defined(__powerpc__)) +#include +#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs) +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_PC] +#define SIGSEGV_REGISTER_FILE (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_PC], (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_R0] +#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction +#endif #endif #if defined(__linux__) #if (defined(i386) || defined(__i386__)) #include #define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) #define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */ -#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS +#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS #define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction #endif #if (defined(x86_64) || defined(__x86_64__)) #include #define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) #define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */ -#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS +#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS #define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction #endif #if (defined(ia64) || defined(__ia64__)) -#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */ +#define SIGSEGV_CONTEXT_REGS ((struct sigcontext *)scp) +#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */ +#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS +#define SIGSEGV_SKIP_INSTRUCTION ia64_skip_instruction #endif #if (defined(powerpc) || defined(__powerpc__)) #include #define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.regs) #define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->nip) -#define SIGSEGV_REGISTER_FILE (unsigned int *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned int *)(SIGSEGV_CONTEXT_REGS->gpr) +#define SIGSEGV_REGISTER_FILE (unsigned long *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned long *)(SIGSEGV_CONTEXT_REGS->gpr) #define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction #endif #if (defined(hppa) || defined(__hppa__)) #undef SIGSEGV_FAULT_ADDRESS #define SIGSEGV_FAULT_ADDRESS sip->si_ptr #endif +#if (defined(arm) || defined(__arm__)) +#include /* use kernel structure, glibc may not be in sync */ +#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext) +#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.arm_pc) +#define SIGSEGV_REGISTER_FILE (&SIGSEGV_CONTEXT_REGS.arm_r0) +#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction +#endif +#if (defined(mips) || defined(__mips__)) +#include +#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext) +#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.pc) +#define SIGSEGV_REGISTER_FILE &SIGSEGV_CONTEXT_REGS.pc, &SIGSEGV_CONTEXT_REGS.gregs[0] +#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction +#endif #endif #endif @@ -295,7 +362,7 @@ static void powerpc_decode_instruction(i #define SIGSEGV_FAULT_HANDLER_ARGS &scs #define SIGSEGV_FAULT_ADDRESS scp->cr2 #define SIGSEGV_FAULT_INSTRUCTION scp->eip -#define SIGSEGV_REGISTER_FILE (unsigned long *)scp +#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)scp #define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction #endif #if (defined(sparc) || defined(__sparc__)) @@ -310,7 +377,7 @@ static void powerpc_decode_instruction(i #define SIGSEGV_FAULT_HANDLER_ARGS sig, scp #define SIGSEGV_FAULT_ADDRESS scp->regs->dar #define SIGSEGV_FAULT_INSTRUCTION scp->regs->nip -#define SIGSEGV_REGISTER_FILE (unsigned int *)&scp->regs->nip, (unsigned int *)(scp->regs->gpr) +#define SIGSEGV_REGISTER_FILE (unsigned long *)&scp->regs->nip, (unsigned long *)(scp->regs->gpr) #define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction #endif #if (defined(alpha) || defined(__alpha__)) @@ -320,6 +387,15 @@ static void powerpc_decode_instruction(i #define SIGSEGV_FAULT_ADDRESS get_fault_address(scp) #define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc #endif +#if (defined(arm) || defined(__arm__)) +#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int r1, int r2, int r3, struct sigcontext sc +#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp +#define SIGSEGV_FAULT_HANDLER_ARGS &sc +#define SIGSEGV_FAULT_ADDRESS scp->fault_address +#define SIGSEGV_FAULT_INSTRUCTION scp->arm_pc +#define SIGSEGV_REGISTER_FILE &scp->arm_r0 +#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction +#endif #endif // Irix 5 or 6 on MIPS @@ -407,7 +483,7 @@ static sigsegv_address_t get_fault_addre #define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr #define SIGSEGV_FAULT_ADDRESS addr #define SIGSEGV_FAULT_INSTRUCTION scp->sc_eip -#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi) +#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&scp->sc_edi) #define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction #endif #if (defined(alpha) || defined(__alpha__)) @@ -465,6 +541,31 @@ static sigsegv_address_t get_fault_addre #endif #endif +#if HAVE_WIN32_EXCEPTIONS +#define WIN32_LEAN_AND_MEAN /* avoid including junk */ +#include +#include + +#if defined(_M_IX86) +#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo +#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo +#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1] +#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip +#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi) +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction +#endif +#if defined(_M_X64) +#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo +#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo +#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1] +#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Rip +#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax) +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction +#endif +#endif + #if HAVE_MACH_EXCEPTIONS // This can easily be extended to other Mach systems, but really who @@ -525,33 +626,73 @@ if (ret != KERN_SUCCESS) { \ exit (1); \ } -#define SIGSEGV_FAULT_ADDRESS code[1] -#define SIGSEGV_FAULT_INSTRUCTION get_fault_instruction(thread, state) -#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) ((code[0] == KERN_PROTECTION_FAILURE) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE) -#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code, ppc_thread_state_t *state -#define SIGSEGV_FAULT_HANDLER_ARGS thread, code, &state +#ifdef __ppc__ +#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE +#define MACH_FIELD_NAME(X) __CONCAT(__,X) +#endif +#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state_t +#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE +#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE_COUNT +#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar) +#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t +#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE +#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT +#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0) #define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction -#define SIGSEGV_REGISTER_FILE &state->srr0, &state->r0 - -// Given a suspended thread, stuff the current instruction and -// registers into state. -// -// It would have been nice to have this be ppc/x86 independant which -// could have been done easily with a thread_state_t instead of -// ppc_thread_state_t, but because of the way this is called it is -// easier to do it this way. -#if (defined(ppc) || defined(__ppc__)) -static inline sigsegv_address_t get_fault_instruction(mach_port_t thread, ppc_thread_state_t *state) -{ - kern_return_t krc; - mach_msg_type_number_t count; - - count = MACHINE_THREAD_STATE_COUNT; - krc = thread_get_state(thread, MACHINE_THREAD_STATE, (thread_state_t)state, &count); - MACH_CHECK_ERROR (thread_get_state, krc); +#define SIGSEGV_REGISTER_FILE (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0) +#endif +#ifdef __ppc64__ +#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64 +#define MACH_FIELD_NAME(X) __CONCAT(__,X) +#endif +#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state64_t +#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE64 +#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE64_COUNT +#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar) +#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state64_t +#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE64 +#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE64_COUNT +#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0) +#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction +#define SIGSEGV_REGISTER_FILE (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0) +#endif +#ifdef __i386__ +#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32 +#define MACH_FIELD_NAME(X) __CONCAT(__,X) +#endif +#define SIGSEGV_EXCEPTION_STATE_TYPE i386_exception_state_t +#define SIGSEGV_EXCEPTION_STATE_FLAVOR i386_EXCEPTION_STATE +#define SIGSEGV_EXCEPTION_STATE_COUNT i386_EXCEPTION_STATE_COUNT +#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr) +#define SIGSEGV_THREAD_STATE_TYPE i386_thread_state_t +#define SIGSEGV_THREAD_STATE_FLAVOR i386_THREAD_STATE +#define SIGSEGV_THREAD_STATE_COUNT i386_THREAD_STATE_COUNT +#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(eip) +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction +#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(eax)) /* EAX is the first GPR we consider */ +#endif +#ifdef __x86_64__ +#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64 +#define MACH_FIELD_NAME(X) __CONCAT(__,X) +#endif +#define SIGSEGV_EXCEPTION_STATE_TYPE x86_exception_state64_t +#define SIGSEGV_EXCEPTION_STATE_FLAVOR x86_EXCEPTION_STATE64 +#define SIGSEGV_EXCEPTION_STATE_COUNT x86_EXCEPTION_STATE64_COUNT +#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr) +#define SIGSEGV_THREAD_STATE_TYPE x86_thread_state64_t +#define SIGSEGV_THREAD_STATE_FLAVOR x86_THREAD_STATE64 +#define SIGSEGV_THREAD_STATE_COUNT x86_THREAD_STATE64_COUNT +#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(rip) +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction +#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(rax)) /* RAX is the first GPR we consider */ +#endif +#define SIGSEGV_FAULT_ADDRESS_FAST code[1] +#define SIGSEGV_FAULT_INSTRUCTION_FAST SIGSEGV_INVALID_ADDRESS +#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code +#define SIGSEGV_FAULT_HANDLER_ARGS thread, code - return (sigsegv_address_t)state->srr0; -} +#ifndef MACH_FIELD_NAME +#define MACH_FIELD_NAME(X) X #endif // Since there can only be one exception thread running at any time @@ -605,9 +746,13 @@ handleExceptions(void *priv) * Instruction skipping */ +#ifndef SIGSEGV_REGISTER_TYPE +#define SIGSEGV_REGISTER_TYPE sigsegv_uintptr_t +#endif + #ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION // Decode and skip X86 instruction -#if (defined(i386) || defined(__i386__)) || defined(__x86_64__) +#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64)) #if defined(__linux__) enum { #if (defined(i386) || defined(__i386__)) @@ -642,7 +787,22 @@ enum { #endif }; #endif -#if defined(__NetBSD__) || defined(__FreeBSD__) +#if defined(__NetBSD__) +enum { +#if (defined(i386) || defined(__i386__)) + X86_REG_EIP = _REG_EIP, + X86_REG_EAX = _REG_EAX, + X86_REG_ECX = _REG_ECX, + X86_REG_EDX = _REG_EDX, + X86_REG_EBX = _REG_EBX, + X86_REG_ESP = _REG_ESP, + X86_REG_EBP = _REG_EBP, + X86_REG_ESI = _REG_ESI, + X86_REG_EDI = _REG_EDI +#endif +}; +#endif +#if defined(__FreeBSD__) enum { #if (defined(i386) || defined(__i386__)) X86_REG_EIP = 10, @@ -657,6 +817,124 @@ enum { #endif }; #endif +#if defined(__OpenBSD__) +enum { +#if defined(__i386__) + // EDI is the first register we consider +#define OREG(REG) offsetof(struct sigcontext, sc_##REG) +#define DREG(REG) ((OREG(REG) - OREG(edi)) / 4) + X86_REG_EIP = DREG(eip), // 7 + X86_REG_EAX = DREG(eax), // 6 + X86_REG_ECX = DREG(ecx), // 5 + X86_REG_EDX = DREG(edx), // 4 + X86_REG_EBX = DREG(ebx), // 3 + X86_REG_ESP = DREG(esp), // 10 + X86_REG_EBP = DREG(ebp), // 2 + X86_REG_ESI = DREG(esi), // 1 + X86_REG_EDI = DREG(edi) // 0 +#undef DREG +#undef OREG +#endif +}; +#endif +#if defined(__sun__) +// Same as for Linux, need to check for x86-64 +enum { +#if defined(__i386__) + X86_REG_EIP = EIP, + X86_REG_EAX = EAX, + X86_REG_ECX = ECX, + X86_REG_EDX = EDX, + X86_REG_EBX = EBX, + X86_REG_ESP = ESP, + X86_REG_EBP = EBP, + X86_REG_ESI = ESI, + X86_REG_EDI = EDI +#endif +}; +#endif +#if defined(__APPLE__) && defined(__MACH__) +enum { +#if (defined(i386) || defined(__i386__)) +#ifdef i386_SAVED_STATE + // same as FreeBSD (in Open Darwin 8.0.1) + X86_REG_EIP = 10, + X86_REG_EAX = 7, + X86_REG_ECX = 6, + X86_REG_EDX = 5, + X86_REG_EBX = 4, + X86_REG_ESP = 13, + X86_REG_EBP = 2, + X86_REG_ESI = 1, + X86_REG_EDI = 0 +#else + // new layout (MacOS X 10.4.4 for x86) + X86_REG_EIP = 10, + X86_REG_EAX = 0, + X86_REG_ECX = 2, + X86_REG_EDX = 3, + X86_REG_EBX = 1, + X86_REG_ESP = 7, + X86_REG_EBP = 6, + X86_REG_ESI = 5, + X86_REG_EDI = 4 +#endif +#endif +#if defined(__x86_64__) + X86_REG_R8 = 8, + X86_REG_R9 = 9, + X86_REG_R10 = 10, + X86_REG_R11 = 11, + X86_REG_R12 = 12, + X86_REG_R13 = 13, + X86_REG_R14 = 14, + X86_REG_R15 = 15, + X86_REG_EDI = 4, + X86_REG_ESI = 5, + X86_REG_EBP = 6, + X86_REG_EBX = 1, + X86_REG_EDX = 3, + X86_REG_EAX = 0, + X86_REG_ECX = 2, + X86_REG_ESP = 7, + X86_REG_EIP = 16 +#endif +}; +#endif +#if defined(_WIN32) +enum { +#if defined(_M_IX86) + X86_REG_EIP = 7, + X86_REG_EAX = 5, + X86_REG_ECX = 4, + X86_REG_EDX = 3, + X86_REG_EBX = 2, + X86_REG_ESP = 10, + X86_REG_EBP = 6, + X86_REG_ESI = 1, + X86_REG_EDI = 0 +#endif +#if defined(_M_X64) + X86_REG_EAX = 0, + X86_REG_ECX = 1, + X86_REG_EDX = 2, + X86_REG_EBX = 3, + X86_REG_ESP = 4, + X86_REG_EBP = 5, + X86_REG_ESI = 6, + X86_REG_EDI = 7, + X86_REG_R8 = 8, + X86_REG_R9 = 9, + X86_REG_R10 = 10, + X86_REG_R11 = 11, + X86_REG_R12 = 12, + X86_REG_R13 = 13, + X86_REG_R14 = 14, + X86_REG_R15 = 15, + X86_REG_EIP = 16 +#endif +}; +#endif // FIXME: this is partly redundant with the instruction decoding phase // to discover transfer type and register number static inline int ix86_step_over_modrm(unsigned char * p) @@ -691,15 +969,25 @@ static inline int ix86_step_over_modrm(u return offset; } -static bool ix86_skip_instruction(unsigned long * regs) +static bool ix86_skip_instruction(SIGSEGV_REGISTER_TYPE * regs) { unsigned char * eip = (unsigned char *)regs[X86_REG_EIP]; if (eip == 0) return false; +#ifdef _WIN32 + if (IsBadCodePtr((FARPROC)eip)) + return false; +#endif + enum instruction_type_t { + i_MOV, + i_ADD + }; + transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN; transfer_size_t transfer_size = SIZE_LONG; + instruction_type_t instruction_type = i_MOV; int reg = -1; int len = 0; @@ -717,7 +1005,7 @@ static bool ix86_skip_instruction(unsign } // REX prefix -#if defined(__x86_64__) +#if defined(__x86_64__) || defined(_M_X64) struct rex_t { unsigned char W; unsigned char R; @@ -750,84 +1038,106 @@ static bool ix86_skip_instruction(unsign #endif // Decode instruction + int op_len = 1; + int target_size = SIZE_UNKNOWN; switch (eip[0]) { case 0x0f: + target_size = transfer_size; switch (eip[1]) { + case 0xbe: // MOVSX r32, r/m8 case 0xb6: // MOVZX r32, r/m8 + transfer_size = SIZE_BYTE; + goto do_mov_extend; + case 0xbf: // MOVSX r32, r/m16 case 0xb7: // MOVZX r32, r/m16 - switch (eip[2] & 0xc0) { - case 0x80: - reg = (eip[2] >> 3) & 7; - transfer_type = SIGSEGV_TRANSFER_LOAD; - break; - case 0x40: - reg = (eip[2] >> 3) & 7; - transfer_type = SIGSEGV_TRANSFER_LOAD; - break; - case 0x00: - reg = (eip[2] >> 3) & 7; - transfer_type = SIGSEGV_TRANSFER_LOAD; - break; + transfer_size = SIZE_WORD; + goto do_mov_extend; + do_mov_extend: + op_len = 2; + goto do_transfer_load; } - len += 3 + ix86_step_over_modrm(eip + 2); break; - } - break; +#if defined(__x86_64__) || defined(_M_X64) + case 0x63: // MOVSXD r64, r/m32 + if (has_rex && rex.W) { + transfer_size = SIZE_LONG; + target_size = SIZE_QUAD; + } + else if (transfer_size != SIZE_WORD) { + transfer_size = SIZE_LONG; + target_size = SIZE_QUAD; + } + goto do_transfer_load; +#endif + case 0x02: // ADD r8, r/m8 + transfer_size = SIZE_BYTE; + case 0x03: // ADD r32, r/m32 + instruction_type = i_ADD; + goto do_transfer_load; case 0x8a: // MOV r8, r/m8 transfer_size = SIZE_BYTE; case 0x8b: // MOV r32, r/m32 (or 16-bit operation) - switch (eip[1] & 0xc0) { + do_transfer_load: + switch (eip[op_len] & 0xc0) { case 0x80: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_LOAD; break; case 0x40: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_LOAD; break; case 0x00: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_LOAD; break; } - len += 2 + ix86_step_over_modrm(eip + 1); + len += 1 + op_len + ix86_step_over_modrm(eip + op_len); break; + case 0x00: // ADD r/m8, r8 + transfer_size = SIZE_BYTE; + case 0x01: // ADD r/m32, r32 + instruction_type = i_ADD; + goto do_transfer_store; case 0x88: // MOV r/m8, r8 transfer_size = SIZE_BYTE; case 0x89: // MOV r/m32, r32 (or 16-bit operation) - switch (eip[1] & 0xc0) { + do_transfer_store: + switch (eip[op_len] & 0xc0) { case 0x80: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_STORE; break; case 0x40: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_STORE; break; case 0x00: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_STORE; break; } - len += 2 + ix86_step_over_modrm(eip + 1); + len += 1 + op_len + ix86_step_over_modrm(eip + op_len); break; } + if (target_size == SIZE_UNKNOWN) + target_size = transfer_size; if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) { // Unknown machine code, let it crash. Then patch the decoder return false; } -#if defined(__x86_64__) +#if defined(__x86_64__) || defined(_M_X64) if (rex.R) reg += 8; #endif - if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) { + if (instruction_type == i_MOV && transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) { static const int x86_reg_map[] = { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX, X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI, -#if defined(__x86_64__) +#if defined(__x86_64__) || defined(_M_X64) X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11, X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15, #endif @@ -839,7 +1149,7 @@ static bool ix86_skip_instruction(unsign // Set 0 to the relevant register part // NOTE: this is only valid for MOV alike instructions int rloc = x86_reg_map[reg]; - switch (transfer_size) { + switch (target_size) { case SIZE_BYTE: if (has_rex || reg < 4) regs[rloc] = (regs[rloc] & ~0x00ffL); @@ -859,7 +1169,7 @@ static bool ix86_skip_instruction(unsign } #if DEBUG - printf("%08x: %s %s access", regs[X86_REG_EIP], + printf("%p: %s %s access", (void *)regs[X86_REG_EIP], transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : transfer_size == SIZE_LONG ? "long" : @@ -893,7 +1203,7 @@ static bool ix86_skip_instruction(unsign "r12", "r13", "r14", "r15", }; const char * reg_str = NULL; - switch (transfer_size) { + switch (target_size) { case SIZE_BYTE: reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg]; break; @@ -914,9 +1224,736 @@ static bool ix86_skip_instruction(unsign } #endif +// Decode and skip IA-64 instruction +#if defined(__ia64__) +typedef uint64_t ia64_bundle_t[2]; +#if defined(__linux__) +// We can directly patch the slot number +#define IA64_CAN_PATCH_IP_SLOT 1 +// Helper macros to access the machine context +#define IA64_CONTEXT_TYPE struct sigcontext * +#define IA64_CONTEXT scp +#define IA64_GET_IP() (IA64_CONTEXT->sc_ip) +#define IA64_SET_IP(V) (IA64_CONTEXT->sc_ip = (V)) +#define IA64_GET_PR(P) ((IA64_CONTEXT->sc_pr >> (P)) & 1) +#define IA64_GET_NAT(I) ((IA64_CONTEXT->sc_nat >> (I)) & 1) +#define IA64_GET_GR(R) (IA64_CONTEXT->sc_gr[(R)]) +#define _IA64_SET_GR(R,V) (IA64_CONTEXT->sc_gr[(R)] = (V)) +#define _IA64_SET_NAT(I,V) (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) | (((uint64_t)!!(V)) << (I))) +#define IA64_SET_GR(R,V,N) (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N)) + +// Load bundle (in little-endian) +static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip) +{ + uint64_t *ip = (uint64_t *)(raw_ip & ~3ull); + bundle[0] = ip[0]; + bundle[1] = ip[1]; +} +#endif + +// Instruction operations +enum { + IA64_INST_UNKNOWN = 0, + IA64_INST_LD1, // ld1 op0=[op1] + IA64_INST_LD1_UPDATE, // ld1 op0=[op1],op2 + IA64_INST_LD2, // ld2 op0=[op1] + IA64_INST_LD2_UPDATE, // ld2 op0=[op1],op2 + IA64_INST_LD4, // ld4 op0=[op1] + IA64_INST_LD4_UPDATE, // ld4 op0=[op1],op2 + IA64_INST_LD8, // ld8 op0=[op1] + IA64_INST_LD8_UPDATE, // ld8 op0=[op1],op2 + IA64_INST_ST1, // st1 [op0]=op1 + IA64_INST_ST1_UPDATE, // st1 [op0]=op1,op2 + IA64_INST_ST2, // st2 [op0]=op1 + IA64_INST_ST2_UPDATE, // st2 [op0]=op1,op2 + IA64_INST_ST4, // st4 [op0]=op1 + IA64_INST_ST4_UPDATE, // st4 [op0]=op1,op2 + IA64_INST_ST8, // st8 [op0]=op1 + IA64_INST_ST8_UPDATE, // st8 [op0]=op1,op2 + IA64_INST_ADD, // add op0=op1,op2,op3 + IA64_INST_SUB, // sub op0=op1,op2,op3 + IA64_INST_SHLADD, // shladd op0=op1,op3,op2 + IA64_INST_AND, // and op0=op1,op2 + IA64_INST_ANDCM, // andcm op0=op1,op2 + IA64_INST_OR, // or op0=op1,op2 + IA64_INST_XOR, // xor op0=op1,op2 + IA64_INST_SXT1, // sxt1 op0=op1 + IA64_INST_SXT2, // sxt2 op0=op1 + IA64_INST_SXT4, // sxt4 op0=op1 + IA64_INST_ZXT1, // zxt1 op0=op1 + IA64_INST_ZXT2, // zxt2 op0=op1 + IA64_INST_ZXT4, // zxt4 op0=op1 + IA64_INST_NOP // nop op0 +}; + +const int IA64_N_OPERANDS = 4; + +// Decoded operand type +struct ia64_operand_t { + uint8_t commit; // commit result of operation to register file? + uint8_t valid; // XXX: not really used, can be removed (debug) + int8_t index; // index of GPR, or -1 if immediate value + uint8_t nat; // NaT state before operation + uint64_t value; // register contents or immediate value +}; + +// Decoded instruction type +struct ia64_instruction_t { + uint8_t mnemo; // operation to perform + uint8_t pred; // predicate register to check + uint8_t no_memory; // used to emulated main fault instruction + uint64_t inst; // the raw instruction bits (41-bit wide) + ia64_operand_t operands[IA64_N_OPERANDS]; +}; + +// Get immediate sign-bit +static inline int ia64_inst_get_sbit(uint64_t inst) +{ + return (inst >> 36) & 1; +} + +// Get 8-bit immediate value (A3, A8, I27, M30) +static inline uint64_t ia64_inst_get_imm8(uint64_t inst) +{ + uint64_t value = (inst >> 13) & 0x7full; + if (ia64_inst_get_sbit(inst)) + value |= ~0x7full; + return value; +} + +// Get 9-bit immediate value (M3) +static inline uint64_t ia64_inst_get_imm9b(uint64_t inst) +{ + uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f); + if (ia64_inst_get_sbit(inst)) + value |= ~0xffull; + return value; +} + +// Get 9-bit immediate value (M5) +static inline uint64_t ia64_inst_get_imm9a(uint64_t inst) +{ + uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f); + if (ia64_inst_get_sbit(inst)) + value |= ~0xffull; + return value; +} + +// Get 14-bit immediate value (A4) +static inline uint64_t ia64_inst_get_imm14(uint64_t inst) +{ + uint64_t value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f); + if (ia64_inst_get_sbit(inst)) + value |= ~0x1ffull; + return value; +} + +// Get 22-bit immediate value (A5) +static inline uint64_t ia64_inst_get_imm22(uint64_t inst) +{ + uint64_t value = ((((inst >> 22) & 0x1f) << 16) | + (((inst >> 27) & 0x1ff) << 7) | + (inst & 0x7f)); + if (ia64_inst_get_sbit(inst)) + value |= ~0x1fffffull; + return value; +} + +// Get 21-bit immediate value (I19) +static inline uint64_t ia64_inst_get_imm21(uint64_t inst) +{ + return (((inst >> 36) & 1) << 20) | ((inst >> 6) & 0xfffff); +} + +// Get 2-bit count value (A2) +static inline int ia64_inst_get_count2(uint64_t inst) +{ + return (inst >> 27) & 0x3; +} + +// Get bundle template +static inline unsigned int ia64_get_template(uint64_t ip) +{ + ia64_bundle_t bundle; + ia64_load_bundle(bundle, ip); + return bundle[0] & 0x1f; +} + +// Get specified instruction in bundle +static uint64_t ia64_get_instruction(uint64_t ip, int slot) +{ + uint64_t inst; + ia64_bundle_t bundle; + ia64_load_bundle(bundle, ip); +#if DEBUG + printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]); +#endif + + switch (slot) { + case 0: + inst = (bundle[0] >> 5) & 0x1ffffffffffull; + break; + case 1: + inst = ((bundle[1] & 0x7fffffull) << 18) | ((bundle[0] >> 46) & 0x3ffffull); + break; + case 2: + inst = (bundle[1] >> 23) & 0x1ffffffffffull; + break; + case 3: + fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot); + abort(); + break; + } + +#if DEBUG + printf(" Instruction %d: 0x%016llx\n", slot, inst); +#endif + return inst; +} + +// Decode group 0 instructions +static bool ia64_decode_instruction_0(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT) +{ + const int r1 = (inst->inst >> 6) & 0x7f; + const int r3 = (inst->inst >> 20) & 0x7f; + + const int x3 = (inst->inst >> 33) & 0x07; + const int x6 = (inst->inst >> 27) & 0x3f; + const int x2 = (inst->inst >> 31) & 0x03; + const int x4 = (inst->inst >> 27) & 0x0f; + + if (x3 == 0) { + switch (x6) { + case 0x01: // nop.i (I19) + inst->mnemo = IA64_INST_NOP; + inst->operands[0].valid = true; + inst->operands[0].index = -1; + inst->operands[0].value = ia64_inst_get_imm21(inst->inst); + return true; + case 0x14: // sxt1 (I29) + case 0x15: // sxt2 (I29) + case 0x16: // sxt4 (I29) + case 0x10: // zxt1 (I29) + case 0x11: // zxt2 (I29) + case 0x12: // zxt4 (I29) + switch (x6) { + case 0x14: inst->mnemo = IA64_INST_SXT1; break; + case 0x15: inst->mnemo = IA64_INST_SXT2; break; + case 0x16: inst->mnemo = IA64_INST_SXT4; break; + case 0x10: inst->mnemo = IA64_INST_ZXT1; break; + case 0x11: inst->mnemo = IA64_INST_ZXT2; break; + case 0x12: inst->mnemo = IA64_INST_ZXT4; break; + default: abort(); + } + inst->operands[0].valid = true; + inst->operands[0].index = r1; + inst->operands[1].valid = true; + inst->operands[1].index = r3; + inst->operands[1].value = IA64_GET_GR(r3); + inst->operands[1].nat = IA64_GET_NAT(r3); + return true; + } + } + return false; +} + +// Decode group 4 instructions (load/store instructions) +static bool ia64_decode_instruction_4(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT) +{ + const int r1 = (inst->inst >> 6) & 0x7f; + const int r2 = (inst->inst >> 13) & 0x7f; + const int r3 = (inst->inst >> 20) & 0x7f; + + const int m = (inst->inst >> 36) & 1; + const int x = (inst->inst >> 27) & 1; + const int x6 = (inst->inst >> 30) & 0x3f; + + switch (x6) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + if (x == 0) { + inst->operands[0].valid = true; + inst->operands[0].index = r1; + inst->operands[1].valid = true; + inst->operands[1].index = r3; + inst->operands[1].value = IA64_GET_GR(r3); + inst->operands[1].nat = IA64_GET_NAT(r3); + if (m == 0) { + switch (x6) { + case 0x00: inst->mnemo = IA64_INST_LD1; break; + case 0x01: inst->mnemo = IA64_INST_LD2; break; + case 0x02: inst->mnemo = IA64_INST_LD4; break; + case 0x03: inst->mnemo = IA64_INST_LD8; break; + } + } + else { + inst->operands[2].valid = true; + inst->operands[2].index = r2; + inst->operands[2].value = IA64_GET_GR(r2); + inst->operands[2].nat = IA64_GET_NAT(r2); + switch (x6) { + case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break; + case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break; + case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break; + case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break; + } + } + return true; + } + break; + case 0x30: + case 0x31: + case 0x32: + case 0x33: + if (m == 0 && x == 0) { + inst->operands[0].valid = true; + inst->operands[0].index = r3; + inst->operands[0].value = IA64_GET_GR(r3); + inst->operands[0].nat = IA64_GET_NAT(r3); + inst->operands[1].valid = true; + inst->operands[1].index = r2; + inst->operands[1].value = IA64_GET_GR(r2); + inst->operands[1].nat = IA64_GET_NAT(r2); + switch (x6) { + case 0x30: inst->mnemo = IA64_INST_ST1; break; + case 0x31: inst->mnemo = IA64_INST_ST2; break; + case 0x32: inst->mnemo = IA64_INST_ST4; break; + case 0x33: inst->mnemo = IA64_INST_ST8; break; + } + return true; + } + break; + } + return false; +} + +// Decode group 5 instructions (load/store instructions) +static bool ia64_decode_instruction_5(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT) +{ + const int r1 = (inst->inst >> 6) & 0x7f; + const int r2 = (inst->inst >> 13) & 0x7f; + const int r3 = (inst->inst >> 20) & 0x7f; + + const int x6 = (inst->inst >> 30) & 0x3f; + + switch (x6) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + inst->operands[0].valid = true; + inst->operands[0].index = r1; + inst->operands[1].valid = true; + inst->operands[1].index = r3; + inst->operands[1].value = IA64_GET_GR(r3); + inst->operands[1].nat = IA64_GET_NAT(r3); + inst->operands[2].valid = true; + inst->operands[2].index = -1; + inst->operands[2].value = ia64_inst_get_imm9b(inst->inst); + inst->operands[2].nat = 0; + switch (x6) { + case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break; + case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break; + case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break; + case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break; + } + return true; + case 0x30: + case 0x31: + case 0x32: + case 0x33: + inst->operands[0].valid = true; + inst->operands[0].index = r3; + inst->operands[0].value = IA64_GET_GR(r3); + inst->operands[0].nat = IA64_GET_NAT(r3); + inst->operands[1].valid = true; + inst->operands[1].index = r2; + inst->operands[1].value = IA64_GET_GR(r2); + inst->operands[1].nat = IA64_GET_NAT(r2); + inst->operands[2].valid = true; + inst->operands[2].index = -1; + inst->operands[2].value = ia64_inst_get_imm9a(inst->inst); + inst->operands[2].nat = 0; + switch (x6) { + case 0x30: inst->mnemo = IA64_INST_ST1_UPDATE; break; + case 0x31: inst->mnemo = IA64_INST_ST2_UPDATE; break; + case 0x32: inst->mnemo = IA64_INST_ST4_UPDATE; break; + case 0x33: inst->mnemo = IA64_INST_ST8_UPDATE; break; + } + return true; + } + return false; +} + +// Decode group 8 instructions (ALU integer) +static bool ia64_decode_instruction_8(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT) +{ + const int r1 = (inst->inst >> 6) & 0x7f; + const int r2 = (inst->inst >> 13) & 0x7f; + const int r3 = (inst->inst >> 20) & 0x7f; + + const int x2a = (inst->inst >> 34) & 0x3; + const int x2b = (inst->inst >> 27) & 0x3; + const int x4 = (inst->inst >> 29) & 0xf; + const int ve = (inst->inst >> 33) & 0x1; + + // destination register (r1) is always valid in this group + inst->operands[0].valid = true; + inst->operands[0].index = r1; + + // source register (r3) is always valid in this group + inst->operands[2].valid = true; + inst->operands[2].index = r3; + inst->operands[2].value = IA64_GET_GR(r3); + inst->operands[2].nat = IA64_GET_NAT(r3); + + if (x2a == 0 && ve == 0) { + inst->operands[1].valid = true; + inst->operands[1].index = r2; + inst->operands[1].value = IA64_GET_GR(r2); + inst->operands[1].nat = IA64_GET_NAT(r2); + switch (x4) { + case 0x0: // add (A1) + inst->mnemo = IA64_INST_ADD; + inst->operands[3].valid = true; + inst->operands[3].index = -1; + inst->operands[3].value = x2b == 1; + return true; + case 0x1: // add (A1) + inst->mnemo = IA64_INST_SUB; + inst->operands[3].valid = true; + inst->operands[3].index = -1; + inst->operands[3].value = x2b == 0; + return true; + case 0x4: // shladd (A2) + inst->mnemo = IA64_INST_SHLADD; + inst->operands[3].valid = true; + inst->operands[3].index = -1; + inst->operands[3].value = ia64_inst_get_count2(inst->inst); + return true; + case 0x9: + if (x2b == 1) { + inst->mnemo = IA64_INST_SUB; + inst->operands[1].index = -1; + inst->operands[1].value = ia64_inst_get_imm8(inst->inst); + inst->operands[1].nat = 0; + return true; + } + break; + case 0xb: + inst->operands[1].index = -1; + inst->operands[1].value = ia64_inst_get_imm8(inst->inst); + inst->operands[1].nat = 0; + // fall-through + case 0x3: + switch (x2b) { + case 0: inst->mnemo = IA64_INST_AND; break; + case 1: inst->mnemo = IA64_INST_ANDCM; break; + case 2: inst->mnemo = IA64_INST_OR; break; + case 3: inst->mnemo = IA64_INST_XOR; break; + } + return true; + } + } + return false; +} + +// Decode instruction +static bool ia64_decode_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT) +{ + const int major = (inst->inst >> 37) & 0xf; + + inst->mnemo = IA64_INST_UNKNOWN; + inst->pred = inst->inst & 0x3f; + memset(&inst->operands[0], 0, sizeof(inst->operands)); + + switch (major) { + case 0x0: return ia64_decode_instruction_0(inst, IA64_CONTEXT); + case 0x4: return ia64_decode_instruction_4(inst, IA64_CONTEXT); + case 0x5: return ia64_decode_instruction_5(inst, IA64_CONTEXT); + case 0x8: return ia64_decode_instruction_8(inst, IA64_CONTEXT); + } + return false; +} + +static bool ia64_emulate_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT) +{ + // XXX: handle Register NaT Consumption fault? + // XXX: this simple emulator assumes instructions in a bundle + // don't depend on effects of other instructions in the same + // bundle. It probably would be simpler to JIT-generate code to be + // executed natively but probably more costly (inject/extract CPU state) + if (inst->mnemo == IA64_INST_UNKNOWN) + return false; + if (inst->pred && !IA64_GET_PR(inst->pred)) + return true; + + uint8_t nat, nat2; + uint64_t dst, dst2, src1, src2, src3; + + switch (inst->mnemo) { + case IA64_INST_NOP: + break; + case IA64_INST_ADD: + case IA64_INST_SUB: + case IA64_INST_SHLADD: + src3 = inst->operands[3].value; + // fall-through + case IA64_INST_AND: + case IA64_INST_ANDCM: + case IA64_INST_OR: + case IA64_INST_XOR: + src1 = inst->operands[1].value; + src2 = inst->operands[2].value; + switch (inst->mnemo) { + case IA64_INST_ADD: dst = src1 + src2 + src3; break; + case IA64_INST_SUB: dst = src1 - src2 - src3; break; + case IA64_INST_SHLADD: dst = (src1 << src3) + src2; break; + case IA64_INST_AND: dst = src1 & src2; break; + case IA64_INST_ANDCM: dst = src1 &~ src2; break; + case IA64_INST_OR: dst = src1 | src2; break; + case IA64_INST_XOR: dst = src1 ^ src2; break; + } + inst->operands[0].commit = true; + inst->operands[0].value = dst; + inst->operands[0].nat = inst->operands[1].nat | inst->operands[2].nat; + break; + case IA64_INST_SXT1: + case IA64_INST_SXT2: + case IA64_INST_SXT4: + case IA64_INST_ZXT1: + case IA64_INST_ZXT2: + case IA64_INST_ZXT4: + src1 = inst->operands[1].value; + switch (inst->mnemo) { + case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1; break; + case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1; break; + case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1; break; + case IA64_INST_ZXT1: dst = (uint8_t)src1; break; + case IA64_INST_ZXT2: dst = (uint16_t)src1; break; + case IA64_INST_ZXT4: dst = (uint32_t)src1; break; + } + inst->operands[0].commit = true; + inst->operands[0].value = dst; + inst->operands[0].nat = inst->operands[1].nat; + break; + case IA64_INST_LD1_UPDATE: + case IA64_INST_LD2_UPDATE: + case IA64_INST_LD4_UPDATE: + case IA64_INST_LD8_UPDATE: + inst->operands[1].commit = true; + dst2 = inst->operands[1].value + inst->operands[2].value; + nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0; + // fall-through + case IA64_INST_LD1: + case IA64_INST_LD2: + case IA64_INST_LD4: + case IA64_INST_LD8: + src1 = inst->operands[1].value; + if (inst->no_memory) + dst = 0; + else { + switch (inst->mnemo) { + case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((uint8_t *)src1); break; + case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((uint16_t *)src1); break; + case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((uint32_t *)src1); break; + case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((uint64_t *)src1); break; + } + } + inst->operands[0].commit = true; + inst->operands[0].value = dst; + inst->operands[0].nat = 0; + inst->operands[1].value = dst2; + inst->operands[1].nat = nat2; + break; + case IA64_INST_ST1_UPDATE: + case IA64_INST_ST2_UPDATE: + case IA64_INST_ST4_UPDATE: + case IA64_INST_ST8_UPDATE: + inst->operands[0].commit = 0; + dst2 = inst->operands[0].value + inst->operands[2].value; + nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0; + // fall-through + case IA64_INST_ST1: + case IA64_INST_ST2: + case IA64_INST_ST4: + case IA64_INST_ST8: + dst = inst->operands[0].value; + src1 = inst->operands[1].value; + if (!inst->no_memory) { + switch (inst->mnemo) { + case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((uint8_t *)dst) = src1; break; + case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((uint16_t *)dst) = src1; break; + case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((uint32_t *)dst) = src1; break; + case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((uint64_t *)dst) = src1; break; + } + } + inst->operands[0].value = dst2; + inst->operands[0].nat = nat2; + break; + default: + return false; + } + + for (int i = 0; i < IA64_N_OPERANDS; i++) { + ia64_operand_t const & op = inst->operands[i]; + if (!op.commit) + continue; + if (op.index == -1) + return false; // XXX: internal error + IA64_SET_GR(op.index, op.value, op.nat); + } + return true; +} + +static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT) +{ + ia64_instruction_t inst; + memset(&inst, 0, sizeof(inst)); + inst.inst = raw_inst; + if (!ia64_decode_instruction(&inst, IA64_CONTEXT)) + return false; + return ia64_emulate_instruction(&inst, IA64_CONTEXT); +} + +static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT) +{ + uint64_t ip = IA64_GET_IP(); +#if DEBUG + printf("IP: 0x%016llx\n", ip); +#if 0 + printf(" Template 0x%02x\n", ia64_get_template(ip)); + ia64_get_instruction(ip, 0); + ia64_get_instruction(ip, 1); + ia64_get_instruction(ip, 2); +#endif +#endif + + // Select which decode switch to use + ia64_instruction_t inst; + inst.inst = ia64_get_instruction(ip, ip & 3); + if (!ia64_decode_instruction(&inst, IA64_CONTEXT)) { + fprintf(stderr, "ERROR: ia64_skip_instruction(): could not decode instruction\n"); + return false; + } + + transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN; + transfer_size_t transfer_size = SIZE_UNKNOWN; + + switch (inst.mnemo) { + case IA64_INST_LD1: + case IA64_INST_LD2: + case IA64_INST_LD4: + case IA64_INST_LD8: + case IA64_INST_LD1_UPDATE: + case IA64_INST_LD2_UPDATE: + case IA64_INST_LD4_UPDATE: + case IA64_INST_LD8_UPDATE: + transfer_type = SIGSEGV_TRANSFER_LOAD; + break; + case IA64_INST_ST1: + case IA64_INST_ST2: + case IA64_INST_ST4: + case IA64_INST_ST8: + case IA64_INST_ST1_UPDATE: + case IA64_INST_ST2_UPDATE: + case IA64_INST_ST4_UPDATE: + case IA64_INST_ST8_UPDATE: + transfer_type = SIGSEGV_TRANSFER_STORE; + break; + } + + if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) { + // Unknown machine code, let it crash. Then patch the decoder + fprintf(stderr, "ERROR: ia64_skip_instruction(): not a load/store instruction\n"); + return false; + } + + switch (inst.mnemo) { + case IA64_INST_LD1: + case IA64_INST_LD1_UPDATE: + case IA64_INST_ST1: + case IA64_INST_ST1_UPDATE: + transfer_size = SIZE_BYTE; + break; + case IA64_INST_LD2: + case IA64_INST_LD2_UPDATE: + case IA64_INST_ST2: + case IA64_INST_ST2_UPDATE: + transfer_size = SIZE_WORD; + break; + case IA64_INST_LD4: + case IA64_INST_LD4_UPDATE: + case IA64_INST_ST4: + case IA64_INST_ST4_UPDATE: + transfer_size = SIZE_LONG; + break; + case IA64_INST_LD8: + case IA64_INST_LD8_UPDATE: + case IA64_INST_ST8: + case IA64_INST_ST8_UPDATE: + transfer_size = SIZE_QUAD; + break; + } + + if (transfer_size == SIZE_UNKNOWN) { + // Unknown machine code, let it crash. Then patch the decoder + fprintf(stderr, "ERROR: ia64_skip_instruction(): unknown transfer size\n"); + return false; + } + + inst.no_memory = true; + if (!ia64_emulate_instruction(&inst, IA64_CONTEXT)) { + fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate fault instruction\n"); + return false; + } + + int slot = ip & 3; + bool emulate_next = false; + switch (slot) { + case 0: + switch (ia64_get_template(ip)) { + case 0x2: // MI;I + case 0x3: // MI;I; + emulate_next = true; + slot = 2; + break; + case 0xa: // M;MI + case 0xb: // M;MI; + emulate_next = true; + slot = 1; + break; + } + break; + } + if (emulate_next && !IA64_CAN_PATCH_IP_SLOT) { + while (slot < 3) { + if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), IA64_CONTEXT)) { + fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate instruction\n"); + return false; + } + ++slot; + } + } + +#if IA64_CAN_PATCH_IP_SLOT + if ((slot = ip & 3) < 2) + IA64_SET_IP((ip & ~3ull) + (slot + 1)); + else +#endif + IA64_SET_IP((ip & ~3ull) + 16); +#if DEBUG + printf("IP: 0x%016llx\n", IA64_GET_IP()); +#endif + return true; +} +#endif + // Decode and skip PPC instruction -#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__)) -static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs) +#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__)) +static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs) { instruction_t instr; powerpc_decode_instruction(&instr, *nip_p, regs); @@ -928,7 +1965,9 @@ static bool powerpc_skip_instruction(uns #if DEBUG printf("%08x: %s %s access", *nip_p, - instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long", + instr.transfer_size == SIZE_BYTE ? "byte" : + instr.transfer_size == SIZE_WORD ? "word" : + instr.transfer_size == SIZE_LONG ? "long" : "quad", instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write"); if (instr.addr_mode == MODE_U || instr.addr_mode == MODE_UX) @@ -949,14 +1988,9 @@ static bool powerpc_skip_instruction(uns // Decode and skip MIPS instruction #if (defined(mips) || defined(__mips)) -enum { -#if (defined(sgi) || defined(__sgi)) - MIPS_REG_EPC = 35, -#endif -}; -static bool mips_skip_instruction(greg_t * regs) +static bool mips_skip_instruction(greg_t * pc_p, greg_t * regs) { - unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC]; + unsigned int * epc = (unsigned int *)(unsigned long)*pc_p; if (epc == 0) return false; @@ -1105,7 +2139,7 @@ static bool mips_skip_instruction(greg_t mips_gpr_names[reg]); #endif - regs[MIPS_REG_EPC] += 4; + *pc_p += 4; return true; } #endif @@ -1117,6 +2151,7 @@ enum { SPARC_REG_G1 = REG_G1, SPARC_REG_O0 = REG_O0, SPARC_REG_PC = REG_PC, + SPARC_REG_nPC = REG_nPC #endif }; static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin) @@ -1180,7 +2215,7 @@ static bool sparc_skip_instruction(unsig break; case 7: // Store Doubleword transfer_type = SIGSEGV_TRANSFER_STORE; - transfer_size = SIZE_WORD; + transfer_size = SIZE_LONG; register_pair = true; break; } @@ -1190,19 +2225,36 @@ static bool sparc_skip_instruction(unsig return false; } - // Zero target register in case of a load operation const int reg = (opcode >> 25) & 0x1f; + +#if DEBUG + static const char * reg_names[] = { + "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", + "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", + "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", + "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7" + }; + printf("%s %s register %s\n", + transfer_size == SIZE_BYTE ? "byte" : + transfer_size == SIZE_WORD ? "word" : + transfer_size == SIZE_LONG ? "long" : + transfer_size == SIZE_QUAD ? "quad" : "unknown", + transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from", + reg_names[reg]); +#endif + + // Zero target register in case of a load operation if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) { // FIXME: code to handle local & input registers is not tested - if (reg >= 1 && reg <= 7) { + if (reg >= 1 && reg < 8) { // global registers regs[reg - 1 + SPARC_REG_G1] = 0; } - else if (reg >= 8 && reg <= 15) { + else if (reg >= 8 && reg < 16) { // output registers regs[reg - 8 + SPARC_REG_O0] = 0; } - else if (reg >= 16 && reg <= 23) { + else if (reg >= 16 && reg < 24) { // local registers (in register windows) if (gwins) gwins->wbuf->rw_local[reg - 16] = 0; @@ -1218,37 +2270,177 @@ static bool sparc_skip_instruction(unsig } } + regs[SPARC_REG_PC] += 4; + regs[SPARC_REG_nPC] += 4; + return true; +} +#endif +#endif + +// Decode and skip ARM instruction +#if (defined(arm) || defined(__arm__)) +enum { +#if (defined(__linux__)) + ARM_REG_PC = 15, + ARM_REG_CPSR = 16 +#endif +}; +static bool arm_skip_instruction(unsigned long * regs) +{ + unsigned int * pc = (unsigned int *)regs[ARM_REG_PC]; + + if (pc == 0) + return false; + +#if DEBUG + printf("IP: %p [%08x]\n", pc, pc[0]); +#endif + + transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN; + transfer_size_t transfer_size = SIZE_UNKNOWN; + enum { op_sdt = 1, op_sdth = 2 }; + int op = 0; + + // Handle load/store instructions only + const unsigned int opcode = pc[0]; + switch ((opcode >> 25) & 7) { + case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH) + op = op_sdth; + // Determine transfer size (S/H bits) + switch ((opcode >> 5) & 3) { + case 0: // SWP instruction + break; + case 1: // Unsigned halfwords + case 3: // Signed halfwords + transfer_size = SIZE_WORD; + break; + case 2: // Signed byte + transfer_size = SIZE_BYTE; + break; + } + break; + case 2: + case 3: // Single Data Transfer (LDR, STR) + op = op_sdt; + // Determine transfer size (B bit) + if (((opcode >> 22) & 1) == 1) + transfer_size = SIZE_BYTE; + else + transfer_size = SIZE_LONG; + break; + default: + // FIXME: support load/store mutliple? + return false; + } + + // Check for invalid transfer size (SWP instruction?) + if (transfer_size == SIZE_UNKNOWN) + return false; + + // Determine transfer type (L bit) + if (((opcode >> 20) & 1) == 1) + transfer_type = SIGSEGV_TRANSFER_LOAD; + else + transfer_type = SIGSEGV_TRANSFER_STORE; + + // Compute offset + int offset; + if (((opcode >> 25) & 1) == 0) { + if (op == op_sdt) + offset = opcode & 0xfff; + else if (op == op_sdth) { + int rm = opcode & 0xf; + if (((opcode >> 22) & 1) == 0) { + // register offset + offset = regs[rm]; + } + else { + // immediate offset + offset = ((opcode >> 4) & 0xf0) | (opcode & 0x0f); + } + } + } + else { + const int rm = opcode & 0xf; + const int sh = (opcode >> 7) & 0x1f; + if (((opcode >> 4) & 1) == 1) { + // we expect only legal load/store instructions + printf("FATAL: invalid shift operand\n"); + return false; + } + const unsigned int v = regs[rm]; + switch ((opcode >> 5) & 3) { + case 0: // logical shift left + offset = sh ? v << sh : v; + break; + case 1: // logical shift right + offset = sh ? v >> sh : 0; + break; + case 2: // arithmetic shift right + if (sh) + offset = ((signed int)v) >> sh; + else + offset = (v & 0x80000000) ? 0xffffffff : 0; + break; + case 3: // rotate right + if (sh) + offset = (v >> sh) | (v << (32 - sh)); + else + offset = (v >> 1) | ((regs[ARM_REG_CPSR] << 2) & 0x80000000); + break; + } + } + if (((opcode >> 23) & 1) == 0) + offset = -offset; + + int rd = (opcode >> 12) & 0xf; + int rn = (opcode >> 16) & 0xf; #if DEBUG static const char * reg_names[] = { - "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", - "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", - "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7" + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }; printf("%s %s register %s\n", transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : - transfer_size == SIZE_LONG ? "long" : - transfer_size == SIZE_QUAD ? "quad" : "unknown", + transfer_size == SIZE_LONG ? "long" : "unknown", transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from", - reg_names[reg]); + reg_names[rd]); #endif - regs[SPARC_REG_PC] += 4; + unsigned int base = regs[rn]; + if (((opcode >> 24) & 1) == 1) + base += offset; + + if (transfer_type == SIGSEGV_TRANSFER_LOAD) + regs[rd] = 0; + + if (((opcode >> 24) & 1) == 0) // post-index addressing + regs[rn] += offset; + else if (((opcode >> 21) & 1) == 1) // write-back address into base + regs[rn] = base; + + regs[ARM_REG_PC] += 4; return true; } #endif -#endif + // Fallbacks +#ifndef SIGSEGV_FAULT_ADDRESS_FAST +#define SIGSEGV_FAULT_ADDRESS_FAST SIGSEGV_FAULT_ADDRESS +#endif +#ifndef SIGSEGV_FAULT_INSTRUCTION_FAST +#define SIGSEGV_FAULT_INSTRUCTION_FAST SIGSEGV_FAULT_INSTRUCTION +#endif #ifndef SIGSEGV_FAULT_INSTRUCTION -#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_INVALID_PC +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_INVALID_ADDRESS #endif #ifndef SIGSEGV_FAULT_HANDLER_ARGLIST_1 #define SIGSEGV_FAULT_HANDLER_ARGLIST_1 SIGSEGV_FAULT_HANDLER_ARGLIST #endif #ifndef SIGSEGV_FAULT_HANDLER_INVOKE -#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) sigsegv_fault_handler(ADDR, IP) +#define SIGSEGV_FAULT_HANDLER_INVOKE(P) sigsegv_fault_handler(P) #endif // SIGSEGV recovery supported ? @@ -1261,16 +2453,109 @@ static bool sparc_skip_instruction(unsig * SIGSEGV global handler */ -#if defined(HAVE_SIGSEGV_RECOVERY) || defined(HAVE_MACH_EXCEPTIONS) +struct sigsegv_info_t { + sigsegv_address_t addr; + sigsegv_address_t pc; +#ifdef HAVE_MACH_EXCEPTIONS + mach_port_t thread; + bool has_exc_state; + SIGSEGV_EXCEPTION_STATE_TYPE exc_state; + mach_msg_type_number_t exc_state_count; + bool has_thr_state; + SIGSEGV_THREAD_STATE_TYPE thr_state; + mach_msg_type_number_t thr_state_count; +#endif +}; + +#ifdef HAVE_MACH_EXCEPTIONS +static void mach_get_exception_state(sigsegv_info_t *SIP) +{ + SIP->exc_state_count = SIGSEGV_EXCEPTION_STATE_COUNT; + kern_return_t krc = thread_get_state(SIP->thread, + SIGSEGV_EXCEPTION_STATE_FLAVOR, + (natural_t *)&SIP->exc_state, + &SIP->exc_state_count); + MACH_CHECK_ERROR(thread_get_state, krc); + SIP->has_exc_state = true; +} + +static void mach_get_thread_state(sigsegv_info_t *SIP) +{ + SIP->thr_state_count = SIGSEGV_THREAD_STATE_COUNT; + kern_return_t krc = thread_get_state(SIP->thread, + SIGSEGV_THREAD_STATE_FLAVOR, + (natural_t *)&SIP->thr_state, + &SIP->thr_state_count); + MACH_CHECK_ERROR(thread_get_state, krc); + SIP->has_thr_state = true; +} + +static void mach_set_thread_state(sigsegv_info_t *SIP) +{ + kern_return_t krc = thread_set_state(SIP->thread, + SIGSEGV_THREAD_STATE_FLAVOR, + (natural_t *)&SIP->thr_state, + SIP->thr_state_count); + MACH_CHECK_ERROR(thread_set_state, krc); +} +#endif + +// Return the address of the invalid memory reference +sigsegv_address_t sigsegv_get_fault_address(sigsegv_info_t *SIP) +{ +#ifdef HAVE_MACH_EXCEPTIONS + static int use_fast_path = -1; + if (use_fast_path != 1 && !SIP->has_exc_state) { + mach_get_exception_state(SIP); + + sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS; + if (use_fast_path < 0) { + const char *machfault = getenv("SIGSEGV_MACH_FAULT"); + if (machfault) { + if (strcmp(machfault, "fast") == 0) + use_fast_path = 1; + else if (strcmp(machfault, "slow") == 0) + use_fast_path = 0; + } + if (use_fast_path < 0) + use_fast_path = addr == SIP->addr; + } + SIP->addr = addr; + } +#endif + return SIP->addr; +} + +// Return the address of the instruction that caused the fault, or +// SIGSEGV_INVALID_ADDRESS if we could not retrieve this information +sigsegv_address_t sigsegv_get_fault_instruction_address(sigsegv_info_t *SIP) +{ +#ifdef HAVE_MACH_EXCEPTIONS + if (!SIP->has_thr_state) { + mach_get_thread_state(SIP); + + SIP->pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION; + } +#endif + return SIP->pc; +} + // This function handles the badaccess to memory. // It is called from the signal handler or the exception handler. static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1) { - sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS; - sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION; - + sigsegv_info_t SI; + SI.addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS_FAST; + SI.pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION_FAST; +#ifdef HAVE_MACH_EXCEPTIONS + SI.thread = thread; + SI.has_exc_state = false; + SI.has_thr_state = false; +#endif + sigsegv_info_t * const SIP = &SI; + // Call user's handler and reinstall the global handler, if required - switch (SIGSEGV_FAULT_HANDLER_INVOKE(fault_address, fault_instruction)) { + switch (SIGSEGV_FAULT_HANDLER_INVOKE(SIP)) { case SIGSEGV_RETURN_SUCCESS: return true; @@ -1278,32 +2563,31 @@ static bool handle_badaccess(SIGSEGV_FAU case SIGSEGV_RETURN_SKIP_INSTRUCTION: // Call the instruction skipper with the register file // available +#ifdef HAVE_MACH_EXCEPTIONS + if (!SIP->has_thr_state) + mach_get_thread_state(SIP); +#endif if (SIGSEGV_SKIP_INSTRUCTION(SIGSEGV_REGISTER_FILE)) { #ifdef HAVE_MACH_EXCEPTIONS // Unlike UNIX signals where the thread state // is modified off of the stack, in Mach we // need to actually call thread_set_state to // have the register values updated. - kern_return_t krc; - - krc = thread_set_state(thread, - MACHINE_THREAD_STATE, (thread_state_t)state, - MACHINE_THREAD_STATE_COUNT); - MACH_CHECK_ERROR (thread_get_state, krc); + mach_set_thread_state(SIP); #endif return true; } break; #endif + case SIGSEGV_RETURN_FAILURE: + // We can't do anything with the fault_address, dump state? + if (sigsegv_state_dumper != 0) + sigsegv_state_dumper(SIP); + break; } - - // We can't do anything with the fault_address, dump state? - if (sigsegv_state_dumper != 0) - sigsegv_state_dumper(fault_address, fault_instruction); return false; } -#endif /* @@ -1340,7 +2624,7 @@ forward_exception(mach_port_t thread_por mach_port_t port; exception_behavior_t behavior; thread_state_flavor_t flavor; - thread_state_t thread_state; + thread_state_data_t thread_state; mach_msg_type_number_t thread_state_count; for (portIndex = 0; portIndex < oldExceptionPorts->maskCount; portIndex++) { @@ -1359,13 +2643,18 @@ forward_exception(mach_port_t thread_por behavior = oldExceptionPorts->behaviors[portIndex]; flavor = oldExceptionPorts->flavors[portIndex]; + if (!VALID_THREAD_STATE_FLAVOR(flavor)) { + fprintf(stderr, "Invalid thread_state flavor = %d. Not forwarding\n", flavor); + return KERN_FAILURE; + } + /* fprintf(stderr, "forwarding exception, port = 0x%x, behaviour = %d, flavor = %d\n", port, behavior, flavor); */ if (behavior != EXCEPTION_DEFAULT) { thread_state_count = THREAD_STATE_MAX; - kret = thread_get_state (thread_port, flavor, thread_state, + kret = thread_get_state (thread_port, flavor, (natural_t *)&thread_state, &thread_state_count); MACH_CHECK_ERROR (thread_get_state, kret); } @@ -1381,8 +2670,8 @@ forward_exception(mach_port_t thread_por // fprintf(stderr, "forwarding to exception_raise_state\n"); kret = exception_raise_state(port, exception_type, exception_data, data_count, &flavor, - thread_state, thread_state_count, - thread_state, &thread_state_count); + (natural_t *)&thread_state, thread_state_count, + (natural_t *)&thread_state, &thread_state_count); MACH_CHECK_ERROR (exception_raise_state, kret); break; case EXCEPTION_STATE_IDENTITY: @@ -1390,22 +2679,23 @@ forward_exception(mach_port_t thread_por kret = exception_raise_state_identity(port, thread_port, task_port, exception_type, exception_data, data_count, &flavor, - thread_state, thread_state_count, - thread_state, &thread_state_count); + (natural_t *)&thread_state, thread_state_count, + (natural_t *)&thread_state, &thread_state_count); MACH_CHECK_ERROR (exception_raise_state_identity, kret); break; default: fprintf(stderr, "forward_exception got unknown behavior\n"); + kret = KERN_FAILURE; break; } if (behavior != EXCEPTION_DEFAULT) { - kret = thread_set_state (thread_port, flavor, thread_state, + kret = thread_set_state (thread_port, flavor, (natural_t *)&thread_state, thread_state_count); MACH_CHECK_ERROR (thread_set_state, kret); } - return KERN_SUCCESS; + return kret; } /* @@ -1433,20 +2723,24 @@ catch_exception_raise(mach_port_t except mach_port_t task, exception_type_t exception, exception_data_t code, - mach_msg_type_number_t codeCount) + mach_msg_type_number_t code_count) { - ppc_thread_state_t state; kern_return_t krc; - if ((exception == EXC_BAD_ACCESS) && (codeCount >= 2)) { - if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS)) - return KERN_SUCCESS; + if (exception == EXC_BAD_ACCESS) { + switch (code[0]) { + case KERN_PROTECTION_FAILURE: + case KERN_INVALID_ADDRESS: + if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS)) + return KERN_SUCCESS; + break; + } } // In Mach we do not need to remove the exception handler. // If we forward the exception, eventually some exception handler // will take care of this exception. - krc = forward_exception(thread, task, exception, code, codeCount, &ports); + krc = forward_exception(thread, task, exception, code, code_count, &ports); return krc; } @@ -1574,7 +2868,7 @@ static bool sigsegv_do_install_handler(s // addressing modes) used in PPC instructions, you will need the // GPR state anyway. krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort, - EXCEPTION_DEFAULT, MACHINE_THREAD_STATE); + EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR); if (krc != KERN_SUCCESS) { mach_error("thread_set_exception_ports", krc); return false; @@ -1597,6 +2891,95 @@ static bool sigsegv_do_install_handler(s } #endif +#ifdef HAVE_WIN32_EXCEPTIONS +static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo) +{ + if (sigsegv_fault_handler != NULL + && ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION + && ExceptionInfo->ExceptionRecord->NumberParameters == 2 + && handle_badaccess(ExceptionInfo)) + return EXCEPTION_CONTINUE_EXECUTION; + + return EXCEPTION_CONTINUE_SEARCH; +} + +#if defined __CYGWIN__ && defined __i386__ +/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin + installs a global exception handler. We have to dig deep in order to install + our main_exception_filter. */ + +/* Data structures for the current thread's exception handler chain. + On the x86 Windows uses register fs, offset 0 to point to the current + exception handler; Cygwin mucks with it, so we must do the same... :-/ */ + +/* Magic taken from winsup/cygwin/include/exceptions.h. */ + +struct exception_list { + struct exception_list *prev; + int (*handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *); +}; +typedef struct exception_list exception_list; + +/* Magic taken from winsup/cygwin/exceptions.cc. */ + +__asm__ (".equ __except_list,0"); + +extern exception_list *_except_list __asm__ ("%fs:__except_list"); + +/* For debugging. _except_list is not otherwise accessible from gdb. */ +static exception_list * +debug_get_except_list () +{ + return _except_list; +} + +/* Cygwin's original exception handler. */ +static int (*cygwin_exception_handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *); + +/* Our exception handler. */ +static int +libsigsegv_exception_handler (EXCEPTION_RECORD *exception, void *frame, CONTEXT *context, void *dispatch) +{ + EXCEPTION_POINTERS ExceptionInfo; + ExceptionInfo.ExceptionRecord = exception; + ExceptionInfo.ContextRecord = context; + if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH) + return cygwin_exception_handler (exception, frame, context, dispatch); + else + return 0; +} + +static void +do_install_main_exception_filter () +{ + /* We cannot insert any handler into the chain, because such handlers + must lie on the stack (?). Instead, we have to replace(!) Cygwin's + global exception handler. */ + cygwin_exception_handler = _except_list->handler; + _except_list->handler = libsigsegv_exception_handler; +} + +#else + +static void +do_install_main_exception_filter () +{ + SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter); +} +#endif + +static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler) +{ + static bool main_exception_filter_installed = false; + if (!main_exception_filter_installed) { + do_install_main_exception_filter(); + main_exception_filter_installed = true; + } + sigsegv_fault_handler = handler; + return true; +} +#endif + bool sigsegv_install_handler(sigsegv_fault_handler_t handler) { #if defined(HAVE_SIGSEGV_RECOVERY) @@ -1607,7 +2990,7 @@ bool sigsegv_install_handler(sigsegv_fau if (success) sigsegv_fault_handler = handler; return success; -#elif defined(HAVE_MACH_EXCEPTIONS) +#elif defined(HAVE_MACH_EXCEPTIONS) || defined(HAVE_WIN32_EXCEPTIONS) return sigsegv_do_install_handler(handler); #else // FAIL: no siginfo_t nor sigcontext subterfuge is available @@ -1633,6 +3016,9 @@ void sigsegv_deinstall_handler(void) SIGSEGV_ALL_SIGNALS #undef FAULT_HANDLER #endif +#ifdef HAVE_WIN32_EXCEPTIONS + sigsegv_fault_handler = NULL; +#endif } @@ -1654,23 +3040,34 @@ void sigsegv_set_dump_state(sigsegv_stat #include #include #include +#ifdef HAVE_SYS_MMAN_H #include +#endif #include "vm_alloc.h" const int REF_INDEX = 123; const int REF_VALUE = 45; -static int page_size; +static sigsegv_uintptr_t page_size; static volatile char * page = 0; static volatile int handler_called = 0; +/* Barriers */ +#ifdef __GNUC__ +#define BARRIER() asm volatile ("" : : : "memory") +#else +#define BARRIER() /* nothing */ +#endif + #ifdef __GNUC__ // Code range where we expect the fault to come from static void *b_region, *e_region; #endif -static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address) +static sigsegv_return_t sigsegv_test_handler(sigsegv_info_t *sip) { + const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip); + const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip); #if DEBUG printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address); printf("expected fault at %p\n", page + REF_INDEX); @@ -1684,24 +3081,29 @@ static sigsegv_return_t sigsegv_test_han #ifdef __GNUC__ // Make sure reported fault instruction address falls into // expected code range - if (instruction_address != SIGSEGV_INVALID_PC + if (instruction_address != SIGSEGV_INVALID_ADDRESS && ((instruction_address < (sigsegv_address_t)b_region) || (instruction_address >= (sigsegv_address_t)e_region))) exit(11); #endif - if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0) + if (vm_protect((char *)((sigsegv_uintptr_t)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0) exit(12); return SIGSEGV_RETURN_SUCCESS; } #ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION -static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address) +static sigsegv_return_t sigsegv_insn_handler(sigsegv_info_t *sip) { - if (((unsigned long)fault_address - (unsigned long)page) < page_size) { + const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip); + const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip); +#if DEBUG + printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address); +#endif + if (((sigsegv_uintptr_t)fault_address - (sigsegv_uintptr_t)page) < page_size) { #ifdef __GNUC__ // Make sure reported fault instruction address falls into // expected code range - if (instruction_address != SIGSEGV_INVALID_PC + if (instruction_address != SIGSEGV_INVALID_ADDRESS && ((instruction_address < (sigsegv_address_t)b_region) || (instruction_address >= (sigsegv_address_t)e_region))) return SIGSEGV_RETURN_FAILURE; @@ -1715,7 +3117,7 @@ static sigsegv_return_t sigsegv_insn_han // More sophisticated tests for instruction skipper static bool arch_insn_skipper_tests() { -#if (defined(i386) || defined(__i386__)) || defined(__x86_64__) +#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64)) static const unsigned char code[] = { 0x8a, 0x00, // mov (%eax),%al 0x8a, 0x2c, 0x18, // mov (%eax,%ebx,1),%ch @@ -1729,7 +3131,7 @@ static bool arch_insn_skipper_tests() 0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%ecx 0x89, 0x00, // mov %eax,(%eax) 0x89, 0x0c, 0x18, // mov %ecx,(%eax,%ebx,1) -#if defined(__x86_64__) +#if defined(__x86_64__) || defined(_M_X64) 0x44, 0x8a, 0x00, // mov (%rax),%r8b 0x44, 0x8a, 0x20, // mov (%rax),%r12b 0x42, 0x8a, 0x3c, 0x10, // mov (%rax,%r10,1),%dil @@ -1752,14 +3154,16 @@ static bool arch_insn_skipper_tests() 0x4c, 0x89, 0x18, // mov %r11,(%rax) 0x4a, 0x89, 0x0c, 0x10, // mov %rcx,(%rax,%r10,1) 0x4e, 0x89, 0x1c, 0x10, // mov %r11,(%rax,%r10,1) + 0x63, 0x47, 0x04, // movslq 4(%rdi),%eax + 0x48, 0x63, 0x47, 0x04, // movslq 4(%rdi),%rax #endif 0 // end }; const int N_REGS = 20; - unsigned long regs[N_REGS]; + SIGSEGV_REGISTER_TYPE regs[N_REGS]; for (int i = 0; i < N_REGS; i++) regs[i] = i; - const unsigned long start_code = (unsigned long)&code; + const sigsegv_uintptr_t start_code = (sigsegv_uintptr_t)&code; regs[X86_REG_EIP] = start_code; while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1) && ix86_skip_instruction(regs)) @@ -1775,7 +3179,7 @@ int main(void) if (vm_init() < 0) return 1; - page_size = getpagesize(); + page_size = vm_get_page_size(); if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED) return 2; @@ -1785,17 +3189,30 @@ int main(void) if (!sigsegv_install_handler(sigsegv_test_handler)) return 4; - + #ifdef __GNUC__ b_region = &&L_b_region1; e_region = &&L_e_region1; #endif - L_b_region1: - page[REF_INDEX] = REF_VALUE; - if (page[REF_INDEX] != REF_VALUE) - exit(20); - page[REF_INDEX] = REF_VALUE; - L_e_region1: + /* This is a really awful hack but otherwise gcc is smart enough + * (or bug'ous enough?) to optimize the labels and place them + * e.g. at the "main" entry point, which is wrong. + */ + volatile int label_hack = 1; + switch (label_hack) { + case 1: + L_b_region1: + page[REF_INDEX] = REF_VALUE; + if (page[REF_INDEX] != REF_VALUE) + exit(20); + page[REF_INDEX] = REF_VALUE; + BARRIER(); + // fall-through + case 2: + L_e_region1: + BARRIER(); + break; + } if (handler_called != 1) return 5; @@ -1826,13 +3243,24 @@ int main(void) b_region = &&L_b_region2; e_region = &&L_e_region2; #endif - L_b_region2: - TEST_SKIP_INSTRUCTION(unsigned char); - TEST_SKIP_INSTRUCTION(unsigned short); - TEST_SKIP_INSTRUCTION(unsigned int); - TEST_SKIP_INSTRUCTION(unsigned long); - L_e_region2: - + switch (label_hack) { + case 1: + L_b_region2: + TEST_SKIP_INSTRUCTION(unsigned char); + TEST_SKIP_INSTRUCTION(unsigned short); + TEST_SKIP_INSTRUCTION(unsigned int); + TEST_SKIP_INSTRUCTION(unsigned long); + TEST_SKIP_INSTRUCTION(signed char); + TEST_SKIP_INSTRUCTION(signed short); + TEST_SKIP_INSTRUCTION(signed int); + TEST_SKIP_INSTRUCTION(signed long); + BARRIER(); + // fall-through + case 2: + L_e_region2: + BARRIER(); + break; + } if (!arch_insn_skipper_tests()) return 20; #endif