[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.76 by gbeauche, 2008-01-06T16:36:00Z vs.
Revision 1.85 by gbeauche, 2008-01-20T22:24:53Z

#	Line 49 \| Line 49 \| using std::list;
49		#define RETSIGTYPE void
50		#endif
51
52	+	// Size of an unsigned integer large enough to hold all bits of a pointer
53	+	// NOTE: this can be different than SIGSEGV_REGISTER_TYPE. In
54	+	// particular, on ILP32 systems with a 64-bit kernel (HP-UX/ia64?)
55	+	#ifdef HAVE_WIN32_VM
56	+	// Windows is either ILP32 or LLP64
57	+	typedef UINT_PTR sigsegv_uintptr_t;
58	+	#else
59	+	// Other systems are sane enough to follow ILP32 or LP64 models
60	+	typedef unsigned long sigsegv_uintptr_t;
61	+	#endif
62	+
63		// Type of the system signal handler
64		typedef RETSIGTYPE (*signal_handler)(int);
65
#	Line 232 \| Line 243 \| static void powerpc_decode_instruction(i
243		// Generic extended signal handler
244		#if defined(__FreeBSD__)
245		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
246	+	#elif defined(__hpux)
247	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) FAULT_HANDLER(SIGBUS)
248		#else
249		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
250		#endif
#	Line 264 \| Line 277 \| static void powerpc_decode_instruction(i
277		#include <sys/regset.h>
278		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
279		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[EIP]
280	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
280	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
281		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
282		#endif
283		#endif
284		#if defined(__FreeBSD__) \|\| defined(__OpenBSD__)
285		#if (defined(i386) \|\| defined(__i386__))
286		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
287	<	#define SIGSEGV_REGISTER_FILE ((unsigned long )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
287	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
288		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
289		#endif
290		#endif
#	Line 280 \| Line 293 \| static void powerpc_decode_instruction(i
293		#include <sys/ucontext.h>
294		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
295		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP]
296	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
296	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
297		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
298		#endif
299		#if (defined(powerpc) \|\| defined(__powerpc__))
#	Line 296 \| Line 309 \| static void powerpc_decode_instruction(i
309		#include <sys/ucontext.h>
310		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
311		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
312	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
312	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
313		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
314		#endif
315		#if (defined(x86_64) \|\| defined(__x86_64__))
316		#include <sys/ucontext.h>
317		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
318		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
319	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
319	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
320		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
321		#endif
322		#if (defined(ia64) \|\| defined(__ia64__))
323		#define SIGSEGV_CONTEXT_REGS ((struct sigcontext *)scp)
324		#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
325	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
325	>	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
326		#define SIGSEGV_SKIP_INSTRUCTION ia64_skip_instruction
327		#endif
328		#if (defined(powerpc) \|\| defined(__powerpc__))
#	Line 338 \| Line 351 \| static void powerpc_decode_instruction(i
351		#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
352		#endif
353		#endif
354	+	#if (defined(__hpux) \|\| defined(__hpux__))
355	+	#if (defined(__hppa) \|\| defined(__hppa__))
356	+	#define SIGSEGV_CONTEXT_REGS (&((ucontext_t *)scp)->uc_mcontext)
357	+	#define SIGSEGV_FAULT_INSTRUCTION_32 (SIGSEGV_CONTEXT_REGS->ss_narrow.ss_pcoq_head & ~3ul)
358	+	#define SIGSEGV_FAULT_INSTRUCTION_64 (SIGSEGV_CONTEXT_REGS->ss_wide.ss_64.ss_pcoq_head & ~3ull)
359	+	#if defined(__LP64__)
360	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_FAULT_INSTRUCTION_64
361	+	#else
362	+	#define SIGSEGV_FAULT_INSTRUCTION ((SIGSEGV_CONTEXT_REGS->ss_flags & SS_WIDEREGS) ? \
363	+	(uint32_t)SIGSEGV_FAULT_INSTRUCTION_64 : \
364	+	SIGSEGV_FAULT_INSTRUCTION_32)
365	+	#endif
366	+	#endif
367	+	#if (defined(__ia64) \|\| defined(__ia64__))
368	+	#include <sys/ucontext.h>
369	+	#define SIGSEGV_CONTEXT_REGS ((ucontext_t *)scp)
370	+	#define SIGSEGV_FAULT_INSTRUCTION get_fault_instruction(SIGSEGV_CONTEXT_REGS)
371	+	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
372	+	#define SIGSEGV_SKIP_INSTRUCTION ia64_skip_instruction
373	+
374	+	#include <sys/uc_access.h>
375	+	static inline sigsegv_address_t get_fault_instruction(const ucontext_t *ucp)
376	+	{
377	+	uint64_t ip;
378	+	if (__uc_get_ip(ucp, &ip) != 0)
379	+	return SIGSEGV_INVALID_ADDRESS;
380	+	return (sigsegv_address_t)(ip & ~3ULL);
381	+	}
382	+	#endif
383	+	#endif
384		#endif
385
386		#if HAVE_SIGCONTEXT_SUBTERFUGE
#	Line 351 \| Line 394 \| static void powerpc_decode_instruction(i
394		#define SIGSEGV_FAULT_HANDLER_ARGS &scs
395		#define SIGSEGV_FAULT_ADDRESS scp->cr2
396		#define SIGSEGV_FAULT_INSTRUCTION scp->eip
397	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)scp
397	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)scp
398		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
399		#endif
400		#if (defined(sparc) \|\| defined(__sparc__))
#	Line 472 \| Line 515 \| static sigsegv_address_t get_fault_addre
515		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr
516		#define SIGSEGV_FAULT_ADDRESS addr
517		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_eip
518	<	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi)
518	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&scp->sc_edi)
519		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
520		#endif
521		#if (defined(alpha) \|\| defined(__alpha__))
#	Line 539 \| Line 582 \| static sigsegv_address_t get_fault_addre
582		#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo
583		#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
584		#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord
585	+	#if defined(_M_IX86)
586		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip
587	<	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
587	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi)
588		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
589		#endif
590	+	#if defined(_M_X64)
591	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Rip
592	+	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax)
593	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
594	+	#endif
595	+	#if defined(_M_IA64)
596	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->StIIP
597	+	#endif
598	+	#endif
599
600		#if HAVE_MACH_EXCEPTIONS
601
#	Line 564 \| Line 617 \| extern "C" {
617		#include <mach/mach.h>
618		#include <mach/mach_error.h>
619
620	<	extern boolean_t exc_server(mach_msg_header_t , mach_msg_header_t );
621	<	extern kern_return_t catch_exception_raise(mach_port_t, mach_port_t,
622	<	mach_port_t, exception_type_t, exception_data_t, mach_msg_type_number_t);
623	<	extern kern_return_t exception_raise(mach_port_t, mach_port_t, mach_port_t,
624	<	exception_type_t, exception_data_t, mach_msg_type_number_t);
625	<	extern kern_return_t exception_raise_state(mach_port_t, exception_type_t,
626	<	exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
620	>	#ifndef HAVE_MACH64_VM
621	>	#define MACH_EXCEPTION_CODES 0
622	>	#define mach_exception_data_t exception_data_t
623	>	#define mach_exception_data_type_t exception_data_type_t
624	>	#define mach_exc_server exc_server
625	>	#define catch_mach_exception_raise catch_exception_raise
626	>	#define mach_exception_raise exception_raise
627	>	#define mach_exception_raise_state exception_raise_state
628	>	#define mach_exception_raise_state_identity exception_raise_state_identity
629	>	#endif
630	>
631	>	extern boolean_t mach_exc_server(mach_msg_header_t , mach_msg_header_t );
632	>	extern kern_return_t catch_mach_exception_raise(mach_port_t, mach_port_t,
633	>	mach_port_t, exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
634	>	extern kern_return_t catch_mach_exception_raise_state(mach_port_t exception_port,
635	>	exception_type_t exception, mach_exception_data_t code, mach_msg_type_number_t code_count,
636	>	int *flavor,
637	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
638	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
639	>	extern kern_return_t catch_mach_exception_raise_state_identity(mach_port_t exception_port,
640	>	mach_port_t thread_port, mach_port_t task_port, exception_type_t exception,
641	>	mach_exception_data_t code, mach_msg_type_number_t code_count,
642	>	int *flavor,
643	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
644	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
645	>	extern kern_return_t mach_exception_raise(mach_port_t, mach_port_t, mach_port_t,
646	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
647	>	extern kern_return_t mach_exception_raise_state(mach_port_t, exception_type_t,
648	>	mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
649		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
650	<	extern kern_return_t exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
651	<	exception_type_t, exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
650	>	extern kern_return_t mach_exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
651	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
652		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
653		}
654
#	Line 605 \| Line 680 \| if (ret != KERN_SUCCESS) { \
680		}
681
682		#ifdef __ppc__
683	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE
684	+	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
685	+	#endif
686		#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state_t
687		#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE
688		#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE_COUNT
689	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.dar
689	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar)
690		#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t
691		#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE
692		#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT
693	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.srr0
693	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0)
694		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
695	<	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.srr0, (unsigned long )&SIP->thr_state.r0
695	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(r0)
696		#endif
697		#ifdef __ppc64__
698	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64
699	+	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
700	+	#endif
701		#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state64_t
702		#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE64
703		#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE64_COUNT
704	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.dar
704	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar)
705		#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state64_t
706		#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE64
707		#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE64_COUNT
708	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.srr0
708	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0)
709		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
710	<	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.srr0, (unsigned long )&SIP->thr_state.r0
710	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(r0)
711		#endif
712		#ifdef __i386__
713	<	#define SIGSEGV_EXCEPTION_STATE_TYPE struct i386_exception_state
713	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32
714	>	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
715	>	#endif
716	>	#define SIGSEGV_EXCEPTION_STATE_TYPE i386_exception_state_t
717		#define SIGSEGV_EXCEPTION_STATE_FLAVOR i386_EXCEPTION_STATE
718		#define SIGSEGV_EXCEPTION_STATE_COUNT i386_EXCEPTION_STATE_COUNT
719	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.faultvaddr
720	<	#define SIGSEGV_THREAD_STATE_TYPE struct i386_thread_state
719	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
720	>	#define SIGSEGV_THREAD_STATE_TYPE i386_thread_state_t
721		#define SIGSEGV_THREAD_STATE_FLAVOR i386_THREAD_STATE
722		#define SIGSEGV_THREAD_STATE_COUNT i386_THREAD_STATE_COUNT
723	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.eip
723	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(eip)
724		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
725	<	#define SIGSEGV_REGISTER_FILE ((unsigned long )&SIP->thr_state.eax) / EAX is the first GPR we consider */
725	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.MACH_FIELD_NAME(eax)) / EAX is the first GPR we consider */
726		#endif
727		#ifdef __x86_64__
728	<	#define SIGSEGV_EXCEPTION_STATE_TYPE struct x86_exception_state64
728	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64
729	>	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
730	>	#endif
731	>	#define SIGSEGV_EXCEPTION_STATE_TYPE x86_exception_state64_t
732		#define SIGSEGV_EXCEPTION_STATE_FLAVOR x86_EXCEPTION_STATE64
733		#define SIGSEGV_EXCEPTION_STATE_COUNT x86_EXCEPTION_STATE64_COUNT
734	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.faultvaddr
735	<	#define SIGSEGV_THREAD_STATE_TYPE struct x86_thread_state64
734	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
735	>	#define SIGSEGV_THREAD_STATE_TYPE x86_thread_state64_t
736		#define SIGSEGV_THREAD_STATE_FLAVOR x86_THREAD_STATE64
737		#define SIGSEGV_THREAD_STATE_COUNT x86_THREAD_STATE64_COUNT
738	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.rip
738	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(rip)
739		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
740	<	#define SIGSEGV_REGISTER_FILE ((unsigned long )&SIP->thr_state.rax) / RAX is the first GPR we consider */
740	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.MACH_FIELD_NAME(rax)) / RAX is the first GPR we consider */
741		#endif
742		#define SIGSEGV_FAULT_ADDRESS_FAST code[1]
743		#define SIGSEGV_FAULT_INSTRUCTION_FAST SIGSEGV_INVALID_ADDRESS
744	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code
744	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, mach_exception_data_t code
745		#define SIGSEGV_FAULT_HANDLER_ARGS thread, code
746
747	+	#ifndef MACH_FIELD_NAME
748	+	#define MACH_FIELD_NAME(X) X
749	+	#endif
750	+
751		// Since there can only be one exception thread running at any time
752		// this is not a problem.
753		#define MSG_SIZE 512
#	Line 686 \| Line 777 \| *handleExceptions(void priv)**
777		_exceptionPort, 0, MACH_PORT_NULL);
778		MACH_CHECK_ERROR(mach_msg, krc);
779
780	<	if (!exc_server(msg, reply)) {
780	>	if (!mach_exc_server(msg, reply)) {
781		fprintf(stderr, "exc_server hated the message\n");
782		exit(1);
783		}
#	Line 708 \| Line 799 \| *handleExceptions(void priv)**
799		* Instruction skipping
800		*/
801
802	+	#ifndef SIGSEGV_REGISTER_TYPE
803	+	#define SIGSEGV_REGISTER_TYPE sigsegv_uintptr_t
804	+	#endif
805	+
806		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
807		// Decode and skip X86 instruction
808	<	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
808	>	#if (defined(i386) \|\| defined(__i386__)) \|\| (defined(__x86_64__) \|\| defined(_M_X64))
809		#if defined(__linux__)
810		enum {
811		#if (defined(i386) \|\| defined(__i386__))
#	Line 861 \| Line 956 \| enum {
956		#endif
957		#if defined(_WIN32)
958		enum {
959	<	#if (defined(i386) \|\| defined(__i386__))
959	>	#if defined(_M_IX86)
960		X86_REG_EIP = 7,
961		X86_REG_EAX = 5,
962		X86_REG_ECX = 4,
#	Line 872 \| Line 967 \| enum {
967		X86_REG_ESI = 1,
968		X86_REG_EDI = 0
969		#endif
970	+	#if defined(_M_X64)
971	+	X86_REG_EAX = 0,
972	+	X86_REG_ECX = 1,
973	+	X86_REG_EDX = 2,
974	+	X86_REG_EBX = 3,
975	+	X86_REG_ESP = 4,
976	+	X86_REG_EBP = 5,
977	+	X86_REG_ESI = 6,
978	+	X86_REG_EDI = 7,
979	+	X86_REG_R8 = 8,
980	+	X86_REG_R9 = 9,
981	+	X86_REG_R10 = 10,
982	+	X86_REG_R11 = 11,
983	+	X86_REG_R12 = 12,
984	+	X86_REG_R13 = 13,
985	+	X86_REG_R14 = 14,
986	+	X86_REG_R15 = 15,
987	+	X86_REG_EIP = 16
988	+	#endif
989		};
990		#endif
991		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 908 \| Line 1022 \| static inline int ix86_step_over_modrm(u
1022		return offset;
1023		}
1024
1025	<	static bool ix86_skip_instruction(unsigned long * regs)
1025	>	static bool ix86_skip_instruction(SIGSEGV_REGISTER_TYPE * regs)
1026		{
1027		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
1028
#	Line 944 \| Line 1058 \| static bool ix86_skip_instruction(unsign
1058		}
1059
1060		// REX prefix
1061	<	#if defined(__x86_64__)
1061	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1062		struct rex_t {
1063		unsigned char W;
1064		unsigned char R;
#	Line 996 \| Line 1110 \| static bool ix86_skip_instruction(unsign
1110		goto do_transfer_load;
1111		}
1112		break;
1113	<	#if defined(__x86_64__)
1113	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1114		case 0x63: // MOVSXD r64, r/m32
1115		if (has_rex && rex.W) {
1116		transfer_size = SIZE_LONG;
#	Line 1067 \| Line 1181 \| static bool ix86_skip_instruction(unsign
1181		return false;
1182		}
1183
1184	<	#if defined(__x86_64__)
1184	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1185		if (rex.R)
1186		reg += 8;
1187		#endif
#	Line 1076 \| Line 1190 \| static bool ix86_skip_instruction(unsign
1190		static const int x86_reg_map[] = {
1191		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
1192		X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
1193	<	#if defined(__x86_64__)
1193	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1194		X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
1195		X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
1196		#endif
#	Line 1164 \| Line 1278 \| static bool ix86_skip_instruction(unsign
1278		#endif
1279
1280		// Decode and skip IA-64 instruction
1281	<	#if defined(__ia64__)
1281	>	#if defined(__ia64) \|\| defined(__ia64__)
1282	>	typedef uint64_t ia64_bundle_t[2];
1283		#if defined(__linux__)
1284	<	// XXX: we assume everything is 8-byte aligned
1285	<	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
1286	<	#define IREG(REG) ((OREG(REG) - OREG(flags)) / 8)
1287	<	enum {
1288	<	IA64_REG_IP = IREG(ip),
1289	<	IA64_REG_NAT = IREG(nat),
1290	<	IA64_REG_PR = IREG(pr),
1291	<	IA64_REG_GR = IREG(gr)
1292	<	};
1293	<	#undef IREG
1294	<	#undef OREG
1284	>	// We can directly patch the slot number
1285	>	#define IA64_CAN_PATCH_IP_SLOT 1
1286	>	// Helper macros to access the machine context
1287	>	#define IA64_CONTEXT_TYPE struct sigcontext *
1288	>	#define IA64_CONTEXT scp
1289	>	#define IA64_GET_IP() (IA64_CONTEXT->sc_ip)
1290	>	#define IA64_SET_IP(V) (IA64_CONTEXT->sc_ip = (V))
1291	>	#define IA64_GET_PR(P) ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1292	>	#define IA64_GET_NAT(I) ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1293	>	#define IA64_GET_GR(R) (IA64_CONTEXT->sc_gr[(R)])
1294	>	#define _IA64_SET_GR(R,V) (IA64_CONTEXT->sc_gr[(R)] = (V))
1295	>	#define _IA64_SET_NAT(I,V) (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) \| (((uint64_t)!!(V)) << (I)))
1296	>	#define IA64_SET_GR(R,V,N) (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N))
1297	>
1298	>	// Load bundle (in little-endian)
1299	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1300	>	{
1301	>	uint64_t ip = (uint64_t )(raw_ip & ~3ull);
1302	>	bundle[0] = ip[0];
1303	>	bundle[1] = ip[1];
1304	>	}
1305	>	#endif
1306	>	#if defined(__hpux) \|\| defined(__hpux__)
1307	>	// We can directly patch the slot number
1308	>	#define IA64_CAN_PATCH_IP_SLOT 1
1309	>	// Helper macros to access the machine context
1310	>	#define IA64_CONTEXT_TYPE ucontext_t *
1311	>	#define IA64_CONTEXT ucp
1312	>	#define IA64_GET_IP() ia64_get_ip(IA64_CONTEXT)
1313	>	#define IA64_SET_IP(V) ia64_set_ip(IA64_CONTEXT, V)
1314	>	#define IA64_GET_PR(P) ia64_get_pr(IA64_CONTEXT, P)
1315	>	#define IA64_GET_NAT(I) ia64_get_nat(IA64_CONTEXT, I)
1316	>	#define IA64_GET_GR(R) ia64_get_gr(IA64_CONTEXT, R)
1317	>	#define IA64_SET_GR(R,V,N) ia64_set_gr(IA64_CONTEXT, R, V, N)
1318	>	#define UC_ACCESS(FUNC,ARGS) do { if (__uc_##FUNC ARGS != 0) abort(); } while (0)
1319	>
1320	>	static inline uint64_t ia64_get_ip(IA64_CONTEXT_TYPE IA64_CONTEXT)
1321	>	{ uint64_t v; UC_ACCESS(get_ip,(IA64_CONTEXT, &v)); return v; }
1322	>	static inline void ia64_set_ip(IA64_CONTEXT_TYPE IA64_CONTEXT, uint64_t v)
1323	>	{ UC_ACCESS(set_ip,(IA64_CONTEXT, v)); }
1324	>	static inline unsigned int ia64_get_pr(IA64_CONTEXT_TYPE IA64_CONTEXT, int pr)
1325	>	{ uint64_t v; UC_ACCESS(get_prs,(IA64_CONTEXT, &v)); return (v >> pr) & 1; }
1326	>	static inline unsigned int ia64_get_nat(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1327	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return (nat >> r) & 1; }
1328	>	static inline uint64_t ia64_get_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1329	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return v; }
1330	>
1331	>	static void ia64_set_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r, uint64_t v, unsigned int nat)
1332	>	{
1333	>	if (r == 0)
1334	>	return;
1335	>	if (r > 0 && r < 32)
1336	>	UC_ACCESS(set_grs,(IA64_CONTEXT, r, 1, &v, (!!nat) << r));
1337	>	else {
1338	>	uint64_t bsp, bspstore;
1339	>	UC_ACCESS(get_ar_bsp,(IA64_CONTEXT, &bsp));
1340	>	UC_ACCESS(get_ar_bspstore,(IA64_CONTEXT, &bspstore));
1341	>	abort(); /* XXX: use libunwind, this is not fun... */
1342	>	}
1343	>	}
1344	>
1345	>	// Byte-swapping
1346	>	#if defined(__GNUC__)
1347	>	#define BSWAP64(V) ({ uint64_t r; __asm__ __volatile__("mux1 %0=%1,@rev;;" : "=r" (r) : "r" (V)); r; })
1348	>	#elif defined (__HP_aCC)
1349	>	#define BSWAP64(V) _Asm_mux1(_MBTYPE_REV, V)
1350	>	#else
1351	>	#error "Define byte-swap instruction"
1352		#endif
1353
1354	<	// Helper macros to access the machine context
1355	<	#define IA64_CONTEXT (ctx)
1356	<	#define IA64_GET_PR(P) ((IA64_CONTEXT[IA64_REG_PR] >> (P)) & 1)
1357	<	#define IA64_GET_NAT(I) ((IA64_CONTEXT[IA64_REG_NAT] >> (I)) & 1)
1358	<	#define IA64_SET_NAT(I,V) (IA64_CONTEXT[IA64_REG_NAT] = (IA64_CONTEXT[IA64_REG_NAT] & ~(1ul << (I))) \| (((unsigned long)!!(V)) << (I)))
1359	<	#define IA64_GET_GR(R) (IA64_CONTEXT[IA64_REG_GR + (R)])
1360	<	#define IA64_SET_GR(R,V) (IA64_CONTEXT[IA64_REG_GR + (R)] = (V))
1354	>	// Load bundle (in little-endian)
1355	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1356	>	{
1357	>	uint64_t ip = (uint64_t )(raw_ip & ~3ull);
1358	>	bundle[0] = BSWAP64(ip[0]);
1359	>	bundle[1] = BSWAP64(ip[1]);
1360	>	}
1361	>	#endif
1362
1363		// Instruction operations
1364		enum {
#	Line 1226 \| Line 1399 \| const int IA64_N_OPERANDS = 4;
1399
1400		// Decoded operand type
1401		struct ia64_operand_t {
1402	<	unsigned char commit; // commit result of operation to register file?
1403	<	unsigned char valid; // XXX: not really used, can be removed (debug)
1404	<	signed char index; // index of GPR, or -1 if immediate value
1405	<	unsigned char nat; // NaT state before operation
1406	<	unsigned long value; // register contents or immediate value
1402	>	uint8_t commit; // commit result of operation to register file?
1403	>	uint8_t valid; // XXX: not really used, can be removed (debug)
1404	>	int8_t index; // index of GPR, or -1 if immediate value
1405	>	uint8_t nat; // NaT state before operation
1406	>	uint64_t value; // register contents or immediate value
1407		};
1408
1409		// Decoded instruction type
1410		struct ia64_instruction_t {
1411	<	unsigned char mnemo; // operation to perform
1412	<	unsigned char pred; // predicate register to check
1413	<	unsigned char no_memory; // used to emulated main fault instruction
1414	<	unsigned long inst; // the raw instruction bits (41-bit wide)
1411	>	uint8_t mnemo; // operation to perform
1412	>	uint8_t pred; // predicate register to check
1413	>	uint8_t no_memory; // used to emulated main fault instruction
1414	>	uint64_t inst; // the raw instruction bits (41-bit wide)
1415		ia64_operand_t operands[IA64_N_OPERANDS];
1416		};
1417
1418		// Get immediate sign-bit
1419	<	static inline int ia64_inst_get_sbit(unsigned long inst)
1419	>	static inline int ia64_inst_get_sbit(uint64_t inst)
1420		{
1421		return (inst >> 36) & 1;
1422		}
1423
1424		// Get 8-bit immediate value (A3, A8, I27, M30)
1425	<	static inline unsigned long ia64_inst_get_imm8(unsigned long inst)
1425	>	static inline uint64_t ia64_inst_get_imm8(uint64_t inst)
1426		{
1427	<	unsigned long value = (inst >> 13) & 0x7ful;
1427	>	uint64_t value = (inst >> 13) & 0x7full;
1428		if (ia64_inst_get_sbit(inst))
1429	<	value \|= ~0x7ful;
1429	>	value \|= ~0x7full;
1430		return value;
1431		}
1432
1433		// Get 9-bit immediate value (M3)
1434	<	static inline unsigned long ia64_inst_get_imm9b(unsigned long inst)
1434	>	static inline uint64_t ia64_inst_get_imm9b(uint64_t inst)
1435		{
1436	<	unsigned long value = (((inst >> 27) & 1) << 7) \| ((inst >> 13) & 0x7f);
1436	>	uint64_t value = (((inst >> 27) & 1) << 7) \| ((inst >> 13) & 0x7f);
1437		if (ia64_inst_get_sbit(inst))
1438	<	value \|= ~0xfful;
1438	>	value \|= ~0xffull;
1439		return value;
1440		}
1441
1442		// Get 9-bit immediate value (M5)
1443	<	static inline unsigned long ia64_inst_get_imm9a(unsigned long inst)
1443	>	static inline uint64_t ia64_inst_get_imm9a(uint64_t inst)
1444		{
1445	<	unsigned long value = (((inst >> 27) & 1) << 7) \| ((inst >> 6) & 0x7f);
1445	>	uint64_t value = (((inst >> 27) & 1) << 7) \| ((inst >> 6) & 0x7f);
1446		if (ia64_inst_get_sbit(inst))
1447	<	value \|= ~0xfful;
1447	>	value \|= ~0xffull;
1448		return value;
1449		}
1450
1451		// Get 14-bit immediate value (A4)
1452	<	static inline unsigned long ia64_inst_get_imm14(unsigned long inst)
1452	>	static inline uint64_t ia64_inst_get_imm14(uint64_t inst)
1453		{
1454	<	unsigned long value = (((inst >> 27) & 0x3f) << 7) \| (inst & 0x7f);
1454	>	uint64_t value = (((inst >> 27) & 0x3f) << 7) \| (inst & 0x7f);
1455		if (ia64_inst_get_sbit(inst))
1456	<	value \|= ~0x1fful;
1456	>	value \|= ~0x1ffull;
1457		return value;
1458		}
1459
1460		// Get 22-bit immediate value (A5)
1461	<	static inline unsigned long ia64_inst_get_imm22(unsigned long inst)
1461	>	static inline uint64_t ia64_inst_get_imm22(uint64_t inst)
1462		{
1463	<	unsigned long value = ((((inst >> 22) & 0x1f) << 16) \|
1464	<	(((inst >> 27) & 0x1ff) << 7) \|
1465	<	(inst & 0x7f));
1463	>	uint64_t value = ((((inst >> 22) & 0x1f) << 16) \|
1464	>	(((inst >> 27) & 0x1ff) << 7) \|
1465	>	(inst & 0x7f));
1466		if (ia64_inst_get_sbit(inst))
1467	<	value \|= ~0x1ffffful;
1467	>	value \|= ~0x1fffffull;
1468		return value;
1469		}
1470
1471		// Get 21-bit immediate value (I19)
1472	<	static inline unsigned long ia64_inst_get_imm21(unsigned long inst)
1472	>	static inline uint64_t ia64_inst_get_imm21(uint64_t inst)
1473		{
1474		return (((inst >> 36) & 1) << 20) \| ((inst >> 6) & 0xfffff);
1475		}
1476
1477		// Get 2-bit count value (A2)
1478	<	static inline int ia64_inst_get_count2(unsigned long inst)
1478	>	static inline int ia64_inst_get_count2(uint64_t inst)
1479		{
1480		return (inst >> 27) & 0x3;
1481		}
1482
1483		// Get bundle template
1484	<	static inline unsigned int ia64_get_template(unsigned long raw_ip)
1484	>	static inline unsigned int ia64_get_template(uint64_t ip)
1485		{
1486	<	unsigned long ip = (unsigned long )(raw_ip & ~3ul);
1487	<	return ip[0] & 0x1f;
1486	>	ia64_bundle_t bundle;
1487	>	ia64_load_bundle(bundle, ip);
1488	>	return bundle[0] & 0x1f;
1489		}
1490
1491		// Get specified instruction in bundle
1492	<	static unsigned long ia64_get_instruction(unsigned long raw_ip, int slot)
1492	>	static uint64_t ia64_get_instruction(uint64_t ip, int slot)
1493		{
1494	<	unsigned long inst;
1495	<	unsigned long ip = (unsigned long )(raw_ip & ~3ul);
1494	>	uint64_t inst;
1495	>	ia64_bundle_t bundle;
1496	>	ia64_load_bundle(bundle, ip);
1497		#if DEBUG
1498	<	printf("Bundle: %016lx%016lx\n", ip[1], ip[0]);
1498	>	printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]);
1499		#endif
1500
1501		switch (slot) {
1502		case 0:
1503	<	inst = (ip[0] >> 5) & 0x1fffffffffful;
1503	>	inst = (bundle[0] >> 5) & 0x1ffffffffffull;
1504		break;
1505		case 1:
1506	<	inst = ((ip[1] & 0x7ffffful) << 18) \| ((ip[0] >> 46) & 0x3fffful);
1506	>	inst = ((bundle[1] & 0x7fffffull) << 18) \| ((bundle[0] >> 46) & 0x3ffffull);
1507		break;
1508		case 2:
1509	<	inst = (ip[1] >> 23) & 0x1fffffffffful;
1509	>	inst = (bundle[1] >> 23) & 0x1ffffffffffull;
1510		break;
1511		case 3:
1512		fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
#	Line 1340 \| Line 1515 \| static unsigned long ia64_get_instructio
1515		}
1516
1517		#if DEBUG
1518	<	printf(" Instruction %d: 0x%016lx\n", slot, inst);
1518	>	printf(" Instruction %d: 0x%016llx\n", slot, inst);
1519		#endif
1520		return inst;
1521		}
1522
1523		// Decode group 0 instructions
1524	<	static bool ia64_decode_instruction_0(ia64_instruction_t inst, unsigned long ctx)
1524	>	static bool ia64_decode_instruction_0(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1525		{
1526		const int r1 = (inst->inst >> 6) & 0x7f;
1527		const int r3 = (inst->inst >> 20) & 0x7f;
#	Line 1392 \| Line 1567 \| static bool ia64_decode_instruction_0(ia
1567		}
1568
1569		// Decode group 4 instructions (load/store instructions)
1570	<	static bool ia64_decode_instruction_4(ia64_instruction_t inst, unsigned long ctx)
1570	>	static bool ia64_decode_instruction_4(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1571		{
1572		const int r1 = (inst->inst >> 6) & 0x7f;
1573		const int r2 = (inst->inst >> 13) & 0x7f;
#	Line 1464 \| Line 1639 \| static bool ia64_decode_instruction_4(ia
1639		}
1640
1641		// Decode group 5 instructions (load/store instructions)
1642	<	static bool ia64_decode_instruction_5(ia64_instruction_t inst, unsigned long ctx)
1642	>	static bool ia64_decode_instruction_5(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1643		{
1644		const int r1 = (inst->inst >> 6) & 0x7f;
1645		const int r2 = (inst->inst >> 13) & 0x7f;
#	Line 1522 \| Line 1697 \| static bool ia64_decode_instruction_5(ia
1697		}
1698
1699		// Decode group 8 instructions (ALU integer)
1700	<	static bool ia64_decode_instruction_8(ia64_instruction_t inst, unsigned long ctx)
1700	>	static bool ia64_decode_instruction_8(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1701		{
1702		const int r1 = (inst->inst >> 6) & 0x7f;
1703		const int r2 = (inst->inst >> 13) & 0x7f;
#	Line 1595 \| Line 1770 \| static bool ia64_decode_instruction_8(ia
1770		}
1771
1772		// Decode instruction
1773	<	static bool ia64_decode_instruction(ia64_instruction_t inst, unsigned long ctx)
1773	>	static bool ia64_decode_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1774		{
1775		const int major = (inst->inst >> 37) & 0xf;
1776
#	Line 1604 \| Line 1779 \| static bool ia64_decode_instruction(ia64
1779		memset(&inst->operands[0], 0, sizeof(inst->operands));
1780
1781		switch (major) {
1782	<	case 0x0: return ia64_decode_instruction_0(inst, ctx);
1783	<	case 0x4: return ia64_decode_instruction_4(inst, ctx);
1784	<	case 0x5: return ia64_decode_instruction_5(inst, ctx);
1785	<	case 0x8: return ia64_decode_instruction_8(inst, ctx);
1782	>	case 0x0: return ia64_decode_instruction_0(inst, IA64_CONTEXT);
1783	>	case 0x4: return ia64_decode_instruction_4(inst, IA64_CONTEXT);
1784	>	case 0x5: return ia64_decode_instruction_5(inst, IA64_CONTEXT);
1785	>	case 0x8: return ia64_decode_instruction_8(inst, IA64_CONTEXT);
1786		}
1787		return false;
1788		}
1789
1790	<	static bool ia64_emulate_instruction(ia64_instruction_t inst, unsigned long ctx)
1790	>	static bool ia64_emulate_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1791		{
1792		// XXX: handle Register NaT Consumption fault?
1793		// XXX: this simple emulator assumes instructions in a bundle
#	Line 1624 \| Line 1799 \| static bool ia64_emulate_instruction(ia6
1799		if (inst->pred && !IA64_GET_PR(inst->pred))
1800		return true;
1801
1802	<	unsigned char nat, nat2;
1803	<	unsigned long dst, dst2, src1, src2, src3;
1802	>	uint8_t nat, nat2;
1803	>	uint64_t dst, dst2, src1, src2, src3;
1804
1805		switch (inst->mnemo) {
1806		case IA64_INST_NOP:
#	Line 1662 \| Line 1837 \| static bool ia64_emulate_instruction(ia6
1837		case IA64_INST_ZXT4:
1838		src1 = inst->operands[1].value;
1839		switch (inst->mnemo) {
1840	<	case IA64_INST_SXT1: dst = (signed long)(signed char)src1; break;
1841	<	case IA64_INST_SXT2: dst = (signed long)(signed short)src1; break;
1842	<	case IA64_INST_SXT4: dst = (signed long)(signed int)src1; break;
1843	<	case IA64_INST_ZXT1: dst = (unsigned char)src1; break;
1844	<	case IA64_INST_ZXT2: dst = (unsigned short)src1; break;
1845	<	case IA64_INST_ZXT4: dst = (unsigned int)src1; break;
1840	>	case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1; break;
1841	>	case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1; break;
1842	>	case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1; break;
1843	>	case IA64_INST_ZXT1: dst = (uint8_t)src1; break;
1844	>	case IA64_INST_ZXT2: dst = (uint16_t)src1; break;
1845	>	case IA64_INST_ZXT4: dst = (uint32_t)src1; break;
1846		}
1847		inst->operands[0].commit = true;
1848		inst->operands[0].value = dst;
#	Line 1690 \| Line 1865 \| static bool ia64_emulate_instruction(ia6
1865		dst = 0;
1866		else {
1867		switch (inst->mnemo) {
1868	<	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = ((unsigned char )src1); break;
1869	<	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = ((unsigned short )src1); break;
1870	<	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = ((unsigned int )src1); break;
1871	<	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = ((unsigned long )src1); break;
1868	>	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = ((uint8_t )src1); break;
1869	>	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = ((uint16_t )src1); break;
1870	>	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = ((uint32_t )src1); break;
1871	>	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = ((uint64_t )src1); break;
1872		}
1873		}
1874		inst->operands[0].commit = true;
#	Line 1718 \| Line 1893 \| static bool ia64_emulate_instruction(ia6
1893		src1 = inst->operands[1].value;
1894		if (!inst->no_memory) {
1895		switch (inst->mnemo) {
1896	<	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: ((unsigned char )dst) = src1; break;
1897	<	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: ((unsigned short )dst) = src1; break;
1898	<	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: ((unsigned int )dst) = src1; break;
1899	<	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: ((unsigned long )dst) = src1; break;
1896	>	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: ((uint8_t )dst) = src1; break;
1897	>	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: ((uint16_t )dst) = src1; break;
1898	>	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: ((uint32_t )dst) = src1; break;
1899	>	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: ((uint64_t )dst) = src1; break;
1900		}
1901		}
1902		inst->operands[0].value = dst2;
#	Line 1737 \| Line 1912 \| static bool ia64_emulate_instruction(ia6
1912		continue;
1913		if (op.index == -1)
1914		return false; // XXX: internal error
1915	<	IA64_SET_GR(op.index, op.value);
1741	<	IA64_SET_NAT(op.index, op.nat);
1915	>	IA64_SET_GR(op.index, op.value, op.nat);
1916		}
1917		return true;
1918		}
1919
1920	<	static bool ia64_emulate_instruction(unsigned long raw_inst, unsigned long *ctx)
1920	>	static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1921		{
1922		ia64_instruction_t inst;
1923		memset(&inst, 0, sizeof(inst));
1924		inst.inst = raw_inst;
1925	<	if (!ia64_decode_instruction(&inst, ctx))
1925	>	if (!ia64_decode_instruction(&inst, IA64_CONTEXT))
1926		return false;
1927	<	return ia64_emulate_instruction(&inst, ctx);
1927	>	return ia64_emulate_instruction(&inst, IA64_CONTEXT);
1928		}
1929
1930	<	static bool ia64_skip_instruction(unsigned long *ctx)
1930	>	static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1931		{
1932	<	unsigned long ip = ctx[IA64_REG_IP];
1932	>	uint64_t ip = IA64_GET_IP();
1933		#if DEBUG
1934	<	printf("IP: 0x%016lx\n", ip);
1934	>	printf("IP: 0x%016llx\n", ip);
1935		#if 0
1936		printf(" Template 0x%02x\n", ia64_get_template(ip));
1937		ia64_get_instruction(ip, 0);
#	Line 1769 \| Line 1943 \| static bool ia64_skip_instruction(unsign
1943		// Select which decode switch to use
1944		ia64_instruction_t inst;
1945		inst.inst = ia64_get_instruction(ip, ip & 3);
1946	<	if (!ia64_decode_instruction(&inst, ctx)) {
1946	>	if (!ia64_decode_instruction(&inst, IA64_CONTEXT)) {
1947		fprintf(stderr, "ERROR: ia64_skip_instruction(): could not decode instruction\n");
1948		return false;
1949		}
#	Line 1840 \| Line 2014 \| static bool ia64_skip_instruction(unsign
2014		}
2015
2016		inst.no_memory = true;
2017	<	if (!ia64_emulate_instruction(&inst, ctx)) {
2017	>	if (!ia64_emulate_instruction(&inst, IA64_CONTEXT)) {
2018		fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate fault instruction\n");
2019		return false;
2020		}
#	Line 1863 \| Line 2037 \| static bool ia64_skip_instruction(unsign
2037		}
2038		break;
2039		}
2040	<	if (emulate_next) {
2040	>	if (emulate_next && !IA64_CAN_PATCH_IP_SLOT) {
2041		while (slot < 3) {
2042	<	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), ctx)) {
2042	>	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), IA64_CONTEXT)) {
2043		fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate instruction\n");
2044		return false;
2045		}
#	Line 1873 \| Line 2047 \| static bool ia64_skip_instruction(unsign
2047		}
2048		}
2049
2050	<	ctx[IA64_REG_IP] = (ip & ~3ul) + 16;
2050	>	#if IA64_CAN_PATCH_IP_SLOT
2051	>	if ((slot = ip & 3) < 2)
2052	>	IA64_SET_IP((ip & ~3ull) + (slot + 1));
2053	>	else
2054	>	#endif
2055	>	IA64_SET_IP((ip & ~3ull) + 16);
2056		#if DEBUG
2057	<	printf("IP: 0x%016lx\n", ctx[IA64_REG_IP]);
2057	>	printf("IP: 0x%016llx\n", IA64_GET_IP());
2058		#endif
2059		return true;
2060		}
#	Line 2439 \| Line 2618 \| sigsegv_address_t sigsegv_get_fault_addr
2618		mach_get_exception_state(SIP);
2619
2620		sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
2621	<	if (use_fast_path < 0)
2622	<	use_fast_path = addr == SIP->addr;
2621	>	if (use_fast_path < 0) {
2622	>	const char *machfault = getenv("SIGSEGV_MACH_FAULT");
2623	>	if (machfault) {
2624	>	if (strcmp(machfault, "fast") == 0)
2625	>	use_fast_path = 1;
2626	>	else if (strcmp(machfault, "slow") == 0)
2627	>	use_fast_path = 0;
2628	>	}
2629	>	if (use_fast_path < 0)
2630	>	use_fast_path = addr == SIP->addr;
2631	>	}
2632		SIP->addr = addr;
2633		}
2634		#endif
#	Line 2536 \| Line 2724 \| static inline kern_return_t
2724		forward_exception(mach_port_t thread_port,
2725		mach_port_t task_port,
2726		exception_type_t exception_type,
2727	<	exception_data_t exception_data,
2727	>	mach_exception_data_t exception_data,
2728		mach_msg_type_number_t data_count,
2729		ExceptionPorts *oldExceptionPorts)
2730		{
#	Line 2583 \| Line 2771 \| forward_exception(mach_port_t thread_por
2771		switch (behavior) {
2772		case EXCEPTION_DEFAULT:
2773		// fprintf(stderr, "forwarding to exception_raise\n");
2774	<	kret = exception_raise(port, thread_port, task_port, exception_type,
2775	<	exception_data, data_count);
2776	<	MACH_CHECK_ERROR (exception_raise, kret);
2774	>	kret = mach_exception_raise(port, thread_port, task_port, exception_type,
2775	>	exception_data, data_count);
2776	>	MACH_CHECK_ERROR (mach_exception_raise, kret);
2777		break;
2778		case EXCEPTION_STATE:
2779		// fprintf(stderr, "forwarding to exception_raise_state\n");
2780	<	kret = exception_raise_state(port, exception_type, exception_data,
2781	<	data_count, &flavor,
2782	<	(natural_t *)&thread_state, thread_state_count,
2783	<	(natural_t *)&thread_state, &thread_state_count);
2784	<	MACH_CHECK_ERROR (exception_raise_state, kret);
2780	>	kret = mach_exception_raise_state(port, exception_type, exception_data,
2781	>	data_count, &flavor,
2782	>	(natural_t *)&thread_state, thread_state_count,
2783	>	(natural_t *)&thread_state, &thread_state_count);
2784	>	MACH_CHECK_ERROR (mach_exception_raise_state, kret);
2785		break;
2786		case EXCEPTION_STATE_IDENTITY:
2787		// fprintf(stderr, "forwarding to exception_raise_state_identity\n");
2788	<	kret = exception_raise_state_identity(port, thread_port, task_port,
2789	<	exception_type, exception_data,
2790	<	data_count, &flavor,
2791	<	(natural_t *)&thread_state, thread_state_count,
2792	<	(natural_t *)&thread_state, &thread_state_count);
2793	<	MACH_CHECK_ERROR (exception_raise_state_identity, kret);
2788	>	kret = mach_exception_raise_state_identity(port, thread_port, task_port,
2789	>	exception_type, exception_data,
2790	>	data_count, &flavor,
2791	>	(natural_t *)&thread_state, thread_state_count,
2792	>	(natural_t *)&thread_state, &thread_state_count);
2793	>	MACH_CHECK_ERROR (mach_exception_raise_state_identity, kret);
2794		break;
2795		default:
2796		fprintf(stderr, "forward_exception got unknown behavior\n");
#	Line 2639 \| Line 2827 \| forward_exception(mach_port_t thread_por
2827		* linkage because that is what exc_server expects.
2828		*/
2829		kern_return_t
2830	<	catch_exception_raise(mach_port_t exception_port,
2831	<	mach_port_t thread,
2832	<	mach_port_t task,
2833	<	exception_type_t exception,
2834	<	exception_data_t code,
2835	<	mach_msg_type_number_t code_count)
2830	>	catch_mach_exception_raise(mach_port_t exception_port,
2831	>	mach_port_t thread,
2832	>	mach_port_t task,
2833	>	exception_type_t exception,
2834	>	mach_exception_data_t code,
2835	>	mach_msg_type_number_t code_count)
2836		{
2837		kern_return_t krc;
2838
#	Line 2665 \| Line 2853 \| catch_exception_raise(mach_port_t except
2853
2854		return krc;
2855		}
2856	+
2857	+	/* XXX: borrowed from launchd and gdb */
2858	+	kern_return_t
2859	+	catch_mach_exception_raise_state(mach_port_t exception_port,
2860	+	exception_type_t exception,
2861	+	mach_exception_data_t code,
2862	+	mach_msg_type_number_t code_count,
2863	+	int *flavor,
2864	+	thread_state_t old_state,
2865	+	mach_msg_type_number_t old_state_count,
2866	+	thread_state_t new_state,
2867	+	mach_msg_type_number_t *new_state_count)
2868	+	{
2869	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2870	+	*new_state_count = old_state_count;
2871	+	return KERN_SUCCESS;
2872	+	}
2873	+
2874	+	/* XXX: borrowed from launchd and gdb */
2875	+	kern_return_t
2876	+	catch_mach_exception_raise_state_identity(mach_port_t exception_port,
2877	+	mach_port_t thread_port,
2878	+	mach_port_t task_port,
2879	+	exception_type_t exception,
2880	+	mach_exception_data_t code,
2881	+	mach_msg_type_number_t code_count,
2882	+	int *flavor,
2883	+	thread_state_t old_state,
2884	+	mach_msg_type_number_t old_state_count,
2885	+	thread_state_t new_state,
2886	+	mach_msg_type_number_t *new_state_count)
2887	+	{
2888	+	kern_return_t kret;
2889	+
2890	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2891	+	*new_state_count = old_state_count;
2892	+
2893	+	kret = mach_port_deallocate(mach_task_self(), task_port);
2894	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2895	+	kret = mach_port_deallocate(mach_task_self(), thread_port);
2896	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2897	+
2898	+	return KERN_SUCCESS;
2899	+	}
2900		#endif
2901
2902		#ifdef HAVE_SIGSEGV_RECOVERY
#	Line 2789 \| Line 3021 \| static bool sigsegv_do_install_handler(s
3021		// addressing modes) used in PPC instructions, you will need the
3022		// GPR state anyway.
3023		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
3024	<	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
3024	>	EXCEPTION_DEFAULT \| MACH_EXCEPTION_CODES, SIGSEGV_THREAD_STATE_FLAVOR);
3025		if (krc != KERN_SUCCESS) {
3026		mach_error("thread_set_exception_ports", krc);
3027		return false;
#	Line 2817 \| Line 3049 \| static LONG WINAPI main_exception_filter
3049		{
3050		if (sigsegv_fault_handler != NULL
3051		&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
3052	<	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
3052	>	&& ExceptionInfo->ExceptionRecord->NumberParameters >= 2
3053		&& handle_badaccess(ExceptionInfo))
3054		return EXCEPTION_CONTINUE_EXECUTION;
3055
#	Line 2969 \| Line 3201 \| void sigsegv_set_dump_state(sigsegv_stat
3201		const int REF_INDEX = 123;
3202		const int REF_VALUE = 45;
3203
3204	<	static int page_size;
3204	>	static sigsegv_uintptr_t page_size;
3205		static volatile char * page = 0;
3206		static volatile int handler_called = 0;
3207
#	Line 3007 \| Line 3239 \| static sigsegv_return_t sigsegv_test_han
3239		(instruction_address >= (sigsegv_address_t)e_region)))
3240		exit(11);
3241		#endif
3242	<	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ \| VM_PAGE_WRITE) != 0)
3242	>	if (vm_protect((char *)((sigsegv_uintptr_t)fault_address & -page_size), page_size, VM_PAGE_READ \| VM_PAGE_WRITE) != 0)
3243		exit(12);
3244		return SIGSEGV_RETURN_SUCCESS;
3245		}
#	Line 3020 \| Line 3252 \| static sigsegv_return_t sigsegv_insn_han
3252		#if DEBUG
3253		printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
3254		#endif
3255	<	if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
3255	>	if (((sigsegv_uintptr_t)fault_address - (sigsegv_uintptr_t)page) < page_size) {
3256		#ifdef __GNUC__
3257		// Make sure reported fault instruction address falls into
3258		// expected code range
#	Line 3038 \| Line 3270 \| static sigsegv_return_t sigsegv_insn_han
3270		// More sophisticated tests for instruction skipper
3271		static bool arch_insn_skipper_tests()
3272		{
3273	<	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
3273	>	#if (defined(i386) \|\| defined(__i386__)) \|\| (defined(__x86_64__) \|\| defined(_M_X64))
3274		static const unsigned char code[] = {
3275		0x8a, 0x00, // mov (%eax),%al
3276		0x8a, 0x2c, 0x18, // mov (%eax,%ebx,1),%ch
#	Line 3052 \| Line 3284 \| static bool arch_insn_skipper_tests()
3284		0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%ecx
3285		0x89, 0x00, // mov %eax,(%eax)
3286		0x89, 0x0c, 0x18, // mov %ecx,(%eax,%ebx,1)
3287	<	#if defined(__x86_64__)
3287	>	#if defined(__x86_64__) \|\| defined(_M_X64)
3288		0x44, 0x8a, 0x00, // mov (%rax),%r8b
3289		0x44, 0x8a, 0x20, // mov (%rax),%r12b
3290		0x42, 0x8a, 0x3c, 0x10, // mov (%rax,%r10,1),%dil
#	Line 3081 \| Line 3313 \| static bool arch_insn_skipper_tests()
3313		0 // end
3314		};
3315		const int N_REGS = 20;
3316	<	unsigned long regs[N_REGS];
3316	>	SIGSEGV_REGISTER_TYPE regs[N_REGS];
3317		for (int i = 0; i < N_REGS; i++)
3318		regs[i] = i;
3319	<	const unsigned long start_code = (unsigned long)&code;
3319	>	const sigsegv_uintptr_t start_code = (sigsegv_uintptr_t)&code;
3320		regs[X86_REG_EIP] = start_code;
3321		while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
3322		&& ix86_skip_instruction(regs))

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+Removed lines
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+Changed lines

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.76 by gbeauche, 2008-01-06T16:36:00Z vs. Revision 1.85 by gbeauche, 2008-01-20T22:24:53Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.76 by gbeauche, 2008-01-06T16:36:00Z vs.
Revision 1.85 by gbeauche, 2008-01-20T22:24:53Z