[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.76 by gbeauche, 2008-01-06T16:36:00Z vs.
Revision 1.84 by gbeauche, 2008-01-20T17:09:34Z

#	Line 49 \| Line 49 \| using std::list;
49		#define RETSIGTYPE void
50		#endif
51
52	+	// Size of an unsigned integer large enough to hold all bits of a pointer
53	+	// NOTE: this can be different than SIGSEGV_REGISTER_TYPE. In
54	+	// particular, on ILP32 systems with a 64-bit kernel (HP-UX/ia64?)
55	+	#ifdef HAVE_WIN32_VM
56	+	// Windows is either ILP32 or LLP64
57	+	typedef UINT_PTR sigsegv_uintptr_t;
58	+	#else
59	+	// Other systems are sane enough to follow ILP32 or LP64 models
60	+	typedef unsigned long sigsegv_uintptr_t;
61	+	#endif
62	+
63		// Type of the system signal handler
64		typedef RETSIGTYPE (*signal_handler)(int);
65
#	Line 232 \| Line 243 \| static void powerpc_decode_instruction(i
243		// Generic extended signal handler
244		#if defined(__FreeBSD__)
245		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
246	+	#elif defined(__hpux)
247	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) FAULT_HANDLER(SIGBUS)
248		#else
249		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
250		#endif
#	Line 264 \| Line 277 \| static void powerpc_decode_instruction(i
277		#include <sys/regset.h>
278		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
279		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[EIP]
280	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
280	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
281		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
282		#endif
283		#endif
284		#if defined(__FreeBSD__) \|\| defined(__OpenBSD__)
285		#if (defined(i386) \|\| defined(__i386__))
286		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
287	<	#define SIGSEGV_REGISTER_FILE ((unsigned long )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
287	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
288		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
289		#endif
290		#endif
#	Line 280 \| Line 293 \| static void powerpc_decode_instruction(i
293		#include <sys/ucontext.h>
294		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
295		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP]
296	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
296	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
297		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
298		#endif
299		#if (defined(powerpc) \|\| defined(__powerpc__))
#	Line 296 \| Line 309 \| static void powerpc_decode_instruction(i
309		#include <sys/ucontext.h>
310		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
311		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
312	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
312	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
313		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
314		#endif
315		#if (defined(x86_64) \|\| defined(__x86_64__))
316		#include <sys/ucontext.h>
317		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
318		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
319	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
319	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
320		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
321		#endif
322		#if (defined(ia64) \|\| defined(__ia64__))
323		#define SIGSEGV_CONTEXT_REGS ((struct sigcontext *)scp)
324		#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
325	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
325	>	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
326		#define SIGSEGV_SKIP_INSTRUCTION ia64_skip_instruction
327		#endif
328		#if (defined(powerpc) \|\| defined(__powerpc__))
#	Line 338 \| Line 351 \| static void powerpc_decode_instruction(i
351		#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
352		#endif
353		#endif
354	+	#if (defined(__hpux) \|\| defined(__hpux__))
355	+	#if (defined(__hppa) \|\| defined(__hppa__))
356	+	#define SIGSEGV_CONTEXT_REGS (&((ucontext_t *)scp)->uc_mcontext)
357	+	#define SIGSEGV_FAULT_INSTRUCTION_32 (SIGSEGV_CONTEXT_REGS->ss_narrow.ss_pcoq_head & ~3ul)
358	+	#define SIGSEGV_FAULT_INSTRUCTION_64 (SIGSEGV_CONTEXT_REGS->ss_wide.ss_64.ss_pcoq_head & ~3ull)
359	+	#if defined(__LP64__)
360	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_FAULT_INSTRUCTION_64
361	+	#else
362	+	#define SIGSEGV_FAULT_INSTRUCTION ((SIGSEGV_CONTEXT_REGS->ss_flags & SS_WIDEREGS) ? \
363	+	(uint32_t)SIGSEGV_FAULT_INSTRUCTION_64 : \
364	+	SIGSEGV_FAULT_INSTRUCTION_32)
365	+	#endif
366	+	#endif
367	+	#if (defined(__ia64) \|\| defined(__ia64__))
368	+	#include <sys/ucontext.h>
369	+	#define SIGSEGV_CONTEXT_REGS ((ucontext_t *)scp)
370	+	#define SIGSEGV_FAULT_INSTRUCTION get_fault_instruction(SIGSEGV_CONTEXT_REGS)
371	+	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
372	+	#define SIGSEGV_SKIP_INSTRUCTION ia64_skip_instruction
373	+
374	+	#include <sys/uc_access.h>
375	+	static inline sigsegv_address_t get_fault_instruction(const ucontext_t *ucp)
376	+	{
377	+	uint64_t ip;
378	+	if (__uc_get_ip(ucp, &ip) != 0)
379	+	return SIGSEGV_INVALID_ADDRESS;
380	+	return (sigsegv_address_t)(ip & ~3ULL);
381	+	}
382	+	#endif
383	+	#endif
384		#endif
385
386		#if HAVE_SIGCONTEXT_SUBTERFUGE
#	Line 351 \| Line 394 \| static void powerpc_decode_instruction(i
394		#define SIGSEGV_FAULT_HANDLER_ARGS &scs
395		#define SIGSEGV_FAULT_ADDRESS scp->cr2
396		#define SIGSEGV_FAULT_INSTRUCTION scp->eip
397	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)scp
397	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)scp
398		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
399		#endif
400		#if (defined(sparc) \|\| defined(__sparc__))
#	Line 472 \| Line 515 \| static sigsegv_address_t get_fault_addre
515		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr
516		#define SIGSEGV_FAULT_ADDRESS addr
517		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_eip
518	<	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi)
518	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&scp->sc_edi)
519		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
520		#endif
521		#if (defined(alpha) \|\| defined(__alpha__))
#	Line 539 \| Line 582 \| static sigsegv_address_t get_fault_addre
582		#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo
583		#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
584		#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord
585	+	#if defined(_M_IX86)
586		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip
587	<	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
587	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi)
588	>	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
589	>	#endif
590	>	#if defined(_M_X64)
591	>	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Rip
592	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax)
593		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
594		#endif
595	+	#if defined(_M_IA64)
596	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->StIIP
597	+	#endif
598	+	#endif
599
600		#if HAVE_MACH_EXCEPTIONS
601
#	Line 605 \| Line 658 \| if (ret != KERN_SUCCESS) { \
658		}
659
660		#ifdef __ppc__
661	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE
662	+	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
663	+	#endif
664		#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state_t
665		#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE
666		#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE_COUNT
667	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.dar
667	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar)
668		#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t
669		#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE
670		#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT
671	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.srr0
671	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0)
672		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
673	<	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.srr0, (unsigned long )&SIP->thr_state.r0
673	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(r0)
674		#endif
675		#ifdef __ppc64__
676	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64
677	+	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
678	+	#endif
679		#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state64_t
680		#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE64
681		#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE64_COUNT
682	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.dar
682	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar)
683		#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state64_t
684		#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE64
685		#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE64_COUNT
686	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.srr0
686	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0)
687		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
688	<	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.srr0, (unsigned long )&SIP->thr_state.r0
688	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(r0)
689		#endif
690		#ifdef __i386__
691	<	#define SIGSEGV_EXCEPTION_STATE_TYPE struct i386_exception_state
691	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32
692	>	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
693	>	#endif
694	>	#define SIGSEGV_EXCEPTION_STATE_TYPE i386_exception_state_t
695		#define SIGSEGV_EXCEPTION_STATE_FLAVOR i386_EXCEPTION_STATE
696		#define SIGSEGV_EXCEPTION_STATE_COUNT i386_EXCEPTION_STATE_COUNT
697	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.faultvaddr
698	<	#define SIGSEGV_THREAD_STATE_TYPE struct i386_thread_state
697	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
698	>	#define SIGSEGV_THREAD_STATE_TYPE i386_thread_state_t
699		#define SIGSEGV_THREAD_STATE_FLAVOR i386_THREAD_STATE
700		#define SIGSEGV_THREAD_STATE_COUNT i386_THREAD_STATE_COUNT
701	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.eip
701	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(eip)
702		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
703	<	#define SIGSEGV_REGISTER_FILE ((unsigned long )&SIP->thr_state.eax) / EAX is the first GPR we consider */
703	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.MACH_FIELD_NAME(eax)) / EAX is the first GPR we consider */
704		#endif
705		#ifdef __x86_64__
706	<	#define SIGSEGV_EXCEPTION_STATE_TYPE struct x86_exception_state64
706	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64
707	>	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
708	>	#endif
709	>	#define SIGSEGV_EXCEPTION_STATE_TYPE x86_exception_state64_t
710		#define SIGSEGV_EXCEPTION_STATE_FLAVOR x86_EXCEPTION_STATE64
711		#define SIGSEGV_EXCEPTION_STATE_COUNT x86_EXCEPTION_STATE64_COUNT
712	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.faultvaddr
713	<	#define SIGSEGV_THREAD_STATE_TYPE struct x86_thread_state64
712	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
713	>	#define SIGSEGV_THREAD_STATE_TYPE x86_thread_state64_t
714		#define SIGSEGV_THREAD_STATE_FLAVOR x86_THREAD_STATE64
715		#define SIGSEGV_THREAD_STATE_COUNT x86_THREAD_STATE64_COUNT
716	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.rip
716	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(rip)
717		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
718	<	#define SIGSEGV_REGISTER_FILE ((unsigned long )&SIP->thr_state.rax) / RAX is the first GPR we consider */
718	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.MACH_FIELD_NAME(rax)) / RAX is the first GPR we consider */
719		#endif
720		#define SIGSEGV_FAULT_ADDRESS_FAST code[1]
721		#define SIGSEGV_FAULT_INSTRUCTION_FAST SIGSEGV_INVALID_ADDRESS
722		#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code
723		#define SIGSEGV_FAULT_HANDLER_ARGS thread, code
724
725	+	#ifndef MACH_FIELD_NAME
726	+	#define MACH_FIELD_NAME(X) X
727	+	#endif
728	+
729		// Since there can only be one exception thread running at any time
730		// this is not a problem.
731		#define MSG_SIZE 512
#	Line 708 \| Line 777 \| *handleExceptions(void priv)**
777		* Instruction skipping
778		*/
779
780	+	#ifndef SIGSEGV_REGISTER_TYPE
781	+	#define SIGSEGV_REGISTER_TYPE sigsegv_uintptr_t
782	+	#endif
783	+
784		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
785		// Decode and skip X86 instruction
786	<	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
786	>	#if (defined(i386) \|\| defined(__i386__)) \|\| (defined(__x86_64__) \|\| defined(_M_X64))
787		#if defined(__linux__)
788		enum {
789		#if (defined(i386) \|\| defined(__i386__))
#	Line 861 \| Line 934 \| enum {
934		#endif
935		#if defined(_WIN32)
936		enum {
937	<	#if (defined(i386) \|\| defined(__i386__))
937	>	#if defined(_M_IX86)
938		X86_REG_EIP = 7,
939		X86_REG_EAX = 5,
940		X86_REG_ECX = 4,
#	Line 872 \| Line 945 \| enum {
945		X86_REG_ESI = 1,
946		X86_REG_EDI = 0
947		#endif
948	+	#if defined(_M_X64)
949	+	X86_REG_EAX = 0,
950	+	X86_REG_ECX = 1,
951	+	X86_REG_EDX = 2,
952	+	X86_REG_EBX = 3,
953	+	X86_REG_ESP = 4,
954	+	X86_REG_EBP = 5,
955	+	X86_REG_ESI = 6,
956	+	X86_REG_EDI = 7,
957	+	X86_REG_R8 = 8,
958	+	X86_REG_R9 = 9,
959	+	X86_REG_R10 = 10,
960	+	X86_REG_R11 = 11,
961	+	X86_REG_R12 = 12,
962	+	X86_REG_R13 = 13,
963	+	X86_REG_R14 = 14,
964	+	X86_REG_R15 = 15,
965	+	X86_REG_EIP = 16
966	+	#endif
967		};
968		#endif
969		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 908 \| Line 1000 \| static inline int ix86_step_over_modrm(u
1000		return offset;
1001		}
1002
1003	<	static bool ix86_skip_instruction(unsigned long * regs)
1003	>	static bool ix86_skip_instruction(SIGSEGV_REGISTER_TYPE * regs)
1004		{
1005		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
1006
#	Line 944 \| Line 1036 \| static bool ix86_skip_instruction(unsign
1036		}
1037
1038		// REX prefix
1039	<	#if defined(__x86_64__)
1039	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1040		struct rex_t {
1041		unsigned char W;
1042		unsigned char R;
#	Line 996 \| Line 1088 \| static bool ix86_skip_instruction(unsign
1088		goto do_transfer_load;
1089		}
1090		break;
1091	<	#if defined(__x86_64__)
1091	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1092		case 0x63: // MOVSXD r64, r/m32
1093		if (has_rex && rex.W) {
1094		transfer_size = SIZE_LONG;
#	Line 1067 \| Line 1159 \| static bool ix86_skip_instruction(unsign
1159		return false;
1160		}
1161
1162	<	#if defined(__x86_64__)
1162	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1163		if (rex.R)
1164		reg += 8;
1165		#endif
#	Line 1076 \| Line 1168 \| static bool ix86_skip_instruction(unsign
1168		static const int x86_reg_map[] = {
1169		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
1170		X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
1171	<	#if defined(__x86_64__)
1171	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1172		X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
1173		X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
1174		#endif
#	Line 1164 \| Line 1256 \| static bool ix86_skip_instruction(unsign
1256		#endif
1257
1258		// Decode and skip IA-64 instruction
1259	<	#if defined(__ia64__)
1259	>	#if defined(__ia64) \|\| defined(__ia64__)
1260	>	typedef uint64_t ia64_bundle_t[2];
1261		#if defined(__linux__)
1262	<	// XXX: we assume everything is 8-byte aligned
1263	<	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
1264	<	#define IREG(REG) ((OREG(REG) - OREG(flags)) / 8)
1265	<	enum {
1266	<	IA64_REG_IP = IREG(ip),
1267	<	IA64_REG_NAT = IREG(nat),
1268	<	IA64_REG_PR = IREG(pr),
1269	<	IA64_REG_GR = IREG(gr)
1270	<	};
1271	<	#undef IREG
1272	<	#undef OREG
1262	>	// We can directly patch the slot number
1263	>	#define IA64_CAN_PATCH_IP_SLOT 1
1264	>	// Helper macros to access the machine context
1265	>	#define IA64_CONTEXT_TYPE struct sigcontext *
1266	>	#define IA64_CONTEXT scp
1267	>	#define IA64_GET_IP() (IA64_CONTEXT->sc_ip)
1268	>	#define IA64_SET_IP(V) (IA64_CONTEXT->sc_ip = (V))
1269	>	#define IA64_GET_PR(P) ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1270	>	#define IA64_GET_NAT(I) ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1271	>	#define IA64_GET_GR(R) (IA64_CONTEXT->sc_gr[(R)])
1272	>	#define _IA64_SET_GR(R,V) (IA64_CONTEXT->sc_gr[(R)] = (V))
1273	>	#define _IA64_SET_NAT(I,V) (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) \| (((uint64_t)!!(V)) << (I)))
1274	>	#define IA64_SET_GR(R,V,N) (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N))
1275	>
1276	>	// Load bundle (in little-endian)
1277	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1278	>	{
1279	>	uint64_t ip = (uint64_t )(raw_ip & ~3ull);
1280	>	bundle[0] = ip[0];
1281	>	bundle[1] = ip[1];
1282	>	}
1283	>	#endif
1284	>	#if defined(__hpux) \|\| defined(__hpux__)
1285	>	// We can directly patch the slot number
1286	>	#define IA64_CAN_PATCH_IP_SLOT 1
1287	>	// Helper macros to access the machine context
1288	>	#define IA64_CONTEXT_TYPE ucontext_t *
1289	>	#define IA64_CONTEXT ucp
1290	>	#define IA64_GET_IP() ia64_get_ip(IA64_CONTEXT)
1291	>	#define IA64_SET_IP(V) ia64_set_ip(IA64_CONTEXT, V)
1292	>	#define IA64_GET_PR(P) ia64_get_pr(IA64_CONTEXT, P)
1293	>	#define IA64_GET_NAT(I) ia64_get_nat(IA64_CONTEXT, I)
1294	>	#define IA64_GET_GR(R) ia64_get_gr(IA64_CONTEXT, R)
1295	>	#define IA64_SET_GR(R,V,N) ia64_set_gr(IA64_CONTEXT, R, V, N)
1296	>	#define UC_ACCESS(FUNC,ARGS) do { if (__uc_##FUNC ARGS != 0) abort(); } while (0)
1297	>
1298	>	static inline uint64_t ia64_get_ip(IA64_CONTEXT_TYPE IA64_CONTEXT)
1299	>	{ uint64_t v; UC_ACCESS(get_ip,(IA64_CONTEXT, &v)); return v; }
1300	>	static inline void ia64_set_ip(IA64_CONTEXT_TYPE IA64_CONTEXT, uint64_t v)
1301	>	{ UC_ACCESS(set_ip,(IA64_CONTEXT, v)); }
1302	>	static inline unsigned int ia64_get_pr(IA64_CONTEXT_TYPE IA64_CONTEXT, int pr)
1303	>	{ uint64_t v; UC_ACCESS(get_prs,(IA64_CONTEXT, &v)); return (v >> pr) & 1; }
1304	>	static inline unsigned int ia64_get_nat(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1305	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return (nat >> r) & 1; }
1306	>	static inline uint64_t ia64_get_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1307	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return v; }
1308	>
1309	>	static void ia64_set_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r, uint64_t v, unsigned int nat)
1310	>	{
1311	>	if (r == 0)
1312	>	return;
1313	>	if (r > 0 && r < 32)
1314	>	UC_ACCESS(set_grs,(IA64_CONTEXT, r, 1, &v, (!!nat) << r));
1315	>	else {
1316	>	uint64_t bsp, bspstore;
1317	>	UC_ACCESS(get_ar_bsp,(IA64_CONTEXT, &bsp));
1318	>	UC_ACCESS(get_ar_bspstore,(IA64_CONTEXT, &bspstore));
1319	>	abort(); /* XXX: use libunwind, this is not fun... */
1320	>	}
1321	>	}
1322	>
1323	>	// Byte-swapping
1324	>	#if defined(__GNUC__)
1325	>	#define BSWAP64(V) ({ uint64_t r; __asm__ __volatile__("mux1 %0=%1,@rev;;" : "=r" (r) : "r" (V)); r; })
1326	>	#elif defined (__HP_aCC)
1327	>	#define BSWAP64(V) _Asm_mux1(_MBTYPE_REV, V)
1328	>	#else
1329	>	#error "Define byte-swap instruction"
1330		#endif
1331
1332	<	// Helper macros to access the machine context
1333	<	#define IA64_CONTEXT (ctx)
1334	<	#define IA64_GET_PR(P) ((IA64_CONTEXT[IA64_REG_PR] >> (P)) & 1)
1335	<	#define IA64_GET_NAT(I) ((IA64_CONTEXT[IA64_REG_NAT] >> (I)) & 1)
1336	<	#define IA64_SET_NAT(I,V) (IA64_CONTEXT[IA64_REG_NAT] = (IA64_CONTEXT[IA64_REG_NAT] & ~(1ul << (I))) \| (((unsigned long)!!(V)) << (I)))
1337	<	#define IA64_GET_GR(R) (IA64_CONTEXT[IA64_REG_GR + (R)])
1338	<	#define IA64_SET_GR(R,V) (IA64_CONTEXT[IA64_REG_GR + (R)] = (V))
1332	>	// Load bundle (in little-endian)
1333	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1334	>	{
1335	>	uint64_t ip = (uint64_t )(raw_ip & ~3ull);
1336	>	bundle[0] = BSWAP64(ip[0]);
1337	>	bundle[1] = BSWAP64(ip[1]);
1338	>	}
1339	>	#endif
1340
1341		// Instruction operations
1342		enum {
#	Line 1226 \| Line 1377 \| const int IA64_N_OPERANDS = 4;
1377
1378		// Decoded operand type
1379		struct ia64_operand_t {
1380	<	unsigned char commit; // commit result of operation to register file?
1381	<	unsigned char valid; // XXX: not really used, can be removed (debug)
1382	<	signed char index; // index of GPR, or -1 if immediate value
1383	<	unsigned char nat; // NaT state before operation
1384	<	unsigned long value; // register contents or immediate value
1380	>	uint8_t commit; // commit result of operation to register file?
1381	>	uint8_t valid; // XXX: not really used, can be removed (debug)
1382	>	int8_t index; // index of GPR, or -1 if immediate value
1383	>	uint8_t nat; // NaT state before operation
1384	>	uint64_t value; // register contents or immediate value
1385		};
1386
1387		// Decoded instruction type
1388		struct ia64_instruction_t {
1389	<	unsigned char mnemo; // operation to perform
1390	<	unsigned char pred; // predicate register to check
1391	<	unsigned char no_memory; // used to emulated main fault instruction
1392	<	unsigned long inst; // the raw instruction bits (41-bit wide)
1389	>	uint8_t mnemo; // operation to perform
1390	>	uint8_t pred; // predicate register to check
1391	>	uint8_t no_memory; // used to emulated main fault instruction
1392	>	uint64_t inst; // the raw instruction bits (41-bit wide)
1393		ia64_operand_t operands[IA64_N_OPERANDS];
1394		};
1395
1396		// Get immediate sign-bit
1397	<	static inline int ia64_inst_get_sbit(unsigned long inst)
1397	>	static inline int ia64_inst_get_sbit(uint64_t inst)
1398		{
1399		return (inst >> 36) & 1;
1400		}
1401
1402		// Get 8-bit immediate value (A3, A8, I27, M30)
1403	<	static inline unsigned long ia64_inst_get_imm8(unsigned long inst)
1403	>	static inline uint64_t ia64_inst_get_imm8(uint64_t inst)
1404		{
1405	<	unsigned long value = (inst >> 13) & 0x7ful;
1405	>	uint64_t value = (inst >> 13) & 0x7full;
1406		if (ia64_inst_get_sbit(inst))
1407	<	value \|= ~0x7ful;
1407	>	value \|= ~0x7full;
1408		return value;
1409		}
1410
1411		// Get 9-bit immediate value (M3)
1412	<	static inline unsigned long ia64_inst_get_imm9b(unsigned long inst)
1412	>	static inline uint64_t ia64_inst_get_imm9b(uint64_t inst)
1413		{
1414	<	unsigned long value = (((inst >> 27) & 1) << 7) \| ((inst >> 13) & 0x7f);
1414	>	uint64_t value = (((inst >> 27) & 1) << 7) \| ((inst >> 13) & 0x7f);
1415		if (ia64_inst_get_sbit(inst))
1416	<	value \|= ~0xfful;
1416	>	value \|= ~0xffull;
1417		return value;
1418		}
1419
1420		// Get 9-bit immediate value (M5)
1421	<	static inline unsigned long ia64_inst_get_imm9a(unsigned long inst)
1421	>	static inline uint64_t ia64_inst_get_imm9a(uint64_t inst)
1422		{
1423	<	unsigned long value = (((inst >> 27) & 1) << 7) \| ((inst >> 6) & 0x7f);
1423	>	uint64_t value = (((inst >> 27) & 1) << 7) \| ((inst >> 6) & 0x7f);
1424		if (ia64_inst_get_sbit(inst))
1425	<	value \|= ~0xfful;
1425	>	value \|= ~0xffull;
1426		return value;
1427		}
1428
1429		// Get 14-bit immediate value (A4)
1430	<	static inline unsigned long ia64_inst_get_imm14(unsigned long inst)
1430	>	static inline uint64_t ia64_inst_get_imm14(uint64_t inst)
1431		{
1432	<	unsigned long value = (((inst >> 27) & 0x3f) << 7) \| (inst & 0x7f);
1432	>	uint64_t value = (((inst >> 27) & 0x3f) << 7) \| (inst & 0x7f);
1433		if (ia64_inst_get_sbit(inst))
1434	<	value \|= ~0x1fful;
1434	>	value \|= ~0x1ffull;
1435		return value;
1436		}
1437
1438		// Get 22-bit immediate value (A5)
1439	<	static inline unsigned long ia64_inst_get_imm22(unsigned long inst)
1439	>	static inline uint64_t ia64_inst_get_imm22(uint64_t inst)
1440		{
1441	<	unsigned long value = ((((inst >> 22) & 0x1f) << 16) \|
1442	<	(((inst >> 27) & 0x1ff) << 7) \|
1443	<	(inst & 0x7f));
1441	>	uint64_t value = ((((inst >> 22) & 0x1f) << 16) \|
1442	>	(((inst >> 27) & 0x1ff) << 7) \|
1443	>	(inst & 0x7f));
1444		if (ia64_inst_get_sbit(inst))
1445	<	value \|= ~0x1ffffful;
1445	>	value \|= ~0x1fffffull;
1446		return value;
1447		}
1448
1449		// Get 21-bit immediate value (I19)
1450	<	static inline unsigned long ia64_inst_get_imm21(unsigned long inst)
1450	>	static inline uint64_t ia64_inst_get_imm21(uint64_t inst)
1451		{
1452		return (((inst >> 36) & 1) << 20) \| ((inst >> 6) & 0xfffff);
1453		}
1454
1455		// Get 2-bit count value (A2)
1456	<	static inline int ia64_inst_get_count2(unsigned long inst)
1456	>	static inline int ia64_inst_get_count2(uint64_t inst)
1457		{
1458		return (inst >> 27) & 0x3;
1459		}
1460
1461		// Get bundle template
1462	<	static inline unsigned int ia64_get_template(unsigned long raw_ip)
1462	>	static inline unsigned int ia64_get_template(uint64_t ip)
1463		{
1464	<	unsigned long ip = (unsigned long )(raw_ip & ~3ul);
1465	<	return ip[0] & 0x1f;
1464	>	ia64_bundle_t bundle;
1465	>	ia64_load_bundle(bundle, ip);
1466	>	return bundle[0] & 0x1f;
1467		}
1468
1469		// Get specified instruction in bundle
1470	<	static unsigned long ia64_get_instruction(unsigned long raw_ip, int slot)
1470	>	static uint64_t ia64_get_instruction(uint64_t ip, int slot)
1471		{
1472	<	unsigned long inst;
1473	<	unsigned long ip = (unsigned long )(raw_ip & ~3ul);
1472	>	uint64_t inst;
1473	>	ia64_bundle_t bundle;
1474	>	ia64_load_bundle(bundle, ip);
1475		#if DEBUG
1476	<	printf("Bundle: %016lx%016lx\n", ip[1], ip[0]);
1476	>	printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]);
1477		#endif
1478
1479		switch (slot) {
1480		case 0:
1481	<	inst = (ip[0] >> 5) & 0x1fffffffffful;
1481	>	inst = (bundle[0] >> 5) & 0x1ffffffffffull;
1482		break;
1483		case 1:
1484	<	inst = ((ip[1] & 0x7ffffful) << 18) \| ((ip[0] >> 46) & 0x3fffful);
1484	>	inst = ((bundle[1] & 0x7fffffull) << 18) \| ((bundle[0] >> 46) & 0x3ffffull);
1485		break;
1486		case 2:
1487	<	inst = (ip[1] >> 23) & 0x1fffffffffful;
1487	>	inst = (bundle[1] >> 23) & 0x1ffffffffffull;
1488		break;
1489		case 3:
1490		fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
#	Line 1340 \| Line 1493 \| static unsigned long ia64_get_instructio
1493		}
1494
1495		#if DEBUG
1496	<	printf(" Instruction %d: 0x%016lx\n", slot, inst);
1496	>	printf(" Instruction %d: 0x%016llx\n", slot, inst);
1497		#endif
1498		return inst;
1499		}
1500
1501		// Decode group 0 instructions
1502	<	static bool ia64_decode_instruction_0(ia64_instruction_t inst, unsigned long ctx)
1502	>	static bool ia64_decode_instruction_0(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1503		{
1504		const int r1 = (inst->inst >> 6) & 0x7f;
1505		const int r3 = (inst->inst >> 20) & 0x7f;
#	Line 1392 \| Line 1545 \| static bool ia64_decode_instruction_0(ia
1545		}
1546
1547		// Decode group 4 instructions (load/store instructions)
1548	<	static bool ia64_decode_instruction_4(ia64_instruction_t inst, unsigned long ctx)
1548	>	static bool ia64_decode_instruction_4(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1549		{
1550		const int r1 = (inst->inst >> 6) & 0x7f;
1551		const int r2 = (inst->inst >> 13) & 0x7f;
#	Line 1464 \| Line 1617 \| static bool ia64_decode_instruction_4(ia
1617		}
1618
1619		// Decode group 5 instructions (load/store instructions)
1620	<	static bool ia64_decode_instruction_5(ia64_instruction_t inst, unsigned long ctx)
1620	>	static bool ia64_decode_instruction_5(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1621		{
1622		const int r1 = (inst->inst >> 6) & 0x7f;
1623		const int r2 = (inst->inst >> 13) & 0x7f;
#	Line 1522 \| Line 1675 \| static bool ia64_decode_instruction_5(ia
1675		}
1676
1677		// Decode group 8 instructions (ALU integer)
1678	<	static bool ia64_decode_instruction_8(ia64_instruction_t inst, unsigned long ctx)
1678	>	static bool ia64_decode_instruction_8(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1679		{
1680		const int r1 = (inst->inst >> 6) & 0x7f;
1681		const int r2 = (inst->inst >> 13) & 0x7f;
#	Line 1595 \| Line 1748 \| static bool ia64_decode_instruction_8(ia
1748		}
1749
1750		// Decode instruction
1751	<	static bool ia64_decode_instruction(ia64_instruction_t inst, unsigned long ctx)
1751	>	static bool ia64_decode_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1752		{
1753		const int major = (inst->inst >> 37) & 0xf;
1754
#	Line 1604 \| Line 1757 \| static bool ia64_decode_instruction(ia64
1757		memset(&inst->operands[0], 0, sizeof(inst->operands));
1758
1759		switch (major) {
1760	<	case 0x0: return ia64_decode_instruction_0(inst, ctx);
1761	<	case 0x4: return ia64_decode_instruction_4(inst, ctx);
1762	<	case 0x5: return ia64_decode_instruction_5(inst, ctx);
1763	<	case 0x8: return ia64_decode_instruction_8(inst, ctx);
1760	>	case 0x0: return ia64_decode_instruction_0(inst, IA64_CONTEXT);
1761	>	case 0x4: return ia64_decode_instruction_4(inst, IA64_CONTEXT);
1762	>	case 0x5: return ia64_decode_instruction_5(inst, IA64_CONTEXT);
1763	>	case 0x8: return ia64_decode_instruction_8(inst, IA64_CONTEXT);
1764		}
1765		return false;
1766		}
1767
1768	<	static bool ia64_emulate_instruction(ia64_instruction_t inst, unsigned long ctx)
1768	>	static bool ia64_emulate_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1769		{
1770		// XXX: handle Register NaT Consumption fault?
1771		// XXX: this simple emulator assumes instructions in a bundle
#	Line 1624 \| Line 1777 \| static bool ia64_emulate_instruction(ia6
1777		if (inst->pred && !IA64_GET_PR(inst->pred))
1778		return true;
1779
1780	<	unsigned char nat, nat2;
1781	<	unsigned long dst, dst2, src1, src2, src3;
1780	>	uint8_t nat, nat2;
1781	>	uint64_t dst, dst2, src1, src2, src3;
1782
1783		switch (inst->mnemo) {
1784		case IA64_INST_NOP:
#	Line 1662 \| Line 1815 \| static bool ia64_emulate_instruction(ia6
1815		case IA64_INST_ZXT4:
1816		src1 = inst->operands[1].value;
1817		switch (inst->mnemo) {
1818	<	case IA64_INST_SXT1: dst = (signed long)(signed char)src1; break;
1819	<	case IA64_INST_SXT2: dst = (signed long)(signed short)src1; break;
1820	<	case IA64_INST_SXT4: dst = (signed long)(signed int)src1; break;
1821	<	case IA64_INST_ZXT1: dst = (unsigned char)src1; break;
1822	<	case IA64_INST_ZXT2: dst = (unsigned short)src1; break;
1823	<	case IA64_INST_ZXT4: dst = (unsigned int)src1; break;
1818	>	case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1; break;
1819	>	case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1; break;
1820	>	case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1; break;
1821	>	case IA64_INST_ZXT1: dst = (uint8_t)src1; break;
1822	>	case IA64_INST_ZXT2: dst = (uint16_t)src1; break;
1823	>	case IA64_INST_ZXT4: dst = (uint32_t)src1; break;
1824		}
1825		inst->operands[0].commit = true;
1826		inst->operands[0].value = dst;
#	Line 1690 \| Line 1843 \| static bool ia64_emulate_instruction(ia6
1843		dst = 0;
1844		else {
1845		switch (inst->mnemo) {
1846	<	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = ((unsigned char )src1); break;
1847	<	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = ((unsigned short )src1); break;
1848	<	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = ((unsigned int )src1); break;
1849	<	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = ((unsigned long )src1); break;
1846	>	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = ((uint8_t )src1); break;
1847	>	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = ((uint16_t )src1); break;
1848	>	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = ((uint32_t )src1); break;
1849	>	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = ((uint64_t )src1); break;
1850		}
1851		}
1852		inst->operands[0].commit = true;
#	Line 1718 \| Line 1871 \| static bool ia64_emulate_instruction(ia6
1871		src1 = inst->operands[1].value;
1872		if (!inst->no_memory) {
1873		switch (inst->mnemo) {
1874	<	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: ((unsigned char )dst) = src1; break;
1875	<	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: ((unsigned short )dst) = src1; break;
1876	<	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: ((unsigned int )dst) = src1; break;
1877	<	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: ((unsigned long )dst) = src1; break;
1874	>	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: ((uint8_t )dst) = src1; break;
1875	>	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: ((uint16_t )dst) = src1; break;
1876	>	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: ((uint32_t )dst) = src1; break;
1877	>	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: ((uint64_t )dst) = src1; break;
1878		}
1879		}
1880		inst->operands[0].value = dst2;
#	Line 1737 \| Line 1890 \| static bool ia64_emulate_instruction(ia6
1890		continue;
1891		if (op.index == -1)
1892		return false; // XXX: internal error
1893	<	IA64_SET_GR(op.index, op.value);
1741	<	IA64_SET_NAT(op.index, op.nat);
1893	>	IA64_SET_GR(op.index, op.value, op.nat);
1894		}
1895		return true;
1896		}
1897
1898	<	static bool ia64_emulate_instruction(unsigned long raw_inst, unsigned long *ctx)
1898	>	static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1899		{
1900		ia64_instruction_t inst;
1901		memset(&inst, 0, sizeof(inst));
1902		inst.inst = raw_inst;
1903	<	if (!ia64_decode_instruction(&inst, ctx))
1903	>	if (!ia64_decode_instruction(&inst, IA64_CONTEXT))
1904		return false;
1905	<	return ia64_emulate_instruction(&inst, ctx);
1905	>	return ia64_emulate_instruction(&inst, IA64_CONTEXT);
1906		}
1907
1908	<	static bool ia64_skip_instruction(unsigned long *ctx)
1908	>	static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1909		{
1910	<	unsigned long ip = ctx[IA64_REG_IP];
1910	>	uint64_t ip = IA64_GET_IP();
1911		#if DEBUG
1912	<	printf("IP: 0x%016lx\n", ip);
1912	>	printf("IP: 0x%016llx\n", ip);
1913		#if 0
1914		printf(" Template 0x%02x\n", ia64_get_template(ip));
1915		ia64_get_instruction(ip, 0);
#	Line 1769 \| Line 1921 \| static bool ia64_skip_instruction(unsign
1921		// Select which decode switch to use
1922		ia64_instruction_t inst;
1923		inst.inst = ia64_get_instruction(ip, ip & 3);
1924	<	if (!ia64_decode_instruction(&inst, ctx)) {
1924	>	if (!ia64_decode_instruction(&inst, IA64_CONTEXT)) {
1925		fprintf(stderr, "ERROR: ia64_skip_instruction(): could not decode instruction\n");
1926		return false;
1927		}
#	Line 1840 \| Line 1992 \| static bool ia64_skip_instruction(unsign
1992		}
1993
1994		inst.no_memory = true;
1995	<	if (!ia64_emulate_instruction(&inst, ctx)) {
1995	>	if (!ia64_emulate_instruction(&inst, IA64_CONTEXT)) {
1996		fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate fault instruction\n");
1997		return false;
1998		}
#	Line 1863 \| Line 2015 \| static bool ia64_skip_instruction(unsign
2015		}
2016		break;
2017		}
2018	<	if (emulate_next) {
2018	>	if (emulate_next && !IA64_CAN_PATCH_IP_SLOT) {
2019		while (slot < 3) {
2020	<	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), ctx)) {
2020	>	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), IA64_CONTEXT)) {
2021		fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate instruction\n");
2022		return false;
2023		}
#	Line 1873 \| Line 2025 \| static bool ia64_skip_instruction(unsign
2025		}
2026		}
2027
2028	<	ctx[IA64_REG_IP] = (ip & ~3ul) + 16;
2028	>	#if IA64_CAN_PATCH_IP_SLOT
2029	>	if ((slot = ip & 3) < 2)
2030	>	IA64_SET_IP((ip & ~3ull) + (slot + 1));
2031	>	else
2032	>	#endif
2033	>	IA64_SET_IP((ip & ~3ull) + 16);
2034		#if DEBUG
2035	<	printf("IP: 0x%016lx\n", ctx[IA64_REG_IP]);
2035	>	printf("IP: 0x%016llx\n", IA64_GET_IP());
2036		#endif
2037		return true;
2038		}
#	Line 2439 \| Line 2596 \| sigsegv_address_t sigsegv_get_fault_addr
2596		mach_get_exception_state(SIP);
2597
2598		sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
2599	<	if (use_fast_path < 0)
2600	<	use_fast_path = addr == SIP->addr;
2599	>	if (use_fast_path < 0) {
2600	>	const char *machfault = getenv("SIGSEGV_MACH_FAULT");
2601	>	if (machfault) {
2602	>	if (strcmp(machfault, "fast") == 0)
2603	>	use_fast_path = 1;
2604	>	else if (strcmp(machfault, "slow") == 0)
2605	>	use_fast_path = 0;
2606	>	}
2607	>	if (use_fast_path < 0)
2608	>	use_fast_path = addr == SIP->addr;
2609	>	}
2610		SIP->addr = addr;
2611		}
2612		#endif
#	Line 2817 \| Line 2983 \| static LONG WINAPI main_exception_filter
2983		{
2984		if (sigsegv_fault_handler != NULL
2985		&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
2986	<	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
2986	>	&& ExceptionInfo->ExceptionRecord->NumberParameters >= 2
2987		&& handle_badaccess(ExceptionInfo))
2988		return EXCEPTION_CONTINUE_EXECUTION;
2989
#	Line 2969 \| Line 3135 \| void sigsegv_set_dump_state(sigsegv_stat
3135		const int REF_INDEX = 123;
3136		const int REF_VALUE = 45;
3137
3138	<	static int page_size;
3138	>	static sigsegv_uintptr_t page_size;
3139		static volatile char * page = 0;
3140		static volatile int handler_called = 0;
3141
#	Line 3007 \| Line 3173 \| static sigsegv_return_t sigsegv_test_han
3173		(instruction_address >= (sigsegv_address_t)e_region)))
3174		exit(11);
3175		#endif
3176	<	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ \| VM_PAGE_WRITE) != 0)
3176	>	if (vm_protect((char *)((sigsegv_uintptr_t)fault_address & -page_size), page_size, VM_PAGE_READ \| VM_PAGE_WRITE) != 0)
3177		exit(12);
3178		return SIGSEGV_RETURN_SUCCESS;
3179		}
#	Line 3020 \| Line 3186 \| static sigsegv_return_t sigsegv_insn_han
3186		#if DEBUG
3187		printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
3188		#endif
3189	<	if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
3189	>	if (((sigsegv_uintptr_t)fault_address - (sigsegv_uintptr_t)page) < page_size) {
3190		#ifdef __GNUC__
3191		// Make sure reported fault instruction address falls into
3192		// expected code range
#	Line 3038 \| Line 3204 \| static sigsegv_return_t sigsegv_insn_han
3204		// More sophisticated tests for instruction skipper
3205		static bool arch_insn_skipper_tests()
3206		{
3207	<	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
3207	>	#if (defined(i386) \|\| defined(__i386__)) \|\| (defined(__x86_64__) \|\| defined(_M_X64))
3208		static const unsigned char code[] = {
3209		0x8a, 0x00, // mov (%eax),%al
3210		0x8a, 0x2c, 0x18, // mov (%eax,%ebx,1),%ch
#	Line 3052 \| Line 3218 \| static bool arch_insn_skipper_tests()
3218		0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%ecx
3219		0x89, 0x00, // mov %eax,(%eax)
3220		0x89, 0x0c, 0x18, // mov %ecx,(%eax,%ebx,1)
3221	<	#if defined(__x86_64__)
3221	>	#if defined(__x86_64__) \|\| defined(_M_X64)
3222		0x44, 0x8a, 0x00, // mov (%rax),%r8b
3223		0x44, 0x8a, 0x20, // mov (%rax),%r12b
3224		0x42, 0x8a, 0x3c, 0x10, // mov (%rax,%r10,1),%dil
#	Line 3081 \| Line 3247 \| static bool arch_insn_skipper_tests()
3247		0 // end
3248		};
3249		const int N_REGS = 20;
3250	<	unsigned long regs[N_REGS];
3250	>	SIGSEGV_REGISTER_TYPE regs[N_REGS];
3251		for (int i = 0; i < N_REGS; i++)
3252		regs[i] = i;
3253	<	const unsigned long start_code = (unsigned long)&code;
3253	>	const sigsegv_uintptr_t start_code = (sigsegv_uintptr_t)&code;
3254		regs[X86_REG_EIP] = start_code;
3255		while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
3256		&& ix86_skip_instruction(regs))

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.76 by gbeauche, 2008-01-06T16:36:00Z vs. Revision 1.84 by gbeauche, 2008-01-20T17:09:34Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.76 by gbeauche, 2008-01-06T16:36:00Z vs.
Revision 1.84 by gbeauche, 2008-01-20T17:09:34Z