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root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.73 by gbeauche, 2008-01-06T16:10:30Z vs.
Revision 1.89 by asvitkine, 2009-04-13T23:13:20Z

#	Line 49 | Line 49 | using std::list;
49		#define RETSIGTYPE void
50		#endif
51
52	+	// Size of an unsigned integer large enough to hold all bits of a pointer
53	+	// NOTE: this can be different than SIGSEGV_REGISTER_TYPE. In
54	+	// particular, on ILP32 systems with a 64-bit kernel (HP-UX/ia64?)
55	+	#if defined(HAVE_WIN32_VM)
56	+	// Windows is either ILP32 or LLP64
57	+	#include <BaseTsd.h>
58	+	typedef UINT_PTR sigsegv_uintptr_t;
59	+	#else
60	+	// Other systems are sane enough to follow ILP32 or LP64 models
61	+	typedef unsigned long sigsegv_uintptr_t;
62	+	#endif
63	+
64		// Type of the system signal handler
65		typedef RETSIGTYPE (*signal_handler)(int);
66
#	Line 232 | Line 244 | static void powerpc_decode_instruction(i
244		// Generic extended signal handler
245		#if defined(__FreeBSD__)
246		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
247	+	#elif defined(__hpux)
248	+	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV) FAULT_HANDLER(SIGBUS)
249		#else
250		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
251		#endif
#	Line 264 | Line 278 | static void powerpc_decode_instruction(i
278		#include <sys/regset.h>
279		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
280		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[EIP]
281	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
281	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
282		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
283		#endif
284		#endif
285		#if defined(__FreeBSD__) || defined(__OpenBSD__)
286		#if (defined(i386) || defined(__i386__))
287		#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_eip)
288	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
288	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
289		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
290		#endif
291		#endif
#	Line 280 | Line 294 | static void powerpc_decode_instruction(i
294		#include <sys/ucontext.h>
295		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.__gregs)
296		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[_REG_EIP]
297	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
297	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
298		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
299		#endif
300		#if (defined(powerpc) || defined(__powerpc__))
#	Line 296 | Line 310 | static void powerpc_decode_instruction(i
310		#include <sys/ucontext.h>
311		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
312		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
313	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
313	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
314		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
315		#endif
316		#if (defined(x86_64) || defined(__x86_64__))
317		#include <sys/ucontext.h>
318		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
319		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
320	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
320	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
321		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
322		#endif
323		#if (defined(ia64) || defined(__ia64__))
324	<	#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
324	>	#define SIGSEGV_CONTEXT_REGS                    ((struct sigcontext *)scp)
325	>	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
326	>	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
327	>	#define SIGSEGV_SKIP_INSTRUCTION                ia64_skip_instruction
328		#endif
329		#if (defined(powerpc) || defined(__powerpc__))
330		#include <sys/ucontext.h>
#	Line 335 | Line 352 | static void powerpc_decode_instruction(i
352		#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
353		#endif
354		#endif
355	+	#if (defined(__hpux) || defined(__hpux__))
356	+	#if (defined(__hppa) || defined(__hppa__))
357	+	#define SIGSEGV_CONTEXT_REGS                    (&((ucontext_t *)scp)->uc_mcontext)
358	+	#define SIGSEGV_FAULT_INSTRUCTION_32    (SIGSEGV_CONTEXT_REGS->ss_narrow.ss_pcoq_head & ~3ul)
359	+	#define SIGSEGV_FAULT_INSTRUCTION_64    (SIGSEGV_CONTEXT_REGS->ss_wide.ss_64.ss_pcoq_head & ~3ull)
360	+	#if defined(__LP64__)
361	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_FAULT_INSTRUCTION_64
362	+	#else
363	+	#define SIGSEGV_FAULT_INSTRUCTION               ((SIGSEGV_CONTEXT_REGS->ss_flags & SS_WIDEREGS) ? \
364	+	(uint32_t)SIGSEGV_FAULT_INSTRUCTION_64 : \
365	+	SIGSEGV_FAULT_INSTRUCTION_32)
366	+	#endif
367	+	#endif
368	+	#if (defined(__ia64) || defined(__ia64__))
369	+	#include <sys/ucontext.h>
370	+	#define SIGSEGV_CONTEXT_REGS                    ((ucontext_t *)scp)
371	+	#define SIGSEGV_FAULT_INSTRUCTION               get_fault_instruction(SIGSEGV_CONTEXT_REGS)
372	+	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
373	+	#define SIGSEGV_SKIP_INSTRUCTION                ia64_skip_instruction
374	+
375	+	#include <sys/uc_access.h>
376	+	static inline sigsegv_address_t get_fault_instruction(const ucontext_t *ucp)
377	+	{
378	+	uint64_t ip;
379	+	if (__uc_get_ip(ucp, &ip) != 0)
380	+	return SIGSEGV_INVALID_ADDRESS;
381	+	return (sigsegv_address_t)(ip & ~3ULL);
382	+	}
383	+	#endif
384	+	#endif
385		#endif
386
387		#if HAVE_SIGCONTEXT_SUBTERFUGE
#	Line 348 | Line 395 | static void powerpc_decode_instruction(i
395		#define SIGSEGV_FAULT_HANDLER_ARGS              &scs
396		#define SIGSEGV_FAULT_ADDRESS                   scp->cr2
397		#define SIGSEGV_FAULT_INSTRUCTION               scp->eip
398	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)scp
398	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)scp
399		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
400		#endif
401		#if (defined(sparc) || defined(__sparc__))
#	Line 469 | Line 516 | static sigsegv_address_t get_fault_addre
516		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp, addr
517		#define SIGSEGV_FAULT_ADDRESS                   addr
518		#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_eip
519	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&scp->sc_edi)
519	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&scp->sc_edi)
520		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
521		#endif
522		#if (defined(alpha) || defined(__alpha__))
#	Line 504 | Line 551 | static sigsegv_address_t get_fault_addre
551		#ifndef HAVE_MACH_EXCEPTIONS
552		#if defined(__APPLE__) && defined(__MACH__)
553		#if (defined(ppc) || defined(__ppc__))
554	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
554	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct __darwin_sigcontext *scp
555		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
556		#define SIGSEGV_FAULT_ADDRESS                   get_fault_address(scp)
557	<	#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_ir
557	>	#define SIGSEGV_FAULT_INSTRUCTION               scp->MACH_FIELD_NAME(sc_ir)
558		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
559		#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&scp->sc_ir, &((unsigned int *) scp->sc_regs)[2]
560		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
#	Line 515 | Line 562 | static sigsegv_address_t get_fault_addre
562		// Use decoding scheme from SheepShaver
563		static sigsegv_address_t get_fault_address(struct sigcontext *scp)
564		{
565	<	unsigned int   nip = (unsigned int) scp->sc_ir;
566	<	unsigned int * gpr = &((unsigned int *) scp->sc_regs)[2];
565	>	unsigned int   nip = (unsigned int) scp->MACH_FIELD_NAME(sc_ir);
566	>	unsigned int * gpr = &((unsigned int *) scp->MACH_FIELD_NAME(sc_regs))[2];
567		instruction_t  instr;
568
569	<	powerpc_decode_instruction(&instr, nip, gpr);
569	>	powerpc_decode_instruction(&instr, nip, (long unsigned int*)gpr);
570		return (sigsegv_address_t)instr.addr;
571		}
572		#endif
#	Line 536 | Line 583 | static sigsegv_address_t get_fault_addre
583		#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
584		#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
585		#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
586	+	#if defined(_M_IX86)
587		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Eip
588	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
588	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi)
589	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
590	>	#endif
591	>	#if defined(_M_X64)
592	>	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Rip
593	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax)
594		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
595		#endif
596	+	#if defined(_M_IA64)
597	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->StIIP
598	+	#endif
599	+	#endif
600
601		#if HAVE_MACH_EXCEPTIONS
602
#	Line 561 | Line 618 | extern "C" {
618		#include <mach/mach.h>
619		#include <mach/mach_error.h>
620
621	<	extern boolean_t exc_server(mach_msg_header_t *, mach_msg_header_t *);
622	<	extern kern_return_t catch_exception_raise(mach_port_t, mach_port_t,
623	<	mach_port_t, exception_type_t, exception_data_t, mach_msg_type_number_t);
624	<	extern kern_return_t exception_raise(mach_port_t, mach_port_t, mach_port_t,
625	<	exception_type_t, exception_data_t, mach_msg_type_number_t);
626	<	extern kern_return_t exception_raise_state(mach_port_t, exception_type_t,
627	<	exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
621	>	#ifndef HAVE_MACH64_VM
622	>
623	>	// Undefine this to prevent a preprocessor warning when compiling on a
624	>	// 32-bit machine with Mac OS X 10.5.
625	>	#undef  MACH_EXCEPTION_CODES
626	>
627	>	#define MACH_EXCEPTION_CODES                                    0
628	>	#define mach_exception_data_t                                   exception_data_t
629	>	#define mach_exception_data_type_t                              exception_data_type_t
630	>	#define mach_exc_server                                                 exc_server
631	>	#define catch_mach_exception_raise                              catch_exception_raise
632	>	#define mach_exception_raise                                    exception_raise
633	>	#define mach_exception_raise_state                              exception_raise_state
634	>	#define mach_exception_raise_state_identity             exception_raise_state_identity
635	>	#endif
636	>
637	>	extern boolean_t mach_exc_server(mach_msg_header_t *, mach_msg_header_t *);
638	>	extern kern_return_t catch_mach_exception_raise(mach_port_t, mach_port_t,
639	>	mach_port_t, exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
640	>	extern kern_return_t catch_mach_exception_raise_state(mach_port_t exception_port,
641	>	exception_type_t exception, mach_exception_data_t code, mach_msg_type_number_t code_count,
642	>	int *flavor,
643	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
644	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
645	>	extern kern_return_t catch_mach_exception_raise_state_identity(mach_port_t exception_port,
646	>	mach_port_t thread_port, mach_port_t task_port, exception_type_t exception,
647	>	mach_exception_data_t code, mach_msg_type_number_t code_count,
648	>	int *flavor,
649	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
650	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
651	>	extern kern_return_t mach_exception_raise(mach_port_t, mach_port_t, mach_port_t,
652	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
653	>	extern kern_return_t mach_exception_raise_state(mach_port_t, exception_type_t,
654	>	mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
655		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
656	<	extern kern_return_t exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
657	<	exception_type_t, exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
656	>	extern kern_return_t mach_exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
657	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
658		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
659		}
660
#	Line 601 | Line 685 | if (ret != KERN_SUCCESS) { \
685		exit (1); \
686		}
687
688	<	#ifdef __ppc__
689	<	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state_t
606	<	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE
607	<	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE_COUNT
608	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.dar
609	<	#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state_t
610	<	#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE
611	<	#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE_COUNT
612	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.srr0
613	<	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
614	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.srr0, (unsigned long *)&SIP->thr_state.r0
615	<	#endif
616	<	#ifdef __ppc64__
617	<	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state64_t
618	<	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE64
619	<	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE64_COUNT
620	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.dar
621	<	#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state64_t
622	<	#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE64
623	<	#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE64_COUNT
624	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.srr0
625	<	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
626	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.srr0, (unsigned long *)&SIP->thr_state.r0
627	<	#endif
628	<	#ifdef __i386__
629	<	#define SIGSEGV_EXCEPTION_STATE_TYPE    struct i386_exception_state
630	<	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  i386_EXCEPTION_STATE
631	<	#define SIGSEGV_EXCEPTION_STATE_COUNT   i386_EXCEPTION_STATE_COUNT
632	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.faultvaddr
633	<	#define SIGSEGV_THREAD_STATE_TYPE               struct i386_thread_state
634	<	#define SIGSEGV_THREAD_STATE_FLAVOR             i386_THREAD_STATE
635	<	#define SIGSEGV_THREAD_STATE_COUNT              i386_THREAD_STATE_COUNT
636	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.eip
637	<	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
638	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIP->thr_state.eax) /* EAX is the first GPR we consider */
688	>	#ifndef MACH_FIELD_NAME
689	>	#define MACH_FIELD_NAME(X) X
690		#endif
640	–	#ifdef __x86_64__
641	–	#define SIGSEGV_EXCEPTION_STATE_TYPE    struct x86_exception_state64
642	–	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  x86_EXCEPTION_STATE64
643	–	#define SIGSEGV_EXCEPTION_STATE_COUNT   x86_EXCEPTION_STATE64_COUNT
644	–	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.faultvaddr
645	–	#define SIGSEGV_THREAD_STATE_TYPE               struct x86_thread_state64
646	–	#define SIGSEGV_THREAD_STATE_FLAVOR             x86_THREAD_STATE64
647	–	#define SIGSEGV_THREAD_STATE_COUNT              x86_THREAD_STATE64_COUNT
648	–	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.rip
649	–	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
650	–	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIP->thr_state.rax) /* RAX is the first GPR we consider */
651	–	#endif
652	–	#define SIGSEGV_FAULT_ADDRESS_FAST              code[1]
653	–	#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_INVALID_ADDRESS
654	–	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code
655	–	#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code
691
692		// Since there can only be one exception thread running at any time
693		// this is not a problem.
#	Line 683 | Line 718 | handleExceptions(void *priv)
718		_exceptionPort, 0, MACH_PORT_NULL);
719		MACH_CHECK_ERROR(mach_msg, krc);
720
721	<	if (!exc_server(msg, reply)) {
721	>	if (!mach_exc_server(msg, reply)) {
722		fprintf(stderr, "exc_server hated the message\n");
723		exit(1);
724		}
#	Line 705 | Line 740 | handleExceptions(void *priv)
740		*  Instruction skipping
741		*/
742
743	+	#ifndef SIGSEGV_REGISTER_TYPE
744	+	#define SIGSEGV_REGISTER_TYPE sigsegv_uintptr_t
745	+	#endif
746	+
747		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
748		// Decode and skip X86 instruction
749	<	#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
749	>	#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64))
750		#if defined(__linux__)
751		enum {
752		#if (defined(i386) || defined(__i386__))
#	Line 858 | Line 897 | enum {
897		#endif
898		#if defined(_WIN32)
899		enum {
900	<	#if (defined(i386) || defined(__i386__))
900	>	#if defined(_M_IX86)
901		X86_REG_EIP = 7,
902		X86_REG_EAX = 5,
903		X86_REG_ECX = 4,
#	Line 869 | Line 908 | enum {
908		X86_REG_ESI = 1,
909		X86_REG_EDI = 0
910		#endif
911	+	#if defined(_M_X64)
912	+	X86_REG_EAX = 0,
913	+	X86_REG_ECX = 1,
914	+	X86_REG_EDX = 2,
915	+	X86_REG_EBX = 3,
916	+	X86_REG_ESP = 4,
917	+	X86_REG_EBP = 5,
918	+	X86_REG_ESI = 6,
919	+	X86_REG_EDI = 7,
920	+	X86_REG_R8  = 8,
921	+	X86_REG_R9  = 9,
922	+	X86_REG_R10 = 10,
923	+	X86_REG_R11 = 11,
924	+	X86_REG_R12 = 12,
925	+	X86_REG_R13 = 13,
926	+	X86_REG_R14 = 14,
927	+	X86_REG_R15 = 15,
928	+	X86_REG_EIP = 16
929	+	#endif
930		};
931		#endif
932		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 905 | Line 963 | static inline int ix86_step_over_modrm(u
963		return offset;
964		}
965
966	<	static bool ix86_skip_instruction(unsigned long * regs)
966	>	static bool ix86_skip_instruction(SIGSEGV_REGISTER_TYPE * regs)
967		{
968		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
969
#	Line 941 | Line 999 | static bool ix86_skip_instruction(unsign
999		}
1000
1001		// REX prefix
1002	<	#if defined(__x86_64__)
1002	>	#if defined(__x86_64__) || defined(_M_X64)
1003		struct rex_t {
1004		unsigned char W;
1005		unsigned char R;
#	Line 993 | Line 1051 | static bool ix86_skip_instruction(unsign
1051		goto do_transfer_load;
1052		}
1053		break;
1054	<	#if defined(__x86_64__)
1054	>	#if defined(__x86_64__) || defined(_M_X64)
1055		case 0x63: // MOVSXD r64, r/m32
1056		if (has_rex && rex.W) {
1057		transfer_size = SIZE_LONG;
#	Line 1064 | Line 1122 | static bool ix86_skip_instruction(unsign
1122		return false;
1123		}
1124
1125	<	#if defined(__x86_64__)
1125	>	#if defined(__x86_64__) || defined(_M_X64)
1126		if (rex.R)
1127		reg += 8;
1128		#endif
#	Line 1073 | Line 1131 | static bool ix86_skip_instruction(unsign
1131		static const int x86_reg_map[] = {
1132		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
1133		X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
1134	<	#if defined(__x86_64__)
1134	>	#if defined(__x86_64__) || defined(_M_X64)
1135		X86_REG_R8,  X86_REG_R9,  X86_REG_R10, X86_REG_R11,
1136		X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
1137		#endif
#	Line 1160 | Line 1218 | static bool ix86_skip_instruction(unsign
1218		}
1219		#endif
1220
1221	+	// Decode and skip IA-64 instruction
1222	+	#if defined(__ia64) || defined(__ia64__)
1223	+	typedef uint64_t ia64_bundle_t[2];
1224	+	#if defined(__linux__)
1225	+	// We can directly patch the slot number
1226	+	#define IA64_CAN_PATCH_IP_SLOT  1
1227	+	// Helper macros to access the machine context
1228	+	#define IA64_CONTEXT_TYPE               struct sigcontext *
1229	+	#define IA64_CONTEXT                    scp
1230	+	#define IA64_GET_IP()                   (IA64_CONTEXT->sc_ip)
1231	+	#define IA64_SET_IP(V)                  (IA64_CONTEXT->sc_ip = (V))
1232	+	#define IA64_GET_PR(P)                  ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1233	+	#define IA64_GET_NAT(I)                 ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1234	+	#define IA64_GET_GR(R)                  (IA64_CONTEXT->sc_gr[(R)])
1235	+	#define _IA64_SET_GR(R,V)               (IA64_CONTEXT->sc_gr[(R)] = (V))
1236	+	#define _IA64_SET_NAT(I,V)              (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) | (((uint64_t)!!(V)) << (I)))
1237	+	#define IA64_SET_GR(R,V,N)              (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N))
1238	+
1239	+	// Load bundle (in little-endian)
1240	+	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1241	+	{
1242	+	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1243	+	bundle[0] = ip[0];
1244	+	bundle[1] = ip[1];
1245	+	}
1246	+	#endif
1247	+	#if defined(__hpux) || defined(__hpux__)
1248	+	// We can directly patch the slot number
1249	+	#define IA64_CAN_PATCH_IP_SLOT  1
1250	+	// Helper macros to access the machine context
1251	+	#define IA64_CONTEXT_TYPE               ucontext_t *
1252	+	#define IA64_CONTEXT                    ucp
1253	+	#define IA64_GET_IP()                   ia64_get_ip(IA64_CONTEXT)
1254	+	#define IA64_SET_IP(V)                  ia64_set_ip(IA64_CONTEXT, V)
1255	+	#define IA64_GET_PR(P)                  ia64_get_pr(IA64_CONTEXT, P)
1256	+	#define IA64_GET_NAT(I)                 ia64_get_nat(IA64_CONTEXT, I)
1257	+	#define IA64_GET_GR(R)                  ia64_get_gr(IA64_CONTEXT, R)
1258	+	#define IA64_SET_GR(R,V,N)              ia64_set_gr(IA64_CONTEXT, R, V, N)
1259	+	#define UC_ACCESS(FUNC,ARGS)    do { if (__uc_##FUNC ARGS != 0) abort(); } while (0)
1260	+
1261	+	static inline uint64_t ia64_get_ip(IA64_CONTEXT_TYPE IA64_CONTEXT)
1262	+	{ uint64_t v; UC_ACCESS(get_ip,(IA64_CONTEXT, &v)); return v; }
1263	+	static inline void ia64_set_ip(IA64_CONTEXT_TYPE IA64_CONTEXT, uint64_t v)
1264	+	{ UC_ACCESS(set_ip,(IA64_CONTEXT, v)); }
1265	+	static inline unsigned int ia64_get_pr(IA64_CONTEXT_TYPE IA64_CONTEXT, int pr)
1266	+	{ uint64_t v; UC_ACCESS(get_prs,(IA64_CONTEXT, &v)); return (v >> pr) & 1; }
1267	+	static inline unsigned int ia64_get_nat(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1268	+	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return (nat >> r) & 1; }
1269	+	static inline uint64_t ia64_get_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1270	+	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return v; }
1271	+
1272	+	static void ia64_set_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r, uint64_t v, unsigned int nat)
1273	+	{
1274	+	if (r == 0)
1275	+	return;
1276	+	if (r > 0 && r < 32)
1277	+	UC_ACCESS(set_grs,(IA64_CONTEXT, r, 1, &v, (!!nat) << r));
1278	+	else {
1279	+	uint64_t bsp, bspstore;
1280	+	UC_ACCESS(get_ar_bsp,(IA64_CONTEXT, &bsp));
1281	+	UC_ACCESS(get_ar_bspstore,(IA64_CONTEXT, &bspstore));
1282	+	abort(); /* XXX: use libunwind, this is not fun... */
1283	+	}
1284	+	}
1285	+
1286	+	// Byte-swapping
1287	+	#if defined(__GNUC__)
1288	+	#define BSWAP64(V) ({ uint64_t r; __asm__ __volatile__("mux1 %0=%1,@rev;;" : "=r" (r) : "r" (V)); r; })
1289	+	#elif defined (__HP_aCC)
1290	+	#define BSWAP64(V) _Asm_mux1(_MBTYPE_REV, V)
1291	+	#else
1292	+	#error "Define byte-swap instruction"
1293	+	#endif
1294	+
1295	+	// Load bundle (in little-endian)
1296	+	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1297	+	{
1298	+	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1299	+	bundle[0] = BSWAP64(ip[0]);
1300	+	bundle[1] = BSWAP64(ip[1]);
1301	+	}
1302	+	#endif
1303	+
1304	+	// Instruction operations
1305	+	enum {
1306	+	IA64_INST_UNKNOWN = 0,
1307	+	IA64_INST_LD1,                          // ld1 op0=[op1]
1308	+	IA64_INST_LD1_UPDATE,           // ld1 op0=[op1],op2
1309	+	IA64_INST_LD2,                          // ld2 op0=[op1]
1310	+	IA64_INST_LD2_UPDATE,           // ld2 op0=[op1],op2
1311	+	IA64_INST_LD4,                          // ld4 op0=[op1]
1312	+	IA64_INST_LD4_UPDATE,           // ld4 op0=[op1],op2
1313	+	IA64_INST_LD8,                          // ld8 op0=[op1]
1314	+	IA64_INST_LD8_UPDATE,           // ld8 op0=[op1],op2
1315	+	IA64_INST_ST1,                          // st1 [op0]=op1
1316	+	IA64_INST_ST1_UPDATE,           // st1 [op0]=op1,op2
1317	+	IA64_INST_ST2,                          // st2 [op0]=op1
1318	+	IA64_INST_ST2_UPDATE,           // st2 [op0]=op1,op2
1319	+	IA64_INST_ST4,                          // st4 [op0]=op1
1320	+	IA64_INST_ST4_UPDATE,           // st4 [op0]=op1,op2
1321	+	IA64_INST_ST8,                          // st8 [op0]=op1
1322	+	IA64_INST_ST8_UPDATE,           // st8 [op0]=op1,op2
1323	+	IA64_INST_ADD,                          // add op0=op1,op2,op3
1324	+	IA64_INST_SUB,                          // sub op0=op1,op2,op3
1325	+	IA64_INST_SHLADD,                       // shladd op0=op1,op3,op2
1326	+	IA64_INST_AND,                          // and op0=op1,op2
1327	+	IA64_INST_ANDCM,                        // andcm op0=op1,op2
1328	+	IA64_INST_OR,                           // or op0=op1,op2
1329	+	IA64_INST_XOR,                          // xor op0=op1,op2
1330	+	IA64_INST_SXT1,                         // sxt1 op0=op1
1331	+	IA64_INST_SXT2,                         // sxt2 op0=op1
1332	+	IA64_INST_SXT4,                         // sxt4 op0=op1
1333	+	IA64_INST_ZXT1,                         // zxt1 op0=op1
1334	+	IA64_INST_ZXT2,                         // zxt2 op0=op1
1335	+	IA64_INST_ZXT4,                         // zxt4 op0=op1
1336	+	IA64_INST_NOP                           // nop op0
1337	+	};
1338	+
1339	+	const int IA64_N_OPERANDS = 4;
1340	+
1341	+	// Decoded operand type
1342	+	struct ia64_operand_t {
1343	+	uint8_t commit;                         // commit result of operation to register file?
1344	+	uint8_t valid;                          // XXX: not really used, can be removed (debug)
1345	+	int8_t index;                           // index of GPR, or -1 if immediate value
1346	+	uint8_t nat;                            // NaT state before operation
1347	+	uint64_t value;                         // register contents or immediate value
1348	+	};
1349	+
1350	+	// Decoded instruction type
1351	+	struct ia64_instruction_t {
1352	+	uint8_t mnemo;                          // operation to perform
1353	+	uint8_t pred;                           // predicate register to check
1354	+	uint8_t no_memory;                      // used to emulated main fault instruction
1355	+	uint64_t inst;                          // the raw instruction bits (41-bit wide)
1356	+	ia64_operand_t operands[IA64_N_OPERANDS];
1357	+	};
1358	+
1359	+	// Get immediate sign-bit
1360	+	static inline int ia64_inst_get_sbit(uint64_t inst)
1361	+	{
1362	+	return (inst >> 36) & 1;
1363	+	}
1364	+
1365	+	// Get 8-bit immediate value (A3, A8, I27, M30)
1366	+	static inline uint64_t ia64_inst_get_imm8(uint64_t inst)
1367	+	{
1368	+	uint64_t value = (inst >> 13) & 0x7full;
1369	+	if (ia64_inst_get_sbit(inst))
1370	+	value |= ~0x7full;
1371	+	return value;
1372	+	}
1373	+
1374	+	// Get 9-bit immediate value (M3)
1375	+	static inline uint64_t ia64_inst_get_imm9b(uint64_t inst)
1376	+	{
1377	+	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f);
1378	+	if (ia64_inst_get_sbit(inst))
1379	+	value |= ~0xffull;
1380	+	return value;
1381	+	}
1382	+
1383	+	// Get 9-bit immediate value (M5)
1384	+	static inline uint64_t ia64_inst_get_imm9a(uint64_t inst)
1385	+	{
1386	+	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f);
1387	+	if (ia64_inst_get_sbit(inst))
1388	+	value |= ~0xffull;
1389	+	return value;
1390	+	}
1391	+
1392	+	// Get 14-bit immediate value (A4)
1393	+	static inline uint64_t ia64_inst_get_imm14(uint64_t inst)
1394	+	{
1395	+	uint64_t value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f);
1396	+	if (ia64_inst_get_sbit(inst))
1397	+	value |= ~0x1ffull;
1398	+	return value;
1399	+	}
1400	+
1401	+	// Get 22-bit immediate value (A5)
1402	+	static inline uint64_t ia64_inst_get_imm22(uint64_t inst)
1403	+	{
1404	+	uint64_t value = ((((inst >> 22) & 0x1f) << 16) |
1405	+	(((inst >> 27) & 0x1ff) << 7) |
1406	+	(inst & 0x7f));
1407	+	if (ia64_inst_get_sbit(inst))
1408	+	value |= ~0x1fffffull;
1409	+	return value;
1410	+	}
1411	+
1412	+	// Get 21-bit immediate value (I19)
1413	+	static inline uint64_t ia64_inst_get_imm21(uint64_t inst)
1414	+	{
1415	+	return (((inst >> 36) & 1) << 20) | ((inst >> 6) & 0xfffff);
1416	+	}
1417	+
1418	+	// Get 2-bit count value (A2)
1419	+	static inline int ia64_inst_get_count2(uint64_t inst)
1420	+	{
1421	+	return (inst >> 27) & 0x3;
1422	+	}
1423	+
1424	+	// Get bundle template
1425	+	static inline unsigned int ia64_get_template(uint64_t ip)
1426	+	{
1427	+	ia64_bundle_t bundle;
1428	+	ia64_load_bundle(bundle, ip);
1429	+	return bundle[0] & 0x1f;
1430	+	}
1431	+
1432	+	// Get specified instruction in bundle
1433	+	static uint64_t ia64_get_instruction(uint64_t ip, int slot)
1434	+	{
1435	+	uint64_t inst;
1436	+	ia64_bundle_t bundle;
1437	+	ia64_load_bundle(bundle, ip);
1438	+	#if DEBUG
1439	+	printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]);
1440	+	#endif
1441	+
1442	+	switch (slot) {
1443	+	case 0:
1444	+	inst = (bundle[0] >> 5) & 0x1ffffffffffull;
1445	+	break;
1446	+	case 1:
1447	+	inst = ((bundle[1] & 0x7fffffull) << 18) | ((bundle[0] >> 46) & 0x3ffffull);
1448	+	break;
1449	+	case 2:
1450	+	inst = (bundle[1] >> 23) & 0x1ffffffffffull;
1451	+	break;
1452	+	case 3:
1453	+	fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
1454	+	abort();
1455	+	break;
1456	+	}
1457	+
1458	+	#if DEBUG
1459	+	printf(" Instruction %d: 0x%016llx\n", slot, inst);
1460	+	#endif
1461	+	return inst;
1462	+	}
1463	+
1464	+	// Decode group 0 instructions
1465	+	static bool ia64_decode_instruction_0(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1466	+	{
1467	+	const int r1 = (inst->inst >>  6) & 0x7f;
1468	+	const int r3 = (inst->inst >> 20) & 0x7f;
1469	+
1470	+	const int x3 = (inst->inst >> 33) & 0x07;
1471	+	const int x6 = (inst->inst >> 27) & 0x3f;
1472	+	const int x2 = (inst->inst >> 31) & 0x03;
1473	+	const int x4 = (inst->inst >> 27) & 0x0f;
1474	+
1475	+	if (x3 == 0) {
1476	+	switch (x6) {
1477	+	case 0x01:                                              // nop.i (I19)
1478	+	inst->mnemo = IA64_INST_NOP;
1479	+	inst->operands[0].valid = true;
1480	+	inst->operands[0].index = -1;
1481	+	inst->operands[0].value = ia64_inst_get_imm21(inst->inst);
1482	+	return true;
1483	+	case 0x14:                                              // sxt1 (I29)
1484	+	case 0x15:                                              // sxt2 (I29)
1485	+	case 0x16:                                              // sxt4 (I29)
1486	+	case 0x10:                                              // zxt1 (I29)
1487	+	case 0x11:                                              // zxt2 (I29)
1488	+	case 0x12:                                              // zxt4 (I29)
1489	+	switch (x6) {
1490	+	case 0x14: inst->mnemo = IA64_INST_SXT1; break;
1491	+	case 0x15: inst->mnemo = IA64_INST_SXT2; break;
1492	+	case 0x16: inst->mnemo = IA64_INST_SXT4; break;
1493	+	case 0x10: inst->mnemo = IA64_INST_ZXT1; break;
1494	+	case 0x11: inst->mnemo = IA64_INST_ZXT2; break;
1495	+	case 0x12: inst->mnemo = IA64_INST_ZXT4; break;
1496	+	default: abort();
1497	+	}
1498	+	inst->operands[0].valid = true;
1499	+	inst->operands[0].index = r1;
1500	+	inst->operands[1].valid = true;
1501	+	inst->operands[1].index = r3;
1502	+	inst->operands[1].value = IA64_GET_GR(r3);
1503	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1504	+	return true;
1505	+	}
1506	+	}
1507	+	return false;
1508	+	}
1509	+
1510	+	// Decode group 4 instructions (load/store instructions)
1511	+	static bool ia64_decode_instruction_4(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1512	+	{
1513	+	const int r1 = (inst->inst >> 6) & 0x7f;
1514	+	const int r2 = (inst->inst >> 13) & 0x7f;
1515	+	const int r3 = (inst->inst >> 20) & 0x7f;
1516	+
1517	+	const int m  = (inst->inst >> 36) & 1;
1518	+	const int x  = (inst->inst >> 27) & 1;
1519	+	const int x6 = (inst->inst >> 30) & 0x3f;
1520	+
1521	+	switch (x6) {
1522	+	case 0x00:
1523	+	case 0x01:
1524	+	case 0x02:
1525	+	case 0x03:
1526	+	if (x == 0) {
1527	+	inst->operands[0].valid = true;
1528	+	inst->operands[0].index = r1;
1529	+	inst->operands[1].valid = true;
1530	+	inst->operands[1].index = r3;
1531	+	inst->operands[1].value = IA64_GET_GR(r3);
1532	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1533	+	if (m == 0) {
1534	+	switch (x6) {
1535	+	case 0x00: inst->mnemo = IA64_INST_LD1; break;
1536	+	case 0x01: inst->mnemo = IA64_INST_LD2; break;
1537	+	case 0x02: inst->mnemo = IA64_INST_LD4; break;
1538	+	case 0x03: inst->mnemo = IA64_INST_LD8; break;
1539	+	}
1540	+	}
1541	+	else {
1542	+	inst->operands[2].valid = true;
1543	+	inst->operands[2].index = r2;
1544	+	inst->operands[2].value = IA64_GET_GR(r2);
1545	+	inst->operands[2].nat   = IA64_GET_NAT(r2);
1546	+	switch (x6) {
1547	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1548	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1549	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1550	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1551	+	}
1552	+	}
1553	+	return true;
1554	+	}
1555	+	break;
1556	+	case 0x30:
1557	+	case 0x31:
1558	+	case 0x32:
1559	+	case 0x33:
1560	+	if (m == 0 && x == 0) {
1561	+	inst->operands[0].valid = true;
1562	+	inst->operands[0].index = r3;
1563	+	inst->operands[0].value = IA64_GET_GR(r3);
1564	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1565	+	inst->operands[1].valid = true;
1566	+	inst->operands[1].index = r2;
1567	+	inst->operands[1].value = IA64_GET_GR(r2);
1568	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1569	+	switch (x6) {
1570	+	case 0x30: inst->mnemo = IA64_INST_ST1; break;
1571	+	case 0x31: inst->mnemo = IA64_INST_ST2; break;
1572	+	case 0x32: inst->mnemo = IA64_INST_ST4; break;
1573	+	case 0x33: inst->mnemo = IA64_INST_ST8; break;
1574	+	}
1575	+	return true;
1576	+	}
1577	+	break;
1578	+	}
1579	+	return false;
1580	+	}
1581	+
1582	+	// Decode group 5 instructions (load/store instructions)
1583	+	static bool ia64_decode_instruction_5(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1584	+	{
1585	+	const int r1 = (inst->inst >> 6) & 0x7f;
1586	+	const int r2 = (inst->inst >> 13) & 0x7f;
1587	+	const int r3 = (inst->inst >> 20) & 0x7f;
1588	+
1589	+	const int x6 = (inst->inst >> 30) & 0x3f;
1590	+
1591	+	switch (x6) {
1592	+	case 0x00:
1593	+	case 0x01:
1594	+	case 0x02:
1595	+	case 0x03:
1596	+	inst->operands[0].valid = true;
1597	+	inst->operands[0].index = r1;
1598	+	inst->operands[1].valid = true;
1599	+	inst->operands[1].index = r3;
1600	+	inst->operands[1].value = IA64_GET_GR(r3);
1601	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1602	+	inst->operands[2].valid = true;
1603	+	inst->operands[2].index = -1;
1604	+	inst->operands[2].value = ia64_inst_get_imm9b(inst->inst);
1605	+	inst->operands[2].nat   = 0;
1606	+	switch (x6) {
1607	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1608	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1609	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1610	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1611	+	}
1612	+	return true;
1613	+	case 0x30:
1614	+	case 0x31:
1615	+	case 0x32:
1616	+	case 0x33:
1617	+	inst->operands[0].valid = true;
1618	+	inst->operands[0].index = r3;
1619	+	inst->operands[0].value = IA64_GET_GR(r3);
1620	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1621	+	inst->operands[1].valid = true;
1622	+	inst->operands[1].index = r2;
1623	+	inst->operands[1].value = IA64_GET_GR(r2);
1624	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1625	+	inst->operands[2].valid = true;
1626	+	inst->operands[2].index = -1;
1627	+	inst->operands[2].value = ia64_inst_get_imm9a(inst->inst);
1628	+	inst->operands[2].nat   = 0;
1629	+	switch (x6) {
1630	+	case 0x30: inst->mnemo = IA64_INST_ST1_UPDATE; break;
1631	+	case 0x31: inst->mnemo = IA64_INST_ST2_UPDATE; break;
1632	+	case 0x32: inst->mnemo = IA64_INST_ST4_UPDATE; break;
1633	+	case 0x33: inst->mnemo = IA64_INST_ST8_UPDATE; break;
1634	+	}
1635	+	return true;
1636	+	}
1637	+	return false;
1638	+	}
1639	+
1640	+	// Decode group 8 instructions (ALU integer)
1641	+	static bool ia64_decode_instruction_8(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1642	+	{
1643	+	const int r1  = (inst->inst >> 6) & 0x7f;
1644	+	const int r2  = (inst->inst >> 13) & 0x7f;
1645	+	const int r3  = (inst->inst >> 20) & 0x7f;
1646	+
1647	+	const int x2a = (inst->inst >> 34) & 0x3;
1648	+	const int x2b = (inst->inst >> 27) & 0x3;
1649	+	const int x4  = (inst->inst >> 29) & 0xf;
1650	+	const int ve  = (inst->inst >> 33) & 0x1;
1651	+
1652	+	// destination register (r1) is always valid in this group
1653	+	inst->operands[0].valid = true;
1654	+	inst->operands[0].index = r1;
1655	+
1656	+	// source register (r3) is always valid in this group
1657	+	inst->operands[2].valid = true;
1658	+	inst->operands[2].index = r3;
1659	+	inst->operands[2].value = IA64_GET_GR(r3);
1660	+	inst->operands[2].nat   = IA64_GET_NAT(r3);
1661	+
1662	+	if (x2a == 0 && ve == 0) {
1663	+	inst->operands[1].valid = true;
1664	+	inst->operands[1].index = r2;
1665	+	inst->operands[1].value = IA64_GET_GR(r2);
1666	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1667	+	switch (x4) {
1668	+	case 0x0:                               // add (A1)
1669	+	inst->mnemo = IA64_INST_ADD;
1670	+	inst->operands[3].valid = true;
1671	+	inst->operands[3].index = -1;
1672	+	inst->operands[3].value = x2b == 1;
1673	+	return true;
1674	+	case 0x1:                               // add (A1)
1675	+	inst->mnemo = IA64_INST_SUB;
1676	+	inst->operands[3].valid = true;
1677	+	inst->operands[3].index = -1;
1678	+	inst->operands[3].value = x2b == 0;
1679	+	return true;
1680	+	case 0x4:                               // shladd (A2)
1681	+	inst->mnemo = IA64_INST_SHLADD;
1682	+	inst->operands[3].valid = true;
1683	+	inst->operands[3].index = -1;
1684	+	inst->operands[3].value = ia64_inst_get_count2(inst->inst);
1685	+	return true;
1686	+	case 0x9:
1687	+	if (x2b == 1) {
1688	+	inst->mnemo = IA64_INST_SUB;
1689	+	inst->operands[1].index = -1;
1690	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1691	+	inst->operands[1].nat   = 0;
1692	+	return true;
1693	+	}
1694	+	break;
1695	+	case 0xb:
1696	+	inst->operands[1].index = -1;
1697	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1698	+	inst->operands[1].nat   = 0;
1699	+	// fall-through
1700	+	case 0x3:
1701	+	switch (x2b) {
1702	+	case 0: inst->mnemo = IA64_INST_AND;   break;
1703	+	case 1: inst->mnemo = IA64_INST_ANDCM; break;
1704	+	case 2: inst->mnemo = IA64_INST_OR;    break;
1705	+	case 3: inst->mnemo = IA64_INST_XOR;   break;
1706	+	}
1707	+	return true;
1708	+	}
1709	+	}
1710	+	return false;
1711	+	}
1712	+
1713	+	// Decode instruction
1714	+	static bool ia64_decode_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1715	+	{
1716	+	const int major = (inst->inst >> 37) & 0xf;
1717	+
1718	+	inst->mnemo = IA64_INST_UNKNOWN;
1719	+	inst->pred  = inst->inst & 0x3f;
1720	+	memset(&inst->operands[0], 0, sizeof(inst->operands));
1721	+
1722	+	switch (major) {
1723	+	case 0x0: return ia64_decode_instruction_0(inst, IA64_CONTEXT);
1724	+	case 0x4: return ia64_decode_instruction_4(inst, IA64_CONTEXT);
1725	+	case 0x5: return ia64_decode_instruction_5(inst, IA64_CONTEXT);
1726	+	case 0x8: return ia64_decode_instruction_8(inst, IA64_CONTEXT);
1727	+	}
1728	+	return false;
1729	+	}
1730	+
1731	+	static bool ia64_emulate_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1732	+	{
1733	+	// XXX: handle Register NaT Consumption fault?
1734	+	// XXX: this simple emulator assumes instructions in a bundle
1735	+	// don't depend on effects of other instructions in the same
1736	+	// bundle. It probably would be simpler to JIT-generate code to be
1737	+	// executed natively but probably more costly (inject/extract CPU state)
1738	+	if (inst->mnemo == IA64_INST_UNKNOWN)
1739	+	return false;
1740	+	if (inst->pred && !IA64_GET_PR(inst->pred))
1741	+	return true;
1742	+
1743	+	uint8_t nat, nat2;
1744	+	uint64_t dst, dst2, src1, src2, src3;
1745	+
1746	+	switch (inst->mnemo) {
1747	+	case IA64_INST_NOP:
1748	+	break;
1749	+	case IA64_INST_ADD:
1750	+	case IA64_INST_SUB:
1751	+	case IA64_INST_SHLADD:
1752	+	src3 = inst->operands[3].value;
1753	+	// fall-through
1754	+	case IA64_INST_AND:
1755	+	case IA64_INST_ANDCM:
1756	+	case IA64_INST_OR:
1757	+	case IA64_INST_XOR:
1758	+	src1 = inst->operands[1].value;
1759	+	src2 = inst->operands[2].value;
1760	+	switch (inst->mnemo) {
1761	+	case IA64_INST_ADD:   dst = src1 + src2 + src3; break;
1762	+	case IA64_INST_SUB:   dst = src1 - src2 - src3; break;
1763	+	case IA64_INST_SHLADD: dst = (src1 << src3) + src2; break;
1764	+	case IA64_INST_AND:   dst = src1 & src2;                break;
1765	+	case IA64_INST_ANDCM: dst = src1 &~ src2;               break;
1766	+	case IA64_INST_OR:    dst = src1 | src2;                break;
1767	+	case IA64_INST_XOR:   dst = src1 ^ src2;                break;
1768	+	}
1769	+	inst->operands[0].commit = true;
1770	+	inst->operands[0].value  = dst;
1771	+	inst->operands[0].nat    = inst->operands[1].nat | inst->operands[2].nat;
1772	+	break;
1773	+	case IA64_INST_SXT1:
1774	+	case IA64_INST_SXT2:
1775	+	case IA64_INST_SXT4:
1776	+	case IA64_INST_ZXT1:
1777	+	case IA64_INST_ZXT2:
1778	+	case IA64_INST_ZXT4:
1779	+	src1 = inst->operands[1].value;
1780	+	switch (inst->mnemo) {
1781	+	case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1;               break;
1782	+	case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1;              break;
1783	+	case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1;              break;
1784	+	case IA64_INST_ZXT1: dst = (uint8_t)src1;                               break;
1785	+	case IA64_INST_ZXT2: dst = (uint16_t)src1;                              break;
1786	+	case IA64_INST_ZXT4: dst = (uint32_t)src1;                              break;
1787	+	}
1788	+	inst->operands[0].commit = true;
1789	+	inst->operands[0].value  = dst;
1790	+	inst->operands[0].nat    = inst->operands[1].nat;
1791	+	break;
1792	+	case IA64_INST_LD1_UPDATE:
1793	+	case IA64_INST_LD2_UPDATE:
1794	+	case IA64_INST_LD4_UPDATE:
1795	+	case IA64_INST_LD8_UPDATE:
1796	+	inst->operands[1].commit = true;
1797	+	dst2 = inst->operands[1].value + inst->operands[2].value;
1798	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1799	+	// fall-through
1800	+	case IA64_INST_LD1:
1801	+	case IA64_INST_LD2:
1802	+	case IA64_INST_LD4:
1803	+	case IA64_INST_LD8:
1804	+	src1 = inst->operands[1].value;
1805	+	if (inst->no_memory)
1806	+	dst = 0;
1807	+	else {
1808	+	switch (inst->mnemo) {
1809	+	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((uint8_t *)src1);        break;
1810	+	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((uint16_t *)src1);       break;
1811	+	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((uint32_t *)src1);       break;
1812	+	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((uint64_t *)src1);       break;
1813	+	}
1814	+	}
1815	+	inst->operands[0].commit = true;
1816	+	inst->operands[0].value  = dst;
1817	+	inst->operands[0].nat    = 0;
1818	+	inst->operands[1].value  = dst2;
1819	+	inst->operands[1].nat    = nat2;
1820	+	break;
1821	+	case IA64_INST_ST1_UPDATE:
1822	+	case IA64_INST_ST2_UPDATE:
1823	+	case IA64_INST_ST4_UPDATE:
1824	+	case IA64_INST_ST8_UPDATE:
1825	+	inst->operands[0].commit = 0;
1826	+	dst2 = inst->operands[0].value + inst->operands[2].value;
1827	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1828	+	// fall-through
1829	+	case IA64_INST_ST1:
1830	+	case IA64_INST_ST2:
1831	+	case IA64_INST_ST4:
1832	+	case IA64_INST_ST8:
1833	+	dst  = inst->operands[0].value;
1834	+	src1 = inst->operands[1].value;
1835	+	if (!inst->no_memory) {
1836	+	switch (inst->mnemo) {
1837	+	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((uint8_t *)dst) = src1;        break;
1838	+	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((uint16_t *)dst) = src1;       break;
1839	+	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((uint32_t *)dst) = src1;       break;
1840	+	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((uint64_t *)dst) = src1;       break;
1841	+	}
1842	+	}
1843	+	inst->operands[0].value  = dst2;
1844	+	inst->operands[0].nat    = nat2;
1845	+	break;
1846	+	default:
1847	+	return false;
1848	+	}
1849	+
1850	+	for (int i = 0; i < IA64_N_OPERANDS; i++) {
1851	+	ia64_operand_t const & op = inst->operands[i];
1852	+	if (!op.commit)
1853	+	continue;
1854	+	if (op.index == -1)
1855	+	return false; // XXX: internal error
1856	+	IA64_SET_GR(op.index, op.value, op.nat);
1857	+	}
1858	+	return true;
1859	+	}
1860	+
1861	+	static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1862	+	{
1863	+	ia64_instruction_t inst;
1864	+	memset(&inst, 0, sizeof(inst));
1865	+	inst.inst = raw_inst;
1866	+	if (!ia64_decode_instruction(&inst, IA64_CONTEXT))
1867	+	return false;
1868	+	return ia64_emulate_instruction(&inst, IA64_CONTEXT);
1869	+	}
1870	+
1871	+	static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1872	+	{
1873	+	uint64_t ip = IA64_GET_IP();
1874	+	#if DEBUG
1875	+	printf("IP: 0x%016llx\n", ip);
1876	+	#if 0
1877	+	printf(" Template 0x%02x\n", ia64_get_template(ip));
1878	+	ia64_get_instruction(ip, 0);
1879	+	ia64_get_instruction(ip, 1);
1880	+	ia64_get_instruction(ip, 2);
1881	+	#endif
1882	+	#endif
1883	+
1884	+	// Select which decode switch to use
1885	+	ia64_instruction_t inst;
1886	+	inst.inst = ia64_get_instruction(ip, ip & 3);
1887	+	if (!ia64_decode_instruction(&inst, IA64_CONTEXT)) {
1888	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not decode instruction\n");
1889	+	return false;
1890	+	}
1891	+
1892	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1893	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1894	+
1895	+	switch (inst.mnemo) {
1896	+	case IA64_INST_LD1:
1897	+	case IA64_INST_LD2:
1898	+	case IA64_INST_LD4:
1899	+	case IA64_INST_LD8:
1900	+	case IA64_INST_LD1_UPDATE:
1901	+	case IA64_INST_LD2_UPDATE:
1902	+	case IA64_INST_LD4_UPDATE:
1903	+	case IA64_INST_LD8_UPDATE:
1904	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1905	+	break;
1906	+	case IA64_INST_ST1:
1907	+	case IA64_INST_ST2:
1908	+	case IA64_INST_ST4:
1909	+	case IA64_INST_ST8:
1910	+	case IA64_INST_ST1_UPDATE:
1911	+	case IA64_INST_ST2_UPDATE:
1912	+	case IA64_INST_ST4_UPDATE:
1913	+	case IA64_INST_ST8_UPDATE:
1914	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1915	+	break;
1916	+	}
1917	+
1918	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1919	+	// Unknown machine code, let it crash. Then patch the decoder
1920	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): not a load/store instruction\n");
1921	+	return false;
1922	+	}
1923	+
1924	+	switch (inst.mnemo) {
1925	+	case IA64_INST_LD1:
1926	+	case IA64_INST_LD1_UPDATE:
1927	+	case IA64_INST_ST1:
1928	+	case IA64_INST_ST1_UPDATE:
1929	+	transfer_size = SIZE_BYTE;
1930	+	break;
1931	+	case IA64_INST_LD2:
1932	+	case IA64_INST_LD2_UPDATE:
1933	+	case IA64_INST_ST2:
1934	+	case IA64_INST_ST2_UPDATE:
1935	+	transfer_size = SIZE_WORD;
1936	+	break;
1937	+	case IA64_INST_LD4:
1938	+	case IA64_INST_LD4_UPDATE:
1939	+	case IA64_INST_ST4:
1940	+	case IA64_INST_ST4_UPDATE:
1941	+	transfer_size = SIZE_LONG;
1942	+	break;
1943	+	case IA64_INST_LD8:
1944	+	case IA64_INST_LD8_UPDATE:
1945	+	case IA64_INST_ST8:
1946	+	case IA64_INST_ST8_UPDATE:
1947	+	transfer_size = SIZE_QUAD;
1948	+	break;
1949	+	}
1950	+
1951	+	if (transfer_size == SIZE_UNKNOWN) {
1952	+	// Unknown machine code, let it crash. Then patch the decoder
1953	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): unknown transfer size\n");
1954	+	return false;
1955	+	}
1956	+
1957	+	inst.no_memory = true;
1958	+	if (!ia64_emulate_instruction(&inst, IA64_CONTEXT)) {
1959	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate fault instruction\n");
1960	+	return false;
1961	+	}
1962	+
1963	+	int slot = ip & 3;
1964	+	bool emulate_next = false;
1965	+	switch (slot) {
1966	+	case 0:
1967	+	switch (ia64_get_template(ip)) {
1968	+	case 0x2: // MI;I
1969	+	case 0x3: // MI;I;
1970	+	emulate_next = true;
1971	+	slot = 2;
1972	+	break;
1973	+	case 0xa: // M;MI
1974	+	case 0xb: // M;MI;
1975	+	emulate_next = true;
1976	+	slot = 1;
1977	+	break;
1978	+	}
1979	+	break;
1980	+	}
1981	+	if (emulate_next && !IA64_CAN_PATCH_IP_SLOT) {
1982	+	while (slot < 3) {
1983	+	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), IA64_CONTEXT)) {
1984	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate instruction\n");
1985	+	return false;
1986	+	}
1987	+	++slot;
1988	+	}
1989	+	}
1990	+
1991	+	#if IA64_CAN_PATCH_IP_SLOT
1992	+	if ((slot = ip & 3) < 2)
1993	+	IA64_SET_IP((ip & ~3ull) + (slot + 1));
1994	+	else
1995	+	#endif
1996	+	IA64_SET_IP((ip & ~3ull) + 16);
1997	+	#if DEBUG
1998	+	printf("IP: 0x%016llx\n", IA64_GET_IP());
1999	+	#endif
2000	+	return true;
2001	+	}
2002	+	#endif
2003	+
2004		// Decode and skip PPC instruction
2005		#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__))
2006		static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
#	Line 1662 | Line 2503 | static bool arm_skip_instruction(unsigne
2503		*  SIGSEGV global handler
2504		*/
2505
1665	–	struct sigsegv_info_t {
1666	–	sigsegv_address_t addr;
1667	–	sigsegv_address_t pc;
1668	–	#ifdef HAVE_MACH_EXCEPTIONS
1669	–	mach_port_t thread;
1670	–	bool has_exc_state;
1671	–	SIGSEGV_EXCEPTION_STATE_TYPE exc_state;
1672	–	mach_msg_type_number_t exc_state_count;
1673	–	bool has_thr_state;
1674	–	SIGSEGV_THREAD_STATE_TYPE thr_state;
1675	–	mach_msg_type_number_t thr_state_count;
1676	–	#endif
1677	–	};
1678	–
2506		#ifdef HAVE_MACH_EXCEPTIONS
2507		static void mach_get_exception_state(sigsegv_info_t *SIP)
2508		{
#	Line 1713 | Line 2540 | static void mach_set_thread_state(sigseg
2540		sigsegv_address_t sigsegv_get_fault_address(sigsegv_info_t *SIP)
2541		{
2542		#ifdef HAVE_MACH_EXCEPTIONS
2543	+	#ifdef EMULATED_PPC
2544		static int use_fast_path = -1;
2545		if (use_fast_path != 1 && !SIP->has_exc_state) {
2546		mach_get_exception_state(SIP);
2547
2548		sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
2549	<	if (use_fast_path < 0)
2550	<	use_fast_path = addr == SIP->addr;
2549	>	if (use_fast_path < 0) {
2550	>	const char *machfault = getenv("SIGSEGV_MACH_FAULT");
2551	>	if (machfault) {
2552	>	if (strcmp(machfault, "fast") == 0)
2553	>	use_fast_path = 1;
2554	>	else if (strcmp(machfault, "slow") == 0)
2555	>	use_fast_path = 0;
2556	>	}
2557	>	if (use_fast_path < 0)
2558	>	use_fast_path = addr == SIP->addr;
2559	>	}
2560		SIP->addr = addr;
2561		}
2562		#endif
2563	+	#endif
2564		return SIP->addr;
2565		}
2566
#	Line 1731 | Line 2569 | sigsegv_address_t sigsegv_get_fault_addr
2569		sigsegv_address_t sigsegv_get_fault_instruction_address(sigsegv_info_t *SIP)
2570		{
2571		#ifdef HAVE_MACH_EXCEPTIONS
2572	+	#ifdef EMULATED_PPC
2573		if (!SIP->has_thr_state) {
2574		mach_get_thread_state(SIP);
2575
2576		SIP->pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
2577		}
2578		#endif
2579	+	#endif
2580		return SIP->pc;
2581		}
2582
#	Line 1815 | Line 2655 | static inline kern_return_t
2655		forward_exception(mach_port_t thread_port,
2656		mach_port_t task_port,
2657		exception_type_t exception_type,
2658	<	exception_data_t exception_data,
2658	>	mach_exception_data_t exception_data,
2659		mach_msg_type_number_t data_count,
2660		ExceptionPorts *oldExceptionPorts)
2661		{
#	Line 1862 | Line 2702 | forward_exception(mach_port_t thread_por
2702		switch (behavior) {
2703		case EXCEPTION_DEFAULT:
2704		// fprintf(stderr, "forwarding to exception_raise\n");
2705	<	kret = exception_raise(port, thread_port, task_port, exception_type,
2706	<	exception_data, data_count);
2707	<	MACH_CHECK_ERROR (exception_raise, kret);
2705	>	kret = mach_exception_raise(port, thread_port, task_port, exception_type,
2706	>	exception_data, data_count);
2707	>	MACH_CHECK_ERROR (mach_exception_raise, kret);
2708		break;
2709		case EXCEPTION_STATE:
2710		// fprintf(stderr, "forwarding to exception_raise_state\n");
2711	<	kret = exception_raise_state(port, exception_type, exception_data,
2712	<	data_count, &flavor,
2713	<	(natural_t *)&thread_state, thread_state_count,
2714	<	(natural_t *)&thread_state, &thread_state_count);
2715	<	MACH_CHECK_ERROR (exception_raise_state, kret);
2711	>	kret = mach_exception_raise_state(port, exception_type, exception_data,
2712	>	data_count, &flavor,
2713	>	(natural_t *)&thread_state, thread_state_count,
2714	>	(natural_t *)&thread_state, &thread_state_count);
2715	>	MACH_CHECK_ERROR (mach_exception_raise_state, kret);
2716		break;
2717		case EXCEPTION_STATE_IDENTITY:
2718		// fprintf(stderr, "forwarding to exception_raise_state_identity\n");
2719	<	kret = exception_raise_state_identity(port, thread_port, task_port,
2720	<	exception_type, exception_data,
2721	<	data_count, &flavor,
2722	<	(natural_t *)&thread_state, thread_state_count,
2723	<	(natural_t *)&thread_state, &thread_state_count);
2724	<	MACH_CHECK_ERROR (exception_raise_state_identity, kret);
2719	>	kret = mach_exception_raise_state_identity(port, thread_port, task_port,
2720	>	exception_type, exception_data,
2721	>	data_count, &flavor,
2722	>	(natural_t *)&thread_state, thread_state_count,
2723	>	(natural_t *)&thread_state, &thread_state_count);
2724	>	MACH_CHECK_ERROR (mach_exception_raise_state_identity, kret);
2725		break;
2726		default:
2727		fprintf(stderr, "forward_exception got unknown behavior\n");
#	Line 1918 | Line 2758 | forward_exception(mach_port_t thread_por
2758		* linkage because that is what exc_server expects.
2759		*/
2760		kern_return_t
2761	<	catch_exception_raise(mach_port_t exception_port,
2762	<	mach_port_t thread,
2763	<	mach_port_t task,
2764	<	exception_type_t exception,
2765	<	exception_data_t code,
2766	<	mach_msg_type_number_t code_count)
2761	>	catch_mach_exception_raise(mach_port_t exception_port,
2762	>	mach_port_t thread,
2763	>	mach_port_t task,
2764	>	exception_type_t exception,
2765	>	mach_exception_data_t code,
2766	>	mach_msg_type_number_t code_count)
2767		{
2768		kern_return_t krc;
2769
#	Line 1944 | Line 2784 | catch_exception_raise(mach_port_t except
2784
2785		return krc;
2786		}
2787	+
2788	+	/* XXX: borrowed from launchd and gdb */
2789	+	kern_return_t
2790	+	catch_mach_exception_raise_state(mach_port_t exception_port,
2791	+	exception_type_t exception,
2792	+	mach_exception_data_t code,
2793	+	mach_msg_type_number_t code_count,
2794	+	int *flavor,
2795	+	thread_state_t old_state,
2796	+	mach_msg_type_number_t old_state_count,
2797	+	thread_state_t new_state,
2798	+	mach_msg_type_number_t *new_state_count)
2799	+	{
2800	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2801	+	*new_state_count = old_state_count;
2802	+	return KERN_SUCCESS;
2803	+	}
2804	+
2805	+	/* XXX: borrowed from launchd and gdb */
2806	+	kern_return_t
2807	+	catch_mach_exception_raise_state_identity(mach_port_t exception_port,
2808	+	mach_port_t thread_port,
2809	+	mach_port_t task_port,
2810	+	exception_type_t exception,
2811	+	mach_exception_data_t code,
2812	+	mach_msg_type_number_t code_count,
2813	+	int *flavor,
2814	+	thread_state_t old_state,
2815	+	mach_msg_type_number_t old_state_count,
2816	+	thread_state_t new_state,
2817	+	mach_msg_type_number_t *new_state_count)
2818	+	{
2819	+	kern_return_t kret;
2820	+
2821	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2822	+	*new_state_count = old_state_count;
2823	+
2824	+	kret = mach_port_deallocate(mach_task_self(), task_port);
2825	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2826	+	kret = mach_port_deallocate(mach_task_self(), thread_port);
2827	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2828	+
2829	+	return KERN_SUCCESS;
2830	+	}
2831		#endif
2832
2833		#ifdef HAVE_SIGSEGV_RECOVERY
#	Line 2068 | Line 2952 | static bool sigsegv_do_install_handler(s
2952		// addressing modes) used in PPC instructions, you will need the
2953		// GPR state anyway.
2954		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
2955	<	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
2955	>	EXCEPTION_DEFAULT | MACH_EXCEPTION_CODES, SIGSEGV_THREAD_STATE_FLAVOR);
2956		if (krc != KERN_SUCCESS) {
2957		mach_error("thread_set_exception_ports", krc);
2958		return false;
#	Line 2096 | Line 2980 | static LONG WINAPI main_exception_filter
2980		{
2981		if (sigsegv_fault_handler != NULL
2982		&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
2983	<	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
2983	>	&& ExceptionInfo->ExceptionRecord->NumberParameters >= 2
2984		&& handle_badaccess(ExceptionInfo))
2985		return EXCEPTION_CONTINUE_EXECUTION;
2986
#	Line 2248 | Line 3132 | void sigsegv_set_dump_state(sigsegv_stat
3132		const int REF_INDEX = 123;
3133		const int REF_VALUE = 45;
3134
3135	<	static int page_size;
3135	>	static sigsegv_uintptr_t page_size;
3136		static volatile char * page = 0;
3137		static volatile int handler_called = 0;
3138
#	Line 2286 | Line 3170 | static sigsegv_return_t sigsegv_test_han
3170		(instruction_address >= (sigsegv_address_t)e_region)))
3171		exit(11);
3172		#endif
3173	<	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
3173	>	if (vm_protect((char *)((sigsegv_uintptr_t)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
3174		exit(12);
3175		return SIGSEGV_RETURN_SUCCESS;
3176		}
#	Line 2299 | Line 3183 | static sigsegv_return_t sigsegv_insn_han
3183		#if DEBUG
3184		printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
3185		#endif
3186	<	if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
3186	>	if (((sigsegv_uintptr_t)fault_address - (sigsegv_uintptr_t)page) < page_size) {
3187		#ifdef __GNUC__
3188		// Make sure reported fault instruction address falls into
3189		// expected code range
#	Line 2317 | Line 3201 | static sigsegv_return_t sigsegv_insn_han
3201		// More sophisticated tests for instruction skipper
3202		static bool arch_insn_skipper_tests()
3203		{
3204	<	#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
3204	>	#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64))
3205		static const unsigned char code[] = {
3206		0x8a, 0x00,                    // mov    (%eax),%al
3207		0x8a, 0x2c, 0x18,              // mov    (%eax,%ebx,1),%ch
#	Line 2331 | Line 3215 | static bool arch_insn_skipper_tests()
3215		0x8b, 0x0c, 0x18,              // mov    (%eax,%ebx,1),%ecx
3216		0x89, 0x00,                    // mov    %eax,(%eax)
3217		0x89, 0x0c, 0x18,              // mov    %ecx,(%eax,%ebx,1)
3218	<	#if defined(__x86_64__)
3218	>	#if defined(__x86_64__) || defined(_M_X64)
3219		0x44, 0x8a, 0x00,              // mov    (%rax),%r8b
3220		0x44, 0x8a, 0x20,              // mov    (%rax),%r12b
3221		0x42, 0x8a, 0x3c, 0x10,        // mov    (%rax,%r10,1),%dil
#	Line 2360 | Line 3244 | static bool arch_insn_skipper_tests()
3244		0                              // end
3245		};
3246		const int N_REGS = 20;
3247	<	unsigned long regs[N_REGS];
3247	>	SIGSEGV_REGISTER_TYPE regs[N_REGS];
3248		for (int i = 0; i < N_REGS; i++)
3249		regs[i] = i;
3250	<	const unsigned long start_code = (unsigned long)&code;
3250	>	const sigsegv_uintptr_t start_code = (sigsegv_uintptr_t)&code;
3251		regs[X86_REG_EIP] = start_code;
3252		while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
3253		&& ix86_skip_instruction(regs))
#	Line 2389 | Line 3273 | int main(void)
3273
3274		if (!sigsegv_install_handler(sigsegv_test_handler))
3275		return 4;
3276	<
3276	>
3277		#ifdef __GNUC__
3278		b_region = &&L_b_region1;
3279		e_region = &&L_e_region1;
3280		#endif
3281	<	L_b_region1:
3282	<	page[REF_INDEX] = REF_VALUE;
3283	<	if (page[REF_INDEX] != REF_VALUE)
3284	<	exit(20);
3285	<	page[REF_INDEX] = REF_VALUE;
3286	<	BARRIER();
3287	<	L_e_region1:
3281	>	/* This is a really awful hack but otherwise gcc is smart enough
3282	>	* (or bug'ous enough?) to optimize the labels and place them
3283	>	* e.g. at the "main" entry point, which is wrong.
3284	>	*/
3285	>	volatile int label_hack = 1;
3286	>	switch (label_hack) {
3287	>	case 1:
3288	>	L_b_region1:
3289	>	page[REF_INDEX] = REF_VALUE;
3290	>	if (page[REF_INDEX] != REF_VALUE)
3291	>	exit(20);
3292	>	page[REF_INDEX] = REF_VALUE;
3293	>	BARRIER();
3294	>	// fall-through
3295	>	case 2:
3296	>	L_e_region1:
3297	>	BARRIER();
3298	>	break;
3299	>	}
3300
3301		if (handler_called != 1)
3302		return 5;
#	Line 2431 | Line 3327 | int main(void)
3327		b_region = &&L_b_region2;
3328		e_region = &&L_e_region2;
3329		#endif
3330	<	L_b_region2:
3331	<	TEST_SKIP_INSTRUCTION(unsigned char);
3332	<	TEST_SKIP_INSTRUCTION(unsigned short);
3333	<	TEST_SKIP_INSTRUCTION(unsigned int);
3334	<	TEST_SKIP_INSTRUCTION(unsigned long);
3335	<	TEST_SKIP_INSTRUCTION(signed char);
3336	<	TEST_SKIP_INSTRUCTION(signed short);
3337	<	TEST_SKIP_INSTRUCTION(signed int);
3338	<	TEST_SKIP_INSTRUCTION(signed long);
3339	<	BARRIER();
3340	<	L_e_region2:
3341	<
3330	>	switch (label_hack) {
3331	>	case 1:
3332	>	L_b_region2:
3333	>	TEST_SKIP_INSTRUCTION(unsigned char);
3334	>	TEST_SKIP_INSTRUCTION(unsigned short);
3335	>	TEST_SKIP_INSTRUCTION(unsigned int);
3336	>	TEST_SKIP_INSTRUCTION(unsigned long);
3337	>	TEST_SKIP_INSTRUCTION(signed char);
3338	>	TEST_SKIP_INSTRUCTION(signed short);
3339	>	TEST_SKIP_INSTRUCTION(signed int);
3340	>	TEST_SKIP_INSTRUCTION(signed long);
3341	>	BARRIER();
3342	>	// fall-through
3343	>	case 2:
3344	>	L_e_region2:
3345	>	BARRIER();
3346	>	break;
3347	>	}
3348		if (!arch_insn_skipper_tests())
3349		return 20;
3350		#endif

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