--- BasiliskII/src/Unix/sigsegv.cpp 2003/11/10 23:47:39 1.34 +++ BasiliskII/src/Unix/sigsegv.cpp 2008/01/01 09:40:33 1.71 @@ -10,7 +10,7 @@ * tjw@omnigroup.com Sun, 4 Jun 2000 * www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html * - * Basilisk II (C) 1997-2002 Christian Bauer + * Basilisk II (C) 1997-2008 Christian Bauer * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +36,7 @@ #endif #include +#include #include #include "sigsegv.h" @@ -65,6 +66,13 @@ static bool sigsegv_do_install_handler(i * Instruction decoding aids */ +// Transfer type +enum transfer_type_t { + SIGSEGV_TRANSFER_UNKNOWN = 0, + SIGSEGV_TRANSFER_LOAD = 1, + SIGSEGV_TRANSFER_STORE = 2, +}; + // Transfer size enum transfer_size_t { SIZE_UNKNOWN, @@ -74,10 +82,7 @@ enum transfer_size_t { SIZE_QUAD, // 8 bytes }; -// Transfer type -typedef sigsegv_transfer_type_t transfer_type_t; - -#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__)) +#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__)) // Addressing mode enum addressing_mode_t { MODE_UNKNOWN, @@ -96,10 +101,10 @@ struct instruction_t { char ra, rd; }; -static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned int * gpr) +static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned long * gpr) { // Get opcode and divide into fields - unsigned int opcode = *((unsigned int *)nip); + unsigned int opcode = *((unsigned int *)(unsigned long)nip); unsigned int primop = opcode >> 26; unsigned int exop = (opcode >> 1) & 0x3ff; unsigned int ra = (opcode >> 16) & 0x1f; @@ -173,6 +178,18 @@ static void powerpc_decode_instruction(i transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break; case 45: // sthu transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break; + case 58: // ld, ldu, lwa + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_QUAD; + addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM; + imm &= ~3; + break; + case 62: // std, stdu, stq + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_QUAD; + addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM; + imm &= ~3; + break; } // Calculate effective address @@ -213,7 +230,7 @@ static void powerpc_decode_instruction(i #if HAVE_SIGINFO_T // Generic extended signal handler -#if defined(__NetBSD__) || defined(__FreeBSD__) +#if defined(__FreeBSD__) #define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS) #else #define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) @@ -222,20 +239,58 @@ static void powerpc_decode_instruction(i #define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t *sip, void *scp #define SIGSEGV_FAULT_HANDLER_ARGS sip, scp #define SIGSEGV_FAULT_ADDRESS sip->si_addr +#if (defined(sgi) || defined(__sgi)) +#include +#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) +#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC] +#if (defined(mips) || defined(__mips)) +#define SIGSEGV_REGISTER_FILE &SIGSEGV_CONTEXT_REGS[CTX_EPC], &SIGSEGV_CONTEXT_REGS[CTX_R0] +#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction +#endif +#endif #if defined(__sun__) #if (defined(sparc) || defined(__sparc__)) +#include +#include #include #define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) #define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[REG_PC] +#define SIGSEGV_SPARC_GWINDOWS (((ucontext_t *)scp)->uc_mcontext.gwins) +#define SIGSEGV_SPARC_RWINDOW (struct rwindow *)((char *)SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS) +#define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW +#define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction #endif +#if defined(__i386__) +#include +#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[EIP] +#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction #endif -#if defined(__FreeBSD__) +#endif +#if defined(__FreeBSD__) || defined(__OpenBSD__) #if (defined(i386) || defined(__i386__)) #define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip) #define SIGSEGV_REGISTER_FILE ((unsigned long *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */ #define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction #endif #endif +#if defined(__NetBSD__) +#if (defined(i386) || defined(__i386__)) +#include +#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs) +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP] +#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction +#endif +#if (defined(powerpc) || defined(__powerpc__)) +#include +#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs) +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_PC] +#define SIGSEGV_REGISTER_FILE (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_PC], (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_R0] +#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction +#endif +#endif #if defined(__linux__) #if (defined(i386) || defined(__i386__)) #include @@ -258,9 +313,27 @@ static void powerpc_decode_instruction(i #include #define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.regs) #define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->nip) -#define SIGSEGV_REGISTER_FILE (unsigned int *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned int *)(SIGSEGV_CONTEXT_REGS->gpr) +#define SIGSEGV_REGISTER_FILE (unsigned long *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned long *)(SIGSEGV_CONTEXT_REGS->gpr) #define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction #endif +#if (defined(hppa) || defined(__hppa__)) +#undef SIGSEGV_FAULT_ADDRESS +#define SIGSEGV_FAULT_ADDRESS sip->si_ptr +#endif +#if (defined(arm) || defined(__arm__)) +#include /* use kernel structure, glibc may not be in sync */ +#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext) +#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.arm_pc) +#define SIGSEGV_REGISTER_FILE (&SIGSEGV_CONTEXT_REGS.arm_r0) +#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction +#endif +#if (defined(mips) || defined(__mips__)) +#include +#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext) +#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.pc) +#define SIGSEGV_REGISTER_FILE &SIGSEGV_CONTEXT_REGS.pc, &SIGSEGV_CONTEXT_REGS.gregs[0] +#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction +#endif #endif #endif @@ -290,7 +363,7 @@ static void powerpc_decode_instruction(i #define SIGSEGV_FAULT_HANDLER_ARGS sig, scp #define SIGSEGV_FAULT_ADDRESS scp->regs->dar #define SIGSEGV_FAULT_INSTRUCTION scp->regs->nip -#define SIGSEGV_REGISTER_FILE (unsigned int *)&scp->regs->nip, (unsigned int *)(scp->regs->gpr) +#define SIGSEGV_REGISTER_FILE (unsigned long *)&scp->regs->nip, (unsigned long *)(scp->regs->gpr) #define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction #endif #if (defined(alpha) || defined(__alpha__)) @@ -300,14 +373,24 @@ static void powerpc_decode_instruction(i #define SIGSEGV_FAULT_ADDRESS get_fault_address(scp) #define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc #endif +#if (defined(arm) || defined(__arm__)) +#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int r1, int r2, int r3, struct sigcontext sc +#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp +#define SIGSEGV_FAULT_HANDLER_ARGS &sc +#define SIGSEGV_FAULT_ADDRESS scp->fault_address +#define SIGSEGV_FAULT_INSTRUCTION scp->arm_pc +#define SIGSEGV_REGISTER_FILE &scp->arm_r0 +#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction +#endif #endif // Irix 5 or 6 on MIPS -#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(__SYSTYPE_SVR4)) +#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(_SYSTYPE_SVR4)) #include #define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp #define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp -#define SIGSEGV_FAULT_ADDRESS scp->sc_badvaddr +#define SIGSEGV_FAULT_ADDRESS (unsigned long)scp->sc_badvaddr +#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)scp->sc_pc #define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) #endif @@ -380,8 +463,8 @@ static sigsegv_address_t get_fault_addre #endif #endif #if defined(__FreeBSD__) -#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS) #if (defined(i386) || defined(__i386__)) +#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS) #define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp, char *addr #define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr #define SIGSEGV_FAULT_ADDRESS addr @@ -389,6 +472,13 @@ static sigsegv_address_t get_fault_addre #define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi) #define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction #endif +#if (defined(alpha) || defined(__alpha__)) +#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) +#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, char *addr, struct sigcontext *scp +#define SIGSEGV_FAULT_HANDLER_ARGS sig, addr, scp +#define SIGSEGV_FAULT_ADDRESS addr +#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc +#endif #endif // Extract fault address out of a sigcontext @@ -437,6 +527,20 @@ static sigsegv_address_t get_fault_addre #endif #endif +#if HAVE_WIN32_EXCEPTIONS +#define WIN32_LEAN_AND_MEAN /* avoid including junk */ +#include +#include + +#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo +#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo +#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1] +#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip +#define SIGSEGV_REGISTER_FILE ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi) +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction +#endif + #if HAVE_MACH_EXCEPTIONS // This can easily be extended to other Mach systems, but really who @@ -497,34 +601,58 @@ if (ret != KERN_SUCCESS) { \ exit (1); \ } -#define SIGSEGV_FAULT_ADDRESS code[1] -#define SIGSEGV_FAULT_INSTRUCTION get_fault_instruction(thread, state) -#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) ((code[0] == KERN_PROTECTION_FAILURE) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE) -#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code, ppc_thread_state_t *state -#define SIGSEGV_FAULT_HANDLER_ARGS thread, code, &state +#ifdef __ppc__ +#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state_t +#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE +#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE_COUNT +#define SIGSEGV_FAULT_ADDRESS sip->exc_state.dar +#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t +#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE +#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT +#define SIGSEGV_FAULT_INSTRUCTION sip->thr_state.srr0 #define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction -#define SIGSEGV_REGISTER_FILE &state->srr0, &state->r0 - -// Given a suspended thread, stuff the current instruction and -// registers into state. -// -// It would have been nice to have this be ppc/x86 independant which -// could have been done easily with a thread_state_t instead of -// ppc_thread_state_t, but because of the way this is called it is -// easier to do it this way. -#if (defined(ppc) || defined(__ppc__)) -static inline sigsegv_address_t get_fault_instruction(mach_port_t thread, ppc_thread_state_t *state) -{ - kern_return_t krc; - mach_msg_type_number_t count; - - count = MACHINE_THREAD_STATE_COUNT; - krc = thread_get_state(thread, MACHINE_THREAD_STATE, (thread_state_t)state, &count); - MACH_CHECK_ERROR (thread_get_state, krc); - - return (sigsegv_address_t)state->srr0; -} +#define SIGSEGV_REGISTER_FILE (unsigned long *)&sip->thr_state.srr0, (unsigned long *)&sip->thr_state.r0 +#endif +#ifdef __ppc64__ +#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state64_t +#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE64 +#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE64_COUNT +#define SIGSEGV_FAULT_ADDRESS sip->exc_state.dar +#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state64_t +#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE64 +#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE64_COUNT +#define SIGSEGV_FAULT_INSTRUCTION sip->thr_state.srr0 +#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction +#define SIGSEGV_REGISTER_FILE (unsigned long *)&sip->thr_state.srr0, (unsigned long *)&sip->thr_state.r0 +#endif +#ifdef __i386__ +#define SIGSEGV_EXCEPTION_STATE_TYPE struct i386_exception_state +#define SIGSEGV_EXCEPTION_STATE_FLAVOR i386_EXCEPTION_STATE +#define SIGSEGV_EXCEPTION_STATE_COUNT i386_EXCEPTION_STATE_COUNT +#define SIGSEGV_FAULT_ADDRESS sip->exc_state.faultvaddr +#define SIGSEGV_THREAD_STATE_TYPE struct i386_thread_state +#define SIGSEGV_THREAD_STATE_FLAVOR i386_THREAD_STATE +#define SIGSEGV_THREAD_STATE_COUNT i386_THREAD_STATE_COUNT +#define SIGSEGV_FAULT_INSTRUCTION sip->thr_state.eip +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction +#define SIGSEGV_REGISTER_FILE ((unsigned long *)&sip->thr_state.eax) /* EAX is the first GPR we consider */ #endif +#ifdef __x86_64__ +#define SIGSEGV_EXCEPTION_STATE_TYPE struct x86_exception_state64 +#define SIGSEGV_EXCEPTION_STATE_FLAVOR x86_EXCEPTION_STATE64 +#define SIGSEGV_EXCEPTION_STATE_COUNT x86_EXCEPTION_STATE64_COUNT +#define SIGSEGV_FAULT_ADDRESS sip->exc_state.faultvaddr +#define SIGSEGV_THREAD_STATE_TYPE struct x86_thread_state64 +#define SIGSEGV_THREAD_STATE_FLAVOR x86_THREAD_STATE64 +#define SIGSEGV_THREAD_STATE_COUNT x86_THREAD_STATE64_COUNT +#define SIGSEGV_FAULT_INSTRUCTION sip->thr_state.rip +#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction +#define SIGSEGV_REGISTER_FILE ((unsigned long *)&sip->thr_state.rax) /* RAX is the first GPR we consider */ +#endif +#define SIGSEGV_FAULT_ADDRESS_FAST code[1] +#define SIGSEGV_FAULT_INSTRUCTION_FAST SIGSEGV_INVALID_ADDRESS +#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code +#define SIGSEGV_FAULT_HANDLER_ARGS thread, code // Since there can only be one exception thread running at any time // this is not a problem. @@ -614,7 +742,22 @@ enum { #endif }; #endif -#if defined(__NetBSD__) || defined(__FreeBSD__) +#if defined(__NetBSD__) +enum { +#if (defined(i386) || defined(__i386__)) + X86_REG_EIP = _REG_EIP, + X86_REG_EAX = _REG_EAX, + X86_REG_ECX = _REG_ECX, + X86_REG_EDX = _REG_EDX, + X86_REG_EBX = _REG_EBX, + X86_REG_ESP = _REG_ESP, + X86_REG_EBP = _REG_EBP, + X86_REG_ESI = _REG_ESI, + X86_REG_EDI = _REG_EDI +#endif +}; +#endif +#if defined(__FreeBSD__) enum { #if (defined(i386) || defined(__i386__)) X86_REG_EIP = 10, @@ -629,6 +772,105 @@ enum { #endif }; #endif +#if defined(__OpenBSD__) +enum { +#if defined(__i386__) + // EDI is the first register we consider +#define OREG(REG) offsetof(struct sigcontext, sc_##REG) +#define DREG(REG) ((OREG(REG) - OREG(edi)) / 4) + X86_REG_EIP = DREG(eip), // 7 + X86_REG_EAX = DREG(eax), // 6 + X86_REG_ECX = DREG(ecx), // 5 + X86_REG_EDX = DREG(edx), // 4 + X86_REG_EBX = DREG(ebx), // 3 + X86_REG_ESP = DREG(esp), // 10 + X86_REG_EBP = DREG(ebp), // 2 + X86_REG_ESI = DREG(esi), // 1 + X86_REG_EDI = DREG(edi) // 0 +#undef DREG +#undef OREG +#endif +}; +#endif +#if defined(__sun__) +// Same as for Linux, need to check for x86-64 +enum { +#if defined(__i386__) + X86_REG_EIP = EIP, + X86_REG_EAX = EAX, + X86_REG_ECX = ECX, + X86_REG_EDX = EDX, + X86_REG_EBX = EBX, + X86_REG_ESP = ESP, + X86_REG_EBP = EBP, + X86_REG_ESI = ESI, + X86_REG_EDI = EDI +#endif +}; +#endif +#if defined(__APPLE__) && defined(__MACH__) +enum { +#if (defined(i386) || defined(__i386__)) +#ifdef i386_SAVED_STATE + // same as FreeBSD (in Open Darwin 8.0.1) + X86_REG_EIP = 10, + X86_REG_EAX = 7, + X86_REG_ECX = 6, + X86_REG_EDX = 5, + X86_REG_EBX = 4, + X86_REG_ESP = 13, + X86_REG_EBP = 2, + X86_REG_ESI = 1, + X86_REG_EDI = 0 +#else + // new layout (MacOS X 10.4.4 for x86) + X86_REG_EIP = 10, + X86_REG_EAX = 0, + X86_REG_ECX = 2, + X86_REG_EDX = 3, + X86_REG_EBX = 1, + X86_REG_ESP = 7, + X86_REG_EBP = 6, + X86_REG_ESI = 5, + X86_REG_EDI = 4 +#endif +#endif +#if defined(__x86_64__) + X86_REG_R8 = 8, + X86_REG_R9 = 9, + X86_REG_R10 = 10, + X86_REG_R11 = 11, + X86_REG_R12 = 12, + X86_REG_R13 = 13, + X86_REG_R14 = 14, + X86_REG_R15 = 15, + X86_REG_EDI = 4, + X86_REG_ESI = 5, + X86_REG_EBP = 6, + X86_REG_EBX = 1, + X86_REG_EDX = 3, + X86_REG_EAX = 0, + X86_REG_ECX = 2, + X86_REG_ESP = 7, + X86_REG_EIP = 16 +#endif +}; +#endif +#if defined(_WIN32) +enum { +#if (defined(i386) || defined(__i386__)) + X86_REG_EIP = 7, + X86_REG_EAX = 5, + X86_REG_ECX = 4, + X86_REG_EDX = 3, + X86_REG_EBX = 2, + X86_REG_ESP = 10, + X86_REG_EBP = 6, + X86_REG_ESI = 1, + X86_REG_EDI = 0 +#endif +}; +#endif // FIXME: this is partly redundant with the instruction decoding phase // to discover transfer type and register number static inline int ix86_step_over_modrm(unsigned char * p) @@ -669,9 +911,19 @@ static bool ix86_skip_instruction(unsign if (eip == 0) return false; +#ifdef _WIN32 + if (IsBadCodePtr((FARPROC)eip)) + return false; +#endif + enum instruction_type_t { + i_MOV, + i_ADD + }; + transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN; transfer_size_t transfer_size = SIZE_LONG; + instruction_type_t instruction_type = i_MOV; int reg = -1; int len = 0; @@ -722,68 +974,90 @@ static bool ix86_skip_instruction(unsign #endif // Decode instruction + int op_len = 1; + int target_size = SIZE_UNKNOWN; switch (eip[0]) { case 0x0f: + target_size = transfer_size; switch (eip[1]) { + case 0xbe: // MOVSX r32, r/m8 case 0xb6: // MOVZX r32, r/m8 + transfer_size = SIZE_BYTE; + goto do_mov_extend; + case 0xbf: // MOVSX r32, r/m16 case 0xb7: // MOVZX r32, r/m16 - switch (eip[2] & 0xc0) { - case 0x80: - reg = (eip[2] >> 3) & 7; - transfer_type = SIGSEGV_TRANSFER_LOAD; - break; - case 0x40: - reg = (eip[2] >> 3) & 7; - transfer_type = SIGSEGV_TRANSFER_LOAD; - break; - case 0x00: - reg = (eip[2] >> 3) & 7; - transfer_type = SIGSEGV_TRANSFER_LOAD; - break; + transfer_size = SIZE_WORD; + goto do_mov_extend; + do_mov_extend: + op_len = 2; + goto do_transfer_load; } - len += 3 + ix86_step_over_modrm(eip + 2); break; - } - break; +#if defined(__x86_64__) + case 0x63: // MOVSXD r64, r/m32 + if (has_rex && rex.W) { + transfer_size = SIZE_LONG; + target_size = SIZE_QUAD; + } + else if (transfer_size != SIZE_WORD) { + transfer_size = SIZE_LONG; + target_size = SIZE_QUAD; + } + goto do_transfer_load; +#endif + case 0x02: // ADD r8, r/m8 + transfer_size = SIZE_BYTE; + case 0x03: // ADD r32, r/m32 + instruction_type = i_ADD; + goto do_transfer_load; case 0x8a: // MOV r8, r/m8 transfer_size = SIZE_BYTE; case 0x8b: // MOV r32, r/m32 (or 16-bit operation) - switch (eip[1] & 0xc0) { + do_transfer_load: + switch (eip[op_len] & 0xc0) { case 0x80: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_LOAD; break; case 0x40: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_LOAD; break; case 0x00: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_LOAD; break; } - len += 2 + ix86_step_over_modrm(eip + 1); + len += 1 + op_len + ix86_step_over_modrm(eip + op_len); break; + case 0x00: // ADD r/m8, r8 + transfer_size = SIZE_BYTE; + case 0x01: // ADD r/m32, r32 + instruction_type = i_ADD; + goto do_transfer_store; case 0x88: // MOV r/m8, r8 transfer_size = SIZE_BYTE; case 0x89: // MOV r/m32, r32 (or 16-bit operation) - switch (eip[1] & 0xc0) { + do_transfer_store: + switch (eip[op_len] & 0xc0) { case 0x80: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_STORE; break; case 0x40: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_STORE; break; case 0x00: - reg = (eip[1] >> 3) & 7; + reg = (eip[op_len] >> 3) & 7; transfer_type = SIGSEGV_TRANSFER_STORE; break; } - len += 2 + ix86_step_over_modrm(eip + 1); + len += 1 + op_len + ix86_step_over_modrm(eip + op_len); break; } + if (target_size == SIZE_UNKNOWN) + target_size = transfer_size; if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) { // Unknown machine code, let it crash. Then patch the decoder @@ -795,7 +1069,7 @@ static bool ix86_skip_instruction(unsign reg += 8; #endif - if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) { + if (instruction_type == i_MOV && transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) { static const int x86_reg_map[] = { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX, X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI, @@ -811,12 +1085,14 @@ static bool ix86_skip_instruction(unsign // Set 0 to the relevant register part // NOTE: this is only valid for MOV alike instructions int rloc = x86_reg_map[reg]; - switch (transfer_size) { + switch (target_size) { case SIZE_BYTE: - if (!has_rex && reg >= 4) - regs[rloc - 4] = (regs[rloc - 4] & ~0xff00L); - else - regs[rloc] = (regs[rloc] & ~0xffL); + if (has_rex || reg < 4) + regs[rloc] = (regs[rloc] & ~0x00ffL); + else { + rloc = x86_reg_map[reg - 4]; + regs[rloc] = (regs[rloc] & ~0xff00L); + } break; case SIZE_WORD: regs[rloc] = (regs[rloc] & ~0xffffL); @@ -829,7 +1105,7 @@ static bool ix86_skip_instruction(unsign } #if DEBUG - printf("%08x: %s %s access", regs[X86_REG_EIP], + printf("%p: %s %s access", (void *)regs[X86_REG_EIP], transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : transfer_size == SIZE_LONG ? "long" : @@ -863,7 +1139,7 @@ static bool ix86_skip_instruction(unsign "r12", "r13", "r14", "r15", }; const char * reg_str = NULL; - switch (transfer_size) { + switch (target_size) { case SIZE_BYTE: reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg]; break; @@ -885,8 +1161,8 @@ static bool ix86_skip_instruction(unsign #endif // Decode and skip PPC instruction -#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__)) -static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs) +#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__)) +static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs) { instruction_t instr; powerpc_decode_instruction(&instr, *nip_p, regs); @@ -898,7 +1174,9 @@ static bool powerpc_skip_instruction(uns #if DEBUG printf("%08x: %s %s access", *nip_p, - instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long", + instr.transfer_size == SIZE_BYTE ? "byte" : + instr.transfer_size == SIZE_WORD ? "word" : + instr.transfer_size == SIZE_LONG ? "long" : "quad", instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write"); if (instr.addr_mode == MODE_U || instr.addr_mode == MODE_UX) @@ -916,17 +1194,462 @@ static bool powerpc_skip_instruction(uns return true; } #endif + +// Decode and skip MIPS instruction +#if (defined(mips) || defined(__mips)) +static bool mips_skip_instruction(greg_t * pc_p, greg_t * regs) +{ + unsigned int * epc = (unsigned int *)(unsigned long)*pc_p; + + if (epc == 0) + return false; + +#if DEBUG + printf("IP: %p [%08x]\n", epc, epc[0]); +#endif + + transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN; + transfer_size_t transfer_size = SIZE_LONG; + int direction = 0; + + const unsigned int opcode = epc[0]; + switch (opcode >> 26) { + case 32: // Load Byte + case 36: // Load Byte Unsigned + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_BYTE; + break; + case 33: // Load Halfword + case 37: // Load Halfword Unsigned + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_WORD; + break; + case 35: // Load Word + case 39: // Load Word Unsigned + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_LONG; + break; + case 34: // Load Word Left + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_LONG; + direction = -1; + break; + case 38: // Load Word Right + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_LONG; + direction = 1; + break; + case 55: // Load Doubleword + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_QUAD; + break; + case 26: // Load Doubleword Left + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_QUAD; + direction = -1; + break; + case 27: // Load Doubleword Right + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_QUAD; + direction = 1; + break; + case 40: // Store Byte + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_BYTE; + break; + case 41: // Store Halfword + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_WORD; + break; + case 43: // Store Word + case 42: // Store Word Left + case 46: // Store Word Right + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_LONG; + break; + case 63: // Store Doubleword + case 44: // Store Doubleword Left + case 45: // Store Doubleword Right + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_QUAD; + break; + /* Misc instructions unlikely to be used within CPU emulators */ + case 48: // Load Linked Word + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_LONG; + break; + case 52: // Load Linked Doubleword + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_QUAD; + break; + case 56: // Store Conditional Word + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_LONG; + break; + case 60: // Store Conditional Doubleword + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_QUAD; + break; + } + + if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) { + // Unknown machine code, let it crash. Then patch the decoder + return false; + } + + // Zero target register in case of a load operation + const int reg = (opcode >> 16) & 0x1f; + if (transfer_type == SIGSEGV_TRANSFER_LOAD) { + if (direction == 0) + regs[reg] = 0; + else { + // FIXME: untested code + unsigned long ea = regs[(opcode >> 21) & 0x1f]; + ea += (signed long)(signed int)(signed short)(opcode & 0xffff); + const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7); + unsigned long value; + if (direction > 0) { + const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1); + value = regs[reg] & rmask; + } + else { + const unsigned long lmask = (1L << (offset * 8)) - 1; + value = regs[reg] & lmask; + } + // restore most significant bits + if (transfer_size == SIZE_LONG) + value = (signed long)(signed int)value; + regs[reg] = value; + } + } + +#if DEBUG +#if (defined(_ABIN32) || defined(_ABI64)) + static const char * mips_gpr_names[32] = { + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" + }; +#else + static const char * mips_gpr_names[32] = { + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" + }; +#endif + printf("%s %s register %s\n", + transfer_size == SIZE_BYTE ? "byte" : + transfer_size == SIZE_WORD ? "word" : + transfer_size == SIZE_LONG ? "long" : + transfer_size == SIZE_QUAD ? "quad" : "unknown", + transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from", + mips_gpr_names[reg]); +#endif + + *pc_p += 4; + return true; +} +#endif + +// Decode and skip SPARC instruction +#if (defined(sparc) || defined(__sparc__)) +enum { +#if (defined(__sun__)) + SPARC_REG_G1 = REG_G1, + SPARC_REG_O0 = REG_O0, + SPARC_REG_PC = REG_PC, + SPARC_REG_nPC = REG_nPC +#endif +}; +static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin) +{ + unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC]; + + if (pc == 0) + return false; + +#if DEBUG + printf("IP: %p [%08x]\n", pc, pc[0]); +#endif + + transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN; + transfer_size_t transfer_size = SIZE_LONG; + bool register_pair = false; + + const unsigned int opcode = pc[0]; + if ((opcode >> 30) != 3) + return false; + switch ((opcode >> 19) & 0x3f) { + case 9: // Load Signed Byte + case 1: // Load Unsigned Byte + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_BYTE; + break; + case 10:// Load Signed Halfword + case 2: // Load Unsigned Word + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_WORD; + break; + case 8: // Load Word + case 0: // Load Unsigned Word + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_LONG; + break; + case 11:// Load Extended Word + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_QUAD; + break; + case 3: // Load Doubleword + transfer_type = SIGSEGV_TRANSFER_LOAD; + transfer_size = SIZE_LONG; + register_pair = true; + break; + case 5: // Store Byte + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_BYTE; + break; + case 6: // Store Halfword + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_WORD; + break; + case 4: // Store Word + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_LONG; + break; + case 14:// Store Extended Word + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_QUAD; + break; + case 7: // Store Doubleword + transfer_type = SIGSEGV_TRANSFER_STORE; + transfer_size = SIZE_LONG; + register_pair = true; + break; + } + + if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) { + // Unknown machine code, let it crash. Then patch the decoder + return false; + } + + const int reg = (opcode >> 25) & 0x1f; + +#if DEBUG + static const char * reg_names[] = { + "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", + "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", + "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", + "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7" + }; + printf("%s %s register %s\n", + transfer_size == SIZE_BYTE ? "byte" : + transfer_size == SIZE_WORD ? "word" : + transfer_size == SIZE_LONG ? "long" : + transfer_size == SIZE_QUAD ? "quad" : "unknown", + transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from", + reg_names[reg]); +#endif + + // Zero target register in case of a load operation + if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) { + // FIXME: code to handle local & input registers is not tested + if (reg >= 1 && reg < 8) { + // global registers + regs[reg - 1 + SPARC_REG_G1] = 0; + } + else if (reg >= 8 && reg < 16) { + // output registers + regs[reg - 8 + SPARC_REG_O0] = 0; + } + else if (reg >= 16 && reg < 24) { + // local registers (in register windows) + if (gwins) + gwins->wbuf->rw_local[reg - 16] = 0; + else + rwin->rw_local[reg - 16] = 0; + } + else { + // input registers (in register windows) + if (gwins) + gwins->wbuf->rw_in[reg - 24] = 0; + else + rwin->rw_in[reg - 24] = 0; + } + } + + regs[SPARC_REG_PC] += 4; + regs[SPARC_REG_nPC] += 4; + return true; +} +#endif #endif +// Decode and skip ARM instruction +#if (defined(arm) || defined(__arm__)) +enum { +#if (defined(__linux__)) + ARM_REG_PC = 15, + ARM_REG_CPSR = 16 +#endif +}; +static bool arm_skip_instruction(unsigned long * regs) +{ + unsigned int * pc = (unsigned int *)regs[ARM_REG_PC]; + + if (pc == 0) + return false; + +#if DEBUG + printf("IP: %p [%08x]\n", pc, pc[0]); +#endif + + transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN; + transfer_size_t transfer_size = SIZE_UNKNOWN; + enum { op_sdt = 1, op_sdth = 2 }; + int op = 0; + + // Handle load/store instructions only + const unsigned int opcode = pc[0]; + switch ((opcode >> 25) & 7) { + case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH) + op = op_sdth; + // Determine transfer size (S/H bits) + switch ((opcode >> 5) & 3) { + case 0: // SWP instruction + break; + case 1: // Unsigned halfwords + case 3: // Signed halfwords + transfer_size = SIZE_WORD; + break; + case 2: // Signed byte + transfer_size = SIZE_BYTE; + break; + } + break; + case 2: + case 3: // Single Data Transfer (LDR, STR) + op = op_sdt; + // Determine transfer size (B bit) + if (((opcode >> 22) & 1) == 1) + transfer_size = SIZE_BYTE; + else + transfer_size = SIZE_LONG; + break; + default: + // FIXME: support load/store mutliple? + return false; + } + + // Check for invalid transfer size (SWP instruction?) + if (transfer_size == SIZE_UNKNOWN) + return false; + + // Determine transfer type (L bit) + if (((opcode >> 20) & 1) == 1) + transfer_type = SIGSEGV_TRANSFER_LOAD; + else + transfer_type = SIGSEGV_TRANSFER_STORE; + + // Compute offset + int offset; + if (((opcode >> 25) & 1) == 0) { + if (op == op_sdt) + offset = opcode & 0xfff; + else if (op == op_sdth) { + int rm = opcode & 0xf; + if (((opcode >> 22) & 1) == 0) { + // register offset + offset = regs[rm]; + } + else { + // immediate offset + offset = ((opcode >> 4) & 0xf0) | (opcode & 0x0f); + } + } + } + else { + const int rm = opcode & 0xf; + const int sh = (opcode >> 7) & 0x1f; + if (((opcode >> 4) & 1) == 1) { + // we expect only legal load/store instructions + printf("FATAL: invalid shift operand\n"); + return false; + } + const unsigned int v = regs[rm]; + switch ((opcode >> 5) & 3) { + case 0: // logical shift left + offset = sh ? v << sh : v; + break; + case 1: // logical shift right + offset = sh ? v >> sh : 0; + break; + case 2: // arithmetic shift right + if (sh) + offset = ((signed int)v) >> sh; + else + offset = (v & 0x80000000) ? 0xffffffff : 0; + break; + case 3: // rotate right + if (sh) + offset = (v >> sh) | (v << (32 - sh)); + else + offset = (v >> 1) | ((regs[ARM_REG_CPSR] << 2) & 0x80000000); + break; + } + } + if (((opcode >> 23) & 1) == 0) + offset = -offset; + + int rd = (opcode >> 12) & 0xf; + int rn = (opcode >> 16) & 0xf; +#if DEBUG + static const char * reg_names[] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc" + }; + printf("%s %s register %s\n", + transfer_size == SIZE_BYTE ? "byte" : + transfer_size == SIZE_WORD ? "word" : + transfer_size == SIZE_LONG ? "long" : "unknown", + transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from", + reg_names[rd]); +#endif + + unsigned int base = regs[rn]; + if (((opcode >> 24) & 1) == 1) + base += offset; + + if (transfer_type == SIGSEGV_TRANSFER_LOAD) + regs[rd] = 0; + + if (((opcode >> 24) & 1) == 0) // post-index addressing + regs[rn] += offset; + else if (((opcode >> 21) & 1) == 1) // write-back address into base + regs[rn] = base; + + regs[ARM_REG_PC] += 4; + return true; +} +#endif + + // Fallbacks +#ifndef SIGSEGV_FAULT_ADDRESS_FAST +#define SIGSEGV_FAULT_ADDRESS_FAST SIGSEGV_FAULT_ADDRESS +#endif +#ifndef SIGSEGV_FAULT_INSTRUCTION_FAST +#define SIGSEGV_FAULT_INSTRUCTION_FAST SIGSEGV_FAULT_INSTRUCTION +#endif #ifndef SIGSEGV_FAULT_INSTRUCTION -#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_INVALID_PC +#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_INVALID_ADDRESS #endif #ifndef SIGSEGV_FAULT_HANDLER_ARGLIST_1 #define SIGSEGV_FAULT_HANDLER_ARGLIST_1 SIGSEGV_FAULT_HANDLER_ARGLIST #endif #ifndef SIGSEGV_FAULT_HANDLER_INVOKE -#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) sigsegv_fault_handler(ADDR, IP) +#define SIGSEGV_FAULT_HANDLER_INVOKE(P) sigsegv_fault_handler(P) #endif // SIGSEGV recovery supported ? @@ -939,16 +1662,100 @@ static bool powerpc_skip_instruction(uns * SIGSEGV global handler */ -#if defined(HAVE_SIGSEGV_RECOVERY) || defined(HAVE_MACH_EXCEPTIONS) +struct sigsegv_info_t { + sigsegv_address_t addr; + sigsegv_address_t pc; +#ifdef HAVE_MACH_EXCEPTIONS + mach_port_t thread; + bool has_exc_state; + SIGSEGV_EXCEPTION_STATE_TYPE exc_state; + mach_msg_type_number_t exc_state_count; + bool has_thr_state; + SIGSEGV_THREAD_STATE_TYPE thr_state; + mach_msg_type_number_t thr_state_count; +#endif +}; + +#ifdef HAVE_MACH_EXCEPTIONS +static void mach_get_exception_state(sigsegv_info_t *sip) +{ + sip->exc_state_count = SIGSEGV_EXCEPTION_STATE_COUNT; + kern_return_t krc = thread_get_state(sip->thread, + SIGSEGV_EXCEPTION_STATE_FLAVOR, + (natural_t *)&sip->exc_state, + &sip->exc_state_count); + MACH_CHECK_ERROR(thread_get_state, krc); + sip->has_exc_state = true; +} + +static void mach_get_thread_state(sigsegv_info_t *sip) +{ + sip->thr_state_count = SIGSEGV_THREAD_STATE_COUNT; + kern_return_t krc = thread_get_state(sip->thread, + SIGSEGV_THREAD_STATE_FLAVOR, + (natural_t *)&sip->thr_state, + &sip->thr_state_count); + MACH_CHECK_ERROR(thread_get_state, krc); + sip->has_thr_state = true; +} + +static void mach_set_thread_state(sigsegv_info_t *sip) +{ + kern_return_t krc = thread_set_state(sip->thread, + SIGSEGV_THREAD_STATE_FLAVOR, + (natural_t *)&sip->thr_state, + sip->thr_state_count); + MACH_CHECK_ERROR(thread_set_state, krc); +} +#endif + +// Return the address of the invalid memory reference +sigsegv_address_t sigsegv_get_fault_address(sigsegv_info_t *sip) +{ +#ifdef HAVE_MACH_EXCEPTIONS + static int use_fast_path = -1; + if (use_fast_path != 1 && !sip->has_exc_state) { + mach_get_exception_state(sip); + + sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS; + if (use_fast_path < 0) + use_fast_path = addr == sip->addr; + sip->addr = addr; + } +#endif + return sip->addr; +} + +// Return the address of the instruction that caused the fault, or +// SIGSEGV_INVALID_ADDRESS if we could not retrieve this information +sigsegv_address_t sigsegv_get_fault_instruction_address(sigsegv_info_t *sip) +{ +#ifdef HAVE_MACH_EXCEPTIONS + if (!sip->has_thr_state) { + mach_get_thread_state(sip); + + sip->pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION; + } +#endif + return sip->pc; +} + // This function handles the badaccess to memory. // It is called from the signal handler or the exception handler. static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1) { - sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS; - sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION; - + sigsegv_info_t si; + si.addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS_FAST; + si.pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION_FAST; +#ifdef HAVE_MACH_EXCEPTIONS + si.thread = thread; + si.has_exc_state = false; + si.has_thr_state = false; +#endif + sigsegv_info_t * const sip = &si; + // Call user's handler and reinstall the global handler, if required - switch (SIGSEGV_FAULT_HANDLER_INVOKE(fault_address, fault_instruction)) { + switch (SIGSEGV_FAULT_HANDLER_INVOKE(sip)) { case SIGSEGV_RETURN_SUCCESS: return true; @@ -956,32 +1763,31 @@ static bool handle_badaccess(SIGSEGV_FAU case SIGSEGV_RETURN_SKIP_INSTRUCTION: // Call the instruction skipper with the register file // available +#ifdef HAVE_MACH_EXCEPTIONS + if (!sip->has_thr_state) + mach_get_thread_state(sip); +#endif if (SIGSEGV_SKIP_INSTRUCTION(SIGSEGV_REGISTER_FILE)) { #ifdef HAVE_MACH_EXCEPTIONS // Unlike UNIX signals where the thread state // is modified off of the stack, in Mach we // need to actually call thread_set_state to // have the register values updated. - kern_return_t krc; - - krc = thread_set_state(thread, - MACHINE_THREAD_STATE, (thread_state_t)state, - MACHINE_THREAD_STATE_COUNT); - MACH_CHECK_ERROR (thread_get_state, krc); + mach_set_thread_state(sip); #endif return true; } break; #endif + case SIGSEGV_RETURN_FAILURE: + // We can't do anything with the fault_address, dump state? + if (sigsegv_state_dumper != 0) + sigsegv_state_dumper(sip); + break; } - - // We can't do anything with the fault_address, dump state? - if (sigsegv_state_dumper != 0) - sigsegv_state_dumper(fault_address, fault_instruction); return false; } -#endif /* @@ -1018,7 +1824,7 @@ forward_exception(mach_port_t thread_por mach_port_t port; exception_behavior_t behavior; thread_state_flavor_t flavor; - thread_state_t thread_state; + thread_state_data_t thread_state; mach_msg_type_number_t thread_state_count; for (portIndex = 0; portIndex < oldExceptionPorts->maskCount; portIndex++) { @@ -1037,13 +1843,18 @@ forward_exception(mach_port_t thread_por behavior = oldExceptionPorts->behaviors[portIndex]; flavor = oldExceptionPorts->flavors[portIndex]; + if (!VALID_THREAD_STATE_FLAVOR(flavor)) { + fprintf(stderr, "Invalid thread_state flavor = %d. Not forwarding\n", flavor); + return KERN_FAILURE; + } + /* fprintf(stderr, "forwarding exception, port = 0x%x, behaviour = %d, flavor = %d\n", port, behavior, flavor); */ if (behavior != EXCEPTION_DEFAULT) { thread_state_count = THREAD_STATE_MAX; - kret = thread_get_state (thread_port, flavor, thread_state, + kret = thread_get_state (thread_port, flavor, (natural_t *)&thread_state, &thread_state_count); MACH_CHECK_ERROR (thread_get_state, kret); } @@ -1059,8 +1870,8 @@ forward_exception(mach_port_t thread_por // fprintf(stderr, "forwarding to exception_raise_state\n"); kret = exception_raise_state(port, exception_type, exception_data, data_count, &flavor, - thread_state, thread_state_count, - thread_state, &thread_state_count); + (natural_t *)&thread_state, thread_state_count, + (natural_t *)&thread_state, &thread_state_count); MACH_CHECK_ERROR (exception_raise_state, kret); break; case EXCEPTION_STATE_IDENTITY: @@ -1068,22 +1879,23 @@ forward_exception(mach_port_t thread_por kret = exception_raise_state_identity(port, thread_port, task_port, exception_type, exception_data, data_count, &flavor, - thread_state, thread_state_count, - thread_state, &thread_state_count); + (natural_t *)&thread_state, thread_state_count, + (natural_t *)&thread_state, &thread_state_count); MACH_CHECK_ERROR (exception_raise_state_identity, kret); break; default: fprintf(stderr, "forward_exception got unknown behavior\n"); + kret = KERN_FAILURE; break; } if (behavior != EXCEPTION_DEFAULT) { - kret = thread_set_state (thread_port, flavor, thread_state, + kret = thread_set_state (thread_port, flavor, (natural_t *)&thread_state, thread_state_count); MACH_CHECK_ERROR (thread_set_state, kret); } - return KERN_SUCCESS; + return kret; } /* @@ -1111,20 +1923,24 @@ catch_exception_raise(mach_port_t except mach_port_t task, exception_type_t exception, exception_data_t code, - mach_msg_type_number_t codeCount) + mach_msg_type_number_t code_count) { - ppc_thread_state_t state; kern_return_t krc; - if ((exception == EXC_BAD_ACCESS) && (codeCount >= 2)) { - if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS)) - return KERN_SUCCESS; + if (exception == EXC_BAD_ACCESS) { + switch (code[0]) { + case KERN_PROTECTION_FAILURE: + case KERN_INVALID_ADDRESS: + if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS)) + return KERN_SUCCESS; + break; + } } // In Mach we do not need to remove the exception handler. // If we forward the exception, eventually some exception handler // will take care of this exception. - krc = forward_exception(thread, task, exception, code, codeCount, &ports); + krc = forward_exception(thread, task, exception, code, code_count, &ports); return krc; } @@ -1252,7 +2068,7 @@ static bool sigsegv_do_install_handler(s // addressing modes) used in PPC instructions, you will need the // GPR state anyway. krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort, - EXCEPTION_DEFAULT, MACHINE_THREAD_STATE); + EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR); if (krc != KERN_SUCCESS) { mach_error("thread_set_exception_ports", krc); return false; @@ -1275,6 +2091,95 @@ static bool sigsegv_do_install_handler(s } #endif +#ifdef HAVE_WIN32_EXCEPTIONS +static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo) +{ + if (sigsegv_fault_handler != NULL + && ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION + && ExceptionInfo->ExceptionRecord->NumberParameters == 2 + && handle_badaccess(ExceptionInfo)) + return EXCEPTION_CONTINUE_EXECUTION; + + return EXCEPTION_CONTINUE_SEARCH; +} + +#if defined __CYGWIN__ && defined __i386__ +/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin + installs a global exception handler. We have to dig deep in order to install + our main_exception_filter. */ + +/* Data structures for the current thread's exception handler chain. + On the x86 Windows uses register fs, offset 0 to point to the current + exception handler; Cygwin mucks with it, so we must do the same... :-/ */ + +/* Magic taken from winsup/cygwin/include/exceptions.h. */ + +struct exception_list { + struct exception_list *prev; + int (*handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *); +}; +typedef struct exception_list exception_list; + +/* Magic taken from winsup/cygwin/exceptions.cc. */ + +__asm__ (".equ __except_list,0"); + +extern exception_list *_except_list __asm__ ("%fs:__except_list"); + +/* For debugging. _except_list is not otherwise accessible from gdb. */ +static exception_list * +debug_get_except_list () +{ + return _except_list; +} + +/* Cygwin's original exception handler. */ +static int (*cygwin_exception_handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *); + +/* Our exception handler. */ +static int +libsigsegv_exception_handler (EXCEPTION_RECORD *exception, void *frame, CONTEXT *context, void *dispatch) +{ + EXCEPTION_POINTERS ExceptionInfo; + ExceptionInfo.ExceptionRecord = exception; + ExceptionInfo.ContextRecord = context; + if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH) + return cygwin_exception_handler (exception, frame, context, dispatch); + else + return 0; +} + +static void +do_install_main_exception_filter () +{ + /* We cannot insert any handler into the chain, because such handlers + must lie on the stack (?). Instead, we have to replace(!) Cygwin's + global exception handler. */ + cygwin_exception_handler = _except_list->handler; + _except_list->handler = libsigsegv_exception_handler; +} + +#else + +static void +do_install_main_exception_filter () +{ + SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter); +} +#endif + +static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler) +{ + static bool main_exception_filter_installed = false; + if (!main_exception_filter_installed) { + do_install_main_exception_filter(); + main_exception_filter_installed = true; + } + sigsegv_fault_handler = handler; + return true; +} +#endif + bool sigsegv_install_handler(sigsegv_fault_handler_t handler) { #if defined(HAVE_SIGSEGV_RECOVERY) @@ -1285,7 +2190,7 @@ bool sigsegv_install_handler(sigsegv_fau if (success) sigsegv_fault_handler = handler; return success; -#elif defined(HAVE_MACH_EXCEPTIONS) +#elif defined(HAVE_MACH_EXCEPTIONS) || defined(HAVE_WIN32_EXCEPTIONS) return sigsegv_do_install_handler(handler); #else // FAIL: no siginfo_t nor sigcontext subterfuge is available @@ -1311,6 +2216,9 @@ void sigsegv_deinstall_handler(void) SIGSEGV_ALL_SIGNALS #undef FAULT_HANDLER #endif +#ifdef HAVE_WIN32_EXCEPTIONS + sigsegv_fault_handler = NULL; +#endif } @@ -1332,7 +2240,9 @@ void sigsegv_set_dump_state(sigsegv_stat #include #include #include +#ifdef HAVE_SYS_MMAN_H #include +#endif #include "vm_alloc.h" const int REF_INDEX = 123; @@ -1342,20 +2252,36 @@ static int page_size; static volatile char * page = 0; static volatile int handler_called = 0; +/* Barriers */ +#ifdef __GNUC__ +#define BARRIER() asm volatile ("" : : : "memory") +#else +#define BARRIER() /* nothing */ +#endif + #ifdef __GNUC__ // Code range where we expect the fault to come from static void *b_region, *e_region; #endif -static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address) +static sigsegv_return_t sigsegv_test_handler(sigsegv_info_t *sip) { + const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip); + const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip); +#if DEBUG + printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address); + printf("expected fault at %p\n", page + REF_INDEX); +#ifdef __GNUC__ + printf("expected instruction address range: %p-%p\n", b_region, e_region); +#endif +#endif handler_called++; if ((fault_address - REF_INDEX) != page) exit(10); #ifdef __GNUC__ // Make sure reported fault instruction address falls into // expected code range - if (instruction_address != SIGSEGV_INVALID_PC + if (instruction_address != SIGSEGV_INVALID_ADDRESS && ((instruction_address < (sigsegv_address_t)b_region) || (instruction_address >= (sigsegv_address_t)e_region))) exit(11); @@ -1366,13 +2292,18 @@ static sigsegv_return_t sigsegv_test_han } #ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION -static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address) +static sigsegv_return_t sigsegv_insn_handler(sigsegv_info_t *sip) { + const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip); + const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip); +#if DEBUG + printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address); +#endif if (((unsigned long)fault_address - (unsigned long)page) < page_size) { #ifdef __GNUC__ // Make sure reported fault instruction address falls into // expected code range - if (instruction_address != SIGSEGV_INVALID_PC + if (instruction_address != SIGSEGV_INVALID_ADDRESS && ((instruction_address < (sigsegv_address_t)b_region) || (instruction_address >= (sigsegv_address_t)e_region))) return SIGSEGV_RETURN_FAILURE; @@ -1423,6 +2354,8 @@ static bool arch_insn_skipper_tests() 0x4c, 0x89, 0x18, // mov %r11,(%rax) 0x4a, 0x89, 0x0c, 0x10, // mov %rcx,(%rax,%r10,1) 0x4e, 0x89, 0x1c, 0x10, // mov %r11,(%rax,%r10,1) + 0x63, 0x47, 0x04, // movslq 4(%rdi),%eax + 0x48, 0x63, 0x47, 0x04, // movslq 4(%rdi),%rax #endif 0 // end }; @@ -1446,7 +2379,7 @@ int main(void) if (vm_init() < 0) return 1; - page_size = getpagesize(); + page_size = vm_get_page_size(); if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED) return 2; @@ -1466,6 +2399,7 @@ int main(void) if (page[REF_INDEX] != REF_VALUE) exit(20); page[REF_INDEX] = REF_VALUE; + BARRIER(); L_e_region1: if (handler_called != 1) @@ -1502,11 +2436,16 @@ int main(void) TEST_SKIP_INSTRUCTION(unsigned short); TEST_SKIP_INSTRUCTION(unsigned int); TEST_SKIP_INSTRUCTION(unsigned long); + TEST_SKIP_INSTRUCTION(signed char); + TEST_SKIP_INSTRUCTION(signed short); + TEST_SKIP_INSTRUCTION(signed int); + TEST_SKIP_INSTRUCTION(signed long); + BARRIER(); L_e_region2: -#endif if (!arch_insn_skipper_tests()) return 20; +#endif vm_exit(); return 0;