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root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.65 by gbeauche, 2007-06-05T13:15:57Z vs.
Revision 1.75 by gbeauche, 2008-01-06T16:25:03Z

#	Line 10 | Line 10
10		*    tjw@omnigroup.com Sun, 4 Jun 2000
11		*    www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	*  Basilisk II (C) 1997-2005 Christian Bauer
13	>	*  Basilisk II (C) 1997-2008 Christian Bauer
14		*
15		*  This program is free software; you can redistribute it and/or modify
16		*  it under the terms of the GNU General Public License as published by
#	Line 70 | Line 70 | static bool sigsegv_do_install_handler(i
70		enum transfer_type_t {
71		SIGSEGV_TRANSFER_UNKNOWN        = 0,
72		SIGSEGV_TRANSFER_LOAD           = 1,
73	<	SIGSEGV_TRANSFER_STORE          = 2,
73	>	SIGSEGV_TRANSFER_STORE          = 2
74		};
75
76		// Transfer size
#	Line 79 | Line 79 | enum transfer_size_t {
79		SIZE_BYTE,
80		SIZE_WORD, // 2 bytes
81		SIZE_LONG, // 4 bytes
82	<	SIZE_QUAD, // 8 bytes
82	>	SIZE_QUAD  // 8 bytes
83		};
84
85	<	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__))
85	>	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__))
86		// Addressing mode
87		enum addressing_mode_t {
88		MODE_UNKNOWN,
#	Line 307 | Line 307 | static void powerpc_decode_instruction(i
307		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
308		#endif
309		#if (defined(ia64) || defined(__ia64__))
310	<	#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
310	>	#define SIGSEGV_CONTEXT_REGS                    ((struct sigcontext *)scp)
311	>	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
312	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
313	>	#define SIGSEGV_SKIP_INSTRUCTION                ia64_skip_instruction
314		#endif
315		#if (defined(powerpc) || defined(__powerpc__))
316		#include <sys/ucontext.h>
#	Line 602 | Line 605 | if (ret != KERN_SUCCESS) { \
605		}
606
607		#ifdef __ppc__
608	+	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state_t
609	+	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE
610	+	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE_COUNT
611	+	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.dar
612		#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state_t
613		#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE
614		#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE_COUNT
615	<	#define SIGSEGV_FAULT_INSTRUCTION               state->srr0
615	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.srr0
616	>	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
617	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.srr0, (unsigned long *)&SIP->thr_state.r0
618	>	#endif
619	>	#ifdef __ppc64__
620	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state64_t
621	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE64
622	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE64_COUNT
623	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.dar
624	>	#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state64_t
625	>	#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE64
626	>	#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE64_COUNT
627	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.srr0
628		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
629	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&state->srr0, (unsigned long *)&state->r0
629	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.srr0, (unsigned long *)&SIP->thr_state.r0
630		#endif
631		#ifdef __i386__
632	<	#ifdef i386_SAVED_STATE
633	<	#define SIGSEGV_THREAD_STATE_TYPE               struct i386_saved_state
634	<	#define SIGSEGV_THREAD_STATE_FLAVOR             i386_SAVED_STATE
635	<	#define SIGSEGV_THREAD_STATE_COUNT              i386_SAVED_STATE_COUNT
617	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&state->edi) /* EDI is the first GPR we consider */
618	<	#else
632	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    struct i386_exception_state
633	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  i386_EXCEPTION_STATE
634	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   i386_EXCEPTION_STATE_COUNT
635	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.faultvaddr
636		#define SIGSEGV_THREAD_STATE_TYPE               struct i386_thread_state
637		#define SIGSEGV_THREAD_STATE_FLAVOR             i386_THREAD_STATE
638		#define SIGSEGV_THREAD_STATE_COUNT              i386_THREAD_STATE_COUNT
639	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&state->eax) /* EAX is the first GPR we consider */
639	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.eip
640	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
641	>	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIP->thr_state.eax) /* EAX is the first GPR we consider */
642		#endif
643	<	#define SIGSEGV_FAULT_INSTRUCTION               state->eip
643	>	#ifdef __x86_64__
644	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    struct x86_exception_state64
645	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  x86_EXCEPTION_STATE64
646	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   x86_EXCEPTION_STATE64_COUNT
647	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.faultvaddr
648	>	#define SIGSEGV_THREAD_STATE_TYPE               struct x86_thread_state64
649	>	#define SIGSEGV_THREAD_STATE_FLAVOR             x86_THREAD_STATE64
650	>	#define SIGSEGV_THREAD_STATE_COUNT              x86_THREAD_STATE64_COUNT
651	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.rip
652		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
653	+	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIP->thr_state.rax) /* RAX is the first GPR we consider */
654		#endif
655	<	#define SIGSEGV_FAULT_ADDRESS                   code[1]
656	<	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP)  ((code[0] == KERN_PROTECTION_FAILURE || code[0] == KERN_INVALID_ADDRESS) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE)
657	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code, SIGSEGV_THREAD_STATE_TYPE *state
658	<	#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code, &state
655	>	#define SIGSEGV_FAULT_ADDRESS_FAST              code[1]
656	>	#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_INVALID_ADDRESS
657	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code
658	>	#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code
659
660		// Since there can only be one exception thread running at any time
661		// this is not a problem.
#	Line 785 | Line 813 | enum {
813		#endif
814		#if defined(__APPLE__) && defined(__MACH__)
815		enum {
816	+	#if (defined(i386) || defined(__i386__))
817		#ifdef i386_SAVED_STATE
818		// same as FreeBSD (in Open Darwin 8.0.1)
819		X86_REG_EIP = 10,
#	Line 801 | Line 830 | enum {
830		X86_REG_EIP = 10,
831		X86_REG_EAX = 0,
832		X86_REG_ECX = 2,
833	<	X86_REG_EDX = 4,
833	>	X86_REG_EDX = 3,
834		X86_REG_EBX = 1,
835		X86_REG_ESP = 7,
836		X86_REG_EBP = 6,
837		X86_REG_ESI = 5,
838		X86_REG_EDI = 4
839		#endif
840	+	#endif
841	+	#if defined(__x86_64__)
842	+	X86_REG_R8  = 8,
843	+	X86_REG_R9  = 9,
844	+	X86_REG_R10 = 10,
845	+	X86_REG_R11 = 11,
846	+	X86_REG_R12 = 12,
847	+	X86_REG_R13 = 13,
848	+	X86_REG_R14 = 14,
849	+	X86_REG_R15 = 15,
850	+	X86_REG_EDI = 4,
851	+	X86_REG_ESI = 5,
852	+	X86_REG_EBP = 6,
853	+	X86_REG_EBX = 1,
854	+	X86_REG_EDX = 3,
855	+	X86_REG_EAX = 0,
856	+	X86_REG_ECX = 2,
857	+	X86_REG_ESP = 7,
858	+	X86_REG_EIP = 16
859	+	#endif
860		};
861		#endif
862		#if defined(_WIN32)
#	Line 1114 | Line 1163 | static bool ix86_skip_instruction(unsign
1163		}
1164		#endif
1165
1166	+	// Decode and skip IA-64 instruction
1167	+	#if defined(__ia64__)
1168	+	#if defined(__linux__)
1169	+	// XXX: we assume everything is 8-byte aligned
1170	+	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
1171	+	#define IREG(REG) ((OREG(REG) - OREG(flags)) / 8)
1172	+	enum {
1173	+	IA64_REG_IP  = IREG(ip),
1174	+	IA64_REG_NAT = IREG(nat),
1175	+	IA64_REG_PR  = IREG(pr),
1176	+	IA64_REG_GR  = IREG(gr)
1177	+	};
1178	+	#undef IREG
1179	+	#undef OREG
1180	+	#endif
1181	+
1182	+	// Helper macros to access the machine context
1183	+	#define IA64_CONTEXT                    (ctx)
1184	+	#define IA64_GET_PR(P)                  ((IA64_CONTEXT[IA64_REG_PR] >> (P)) & 1)
1185	+	#define IA64_GET_NAT(I)                 ((IA64_CONTEXT[IA64_REG_NAT] >> (I)) & 1)
1186	+	#define IA64_SET_NAT(I,V)               (IA64_CONTEXT[IA64_REG_NAT] = (IA64_CONTEXT[IA64_REG_NAT] & ~(1ul << (I))) | (((unsigned long)!!(V)) << (I)))
1187	+	#define IA64_GET_GR(R)                  (IA64_CONTEXT[IA64_REG_GR + (R)])
1188	+	#define IA64_SET_GR(R,V)                (IA64_CONTEXT[IA64_REG_GR + (R)] = (V))
1189	+
1190	+	// Instruction operations
1191	+	enum {
1192	+	IA64_INST_UNKNOWN = 0,
1193	+	IA64_INST_LD1,                          // ld1 op0=[op1]
1194	+	IA64_INST_LD1_UPDATE,           // ld1 op0=[op1],op2
1195	+	IA64_INST_LD2,                          // ld2 op0=[op1]
1196	+	IA64_INST_LD2_UPDATE,           // ld2 op0=[op1],op2
1197	+	IA64_INST_LD4,                          // ld4 op0=[op1]
1198	+	IA64_INST_LD4_UPDATE,           // ld4 op0=[op1],op2
1199	+	IA64_INST_LD8,                          // ld8 op0=[op1]
1200	+	IA64_INST_LD8_UPDATE,           // ld8 op0=[op1],op2
1201	+	IA64_INST_ST1,                          // st1 [op0]=op1
1202	+	IA64_INST_ST1_UPDATE,           // st1 [op0]=op1,op2
1203	+	IA64_INST_ST2,                          // st2 [op0]=op1
1204	+	IA64_INST_ST2_UPDATE,           // st2 [op0]=op1,op2
1205	+	IA64_INST_ST4,                          // st4 [op0]=op1
1206	+	IA64_INST_ST4_UPDATE,           // st4 [op0]=op1,op2
1207	+	IA64_INST_ST8,                          // st8 [op0]=op1
1208	+	IA64_INST_ST8_UPDATE,           // st8 [op0]=op1,op2
1209	+	IA64_INST_ADD,                          // add op0=op1,op2,op3
1210	+	IA64_INST_SUB,                          // sub op0=op1,op2,op3
1211	+	IA64_INST_SHLADD,                       // shladd op0=op1,op3,op2
1212	+	IA64_INST_AND,                          // and op0=op1,op2
1213	+	IA64_INST_ANDCM,                        // andcm op0=op1,op2
1214	+	IA64_INST_OR,                           // or op0=op1,op2
1215	+	IA64_INST_XOR,                          // xor op0=op1,op2
1216	+	IA64_INST_SXT1,                         // sxt1 op0=op1
1217	+	IA64_INST_SXT2,                         // sxt2 op0=op1
1218	+	IA64_INST_SXT4,                         // sxt4 op0=op1
1219	+	IA64_INST_ZXT1,                         // zxt1 op0=op1
1220	+	IA64_INST_ZXT2,                         // zxt2 op0=op1
1221	+	IA64_INST_ZXT4,                         // zxt4 op0=op1
1222	+	IA64_INST_NOP                           // nop op0
1223	+	};
1224	+
1225	+	const int IA64_N_OPERANDS = 4;
1226	+
1227	+	// Decoded operand type
1228	+	struct ia64_operand_t {
1229	+	unsigned char commit;
1230	+	unsigned char valid;
1231	+	signed char index;
1232	+	unsigned char nat;
1233	+	unsigned long value;
1234	+	};
1235	+
1236	+	// Decoded instruction type
1237	+	struct ia64_instruction_t {
1238	+	unsigned char mnemo;
1239	+	unsigned char pred;
1240	+	unsigned char no_memory;
1241	+	unsigned long inst;
1242	+	ia64_operand_t operands[IA64_N_OPERANDS];
1243	+	};
1244	+
1245	+	// Get immediate sign-bit
1246	+	static inline int ia64_inst_get_sbit(unsigned long inst)
1247	+	{
1248	+	return (inst >> 36) & 1;
1249	+	}
1250	+
1251	+	// Get 8-bit immediate value (A3, A8, I27, M30)
1252	+	static inline unsigned long ia64_inst_get_imm8(unsigned long inst)
1253	+	{
1254	+	unsigned long value = (inst >> 13) & 0x7ful;
1255	+	if (ia64_inst_get_sbit(inst))
1256	+	value |= ~0x7ful;
1257	+	return value;
1258	+	}
1259	+
1260	+	// Get 9-bit immediate value (M3)
1261	+	static inline unsigned long ia64_inst_get_imm9b(unsigned long inst)
1262	+	{
1263	+	unsigned long value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f);
1264	+	if (ia64_inst_get_sbit(inst))
1265	+	value |= ~0xfful;
1266	+	return value;
1267	+	}
1268	+
1269	+	// Get 9-bit immediate value (M5)
1270	+	static inline unsigned long ia64_inst_get_imm9a(unsigned long inst)
1271	+	{
1272	+	unsigned long value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f);
1273	+	if (ia64_inst_get_sbit(inst))
1274	+	value |= ~0xfful;
1275	+	return value;
1276	+	}
1277	+
1278	+	// Get 14-bit immediate value (A4)
1279	+	static inline unsigned long ia64_inst_get_imm14(unsigned long inst)
1280	+	{
1281	+	unsigned long value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f);
1282	+	if (ia64_inst_get_sbit(inst))
1283	+	value |= ~0x1fful;
1284	+	return value;
1285	+	}
1286	+
1287	+	// Get 22-bit immediate value (A5)
1288	+	static inline unsigned long ia64_inst_get_imm22(unsigned long inst)
1289	+	{
1290	+	unsigned long value = ((((inst >> 22) & 0x1f) << 16) |
1291	+	(((inst >> 27) & 0x1ff) << 7) |
1292	+	(inst & 0x7f));
1293	+	if (ia64_inst_get_sbit(inst))
1294	+	value |= ~0x1ffffful;
1295	+	return value;
1296	+	}
1297	+
1298	+	// Get 21-bit immediate value (I19)
1299	+	static inline unsigned long ia64_inst_get_imm21(unsigned long inst)
1300	+	{
1301	+	return (((inst >> 36) & 1) << 20) | ((inst >> 6) & 0xfffff);
1302	+	}
1303	+
1304	+	// Get 2-bit count value (A2)
1305	+	static inline int ia64_inst_get_count2(unsigned long inst)
1306	+	{
1307	+	return (inst >> 27) & 0x3;
1308	+	}
1309	+
1310	+	// Get bundle template
1311	+	static inline unsigned int ia64_get_template(unsigned long raw_ip)
1312	+	{
1313	+	unsigned long *ip = (unsigned long *)(raw_ip & ~3ul);
1314	+	return ip[0] & 0x1f;
1315	+	}
1316	+
1317	+	// Get specified instruction in bundle
1318	+	static unsigned long ia64_get_instruction(unsigned long raw_ip, int slot)
1319	+	{
1320	+	unsigned long inst;
1321	+	unsigned long *ip = (unsigned long *)(raw_ip & ~3ul);
1322	+	#if DEBUG
1323	+	printf("Bundle: %016lx%016lx\n", ip[1], ip[0]);
1324	+	#endif
1325	+
1326	+	switch (slot) {
1327	+	case 0:
1328	+	inst = (ip[0] >> 5) & 0x1fffffffffful;
1329	+	break;
1330	+	case 1:
1331	+	inst = ((ip[1] & 0x7ffffful) << 18) | ((ip[0] >> 46) & 0x3fffful);
1332	+	break;
1333	+	case 2:
1334	+	inst = (ip[1] >> 23) & 0x1fffffffffful;
1335	+	break;
1336	+	case 3:
1337	+	fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
1338	+	abort();
1339	+	break;
1340	+	}
1341	+
1342	+	#if DEBUG
1343	+	printf(" Instruction %d: 0x%016lx\n", slot, inst);
1344	+	#endif
1345	+	return inst;
1346	+	}
1347	+
1348	+	// Decode group 0 instructions
1349	+	static bool ia64_decode_instruction_0(ia64_instruction_t *inst, unsigned long *ctx)
1350	+	{
1351	+	const int r1 = (inst->inst >>  6) & 0x7f;
1352	+	const int r3 = (inst->inst >> 20) & 0x7f;
1353	+
1354	+	const int x3 = (inst->inst >> 33) & 0x07;
1355	+	const int x6 = (inst->inst >> 27) & 0x3f;
1356	+	const int x2 = (inst->inst >> 31) & 0x03;
1357	+	const int x4 = (inst->inst >> 27) & 0x0f;
1358	+
1359	+	if (x3 == 0) {
1360	+	switch (x6) {
1361	+	case 0x01:                                              // nop.i (I19)
1362	+	inst->mnemo = IA64_INST_NOP;
1363	+	inst->operands[0].valid = true;
1364	+	inst->operands[0].index = -1;
1365	+	inst->operands[0].value = ia64_inst_get_imm21(inst->inst);
1366	+	return true;
1367	+	case 0x14:                                              // sxt1 (I29)
1368	+	case 0x15:                                              // sxt2 (I29)
1369	+	case 0x16:                                              // sxt4 (I29)
1370	+	case 0x10:                                              // zxt1 (I29)
1371	+	case 0x11:                                              // zxt2 (I29)
1372	+	case 0x12:                                              // zxt4 (I29)
1373	+	switch (x6) {
1374	+	case 0x14: inst->mnemo = IA64_INST_SXT1; break;
1375	+	case 0x15: inst->mnemo = IA64_INST_SXT2; break;
1376	+	case 0x16: inst->mnemo = IA64_INST_SXT4; break;
1377	+	case 0x10: inst->mnemo = IA64_INST_ZXT1; break;
1378	+	case 0x11: inst->mnemo = IA64_INST_ZXT2; break;
1379	+	case 0x12: inst->mnemo = IA64_INST_ZXT4; break;
1380	+	default: abort();
1381	+	}
1382	+	inst->operands[0].valid = true;
1383	+	inst->operands[0].index = r1;
1384	+	inst->operands[1].valid = true;
1385	+	inst->operands[1].index = r3;
1386	+	inst->operands[1].value = IA64_GET_GR(r3);
1387	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1388	+	return true;
1389	+	}
1390	+	}
1391	+	return false;
1392	+	}
1393	+
1394	+	// Decode group 4 instructions (load/store instructions)
1395	+	static bool ia64_decode_instruction_4(ia64_instruction_t *inst, unsigned long *ctx)
1396	+	{
1397	+	const int r1 = (inst->inst >> 6) & 0x7f;
1398	+	const int r2 = (inst->inst >> 13) & 0x7f;
1399	+	const int r3 = (inst->inst >> 20) & 0x7f;
1400	+
1401	+	const int m  = (inst->inst >> 36) & 1;
1402	+	const int x  = (inst->inst >> 27) & 1;
1403	+	const int x6 = (inst->inst >> 30) & 0x3f;
1404	+
1405	+	switch (x6) {
1406	+	case 0x00:
1407	+	case 0x01:
1408	+	case 0x02:
1409	+	case 0x03:
1410	+	if (x == 0) {
1411	+	inst->operands[0].valid = true;
1412	+	inst->operands[0].index = r1;
1413	+	inst->operands[1].valid = true;
1414	+	inst->operands[1].index = r3;
1415	+	inst->operands[1].value = IA64_GET_GR(r3);
1416	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1417	+	if (m == 0) {
1418	+	switch (x6) {
1419	+	case 0x00: inst->mnemo = IA64_INST_LD1; break;
1420	+	case 0x01: inst->mnemo = IA64_INST_LD2; break;
1421	+	case 0x02: inst->mnemo = IA64_INST_LD4; break;
1422	+	case 0x03: inst->mnemo = IA64_INST_LD8; break;
1423	+	}
1424	+	}
1425	+	else {
1426	+	inst->operands[2].valid = true;
1427	+	inst->operands[2].index = r2;
1428	+	inst->operands[2].value = IA64_GET_GR(r2);
1429	+	inst->operands[2].nat   = IA64_GET_NAT(r2);
1430	+	switch (x6) {
1431	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1432	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1433	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1434	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1435	+	}
1436	+	}
1437	+	return true;
1438	+	}
1439	+	break;
1440	+	case 0x30:
1441	+	case 0x31:
1442	+	case 0x32:
1443	+	case 0x33:
1444	+	if (m == 0 && x == 0) {
1445	+	inst->operands[0].valid = true;
1446	+	inst->operands[0].index = r3;
1447	+	inst->operands[0].value = IA64_GET_GR(r3);
1448	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1449	+	inst->operands[1].valid = true;
1450	+	inst->operands[1].index = r2;
1451	+	inst->operands[1].value = IA64_GET_GR(r2);
1452	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1453	+	switch (x6) {
1454	+	case 0x30: inst->mnemo = IA64_INST_ST1; break;
1455	+	case 0x31: inst->mnemo = IA64_INST_ST2; break;
1456	+	case 0x32: inst->mnemo = IA64_INST_ST4; break;
1457	+	case 0x33: inst->mnemo = IA64_INST_ST8; break;
1458	+	}
1459	+	return true;
1460	+	}
1461	+	break;
1462	+	}
1463	+	return false;
1464	+	}
1465	+
1466	+	// Decode group 5 instructions (load/store instructions)
1467	+	static bool ia64_decode_instruction_5(ia64_instruction_t *inst, unsigned long *ctx)
1468	+	{
1469	+	const int r1 = (inst->inst >> 6) & 0x7f;
1470	+	const int r2 = (inst->inst >> 13) & 0x7f;
1471	+	const int r3 = (inst->inst >> 20) & 0x7f;
1472	+
1473	+	const int x6 = (inst->inst >> 30) & 0x3f;
1474	+
1475	+	switch (x6) {
1476	+	case 0x00:
1477	+	case 0x01:
1478	+	case 0x02:
1479	+	case 0x03:
1480	+	inst->operands[0].valid = true;
1481	+	inst->operands[0].index = r1;
1482	+	inst->operands[1].valid = true;
1483	+	inst->operands[1].index = r3;
1484	+	inst->operands[1].value = IA64_GET_GR(r3);
1485	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1486	+	inst->operands[2].valid = true;
1487	+	inst->operands[2].index = -1;
1488	+	inst->operands[2].value = ia64_inst_get_imm9b(inst->inst);
1489	+	inst->operands[2].nat   = 0;
1490	+	switch (x6) {
1491	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1492	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1493	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1494	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1495	+	}
1496	+	return true;
1497	+	case 0x30:
1498	+	case 0x31:
1499	+	case 0x32:
1500	+	case 0x33:
1501	+	inst->operands[0].valid = true;
1502	+	inst->operands[0].index = r3;
1503	+	inst->operands[0].value = IA64_GET_GR(r3);
1504	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1505	+	inst->operands[1].valid = true;
1506	+	inst->operands[1].index = r2;
1507	+	inst->operands[1].value = IA64_GET_GR(r2);
1508	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1509	+	inst->operands[2].valid = true;
1510	+	inst->operands[2].index = -1;
1511	+	inst->operands[2].value = ia64_inst_get_imm9a(inst->inst);
1512	+	inst->operands[2].nat   = 0;
1513	+	switch (x6) {
1514	+	case 0x30: inst->mnemo = IA64_INST_ST1_UPDATE; break;
1515	+	case 0x31: inst->mnemo = IA64_INST_ST2_UPDATE; break;
1516	+	case 0x32: inst->mnemo = IA64_INST_ST4_UPDATE; break;
1517	+	case 0x33: inst->mnemo = IA64_INST_ST8_UPDATE; break;
1518	+	}
1519	+	return true;
1520	+	}
1521	+	return false;
1522	+	}
1523	+
1524	+	// Decode group 8 instructions (ALU integer)
1525	+	static bool ia64_decode_instruction_8(ia64_instruction_t *inst, unsigned long *ctx)
1526	+	{
1527	+	const int r1  = (inst->inst >> 6) & 0x7f;
1528	+	const int r2  = (inst->inst >> 13) & 0x7f;
1529	+	const int r3  = (inst->inst >> 20) & 0x7f;
1530	+
1531	+	const int x2a = (inst->inst >> 34) & 0x3;
1532	+	const int x2b = (inst->inst >> 27) & 0x3;
1533	+	const int x4  = (inst->inst >> 29) & 0xf;
1534	+	const int ve  = (inst->inst >> 33) & 0x1;
1535	+
1536	+	// destination register (r1) is always valid in this group
1537	+	inst->operands[0].valid = true;
1538	+	inst->operands[0].index = r1;
1539	+
1540	+	// source register (r3) is always valid in this group
1541	+	inst->operands[2].valid = true;
1542	+	inst->operands[2].index = r3;
1543	+	inst->operands[2].value = IA64_GET_GR(r3);
1544	+	inst->operands[2].nat   = IA64_GET_NAT(r3);
1545	+
1546	+	if (x2a == 0 && ve == 0) {
1547	+	inst->operands[1].valid = true;
1548	+	inst->operands[1].index = r2;
1549	+	inst->operands[1].value = IA64_GET_GR(r2);
1550	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1551	+	switch (x4) {
1552	+	case 0x0:                               // add (A1)
1553	+	inst->mnemo = IA64_INST_ADD;
1554	+	inst->operands[3].valid = true;
1555	+	inst->operands[3].index = -1;
1556	+	inst->operands[3].value = x2b == 1;
1557	+	return true;
1558	+	case 0x1:                               // add (A1)
1559	+	inst->mnemo = IA64_INST_SUB;
1560	+	inst->operands[3].valid = true;
1561	+	inst->operands[3].index = -1;
1562	+	inst->operands[3].value = x2b == 0;
1563	+	return true;
1564	+	case 0x4:                               // shladd (A2)
1565	+	inst->mnemo = IA64_INST_SHLADD;
1566	+	inst->operands[3].valid = true;
1567	+	inst->operands[3].index = -1;
1568	+	inst->operands[3].value = ia64_inst_get_count2(inst->inst);
1569	+	return true;
1570	+	case 0x9:
1571	+	if (x2b == 1) {
1572	+	inst->mnemo = IA64_INST_SUB;
1573	+	inst->operands[1].index = -1;
1574	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1575	+	inst->operands[1].nat   = 0;
1576	+	return true;
1577	+	}
1578	+	break;
1579	+	case 0xb:
1580	+	inst->operands[1].index = -1;
1581	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1582	+	inst->operands[1].nat   = 0;
1583	+	// fall-through
1584	+	case 0x3:
1585	+	switch (x2b) {
1586	+	case 0: inst->mnemo = IA64_INST_AND;   break;
1587	+	case 1: inst->mnemo = IA64_INST_ANDCM; break;
1588	+	case 2: inst->mnemo = IA64_INST_OR;    break;
1589	+	case 3: inst->mnemo = IA64_INST_XOR;   break;
1590	+	}
1591	+	return true;
1592	+	}
1593	+	}
1594	+	return false;
1595	+	}
1596	+
1597	+	// Decode instruction
1598	+	static bool ia64_decode_instruction(ia64_instruction_t *inst, unsigned long *ctx)
1599	+	{
1600	+	const int major = (inst->inst >> 37) & 0xf;
1601	+
1602	+	inst->mnemo = IA64_INST_UNKNOWN;
1603	+	inst->pred  = inst->inst & 0x3f;
1604	+	memset(&inst->operands[0], 0, sizeof(inst->operands));
1605	+
1606	+	switch (major) {
1607	+	case 0x0: return ia64_decode_instruction_0(inst, ctx);
1608	+	case 0x4: return ia64_decode_instruction_4(inst, ctx);
1609	+	case 0x5: return ia64_decode_instruction_5(inst, ctx);
1610	+	case 0x8: return ia64_decode_instruction_8(inst, ctx);
1611	+	}
1612	+	return false;
1613	+	}
1614	+
1615	+	static bool ia64_emulate_instruction(ia64_instruction_t *inst, unsigned long *ctx)
1616	+	{
1617	+	if (inst->mnemo == IA64_INST_UNKNOWN)
1618	+	return false;
1619	+	if (inst->pred && !IA64_GET_PR(inst->pred))
1620	+	return true;
1621	+
1622	+	unsigned char nat, nat2;
1623	+	unsigned long dst, dst2, src1, src2, src3;
1624	+
1625	+	switch (inst->mnemo) {
1626	+	case IA64_INST_NOP:
1627	+	break;
1628	+	case IA64_INST_ADD:
1629	+	case IA64_INST_SUB:
1630	+	case IA64_INST_SHLADD:
1631	+	src3 = inst->operands[3].value;
1632	+	// fall-through
1633	+	case IA64_INST_AND:
1634	+	case IA64_INST_ANDCM:
1635	+	case IA64_INST_OR:
1636	+	case IA64_INST_XOR:
1637	+	src1 = inst->operands[1].value;
1638	+	src2 = inst->operands[2].value;
1639	+	switch (inst->mnemo) {
1640	+	case IA64_INST_ADD:   dst = src1 + src2 + src3; break;
1641	+	case IA64_INST_SUB:   dst = src1 - src2 - src3; break;
1642	+	case IA64_INST_SHLADD: dst = (src1 << src3) + src2; break;
1643	+	case IA64_INST_AND:   dst = src1 & src2;                break;
1644	+	case IA64_INST_ANDCM: dst = src1 &~ src2;               break;
1645	+	case IA64_INST_OR:    dst = src1 | src2;                break;
1646	+	case IA64_INST_XOR:   dst = src1 ^ src2;                break;
1647	+	}
1648	+	inst->operands[0].commit = true;
1649	+	inst->operands[0].value  = dst;
1650	+	inst->operands[0].nat    = inst->operands[1].nat | inst->operands[2].nat;
1651	+	break;
1652	+	case IA64_INST_SXT1:
1653	+	case IA64_INST_SXT2:
1654	+	case IA64_INST_SXT4:
1655	+	case IA64_INST_ZXT1:
1656	+	case IA64_INST_ZXT2:
1657	+	case IA64_INST_ZXT4:
1658	+	src1 = inst->operands[1].value;
1659	+	switch (inst->mnemo) {
1660	+	case IA64_INST_SXT1: dst = (signed long)(signed char)src1;              break;
1661	+	case IA64_INST_SXT2: dst = (signed long)(signed short)src1;             break;
1662	+	case IA64_INST_SXT4: dst = (signed long)(signed int)src1;               break;
1663	+	case IA64_INST_ZXT1: dst = (unsigned char)src1;                                 break;
1664	+	case IA64_INST_ZXT2: dst = (unsigned short)src1;                                break;
1665	+	case IA64_INST_ZXT4: dst = (unsigned int)src1;                                  break;
1666	+	}
1667	+	inst->operands[0].commit = true;
1668	+	inst->operands[0].value  = dst;
1669	+	inst->operands[0].nat    = inst->operands[1].nat;
1670	+	break;
1671	+	case IA64_INST_LD1_UPDATE:
1672	+	case IA64_INST_LD2_UPDATE:
1673	+	case IA64_INST_LD4_UPDATE:
1674	+	case IA64_INST_LD8_UPDATE:
1675	+	inst->operands[1].commit = true;
1676	+	dst2 = inst->operands[1].value + inst->operands[2].value;
1677	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1678	+	// fall-through
1679	+	case IA64_INST_LD1:
1680	+	case IA64_INST_LD2:
1681	+	case IA64_INST_LD4:
1682	+	case IA64_INST_LD8:
1683	+	src1 = inst->operands[1].value;
1684	+	if (inst->no_memory)
1685	+	dst = 0;
1686	+	else {
1687	+	switch (inst->mnemo) {
1688	+	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((unsigned char *)src1);  break;
1689	+	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((unsigned short *)src1); break;
1690	+	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((unsigned int *)src1);   break;
1691	+	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((unsigned long *)src1);  break;
1692	+	}
1693	+	}
1694	+	inst->operands[0].commit = true;
1695	+	inst->operands[0].value  = dst;
1696	+	inst->operands[0].nat    = 0;
1697	+	inst->operands[1].value  = dst2;
1698	+	inst->operands[1].nat    = nat2;
1699	+	break;
1700	+	case IA64_INST_ST1_UPDATE:
1701	+	case IA64_INST_ST2_UPDATE:
1702	+	case IA64_INST_ST4_UPDATE:
1703	+	case IA64_INST_ST8_UPDATE:
1704	+	inst->operands[0].commit = 0;
1705	+	dst2 = inst->operands[0].value + inst->operands[2].value;
1706	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1707	+	// fall-through
1708	+	case IA64_INST_ST1:
1709	+	case IA64_INST_ST2:
1710	+	case IA64_INST_ST4:
1711	+	case IA64_INST_ST8:
1712	+	dst  = inst->operands[0].value;
1713	+	src1 = inst->operands[1].value;
1714	+	if (!inst->no_memory) {
1715	+	switch (inst->mnemo) {
1716	+	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((unsigned char *)dst) = src1;  break;
1717	+	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((unsigned short *)dst) = src1; break;
1718	+	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((unsigned int *)dst) = src1;   break;
1719	+	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((unsigned long *)dst) = src1;  break;
1720	+	}
1721	+	}
1722	+	inst->operands[0].value  = dst2;
1723	+	inst->operands[0].nat    = nat2;
1724	+	break;
1725	+	default:
1726	+	return false;
1727	+	}
1728	+
1729	+	for (int i = 0; i < IA64_N_OPERANDS; i++) {
1730	+	ia64_operand_t const & op = inst->operands[i];
1731	+	if (!op.commit)
1732	+	continue;
1733	+	if (op.index == -1)
1734	+	return false; // XXX: internal error
1735	+	IA64_SET_GR(op.index, op.value);
1736	+	IA64_SET_NAT(op.index, op.nat);
1737	+	}
1738	+	return true;
1739	+	}
1740	+
1741	+	static bool ia64_emulate_instruction(unsigned long raw_inst, unsigned long *ctx)
1742	+	{
1743	+	ia64_instruction_t inst;
1744	+	memset(&inst, 0, sizeof(inst));
1745	+	inst.inst = raw_inst;
1746	+	if (!ia64_decode_instruction(&inst, ctx))
1747	+	return false;
1748	+	return ia64_emulate_instruction(&inst, ctx);
1749	+	}
1750	+
1751	+	static bool ia64_skip_instruction(unsigned long *ctx)
1752	+	{
1753	+	unsigned long ip = ctx[IA64_REG_IP];
1754	+	#if DEBUG
1755	+	printf("IP: 0x%016lx\n", ip);
1756	+	#if 0
1757	+	printf(" Template 0x%02x\n", ia64_get_template(ip));
1758	+	ia64_get_instruction(ip, 0);
1759	+	ia64_get_instruction(ip, 1);
1760	+	ia64_get_instruction(ip, 2);
1761	+	#endif
1762	+	#endif
1763	+
1764	+	// Select which decode switch to use
1765	+	ia64_instruction_t inst;
1766	+	inst.inst = ia64_get_instruction(ip, ip & 3);
1767	+	if (!ia64_decode_instruction(&inst, ctx)) {
1768	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not decode instruction\n");
1769	+	return false;
1770	+	}
1771	+
1772	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1773	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1774	+
1775	+	switch (inst.mnemo) {
1776	+	case IA64_INST_LD1:
1777	+	case IA64_INST_LD2:
1778	+	case IA64_INST_LD4:
1779	+	case IA64_INST_LD8:
1780	+	case IA64_INST_LD1_UPDATE:
1781	+	case IA64_INST_LD2_UPDATE:
1782	+	case IA64_INST_LD4_UPDATE:
1783	+	case IA64_INST_LD8_UPDATE:
1784	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1785	+	break;
1786	+	case IA64_INST_ST1:
1787	+	case IA64_INST_ST2:
1788	+	case IA64_INST_ST4:
1789	+	case IA64_INST_ST8:
1790	+	case IA64_INST_ST1_UPDATE:
1791	+	case IA64_INST_ST2_UPDATE:
1792	+	case IA64_INST_ST4_UPDATE:
1793	+	case IA64_INST_ST8_UPDATE:
1794	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1795	+	break;
1796	+	}
1797	+
1798	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1799	+	// Unknown machine code, let it crash. Then patch the decoder
1800	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): not a load/store instruction\n");
1801	+	return false;
1802	+	}
1803	+
1804	+	switch (inst.mnemo) {
1805	+	case IA64_INST_LD1:
1806	+	case IA64_INST_LD1_UPDATE:
1807	+	case IA64_INST_ST1:
1808	+	case IA64_INST_ST1_UPDATE:
1809	+	transfer_size = SIZE_BYTE;
1810	+	break;
1811	+	case IA64_INST_LD2:
1812	+	case IA64_INST_LD2_UPDATE:
1813	+	case IA64_INST_ST2:
1814	+	case IA64_INST_ST2_UPDATE:
1815	+	transfer_size = SIZE_WORD;
1816	+	break;
1817	+	case IA64_INST_LD4:
1818	+	case IA64_INST_LD4_UPDATE:
1819	+	case IA64_INST_ST4:
1820	+	case IA64_INST_ST4_UPDATE:
1821	+	transfer_size = SIZE_LONG;
1822	+	break;
1823	+	case IA64_INST_LD8:
1824	+	case IA64_INST_LD8_UPDATE:
1825	+	case IA64_INST_ST8:
1826	+	case IA64_INST_ST8_UPDATE:
1827	+	transfer_size = SIZE_QUAD;
1828	+	break;
1829	+	}
1830	+
1831	+	if (transfer_size == SIZE_UNKNOWN) {
1832	+	// Unknown machine code, let it crash. Then patch the decoder
1833	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): unknown transfer size\n");
1834	+	return false;
1835	+	}
1836	+
1837	+	inst.no_memory = true;
1838	+	if (!ia64_emulate_instruction(&inst, ctx)) {
1839	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate fault instruction\n");
1840	+	return false;
1841	+	}
1842	+
1843	+	int slot = ip & 3;
1844	+	bool emulate_next = false;
1845	+	switch (slot) {
1846	+	case 0:
1847	+	switch (ia64_get_template(ip)) {
1848	+	case 0x2: // MI;I
1849	+	case 0x3: // MI;I;
1850	+	emulate_next = true;
1851	+	slot = 2;
1852	+	break;
1853	+	case 0xa: // M;MI
1854	+	case 0xb: // M;MI;
1855	+	emulate_next = true;
1856	+	slot = 1;
1857	+	break;
1858	+	}
1859	+	break;
1860	+	}
1861	+	if (emulate_next) {
1862	+	while (slot < 3) {
1863	+	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), ctx)) {
1864	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate instruction\n");
1865	+	return false;
1866	+	}
1867	+	++slot;
1868	+	}
1869	+	}
1870	+
1871	+	ctx[IA64_REG_IP] = (ip & ~3ul) + 16;
1872	+	#if DEBUG
1873	+	printf("IP: 0x%016lx\n", ctx[IA64_REG_IP]);
1874	+	#endif
1875	+	return true;
1876	+	}
1877	+	#endif
1878	+
1879		// Decode and skip PPC instruction
1880	<	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__))
1880	>	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__))
1881		static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
1882		{
1883		instruction_t instr;
#	Line 1590 | Line 2352 | static bool arm_skip_instruction(unsigne
2352
2353
2354		// Fallbacks
2355	+	#ifndef SIGSEGV_FAULT_ADDRESS_FAST
2356	+	#define SIGSEGV_FAULT_ADDRESS_FAST              SIGSEGV_FAULT_ADDRESS
2357	+	#endif
2358	+	#ifndef SIGSEGV_FAULT_INSTRUCTION_FAST
2359	+	#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_FAULT_INSTRUCTION
2360	+	#endif
2361		#ifndef SIGSEGV_FAULT_INSTRUCTION
2362	<	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_INVALID_PC
2362	>	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_INVALID_ADDRESS
2363		#endif
2364		#ifndef SIGSEGV_FAULT_HANDLER_ARGLIST_1
2365		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 SIGSEGV_FAULT_HANDLER_ARGLIST
2366		#endif
2367		#ifndef SIGSEGV_FAULT_HANDLER_INVOKE
2368	<	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP)  sigsegv_fault_handler(ADDR, IP)
2368	>	#define SIGSEGV_FAULT_HANDLER_INVOKE(P) sigsegv_fault_handler(P)
2369		#endif
2370
2371		// SIGSEGV recovery supported ?
#	Line 1610 | Line 2378 | static bool arm_skip_instruction(unsigne
2378		*  SIGSEGV global handler
2379		*/
2380
2381	+	struct sigsegv_info_t {
2382	+	sigsegv_address_t addr;
2383	+	sigsegv_address_t pc;
2384	+	#ifdef HAVE_MACH_EXCEPTIONS
2385	+	mach_port_t thread;
2386	+	bool has_exc_state;
2387	+	SIGSEGV_EXCEPTION_STATE_TYPE exc_state;
2388	+	mach_msg_type_number_t exc_state_count;
2389	+	bool has_thr_state;
2390	+	SIGSEGV_THREAD_STATE_TYPE thr_state;
2391	+	mach_msg_type_number_t thr_state_count;
2392	+	#endif
2393	+	};
2394	+
2395	+	#ifdef HAVE_MACH_EXCEPTIONS
2396	+	static void mach_get_exception_state(sigsegv_info_t *SIP)
2397	+	{
2398	+	SIP->exc_state_count = SIGSEGV_EXCEPTION_STATE_COUNT;
2399	+	kern_return_t krc = thread_get_state(SIP->thread,
2400	+	SIGSEGV_EXCEPTION_STATE_FLAVOR,
2401	+	(natural_t *)&SIP->exc_state,
2402	+	&SIP->exc_state_count);
2403	+	MACH_CHECK_ERROR(thread_get_state, krc);
2404	+	SIP->has_exc_state = true;
2405	+	}
2406	+
2407	+	static void mach_get_thread_state(sigsegv_info_t *SIP)
2408	+	{
2409	+	SIP->thr_state_count = SIGSEGV_THREAD_STATE_COUNT;
2410	+	kern_return_t krc = thread_get_state(SIP->thread,
2411	+	SIGSEGV_THREAD_STATE_FLAVOR,
2412	+	(natural_t *)&SIP->thr_state,
2413	+	&SIP->thr_state_count);
2414	+	MACH_CHECK_ERROR(thread_get_state, krc);
2415	+	SIP->has_thr_state = true;
2416	+	}
2417	+
2418	+	static void mach_set_thread_state(sigsegv_info_t *SIP)
2419	+	{
2420	+	kern_return_t krc = thread_set_state(SIP->thread,
2421	+	SIGSEGV_THREAD_STATE_FLAVOR,
2422	+	(natural_t *)&SIP->thr_state,
2423	+	SIP->thr_state_count);
2424	+	MACH_CHECK_ERROR(thread_set_state, krc);
2425	+	}
2426	+	#endif
2427	+
2428	+	// Return the address of the invalid memory reference
2429	+	sigsegv_address_t sigsegv_get_fault_address(sigsegv_info_t *SIP)
2430	+	{
2431	+	#ifdef HAVE_MACH_EXCEPTIONS
2432	+	static int use_fast_path = -1;
2433	+	if (use_fast_path != 1 && !SIP->has_exc_state) {
2434	+	mach_get_exception_state(SIP);
2435	+
2436	+	sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
2437	+	if (use_fast_path < 0)
2438	+	use_fast_path = addr == SIP->addr;
2439	+	SIP->addr = addr;
2440	+	}
2441	+	#endif
2442	+	return SIP->addr;
2443	+	}
2444	+
2445	+	// Return the address of the instruction that caused the fault, or
2446	+	// SIGSEGV_INVALID_ADDRESS if we could not retrieve this information
2447	+	sigsegv_address_t sigsegv_get_fault_instruction_address(sigsegv_info_t *SIP)
2448	+	{
2449	+	#ifdef HAVE_MACH_EXCEPTIONS
2450	+	if (!SIP->has_thr_state) {
2451	+	mach_get_thread_state(SIP);
2452	+
2453	+	SIP->pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
2454	+	}
2455	+	#endif
2456	+	return SIP->pc;
2457	+	}
2458	+
2459		// This function handles the badaccess to memory.
2460		// It is called from the signal handler or the exception handler.
2461		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
2462		{
2463	+	sigsegv_info_t SI;
2464	+	SI.addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS_FAST;
2465	+	SI.pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION_FAST;
2466		#ifdef HAVE_MACH_EXCEPTIONS
2467	<	// We must match the initial count when writing back the CPU state registers
2468	<	kern_return_t krc;
2469	<	mach_msg_type_number_t count;
1621	<
1622	<	count = SIGSEGV_THREAD_STATE_COUNT;
1623	<	krc = thread_get_state(thread, SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state, &count);
1624	<	MACH_CHECK_ERROR (thread_get_state, krc);
2467	>	SI.thread = thread;
2468	>	SI.has_exc_state = false;
2469	>	SI.has_thr_state = false;
2470		#endif
2471	+	sigsegv_info_t * const SIP = &SI;
2472
1627	–	sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
1628	–	sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
1629	–
2473		// Call user's handler and reinstall the global handler, if required
2474	<	switch (SIGSEGV_FAULT_HANDLER_INVOKE(fault_address, fault_instruction)) {
2474	>	switch (SIGSEGV_FAULT_HANDLER_INVOKE(SIP)) {
2475		case SIGSEGV_RETURN_SUCCESS:
2476		return true;
2477
#	Line 1636 | Line 2479 | static bool handle_badaccess(SIGSEGV_FAU
2479		case SIGSEGV_RETURN_SKIP_INSTRUCTION:
2480		// Call the instruction skipper with the register file
2481		// available
2482	+	#ifdef HAVE_MACH_EXCEPTIONS
2483	+	if (!SIP->has_thr_state)
2484	+	mach_get_thread_state(SIP);
2485	+	#endif
2486		if (SIGSEGV_SKIP_INSTRUCTION(SIGSEGV_REGISTER_FILE)) {
2487		#ifdef HAVE_MACH_EXCEPTIONS
2488		// Unlike UNIX signals where the thread state
2489		// is modified off of the stack, in Mach we
2490		// need to actually call thread_set_state to
2491		// have the register values updated.
2492	<	krc = thread_set_state(thread,
1646	<	SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state,
1647	<	count);
1648	<	MACH_CHECK_ERROR (thread_set_state, krc);
2492	>	mach_set_thread_state(SIP);
2493		#endif
2494		return true;
2495		}
#	Line 1654 | Line 2498 | static bool handle_badaccess(SIGSEGV_FAU
2498		case SIGSEGV_RETURN_FAILURE:
2499		// We can't do anything with the fault_address, dump state?
2500		if (sigsegv_state_dumper != 0)
2501	<	sigsegv_state_dumper(fault_address, fault_instruction);
2501	>	sigsegv_state_dumper(SIP);
2502		break;
2503		}
2504
#	Line 1795 | Line 2639 | catch_exception_raise(mach_port_t except
2639		mach_port_t task,
2640		exception_type_t exception,
2641		exception_data_t code,
2642	<	mach_msg_type_number_t codeCount)
2642	>	mach_msg_type_number_t code_count)
2643		{
1800	–	SIGSEGV_THREAD_STATE_TYPE state;
2644		kern_return_t krc;
2645
2646	<	if ((exception == EXC_BAD_ACCESS)  && (codeCount >= 2)) {
2647	<	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
2648	<	return KERN_SUCCESS;
2646	>	if (exception == EXC_BAD_ACCESS) {
2647	>	switch (code[0]) {
2648	>	case KERN_PROTECTION_FAILURE:
2649	>	case KERN_INVALID_ADDRESS:
2650	>	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
2651	>	return KERN_SUCCESS;
2652	>	break;
2653	>	}
2654		}
2655
2656		// In Mach we do not need to remove the exception handler.
2657		// If we forward the exception, eventually some exception handler
2658		// will take care of this exception.
2659	<	krc = forward_exception(thread, task, exception, code, codeCount, &ports);
2659	>	krc = forward_exception(thread, task, exception, code, code_count, &ports);
2660
2661		return krc;
2662		}
#	Line 2132 | Line 2980 | static volatile int handler_called = 0;
2980		static void *b_region, *e_region;
2981		#endif
2982
2983	<	static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2983	>	static sigsegv_return_t sigsegv_test_handler(sigsegv_info_t *sip)
2984		{
2985	+	const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip);
2986	+	const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip);
2987		#if DEBUG
2988		printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
2989		printf("expected fault at %p\n", page + REF_INDEX);
#	Line 2147 | Line 2997 | static sigsegv_return_t sigsegv_test_han
2997		#ifdef __GNUC__
2998		// Make sure reported fault instruction address falls into
2999		// expected code range
3000	<	if (instruction_address != SIGSEGV_INVALID_PC
3000	>	if (instruction_address != SIGSEGV_INVALID_ADDRESS
3001		&& ((instruction_address <  (sigsegv_address_t)b_region) ||
3002		(instruction_address >= (sigsegv_address_t)e_region)))
3003		exit(11);
#	Line 2158 | Line 3008 | static sigsegv_return_t sigsegv_test_han
3008		}
3009
3010		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
3011	<	static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
3011	>	static sigsegv_return_t sigsegv_insn_handler(sigsegv_info_t *sip)
3012		{
3013	+	const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip);
3014	+	const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip);
3015		#if DEBUG
3016		printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
3017		#endif
#	Line 2167 | Line 3019 | static sigsegv_return_t sigsegv_insn_han
3019		#ifdef __GNUC__
3020		// Make sure reported fault instruction address falls into
3021		// expected code range
3022	<	if (instruction_address != SIGSEGV_INVALID_PC
3022	>	if (instruction_address != SIGSEGV_INVALID_ADDRESS
3023		&& ((instruction_address <  (sigsegv_address_t)b_region) ||
3024		(instruction_address >= (sigsegv_address_t)e_region)))
3025		return SIGSEGV_RETURN_FAILURE;
#	Line 2253 | Line 3105 | int main(void)
3105
3106		if (!sigsegv_install_handler(sigsegv_test_handler))
3107		return 4;
3108	<
3108	>
3109		#ifdef __GNUC__
3110		b_region = &&L_b_region1;
3111		e_region = &&L_e_region1;
3112		#endif
3113	<	L_b_region1:
3114	<	page[REF_INDEX] = REF_VALUE;
3115	<	if (page[REF_INDEX] != REF_VALUE)
3116	<	exit(20);
3117	<	page[REF_INDEX] = REF_VALUE;
3118	<	BARRIER();
3119	<	L_e_region1:
3113	>	/* This is a really awful hack but otherwise gcc is smart enough
3114	>	* (or bug'ous enough?) to optimize the labels and place them
3115	>	* e.g. at the "main" entry point, which is wrong.
3116	>	*/
3117	>	volatile int label_hack = 1;
3118	>	switch (label_hack) {
3119	>	case 1:
3120	>	L_b_region1:
3121	>	page[REF_INDEX] = REF_VALUE;
3122	>	if (page[REF_INDEX] != REF_VALUE)
3123	>	exit(20);
3124	>	page[REF_INDEX] = REF_VALUE;
3125	>	BARRIER();
3126	>	// fall-through
3127	>	case 2:
3128	>	L_e_region1:
3129	>	BARRIER();
3130	>	break;
3131	>	}
3132
3133		if (handler_called != 1)
3134		return 5;
#	Line 2295 | Line 3159 | int main(void)
3159		b_region = &&L_b_region2;
3160		e_region = &&L_e_region2;
3161		#endif
3162	<	L_b_region2:
3163	<	TEST_SKIP_INSTRUCTION(unsigned char);
3164	<	TEST_SKIP_INSTRUCTION(unsigned short);
3165	<	TEST_SKIP_INSTRUCTION(unsigned int);
3166	<	TEST_SKIP_INSTRUCTION(unsigned long);
3167	<	TEST_SKIP_INSTRUCTION(signed char);
3168	<	TEST_SKIP_INSTRUCTION(signed short);
3169	<	TEST_SKIP_INSTRUCTION(signed int);
3170	<	TEST_SKIP_INSTRUCTION(signed long);
3171	<	BARRIER();
3172	<	L_e_region2:
3173	<
3162	>	switch (label_hack) {
3163	>	case 1:
3164	>	L_b_region2:
3165	>	TEST_SKIP_INSTRUCTION(unsigned char);
3166	>	TEST_SKIP_INSTRUCTION(unsigned short);
3167	>	TEST_SKIP_INSTRUCTION(unsigned int);
3168	>	TEST_SKIP_INSTRUCTION(unsigned long);
3169	>	TEST_SKIP_INSTRUCTION(signed char);
3170	>	TEST_SKIP_INSTRUCTION(signed short);
3171	>	TEST_SKIP_INSTRUCTION(signed int);
3172	>	TEST_SKIP_INSTRUCTION(signed long);
3173	>	BARRIER();
3174	>	// fall-through
3175	>	case 2:
3176	>	L_e_region2:
3177	>	BARRIER();
3178	>	break;
3179	>	}
3180		if (!arch_insn_skipper_tests())
3181		return 20;
3182		#endif

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