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root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.34 by gbeauche, 2003-11-10T23:47:39Z vs.
Revision 1.55 by gbeauche, 2005-03-23T22:00:06Z

#	Line 10 | Line 10
10		*    tjw@omnigroup.com Sun, 4 Jun 2000
11		*    www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	*  Basilisk II (C) 1997-2002 Christian Bauer
13	>	*  Basilisk II (C) 1997-2005 Christian Bauer
14		*
15		*  This program is free software; you can redistribute it and/or modify
16		*  it under the terms of the GNU General Public License as published by
#	Line 36 | Line 36
36		#endif
37
38		#include <list>
39	+	#include <stdio.h>
40		#include <signal.h>
41		#include "sigsegv.h"
42
#	Line 96 | Line 97 | struct instruction_t {
97		char                            ra, rd;
98		};
99
100	<	static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned int * gpr)
100	>	static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned long * gpr)
101		{
102		// Get opcode and divide into fields
103	<	unsigned int opcode = *((unsigned int *)nip);
103	>	unsigned int opcode = *((unsigned int *)(unsigned long)nip);
104		unsigned int primop = opcode >> 26;
105		unsigned int exop = (opcode >> 1) & 0x3ff;
106		unsigned int ra = (opcode >> 16) & 0x1f;
#	Line 173 | Line 174 | static void powerpc_decode_instruction(i
174		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break;
175		case 45:        // sthu
176		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break;
177	+	case 58:        // ld, ldu, lwa
178	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
179	+	transfer_size = SIZE_QUAD;
180	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
181	+	imm &= ~3;
182	+	break;
183	+	case 62:        // std, stdu, stq
184	+	transfer_type = SIGSEGV_TRANSFER_STORE;
185	+	transfer_size = SIZE_QUAD;
186	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
187	+	imm &= ~3;
188	+	break;
189		}
190
191		// Calculate effective address
#	Line 213 | Line 226 | static void powerpc_decode_instruction(i
226
227		#if HAVE_SIGINFO_T
228		// Generic extended signal handler
229	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
229	>	#if defined(__FreeBSD__)
230		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
231		#else
232		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
#	Line 222 | Line 235 | static void powerpc_decode_instruction(i
235		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t *sip, void *scp
236		#define SIGSEGV_FAULT_HANDLER_ARGS              sip, scp
237		#define SIGSEGV_FAULT_ADDRESS                   sip->si_addr
238	+	#if (defined(sgi) || defined(__sgi))
239	+	#include <ucontext.h>
240	+	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
241	+	#define SIGSEGV_FAULT_INSTRUCTION               (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
242	+	#if (defined(mips) || defined(__mips))
243	+	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
244	+	#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
245	+	#endif
246	+	#endif
247		#if defined(__sun__)
248		#if (defined(sparc) || defined(__sparc__))
249	+	#include <sys/stack.h>
250	+	#include <sys/regset.h>
251		#include <sys/ucontext.h>
252		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
253		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[REG_PC]
254	+	#define SIGSEGV_SPARC_GWINDOWS                  (((ucontext_t *)scp)->uc_mcontext.gwins)
255	+	#define SIGSEGV_SPARC_RWINDOW                   (struct rwindow *)((char *)SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
256	+	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
257	+	#define SIGSEGV_SKIP_INSTRUCTION                sparc_skip_instruction
258	+	#endif
259	+	#if defined(__i386__)
260	+	#include <sys/regset.h>
261	+	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
262	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[EIP]
263	+	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
264	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
265		#endif
266		#endif
267	<	#if defined(__FreeBSD__)
267	>	#if defined(__FreeBSD__) || defined(__OpenBSD__)
268		#if (defined(i386) || defined(__i386__))
269		#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_eip)
270		#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
271		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
272		#endif
273		#endif
274	+	#if defined(__NetBSD__)
275	+	#if (defined(i386) || defined(__i386__))
276	+	#include <sys/ucontext.h>
277	+	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.__gregs)
278	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[_REG_EIP]
279	+	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
280	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
281	+	#endif
282	+	#if (defined(powerpc) || defined(__powerpc__))
283	+	#include <sys/ucontext.h>
284	+	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.__gregs)
285	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[_REG_PC]
286	+	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_PC], (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_R0]
287	+	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
288	+	#endif
289	+	#endif
290		#if defined(__linux__)
291		#if (defined(i386) || defined(__i386__))
292		#include <sys/ucontext.h>
#	Line 258 | Line 309 | static void powerpc_decode_instruction(i
309		#include <sys/ucontext.h>
310		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.regs)
311		#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS->nip)
312	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned int *)(SIGSEGV_CONTEXT_REGS->gpr)
312	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned long *)(SIGSEGV_CONTEXT_REGS->gpr)
313		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
314		#endif
315	+	#if (defined(hppa) || defined(__hppa__))
316	+	#undef  SIGSEGV_FAULT_ADDRESS
317	+	#define SIGSEGV_FAULT_ADDRESS                   sip->si_ptr
318	+	#endif
319	+	#if (defined(arm) || defined(__arm__))
320	+	#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
321	+	#define SIGSEGV_CONTEXT_REGS                    (((struct ucontext *)scp)->uc_mcontext)
322	+	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS.arm_pc)
323	+	#define SIGSEGV_REGISTER_FILE                   (&SIGSEGV_CONTEXT_REGS.arm_r0)
324	+	#define SIGSEGV_SKIP_INSTRUCTION                arm_skip_instruction
325	+	#endif
326		#endif
327		#endif
328
#	Line 290 | Line 352 | static void powerpc_decode_instruction(i
352		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, scp
353		#define SIGSEGV_FAULT_ADDRESS                   scp->regs->dar
354		#define SIGSEGV_FAULT_INSTRUCTION               scp->regs->nip
355	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&scp->regs->nip, (unsigned int *)(scp->regs->gpr)
355	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&scp->regs->nip, (unsigned long *)(scp->regs->gpr)
356		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
357		#endif
358		#if (defined(alpha) || defined(__alpha__))
#	Line 300 | Line 362 | static void powerpc_decode_instruction(i
362		#define SIGSEGV_FAULT_ADDRESS                   get_fault_address(scp)
363		#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_pc
364		#endif
365	+	#if (defined(arm) || defined(__arm__))
366	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int r1, int r2, int r3, struct sigcontext sc
367	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp
368	+	#define SIGSEGV_FAULT_HANDLER_ARGS              &sc
369	+	#define SIGSEGV_FAULT_ADDRESS                   scp->fault_address
370	+	#define SIGSEGV_FAULT_INSTRUCTION               scp->arm_pc
371	+	#define SIGSEGV_REGISTER_FILE                   &scp->arm_r0
372	+	#define SIGSEGV_SKIP_INSTRUCTION                arm_skip_instruction
373	+	#endif
374		#endif
375
376		// Irix 5 or 6 on MIPS
377	<	#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(__SYSTYPE_SVR4))
377	>	#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(_SYSTYPE_SVR4))
378		#include <ucontext.h>
379		#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
380		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
381	<	#define SIGSEGV_FAULT_ADDRESS                   scp->sc_badvaddr
381	>	#define SIGSEGV_FAULT_ADDRESS                   (unsigned long)scp->sc_badvaddr
382	>	#define SIGSEGV_FAULT_INSTRUCTION               (unsigned long)scp->sc_pc
383		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
384		#endif
385
#	Line 380 | Line 452 | static sigsegv_address_t get_fault_addre
452		#endif
453		#endif
454		#if defined(__FreeBSD__)
383	–	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
455		#if (defined(i386) || defined(__i386__))
456	+	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
457		#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp, char *addr
458		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp, addr
459		#define SIGSEGV_FAULT_ADDRESS                   addr
#	Line 389 | Line 461 | static sigsegv_address_t get_fault_addre
461		#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&scp->sc_edi)
462		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
463		#endif
464	+	#if (defined(alpha) || defined(__alpha__))
465	+	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
466	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, char *addr, struct sigcontext *scp
467	+	#define SIGSEGV_FAULT_HANDLER_ARGS              sig, addr, scp
468	+	#define SIGSEGV_FAULT_ADDRESS                   addr
469	+	#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_pc
470	+	#endif
471		#endif
472
473		// Extract fault address out of a sigcontext
#	Line 437 | Line 516 | static sigsegv_address_t get_fault_addre
516		#endif
517		#endif
518
519	+	#if HAVE_WIN32_EXCEPTIONS
520	+	#define WIN32_LEAN_AND_MEAN /* avoid including junk */
521	+	#include <windows.h>
522	+	#include <winerror.h>
523	+
524	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
525	+	#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
526	+	#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
527	+	#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
528	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Eip
529	+	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
530	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
531	+	#endif
532	+
533		#if HAVE_MACH_EXCEPTIONS
534
535		// This can easily be extended to other Mach systems, but really who
#	Line 614 | Line 707 | enum {
707		#endif
708		};
709		#endif
710	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
710	>	#if defined(__NetBSD__)
711	>	enum {
712	>	#if (defined(i386) || defined(__i386__))
713	>	X86_REG_EIP = _REG_EIP,
714	>	X86_REG_EAX = _REG_EAX,
715	>	X86_REG_ECX = _REG_ECX,
716	>	X86_REG_EDX = _REG_EDX,
717	>	X86_REG_EBX = _REG_EBX,
718	>	X86_REG_ESP = _REG_ESP,
719	>	X86_REG_EBP = _REG_EBP,
720	>	X86_REG_ESI = _REG_ESI,
721	>	X86_REG_EDI = _REG_EDI
722	>	#endif
723	>	};
724	>	#endif
725	>	#if defined(__FreeBSD__)
726		enum {
727		#if (defined(i386) || defined(__i386__))
728		X86_REG_EIP = 10,
#	Line 629 | Line 737 | enum {
737		#endif
738		};
739		#endif
740	+	#if defined(__OpenBSD__)
741	+	enum {
742	+	#if defined(__i386__)
743	+	// EDI is the first register we consider
744	+	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
745	+	#define DREG(REG) ((OREG(REG) - OREG(edi)) / 4)
746	+	X86_REG_EIP = DREG(eip), // 7
747	+	X86_REG_EAX = DREG(eax), // 6
748	+	X86_REG_ECX = DREG(ecx), // 5
749	+	X86_REG_EDX = DREG(edx), // 4
750	+	X86_REG_EBX = DREG(ebx), // 3
751	+	X86_REG_ESP = DREG(esp), // 10
752	+	X86_REG_EBP = DREG(ebp), // 2
753	+	X86_REG_ESI = DREG(esi), // 1
754	+	X86_REG_EDI = DREG(edi)  // 0
755	+	#undef DREG
756	+	#undef OREG
757	+	#endif
758	+	};
759	+	#endif
760	+	#if defined(__sun__)
761	+	// Same as for Linux, need to check for x86-64
762	+	enum {
763	+	#if defined(__i386__)
764	+	X86_REG_EIP = EIP,
765	+	X86_REG_EAX = EAX,
766	+	X86_REG_ECX = ECX,
767	+	X86_REG_EDX = EDX,
768	+	X86_REG_EBX = EBX,
769	+	X86_REG_ESP = ESP,
770	+	X86_REG_EBP = EBP,
771	+	X86_REG_ESI = ESI,
772	+	X86_REG_EDI = EDI
773	+	#endif
774	+	};
775	+	#endif
776	+	#if defined(_WIN32)
777	+	enum {
778	+	#if (defined(i386) || defined(__i386__))
779	+	X86_REG_EIP = 7,
780	+	X86_REG_EAX = 5,
781	+	X86_REG_ECX = 4,
782	+	X86_REG_EDX = 3,
783	+	X86_REG_EBX = 2,
784	+	X86_REG_ESP = 10,
785	+	X86_REG_EBP = 6,
786	+	X86_REG_ESI = 1,
787	+	X86_REG_EDI = 0
788	+	#endif
789	+	};
790	+	#endif
791		// FIXME: this is partly redundant with the instruction decoding phase
792		// to discover transfer type and register number
793		static inline int ix86_step_over_modrm(unsigned char * p)
#	Line 669 | Line 828 | static bool ix86_skip_instruction(unsign
828
829		if (eip == 0)
830		return false;
831	+	#ifdef _WIN32
832	+	if (IsBadCodePtr((FARPROC)eip))
833	+	return false;
834	+	#endif
835
836		transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
837		transfer_size_t transfer_size = SIZE_LONG;
#	Line 722 | Line 885 | static bool ix86_skip_instruction(unsign
885		#endif
886
887		// Decode instruction
888	+	int target_size = SIZE_UNKNOWN;
889		switch (eip[0]) {
890		case 0x0f:
891	+	target_size = transfer_size;
892		switch (eip[1]) {
893	+	case 0xbe: // MOVSX r32, r/m8
894		case 0xb6: // MOVZX r32, r/m8
895	+	transfer_size = SIZE_BYTE;
896	+	goto do_mov_extend;
897	+	case 0xbf: // MOVSX r32, r/m16
898		case 0xb7: // MOVZX r32, r/m16
899	<	switch (eip[2] & 0xc0) {
900	<	case 0x80:
901	<	reg = (eip[2] >> 3) & 7;
902	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
903	<	break;
904	<	case 0x40:
905	<	reg = (eip[2] >> 3) & 7;
906	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
907	<	break;
908	<	case 0x00:
909	<	reg = (eip[2] >> 3) & 7;
910	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
911	<	break;
912	<	}
913	<	len += 3 + ix86_step_over_modrm(eip + 2);
914	<	break;
899	>	transfer_size = SIZE_WORD;
900	>	goto do_mov_extend;
901	>	do_mov_extend:
902	>	switch (eip[2] & 0xc0) {
903	>	case 0x80:
904	>	reg = (eip[2] >> 3) & 7;
905	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
906	>	break;
907	>	case 0x40:
908	>	reg = (eip[2] >> 3) & 7;
909	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
910	>	break;
911	>	case 0x00:
912	>	reg = (eip[2] >> 3) & 7;
913	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
914	>	break;
915	>	}
916	>	len += 3 + ix86_step_over_modrm(eip + 2);
917	>	break;
918		}
919		break;
920		case 0x8a: // MOV r8, r/m8
#	Line 784 | Line 956 | static bool ix86_skip_instruction(unsign
956		len += 2 + ix86_step_over_modrm(eip + 1);
957		break;
958		}
959	+	if (target_size == SIZE_UNKNOWN)
960	+	target_size = transfer_size;
961
962		if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
963		// Unknown machine code, let it crash. Then patch the decoder
#	Line 811 | Line 985 | static bool ix86_skip_instruction(unsign
985		// Set 0 to the relevant register part
986		// NOTE: this is only valid for MOV alike instructions
987		int rloc = x86_reg_map[reg];
988	<	switch (transfer_size) {
988	>	switch (target_size) {
989		case SIZE_BYTE:
990	<	if (!has_rex && reg >= 4)
991	<	regs[rloc - 4] = (regs[rloc - 4] & ~0xff00L);
992	<	else
993	<	regs[rloc] = (regs[rloc] & ~0xffL);
990	>	if (has_rex || reg < 4)
991	>	regs[rloc] = (regs[rloc] & ~0x00ffL);
992	>	else {
993	>	rloc = x86_reg_map[reg - 4];
994	>	regs[rloc] = (regs[rloc] & ~0xff00L);
995	>	}
996		break;
997		case SIZE_WORD:
998		regs[rloc] = (regs[rloc] & ~0xffffL);
#	Line 863 | Line 1039 | static bool ix86_skip_instruction(unsign
1039		"r12", "r13", "r14", "r15",
1040		};
1041		const char * reg_str = NULL;
1042	<	switch (transfer_size) {
1042	>	switch (target_size) {
1043		case SIZE_BYTE:
1044		reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
1045		break;
#	Line 886 | Line 1062 | static bool ix86_skip_instruction(unsign
1062
1063		// Decode and skip PPC instruction
1064		#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__))
1065	<	static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs)
1065	>	static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
1066		{
1067		instruction_t instr;
1068		powerpc_decode_instruction(&instr, *nip_p, regs);
#	Line 898 | Line 1074 | static bool powerpc_skip_instruction(uns
1074
1075		#if DEBUG
1076		printf("%08x: %s %s access", *nip_p,
1077	<	instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long",
1077	>	instr.transfer_size == SIZE_BYTE ? "byte" :
1078	>	instr.transfer_size == SIZE_WORD ? "word" :
1079	>	instr.transfer_size == SIZE_LONG ? "long" : "quad",
1080		instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1081
1082		if (instr.addr_mode == MODE_U || instr.addr_mode == MODE_UX)
#	Line 916 | Line 1094 | static bool powerpc_skip_instruction(uns
1094		return true;
1095		}
1096		#endif
1097	+
1098	+	// Decode and skip MIPS instruction
1099	+	#if (defined(mips) || defined(__mips))
1100	+	enum {
1101	+	#if (defined(sgi) || defined(__sgi))
1102	+	MIPS_REG_EPC = 35,
1103		#endif
1104	+	};
1105	+	static bool mips_skip_instruction(greg_t * regs)
1106	+	{
1107	+	unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC];
1108	+
1109	+	if (epc == 0)
1110	+	return false;
1111	+
1112	+	#if DEBUG
1113	+	printf("IP: %p [%08x]\n", epc, epc[0]);
1114	+	#endif
1115	+
1116	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1117	+	transfer_size_t transfer_size = SIZE_LONG;
1118	+	int direction = 0;
1119	+
1120	+	const unsigned int opcode = epc[0];
1121	+	switch (opcode >> 26) {
1122	+	case 32: // Load Byte
1123	+	case 36: // Load Byte Unsigned
1124	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1125	+	transfer_size = SIZE_BYTE;
1126	+	break;
1127	+	case 33: // Load Halfword
1128	+	case 37: // Load Halfword Unsigned
1129	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1130	+	transfer_size = SIZE_WORD;
1131	+	break;
1132	+	case 35: // Load Word
1133	+	case 39: // Load Word Unsigned
1134	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1135	+	transfer_size = SIZE_LONG;
1136	+	break;
1137	+	case 34: // Load Word Left
1138	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1139	+	transfer_size = SIZE_LONG;
1140	+	direction = -1;
1141	+	break;
1142	+	case 38: // Load Word Right
1143	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1144	+	transfer_size = SIZE_LONG;
1145	+	direction = 1;
1146	+	break;
1147	+	case 55: // Load Doubleword
1148	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1149	+	transfer_size = SIZE_QUAD;
1150	+	break;
1151	+	case 26: // Load Doubleword Left
1152	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1153	+	transfer_size = SIZE_QUAD;
1154	+	direction = -1;
1155	+	break;
1156	+	case 27: // Load Doubleword Right
1157	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1158	+	transfer_size = SIZE_QUAD;
1159	+	direction = 1;
1160	+	break;
1161	+	case 40: // Store Byte
1162	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1163	+	transfer_size = SIZE_BYTE;
1164	+	break;
1165	+	case 41: // Store Halfword
1166	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1167	+	transfer_size = SIZE_WORD;
1168	+	break;
1169	+	case 43: // Store Word
1170	+	case 42: // Store Word Left
1171	+	case 46: // Store Word Right
1172	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1173	+	transfer_size = SIZE_LONG;
1174	+	break;
1175	+	case 63: // Store Doubleword
1176	+	case 44: // Store Doubleword Left
1177	+	case 45: // Store Doubleword Right
1178	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1179	+	transfer_size = SIZE_QUAD;
1180	+	break;
1181	+	/* Misc instructions unlikely to be used within CPU emulators */
1182	+	case 48: // Load Linked Word
1183	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1184	+	transfer_size = SIZE_LONG;
1185	+	break;
1186	+	case 52: // Load Linked Doubleword
1187	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1188	+	transfer_size = SIZE_QUAD;
1189	+	break;
1190	+	case 56: // Store Conditional Word
1191	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1192	+	transfer_size = SIZE_LONG;
1193	+	break;
1194	+	case 60: // Store Conditional Doubleword
1195	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1196	+	transfer_size = SIZE_QUAD;
1197	+	break;
1198	+	}
1199	+
1200	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1201	+	// Unknown machine code, let it crash. Then patch the decoder
1202	+	return false;
1203	+	}
1204	+
1205	+	// Zero target register in case of a load operation
1206	+	const int reg = (opcode >> 16) & 0x1f;
1207	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD) {
1208	+	if (direction == 0)
1209	+	regs[reg] = 0;
1210	+	else {
1211	+	// FIXME: untested code
1212	+	unsigned long ea = regs[(opcode >> 21) & 0x1f];
1213	+	ea += (signed long)(signed int)(signed short)(opcode & 0xffff);
1214	+	const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7);
1215	+	unsigned long value;
1216	+	if (direction > 0) {
1217	+	const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1);
1218	+	value = regs[reg] & rmask;
1219	+	}
1220	+	else {
1221	+	const unsigned long lmask = (1L << (offset * 8)) - 1;
1222	+	value = regs[reg] & lmask;
1223	+	}
1224	+	// restore most significant bits
1225	+	if (transfer_size == SIZE_LONG)
1226	+	value = (signed long)(signed int)value;
1227	+	regs[reg] = value;
1228	+	}
1229	+	}
1230	+
1231	+	#if DEBUG
1232	+	#if (defined(_ABIN32) || defined(_ABI64))
1233	+	static const char * mips_gpr_names[32] = {
1234	+	"zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
1235	+	"t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
1236	+	"s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
1237	+	"t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
1238	+	};
1239	+	#else
1240	+	static const char * mips_gpr_names[32] = {
1241	+	"zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
1242	+	"a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
1243	+	"s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
1244	+	"t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
1245	+	};
1246	+	#endif
1247	+	printf("%s %s register %s\n",
1248	+	transfer_size == SIZE_BYTE ? "byte" :
1249	+	transfer_size == SIZE_WORD ? "word" :
1250	+	transfer_size == SIZE_LONG ? "long" :
1251	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1252	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1253	+	mips_gpr_names[reg]);
1254	+	#endif
1255	+
1256	+	regs[MIPS_REG_EPC] += 4;
1257	+	return true;
1258	+	}
1259	+	#endif
1260	+
1261	+	// Decode and skip SPARC instruction
1262	+	#if (defined(sparc) || defined(__sparc__))
1263	+	enum {
1264	+	#if (defined(__sun__))
1265	+	SPARC_REG_G1 = REG_G1,
1266	+	SPARC_REG_O0 = REG_O0,
1267	+	SPARC_REG_PC = REG_PC,
1268	+	#endif
1269	+	};
1270	+	static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
1271	+	{
1272	+	unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
1273	+
1274	+	if (pc == 0)
1275	+	return false;
1276	+
1277	+	#if DEBUG
1278	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1279	+	#endif
1280	+
1281	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1282	+	transfer_size_t transfer_size = SIZE_LONG;
1283	+	bool register_pair = false;
1284	+
1285	+	const unsigned int opcode = pc[0];
1286	+	if ((opcode >> 30) != 3)
1287	+	return false;
1288	+	switch ((opcode >> 19) & 0x3f) {
1289	+	case 9: // Load Signed Byte
1290	+	case 1: // Load Unsigned Byte
1291	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1292	+	transfer_size = SIZE_BYTE;
1293	+	break;
1294	+	case 10:// Load Signed Halfword
1295	+	case 2: // Load Unsigned Word
1296	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1297	+	transfer_size = SIZE_WORD;
1298	+	break;
1299	+	case 8: // Load Word
1300	+	case 0: // Load Unsigned Word
1301	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1302	+	transfer_size = SIZE_LONG;
1303	+	break;
1304	+	case 11:// Load Extended Word
1305	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1306	+	transfer_size = SIZE_QUAD;
1307	+	break;
1308	+	case 3: // Load Doubleword
1309	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1310	+	transfer_size = SIZE_LONG;
1311	+	register_pair = true;
1312	+	break;
1313	+	case 5: // Store Byte
1314	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1315	+	transfer_size = SIZE_BYTE;
1316	+	break;
1317	+	case 6: // Store Halfword
1318	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1319	+	transfer_size = SIZE_WORD;
1320	+	break;
1321	+	case 4: // Store Word
1322	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1323	+	transfer_size = SIZE_LONG;
1324	+	break;
1325	+	case 14:// Store Extended Word
1326	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1327	+	transfer_size = SIZE_QUAD;
1328	+	break;
1329	+	case 7: // Store Doubleword
1330	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1331	+	transfer_size = SIZE_WORD;
1332	+	register_pair = true;
1333	+	break;
1334	+	}
1335	+
1336	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1337	+	// Unknown machine code, let it crash. Then patch the decoder
1338	+	return false;
1339	+	}
1340	+
1341	+	// Zero target register in case of a load operation
1342	+	const int reg = (opcode >> 25) & 0x1f;
1343	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1344	+	// FIXME: code to handle local & input registers is not tested
1345	+	if (reg >= 1 && reg <= 7) {
1346	+	// global registers
1347	+	regs[reg - 1 + SPARC_REG_G1] = 0;
1348	+	}
1349	+	else if (reg >= 8 && reg <= 15) {
1350	+	// output registers
1351	+	regs[reg - 8 + SPARC_REG_O0] = 0;
1352	+	}
1353	+	else if (reg >= 16 && reg <= 23) {
1354	+	// local registers (in register windows)
1355	+	if (gwins)
1356	+	gwins->wbuf->rw_local[reg - 16] = 0;
1357	+	else
1358	+	rwin->rw_local[reg - 16] = 0;
1359	+	}
1360	+	else {
1361	+	// input registers (in register windows)
1362	+	if (gwins)
1363	+	gwins->wbuf->rw_in[reg - 24] = 0;
1364	+	else
1365	+	rwin->rw_in[reg - 24] = 0;
1366	+	}
1367	+	}
1368	+
1369	+	#if DEBUG
1370	+	static const char * reg_names[] = {
1371	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1372	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1373	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1374	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1375	+	};
1376	+	printf("%s %s register %s\n",
1377	+	transfer_size == SIZE_BYTE ? "byte" :
1378	+	transfer_size == SIZE_WORD ? "word" :
1379	+	transfer_size == SIZE_LONG ? "long" :
1380	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1381	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1382	+	reg_names[reg]);
1383	+	#endif
1384	+
1385	+	regs[SPARC_REG_PC] += 4;
1386	+	return true;
1387	+	}
1388	+	#endif
1389	+	#endif
1390	+
1391	+	// Decode and skip ARM instruction
1392	+	#if (defined(arm) || defined(__arm__))
1393	+	enum {
1394	+	#if (defined(__linux__))
1395	+	ARM_REG_PC = 15,
1396	+	ARM_REG_CPSR = 16
1397	+	#endif
1398	+	};
1399	+	static bool arm_skip_instruction(unsigned long * regs)
1400	+	{
1401	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
1402	+
1403	+	if (pc == 0)
1404	+	return false;
1405	+
1406	+	#if DEBUG
1407	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1408	+	#endif
1409	+
1410	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1411	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1412	+	enum { op_sdt = 1, op_sdth = 2 };
1413	+	int op = 0;
1414	+
1415	+	// Handle load/store instructions only
1416	+	const unsigned int opcode = pc[0];
1417	+	switch ((opcode >> 25) & 7) {
1418	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
1419	+	op = op_sdth;
1420	+	// Determine transfer size (S/H bits)
1421	+	switch ((opcode >> 5) & 3) {
1422	+	case 0: // SWP instruction
1423	+	break;
1424	+	case 1: // Unsigned halfwords
1425	+	case 3: // Signed halfwords
1426	+	transfer_size = SIZE_WORD;
1427	+	break;
1428	+	case 2: // Signed byte
1429	+	transfer_size = SIZE_BYTE;
1430	+	break;
1431	+	}
1432	+	break;
1433	+	case 2:
1434	+	case 3: // Single Data Transfer (LDR, STR)
1435	+	op = op_sdt;
1436	+	// Determine transfer size (B bit)
1437	+	if (((opcode >> 22) & 1) == 1)
1438	+	transfer_size = SIZE_BYTE;
1439	+	else
1440	+	transfer_size = SIZE_LONG;
1441	+	break;
1442	+	default:
1443	+	// FIXME: support load/store mutliple?
1444	+	return false;
1445	+	}
1446	+
1447	+	// Check for invalid transfer size (SWP instruction?)
1448	+	if (transfer_size == SIZE_UNKNOWN)
1449	+	return false;
1450	+
1451	+	// Determine transfer type (L bit)
1452	+	if (((opcode >> 20) & 1) == 1)
1453	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1454	+	else
1455	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1456	+
1457	+	// Compute offset
1458	+	int offset;
1459	+	if (((opcode >> 25) & 1) == 0) {
1460	+	if (op == op_sdt)
1461	+	offset = opcode & 0xfff;
1462	+	else if (op == op_sdth) {
1463	+	int rm = opcode & 0xf;
1464	+	if (((opcode >> 22) & 1) == 0) {
1465	+	// register offset
1466	+	offset = regs[rm];
1467	+	}
1468	+	else {
1469	+	// immediate offset
1470	+	offset = ((opcode >> 4) & 0xf0) | (opcode & 0x0f);
1471	+	}
1472	+	}
1473	+	}
1474	+	else {
1475	+	const int rm = opcode & 0xf;
1476	+	const int sh = (opcode >> 7) & 0x1f;
1477	+	if (((opcode >> 4) & 1) == 1) {
1478	+	// we expect only legal load/store instructions
1479	+	printf("FATAL: invalid shift operand\n");
1480	+	return false;
1481	+	}
1482	+	const unsigned int v = regs[rm];
1483	+	switch ((opcode >> 5) & 3) {
1484	+	case 0: // logical shift left
1485	+	offset = sh ? v << sh : v;
1486	+	break;
1487	+	case 1: // logical shift right
1488	+	offset = sh ? v >> sh : 0;
1489	+	break;
1490	+	case 2: // arithmetic shift right
1491	+	if (sh)
1492	+	offset = ((signed int)v) >> sh;
1493	+	else
1494	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
1495	+	break;
1496	+	case 3: // rotate right
1497	+	if (sh)
1498	+	offset = (v >> sh) | (v << (32 - sh));
1499	+	else
1500	+	offset = (v >> 1) | ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
1501	+	break;
1502	+	}
1503	+	}
1504	+	if (((opcode >> 23) & 1) == 0)
1505	+	offset = -offset;
1506	+
1507	+	int rd = (opcode >> 12) & 0xf;
1508	+	int rn = (opcode >> 16) & 0xf;
1509	+	#if DEBUG
1510	+	static const char * reg_names[] = {
1511	+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1512	+	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
1513	+	};
1514	+	printf("%s %s register %s\n",
1515	+	transfer_size == SIZE_BYTE ? "byte" :
1516	+	transfer_size == SIZE_WORD ? "word" :
1517	+	transfer_size == SIZE_LONG ? "long" : "unknown",
1518	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1519	+	reg_names[rd]);
1520	+	#endif
1521	+
1522	+	unsigned int base = regs[rn];
1523	+	if (((opcode >> 24) & 1) == 1)
1524	+	base += offset;
1525	+
1526	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
1527	+	regs[rd] = 0;
1528	+
1529	+	if (((opcode >> 24) & 1) == 0)                // post-index addressing
1530	+	regs[rn] += offset;
1531	+	else if (((opcode >> 21) & 1) == 1)   // write-back address into base
1532	+	regs[rn] = base;
1533	+
1534	+	regs[ARM_REG_PC] += 4;
1535	+	return true;
1536	+	}
1537	+	#endif
1538	+
1539
1540		// Fallbacks
1541		#ifndef SIGSEGV_FAULT_INSTRUCTION
#	Line 939 | Line 1558 | static bool powerpc_skip_instruction(uns
1558		*  SIGSEGV global handler
1559		*/
1560
942	–	#if defined(HAVE_SIGSEGV_RECOVERY) || defined(HAVE_MACH_EXCEPTIONS)
1561		// This function handles the badaccess to memory.
1562		// It is called from the signal handler or the exception handler.
1563		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
#	Line 973 | Line 1591 | static bool handle_badaccess(SIGSEGV_FAU
1591		}
1592		break;
1593		#endif
1594	+	case SIGSEGV_RETURN_FAILURE:
1595	+	// We can't do anything with the fault_address, dump state?
1596	+	if (sigsegv_state_dumper != 0)
1597	+	sigsegv_state_dumper(fault_address, fault_instruction);
1598	+	break;
1599		}
977	–
978	–	// We can't do anything with the fault_address, dump state?
979	–	if (sigsegv_state_dumper != 0)
980	–	sigsegv_state_dumper(fault_address, fault_instruction);
1600
1601		return false;
1602		}
984	–	#endif
1603
1604
1605		/*
#	Line 1275 | Line 1893 | static bool sigsegv_do_install_handler(s
1893		}
1894		#endif
1895
1896	+	#ifdef HAVE_WIN32_EXCEPTIONS
1897	+	static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo)
1898	+	{
1899	+	if (sigsegv_fault_handler != NULL
1900	+	&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
1901	+	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
1902	+	&& handle_badaccess(ExceptionInfo))
1903	+	return EXCEPTION_CONTINUE_EXECUTION;
1904	+
1905	+	return EXCEPTION_CONTINUE_SEARCH;
1906	+	}
1907	+
1908	+	#if defined __CYGWIN__ && defined __i386__
1909	+	/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin
1910	+	installs a global exception handler.  We have to dig deep in order to install
1911	+	our main_exception_filter.  */
1912	+
1913	+	/* Data structures for the current thread's exception handler chain.
1914	+	On the x86 Windows uses register fs, offset 0 to point to the current
1915	+	exception handler; Cygwin mucks with it, so we must do the same... :-/ */
1916	+
1917	+	/* Magic taken from winsup/cygwin/include/exceptions.h.  */
1918	+
1919	+	struct exception_list {
1920	+	struct exception_list *prev;
1921	+	int (*handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *);
1922	+	};
1923	+	typedef struct exception_list exception_list;
1924	+
1925	+	/* Magic taken from winsup/cygwin/exceptions.cc.  */
1926	+
1927	+	__asm__ (".equ __except_list,0");
1928	+
1929	+	extern exception_list *_except_list __asm__ ("%fs:__except_list");
1930	+
1931	+	/* For debugging.  _except_list is not otherwise accessible from gdb.  */
1932	+	static exception_list *
1933	+	debug_get_except_list ()
1934	+	{
1935	+	return _except_list;
1936	+	}
1937	+
1938	+	/* Cygwin's original exception handler.  */
1939	+	static int (*cygwin_exception_handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *);
1940	+
1941	+	/* Our exception handler.  */
1942	+	static int
1943	+	libsigsegv_exception_handler (EXCEPTION_RECORD *exception, void *frame, CONTEXT *context, void *dispatch)
1944	+	{
1945	+	EXCEPTION_POINTERS ExceptionInfo;
1946	+	ExceptionInfo.ExceptionRecord = exception;
1947	+	ExceptionInfo.ContextRecord = context;
1948	+	if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH)
1949	+	return cygwin_exception_handler (exception, frame, context, dispatch);
1950	+	else
1951	+	return 0;
1952	+	}
1953	+
1954	+	static void
1955	+	do_install_main_exception_filter ()
1956	+	{
1957	+	/* We cannot insert any handler into the chain, because such handlers
1958	+	must lie on the stack (?).  Instead, we have to replace(!) Cygwin's
1959	+	global exception handler.  */
1960	+	cygwin_exception_handler = _except_list->handler;
1961	+	_except_list->handler = libsigsegv_exception_handler;
1962	+	}
1963	+
1964	+	#else
1965	+
1966	+	static void
1967	+	do_install_main_exception_filter ()
1968	+	{
1969	+	SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter);
1970	+	}
1971	+	#endif
1972	+
1973	+	static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler)
1974	+	{
1975	+	static bool main_exception_filter_installed = false;
1976	+	if (!main_exception_filter_installed) {
1977	+	do_install_main_exception_filter();
1978	+	main_exception_filter_installed = true;
1979	+	}
1980	+	sigsegv_fault_handler = handler;
1981	+	return true;
1982	+	}
1983	+	#endif
1984	+
1985		bool sigsegv_install_handler(sigsegv_fault_handler_t handler)
1986		{
1987		#if defined(HAVE_SIGSEGV_RECOVERY)
#	Line 1285 | Line 1992 | bool sigsegv_install_handler(sigsegv_fau
1992		if (success)
1993		sigsegv_fault_handler = handler;
1994		return success;
1995	<	#elif defined(HAVE_MACH_EXCEPTIONS)
1995	>	#elif defined(HAVE_MACH_EXCEPTIONS) || defined(HAVE_WIN32_EXCEPTIONS)
1996		return sigsegv_do_install_handler(handler);
1997		#else
1998		// FAIL: no siginfo_t nor sigcontext subterfuge is available
#	Line 1311 | Line 2018 | void sigsegv_deinstall_handler(void)
2018		SIGSEGV_ALL_SIGNALS
2019		#undef FAULT_HANDLER
2020		#endif
2021	+	#ifdef HAVE_WIN32_EXCEPTIONS
2022	+	sigsegv_fault_handler = NULL;
2023	+	#endif
2024		}
2025
2026
#	Line 1332 | Line 2042 | void sigsegv_set_dump_state(sigsegv_stat
2042		#include <stdio.h>
2043		#include <stdlib.h>
2044		#include <fcntl.h>
2045	+	#ifdef HAVE_SYS_MMAN_H
2046		#include <sys/mman.h>
2047	+	#endif
2048		#include "vm_alloc.h"
2049
2050		const int REF_INDEX = 123;
#	Line 1349 | Line 2061 | static void *b_region, *e_region;
2061
2062		static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2063		{
2064	+	#if DEBUG
2065	+	printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
2066	+	printf("expected fault at %p\n", page + REF_INDEX);
2067	+	#ifdef __GNUC__
2068	+	printf("expected instruction address range: %p-%p\n", b_region, e_region);
2069	+	#endif
2070	+	#endif
2071		handler_called++;
2072		if ((fault_address - REF_INDEX) != page)
2073		exit(10);
#	Line 1368 | Line 2087 | static sigsegv_return_t sigsegv_test_han
2087		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
2088		static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2089		{
2090	+	#if DEBUG
2091	+	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
2092	+	#endif
2093		if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
2094		#ifdef __GNUC__
2095		// Make sure reported fault instruction address falls into
#	Line 1446 | Line 2168 | int main(void)
2168		if (vm_init() < 0)
2169		return 1;
2170
2171	<	page_size = getpagesize();
2171	>	page_size = vm_get_page_size();
2172		if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED)
2173		return 2;
2174
#	Line 1502 | Line 2224 | int main(void)
2224		TEST_SKIP_INSTRUCTION(unsigned short);
2225		TEST_SKIP_INSTRUCTION(unsigned int);
2226		TEST_SKIP_INSTRUCTION(unsigned long);
2227	+	TEST_SKIP_INSTRUCTION(signed char);
2228	+	TEST_SKIP_INSTRUCTION(signed short);
2229	+	TEST_SKIP_INSTRUCTION(signed int);
2230	+	TEST_SKIP_INSTRUCTION(signed long);
2231		L_e_region2:
1506	–	#endif
2232
2233		if (!arch_insn_skipper_tests())
2234		return 20;
2235	+	#endif
2236
2237		vm_exit();
2238		return 0;

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