[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.42 by gbeauche, 2004-01-19T16:59:13Z vs.
Revision 1.66 by gbeauche, 2007-06-16T06:21:57Z

#	Line 10 \| Line 10
10		* tjw@omnigroup.com Sun, 4 Jun 2000
11		* www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	* Basilisk II (C) 1997-2004 Christian Bauer
13	>	* Basilisk II (C) 1997-2005 Christian Bauer
14		*
15		* This program is free software; you can redistribute it and/or modify
16		* it under the terms of the GNU General Public License as published by
#	Line 66 \| Line 66 \| static bool sigsegv_do_install_handler(i
66		* Instruction decoding aids
67		*/
68
69	+	// Transfer type
70	+	enum transfer_type_t {
71	+	SIGSEGV_TRANSFER_UNKNOWN = 0,
72	+	SIGSEGV_TRANSFER_LOAD = 1,
73	+	SIGSEGV_TRANSFER_STORE = 2,
74	+	};
75	+
76		// Transfer size
77		enum transfer_size_t {
78		SIZE_UNKNOWN,
#	Line 75 \| Line 82 \| enum transfer_size_t {
82		SIZE_QUAD, // 8 bytes
83		};
84
78	–	// Transfer type
79	–	typedef sigsegv_transfer_type_t transfer_type_t;
80	–
85		#if (defined(powerpc) \|\| defined(__powerpc__) \|\| defined(__ppc__))
86		// Addressing mode
87		enum addressing_mode_t {
#	Line 97 \| Line 101 \| struct instruction_t {
101		char ra, rd;
102		};
103
104	<	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned int gpr)
104	>	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned long gpr)
105		{
106		// Get opcode and divide into fields
107	<	unsigned int opcode = ((unsigned int )nip);
107	>	unsigned int opcode = ((unsigned int )(unsigned long)nip);
108		unsigned int primop = opcode >> 26;
109		unsigned int exop = (opcode >> 1) & 0x3ff;
110		unsigned int ra = (opcode >> 16) & 0x1f;
#	Line 174 \| Line 178 \| static void powerpc_decode_instruction(i
178		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break;
179		case 45: // sthu
180		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break;
181	+	case 58: // ld, ldu, lwa
182	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
183	+	transfer_size = SIZE_QUAD;
184	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
185	+	imm &= ~3;
186	+	break;
187	+	case 62: // std, stdu, stq
188	+	transfer_type = SIGSEGV_TRANSFER_STORE;
189	+	transfer_size = SIZE_QUAD;
190	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
191	+	imm &= ~3;
192	+	break;
193		}
194
195		// Calculate effective address
#	Line 214 \| Line 230 \| static void powerpc_decode_instruction(i
230
231		#if HAVE_SIGINFO_T
232		// Generic extended signal handler
233	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
233	>	#if defined(__FreeBSD__)
234		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
235		#else
236		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
#	Line 228 \| Line 244 \| static void powerpc_decode_instruction(i
244		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
245		#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
246		#if (defined(mips) \|\| defined(__mips))
247	<	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
247	>	#define SIGSEGV_REGISTER_FILE &SIGSEGV_CONTEXT_REGS[CTX_EPC], &SIGSEGV_CONTEXT_REGS[CTX_R0]
248		#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
249		#endif
250		#endif
#	Line 244 \| Line 260 \| static void powerpc_decode_instruction(i
260		#define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
261		#define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction
262		#endif
263	+	#if defined(__i386__)
264	+	#include <sys/regset.h>
265	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
266	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[EIP]
267	+	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
268	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
269		#endif
270	<	#if defined(__FreeBSD__)
270	>	#endif
271	>	#if defined(__FreeBSD__) \|\| defined(__OpenBSD__)
272		#if (defined(i386) \|\| defined(__i386__))
273		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
274		#define SIGSEGV_REGISTER_FILE ((unsigned long )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
275		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
276		#endif
277		#endif
278	+	#if defined(__NetBSD__)
279	+	#if (defined(i386) \|\| defined(__i386__))
280	+	#include <sys/ucontext.h>
281	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
282	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP]
283	+	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
284	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
285	+	#endif
286	+	#if (defined(powerpc) \|\| defined(__powerpc__))
287	+	#include <sys/ucontext.h>
288	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
289	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_PC]
290	+	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIGSEGV_CONTEXT_REGS[_REG_PC], (unsigned long )&SIGSEGV_CONTEXT_REGS[_REG_R0]
291	+	#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
292	+	#endif
293	+	#endif
294		#if defined(__linux__)
295		#if (defined(i386) \|\| defined(__i386__))
296		#include <sys/ucontext.h>
#	Line 274 \| Line 313 \| static void powerpc_decode_instruction(i
313		#include <sys/ucontext.h>
314		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.regs)
315		#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->nip)
316	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&SIGSEGV_CONTEXT_REGS->nip, (unsigned int )(SIGSEGV_CONTEXT_REGS->gpr)
316	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIGSEGV_CONTEXT_REGS->nip, (unsigned long )(SIGSEGV_CONTEXT_REGS->gpr)
317		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
318		#endif
319		#if (defined(hppa) \|\| defined(__hppa__))
#	Line 285 \| Line 324 \| static void powerpc_decode_instruction(i
324		#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
325		#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext)
326		#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.arm_pc)
327	+	#define SIGSEGV_REGISTER_FILE (&SIGSEGV_CONTEXT_REGS.arm_r0)
328	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
329	+	#endif
330	+	#if (defined(mips) \|\| defined(__mips__))
331	+	#include <sys/ucontext.h>
332	+	#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext)
333	+	#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.pc)
334	+	#define SIGSEGV_REGISTER_FILE &SIGSEGV_CONTEXT_REGS.pc, &SIGSEGV_CONTEXT_REGS.gregs[0]
335	+	#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
336		#endif
337		#endif
338		#endif
#	Line 315 \| Line 363 \| static void powerpc_decode_instruction(i
363		#define SIGSEGV_FAULT_HANDLER_ARGS sig, scp
364		#define SIGSEGV_FAULT_ADDRESS scp->regs->dar
365		#define SIGSEGV_FAULT_INSTRUCTION scp->regs->nip
366	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&scp->regs->nip, (unsigned int )(scp->regs->gpr)
366	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&scp->regs->nip, (unsigned long )(scp->regs->gpr)
367		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
368		#endif
369		#if (defined(alpha) \|\| defined(__alpha__))
#	Line 331 \| Line 379 \| static void powerpc_decode_instruction(i
379		#define SIGSEGV_FAULT_HANDLER_ARGS &sc
380		#define SIGSEGV_FAULT_ADDRESS scp->fault_address
381		#define SIGSEGV_FAULT_INSTRUCTION scp->arm_pc
382	+	#define SIGSEGV_REGISTER_FILE &scp->arm_r0
383	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
384		#endif
385		#endif
386
#	Line 477 \| Line 527 \| static sigsegv_address_t get_fault_addre
527		#endif
528		#endif
529
530	+	#if HAVE_WIN32_EXCEPTIONS
531	+	#define WIN32_LEAN_AND_MEAN /* avoid including junk */
532	+	#include <windows.h>
533	+	#include <winerror.h>
534	+
535	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo
536	+	#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo
537	+	#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
538	+	#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord
539	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip
540	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
541	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
542	+	#endif
543	+
544		#if HAVE_MACH_EXCEPTIONS
545
546		// This can easily be extended to other Mach systems, but really who
#	Line 537 \| Line 601 \| if (ret != KERN_SUCCESS) { \
601		exit (1); \
602		}
603
604	<	#define SIGSEGV_FAULT_ADDRESS code[1]
605	<	#define SIGSEGV_FAULT_INSTRUCTION get_fault_instruction(thread, state)
606	<	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) ((code[0] == KERN_PROTECTION_FAILURE) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE)
607	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code, ppc_thread_state_t *state
608	<	#define SIGSEGV_FAULT_HANDLER_ARGS thread, code, &state
604	>	#ifdef __ppc__
605	>	#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state_t
606	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE
607	>	#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE_COUNT
608	>	#define SIGSEGV_FAULT_ADDRESS exc_state->dar
609	>	#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t
610	>	#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE
611	>	#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT
612	>	#define SIGSEGV_FAULT_INSTRUCTION state.srr0
613		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
614	<	#define SIGSEGV_REGISTER_FILE &state->srr0, &state->r0
615	<
616	<	// Given a suspended thread, stuff the current instruction and
617	<	// registers into state.
618	<	//
619	<	// It would have been nice to have this be ppc/x86 independant which
620	<	// could have been done easily with a thread_state_t instead of
621	<	// ppc_thread_state_t, but because of the way this is called it is
622	<	// easier to do it this way.
623	<	#if (defined(ppc) \|\| defined(__ppc__))
624	<	static inline sigsegv_address_t get_fault_instruction(mach_port_t thread, ppc_thread_state_t *state)
625	<	{
626	<	kern_return_t krc;
627	<	mach_msg_type_number_t count;
628	<
629	<	count = MACHINE_THREAD_STATE_COUNT;
630	<	krc = thread_get_state(thread, MACHINE_THREAD_STATE, (thread_state_t)state, &count);
631	<	MACH_CHECK_ERROR (thread_get_state, krc);
632	<
633	<	return (sigsegv_address_t)state->srr0;
634	<	}
614	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&state.srr0, (unsigned long )&state.r0
615	>	#endif
616	>	#ifdef __i386__
617	>	#ifdef i386_SAVED_STATE
618	>	#define SIGSEGV_THREAD_STATE_TYPE struct i386_saved_state
619	>	#define SIGSEGV_THREAD_STATE_FLAVOR i386_SAVED_STATE
620	>	#define SIGSEGV_THREAD_STATE_COUNT i386_SAVED_STATE_COUNT
621	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&state.edi) / EDI is the first GPR we consider */
622	>	#else
623	>	#define SIGSEGV_EXCEPTION_STATE_TYPE struct i386_exception_state
624	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR i386_EXCEPTION_STATE
625	>	#define SIGSEGV_EXCEPTION_STATE_COUNT i386_EXCEPTION_STATE_COUNT
626	>	#define SIGSEGV_FAULT_ADDRESS exc_state->faultvaddr
627	>	#define SIGSEGV_THREAD_STATE_TYPE struct i386_thread_state
628	>	#define SIGSEGV_THREAD_STATE_FLAVOR i386_THREAD_STATE
629	>	#define SIGSEGV_THREAD_STATE_COUNT i386_THREAD_STATE_COUNT
630	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&state.eax) / EAX is the first GPR we consider */
631	>	#endif
632	>	#define SIGSEGV_FAULT_INSTRUCTION state.eip
633	>	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
634	>	#endif
635	>	#ifdef __x86_64__
636	>	#define SIGSEGV_EXCEPTION_STATE_TYPE struct x86_exception_state64
637	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR x86_EXCEPTION_STATE64
638	>	#define SIGSEGV_EXCEPTION_STATE_COUNT x86_EXCEPTION_STATE64_COUNT
639	>	#define SIGSEGV_FAULT_ADDRESS exc_state->faultvaddr
640	>	#define SIGSEGV_THREAD_STATE_TYPE struct x86_thread_state64
641	>	#define SIGSEGV_THREAD_STATE_FLAVOR x86_THREAD_STATE64
642	>	#define SIGSEGV_THREAD_STATE_COUNT x86_THREAD_STATE64_COUNT
643	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&state.rax) / RAX is the first GPR we consider */
644	>	#define SIGSEGV_FAULT_INSTRUCTION state.rip
645	>	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
646	>	#endif
647	>	#ifdef SIGSEGV_EXCEPTION_STATE_TYPE
648	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, SIGSEGV_EXCEPTION_STATE_TYPE *exc_state
649	>	#define SIGSEGV_FAULT_HANDLER_ARGS thread, &exc_state
650	>	#else
651	>	#define SIGSEGV_FAULT_ADDRESS code[1]
652	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code
653	>	#define SIGSEGV_FAULT_HANDLER_ARGS thread, code
654		#endif
655
656		// Since there can only be one exception thread running at any time
#	Line 654 \| Line 741 \| enum {
741		#endif
742		};
743		#endif
744	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
744	>	#if defined(__NetBSD__)
745	>	enum {
746	>	#if (defined(i386) \|\| defined(__i386__))
747	>	X86_REG_EIP = _REG_EIP,
748	>	X86_REG_EAX = _REG_EAX,
749	>	X86_REG_ECX = _REG_ECX,
750	>	X86_REG_EDX = _REG_EDX,
751	>	X86_REG_EBX = _REG_EBX,
752	>	X86_REG_ESP = _REG_ESP,
753	>	X86_REG_EBP = _REG_EBP,
754	>	X86_REG_ESI = _REG_ESI,
755	>	X86_REG_EDI = _REG_EDI
756	>	#endif
757	>	};
758	>	#endif
759	>	#if defined(__FreeBSD__)
760		enum {
761		#if (defined(i386) \|\| defined(__i386__))
762		X86_REG_EIP = 10,
#	Line 669 \| Line 771 \| enum {
771		#endif
772		};
773		#endif
774	+	#if defined(__OpenBSD__)
775	+	enum {
776	+	#if defined(__i386__)
777	+	// EDI is the first register we consider
778	+	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
779	+	#define DREG(REG) ((OREG(REG) - OREG(edi)) / 4)
780	+	X86_REG_EIP = DREG(eip), // 7
781	+	X86_REG_EAX = DREG(eax), // 6
782	+	X86_REG_ECX = DREG(ecx), // 5
783	+	X86_REG_EDX = DREG(edx), // 4
784	+	X86_REG_EBX = DREG(ebx), // 3
785	+	X86_REG_ESP = DREG(esp), // 10
786	+	X86_REG_EBP = DREG(ebp), // 2
787	+	X86_REG_ESI = DREG(esi), // 1
788	+	X86_REG_EDI = DREG(edi) // 0
789	+	#undef DREG
790	+	#undef OREG
791	+	#endif
792	+	};
793	+	#endif
794	+	#if defined(__sun__)
795	+	// Same as for Linux, need to check for x86-64
796	+	enum {
797	+	#if defined(__i386__)
798	+	X86_REG_EIP = EIP,
799	+	X86_REG_EAX = EAX,
800	+	X86_REG_ECX = ECX,
801	+	X86_REG_EDX = EDX,
802	+	X86_REG_EBX = EBX,
803	+	X86_REG_ESP = ESP,
804	+	X86_REG_EBP = EBP,
805	+	X86_REG_ESI = ESI,
806	+	X86_REG_EDI = EDI
807	+	#endif
808	+	};
809	+	#endif
810	+	#if defined(__APPLE__) && defined(__MACH__)
811	+	enum {
812	+	#if (defined(i386) \|\| defined(__i386__))
813	+	#ifdef i386_SAVED_STATE
814	+	// same as FreeBSD (in Open Darwin 8.0.1)
815	+	X86_REG_EIP = 10,
816	+	X86_REG_EAX = 7,
817	+	X86_REG_ECX = 6,
818	+	X86_REG_EDX = 5,
819	+	X86_REG_EBX = 4,
820	+	X86_REG_ESP = 13,
821	+	X86_REG_EBP = 2,
822	+	X86_REG_ESI = 1,
823	+	X86_REG_EDI = 0
824	+	#else
825	+	// new layout (MacOS X 10.4.4 for x86)
826	+	X86_REG_EIP = 10,
827	+	X86_REG_EAX = 0,
828	+	X86_REG_ECX = 2,
829	+	X86_REG_EDX = 3,
830	+	X86_REG_EBX = 1,
831	+	X86_REG_ESP = 7,
832	+	X86_REG_EBP = 6,
833	+	X86_REG_ESI = 5,
834	+	X86_REG_EDI = 4
835	+	#endif
836	+	#endif
837	+	#if defined(__x86_64__)
838	+	X86_REG_R8 = 8,
839	+	X86_REG_R9 = 9,
840	+	X86_REG_R10 = 10,
841	+	X86_REG_R11 = 11,
842	+	X86_REG_R12 = 12,
843	+	X86_REG_R13 = 13,
844	+	X86_REG_R14 = 14,
845	+	X86_REG_R15 = 15,
846	+	X86_REG_EDI = 4,
847	+	X86_REG_ESI = 5,
848	+	X86_REG_EBP = 6,
849	+	X86_REG_EBX = 1,
850	+	X86_REG_EDX = 3,
851	+	X86_REG_EAX = 0,
852	+	X86_REG_ECX = 2,
853	+	X86_REG_ESP = 7,
854	+	X86_REG_EIP = 16
855	+	#endif
856	+	};
857	+	#endif
858	+	#if defined(_WIN32)
859	+	enum {
860	+	#if (defined(i386) \|\| defined(__i386__))
861	+	X86_REG_EIP = 7,
862	+	X86_REG_EAX = 5,
863	+	X86_REG_ECX = 4,
864	+	X86_REG_EDX = 3,
865	+	X86_REG_EBX = 2,
866	+	X86_REG_ESP = 10,
867	+	X86_REG_EBP = 6,
868	+	X86_REG_ESI = 1,
869	+	X86_REG_EDI = 0
870	+	#endif
871	+	};
872	+	#endif
873		// FIXME: this is partly redundant with the instruction decoding phase
874		// to discover transfer type and register number
875		static inline int ix86_step_over_modrm(unsigned char * p)
#	Line 709 \| Line 910 \| static bool ix86_skip_instruction(unsign
910
911		if (eip == 0)
912		return false;
913	+	#ifdef _WIN32
914	+	if (IsBadCodePtr((FARPROC)eip))
915	+	return false;
916	+	#endif
917
918	+	enum instruction_type_t {
919	+	i_MOV,
920	+	i_ADD
921	+	};
922	+
923		transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
924		transfer_size_t transfer_size = SIZE_LONG;
925	+	instruction_type_t instruction_type = i_MOV;
926
927		int reg = -1;
928		int len = 0;
#	Line 762 \| Line 973 \| static bool ix86_skip_instruction(unsign
973		#endif
974
975		// Decode instruction
976	+	int op_len = 1;
977	+	int target_size = SIZE_UNKNOWN;
978		switch (eip[0]) {
979		case 0x0f:
980	+	target_size = transfer_size;
981		switch (eip[1]) {
982	+	case 0xbe: // MOVSX r32, r/m8
983		case 0xb6: // MOVZX r32, r/m8
984	+	transfer_size = SIZE_BYTE;
985	+	goto do_mov_extend;
986	+	case 0xbf: // MOVSX r32, r/m16
987		case 0xb7: // MOVZX r32, r/m16
988	<	switch (eip[2] & 0xc0) {
989	<	case 0x80:
990	<	reg = (eip[2] >> 3) & 7;
991	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
992	<	break;
775	<	case 0x40:
776	<	reg = (eip[2] >> 3) & 7;
777	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
778	<	break;
779	<	case 0x00:
780	<	reg = (eip[2] >> 3) & 7;
781	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
782	<	break;
988	>	transfer_size = SIZE_WORD;
989	>	goto do_mov_extend;
990	>	do_mov_extend:
991	>	op_len = 2;
992	>	goto do_transfer_load;
993		}
784	–	len += 3 + ix86_step_over_modrm(eip + 2);
994		break;
995	<	}
996	<	break;
995	>	#if defined(__x86_64__)
996	>	case 0x63: // MOVSXD r64, r/m32
997	>	if (has_rex && rex.W) {
998	>	transfer_size = SIZE_LONG;
999	>	target_size = SIZE_QUAD;
1000	>	}
1001	>	else if (transfer_size != SIZE_WORD) {
1002	>	transfer_size = SIZE_LONG;
1003	>	target_size = SIZE_QUAD;
1004	>	}
1005	>	goto do_transfer_load;
1006	>	#endif
1007	>	case 0x02: // ADD r8, r/m8
1008	>	transfer_size = SIZE_BYTE;
1009	>	case 0x03: // ADD r32, r/m32
1010	>	instruction_type = i_ADD;
1011	>	goto do_transfer_load;
1012		case 0x8a: // MOV r8, r/m8
1013		transfer_size = SIZE_BYTE;
1014		case 0x8b: // MOV r32, r/m32 (or 16-bit operation)
1015	<	switch (eip[1] & 0xc0) {
1015	>	do_transfer_load:
1016	>	switch (eip[op_len] & 0xc0) {
1017		case 0x80:
1018	<	reg = (eip[1] >> 3) & 7;
1018	>	reg = (eip[op_len] >> 3) & 7;
1019		transfer_type = SIGSEGV_TRANSFER_LOAD;
1020		break;
1021		case 0x40:
1022	<	reg = (eip[1] >> 3) & 7;
1022	>	reg = (eip[op_len] >> 3) & 7;
1023		transfer_type = SIGSEGV_TRANSFER_LOAD;
1024		break;
1025		case 0x00:
1026	<	reg = (eip[1] >> 3) & 7;
1026	>	reg = (eip[op_len] >> 3) & 7;
1027		transfer_type = SIGSEGV_TRANSFER_LOAD;
1028		break;
1029		}
1030	<	len += 2 + ix86_step_over_modrm(eip + 1);
1030	>	len += 1 + op_len + ix86_step_over_modrm(eip + op_len);
1031		break;
1032	+	case 0x00: // ADD r/m8, r8
1033	+	transfer_size = SIZE_BYTE;
1034	+	case 0x01: // ADD r/m32, r32
1035	+	instruction_type = i_ADD;
1036	+	goto do_transfer_store;
1037		case 0x88: // MOV r/m8, r8
1038		transfer_size = SIZE_BYTE;
1039		case 0x89: // MOV r/m32, r32 (or 16-bit operation)
1040	<	switch (eip[1] & 0xc0) {
1040	>	do_transfer_store:
1041	>	switch (eip[op_len] & 0xc0) {
1042		case 0x80:
1043	<	reg = (eip[1] >> 3) & 7;
1043	>	reg = (eip[op_len] >> 3) & 7;
1044		transfer_type = SIGSEGV_TRANSFER_STORE;
1045		break;
1046		case 0x40:
1047	<	reg = (eip[1] >> 3) & 7;
1047	>	reg = (eip[op_len] >> 3) & 7;
1048		transfer_type = SIGSEGV_TRANSFER_STORE;
1049		break;
1050		case 0x00:
1051	<	reg = (eip[1] >> 3) & 7;
1051	>	reg = (eip[op_len] >> 3) & 7;
1052		transfer_type = SIGSEGV_TRANSFER_STORE;
1053		break;
1054		}
1055	<	len += 2 + ix86_step_over_modrm(eip + 1);
1055	>	len += 1 + op_len + ix86_step_over_modrm(eip + op_len);
1056		break;
1057		}
1058	+	if (target_size == SIZE_UNKNOWN)
1059	+	target_size = transfer_size;
1060
1061		if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1062		// Unknown machine code, let it crash. Then patch the decoder
#	Line 835 \| Line 1068 \| static bool ix86_skip_instruction(unsign
1068		reg += 8;
1069		#endif
1070
1071	<	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
1071	>	if (instruction_type == i_MOV && transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
1072		static const int x86_reg_map[] = {
1073		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
1074		X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
#	Line 851 \| Line 1084 \| static bool ix86_skip_instruction(unsign
1084		// Set 0 to the relevant register part
1085		// NOTE: this is only valid for MOV alike instructions
1086		int rloc = x86_reg_map[reg];
1087	<	switch (transfer_size) {
1087	>	switch (target_size) {
1088		case SIZE_BYTE:
1089		if (has_rex \|\| reg < 4)
1090		regs[rloc] = (regs[rloc] & ~0x00ffL);
#	Line 871 \| Line 1104 \| static bool ix86_skip_instruction(unsign
1104		}
1105
1106		#if DEBUG
1107	<	printf("%08x: %s %s access", regs[X86_REG_EIP],
1107	>	printf("%p: %s %s access", (void *)regs[X86_REG_EIP],
1108		transfer_size == SIZE_BYTE ? "byte" :
1109		transfer_size == SIZE_WORD ? "word" :
1110		transfer_size == SIZE_LONG ? "long" :
#	Line 905 \| Line 1138 \| static bool ix86_skip_instruction(unsign
1138		"r12", "r13", "r14", "r15",
1139		};
1140		const char * reg_str = NULL;
1141	<	switch (transfer_size) {
1141	>	switch (target_size) {
1142		case SIZE_BYTE:
1143		reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
1144		break;
#	Line 928 \| Line 1161 \| static bool ix86_skip_instruction(unsign
1161
1162		// Decode and skip PPC instruction
1163		#if (defined(powerpc) \|\| defined(__powerpc__) \|\| defined(__ppc__))
1164	<	static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs)
1164	>	static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
1165		{
1166		instruction_t instr;
1167		powerpc_decode_instruction(&instr, *nip_p, regs);
#	Line 940 \| Line 1173 \| static bool powerpc_skip_instruction(uns
1173
1174		#if DEBUG
1175		printf("%08x: %s %s access", *nip_p,
1176	<	instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long",
1176	>	instr.transfer_size == SIZE_BYTE ? "byte" :
1177	>	instr.transfer_size == SIZE_WORD ? "word" :
1178	>	instr.transfer_size == SIZE_LONG ? "long" : "quad",
1179		instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1180
1181		if (instr.addr_mode == MODE_U \|\| instr.addr_mode == MODE_UX)
#	Line 961 \| Line 1196 \| static bool powerpc_skip_instruction(uns
1196
1197		// Decode and skip MIPS instruction
1198		#if (defined(mips) \|\| defined(__mips))
1199	<	enum {
965	<	#if (defined(sgi) \|\| defined(__sgi))
966	<	MIPS_REG_EPC = 35,
967	<	#endif
968	<	};
969	<	static bool mips_skip_instruction(greg_t * regs)
1199	>	static bool mips_skip_instruction(greg_t * pc_p, greg_t * regs)
1200		{
1201	<	unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC];
1201	>	unsigned int * epc = (unsigned int )(unsigned long)pc_p;
1202
1203		if (epc == 0)
1204		return false;
#	Line 1117 \| Line 1347 \| static bool mips_skip_instruction(greg_t
1347		mips_gpr_names[reg]);
1348		#endif
1349
1350	<	regs[MIPS_REG_EPC] += 4;
1350	>	*pc_p += 4;
1351		return true;
1352		}
1353		#endif
#	Line 1129 \| Line 1359 \| enum {
1359		SPARC_REG_G1 = REG_G1,
1360		SPARC_REG_O0 = REG_O0,
1361		SPARC_REG_PC = REG_PC,
1362	+	SPARC_REG_nPC = REG_nPC
1363		#endif
1364		};
1365		static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
#	Line 1192 \| Line 1423 \| static bool sparc_skip_instruction(unsig
1423		break;
1424		case 7: // Store Doubleword
1425		transfer_type = SIGSEGV_TRANSFER_STORE;
1426	<	transfer_size = SIZE_WORD;
1426	>	transfer_size = SIZE_LONG;
1427		register_pair = true;
1428		break;
1429		}
#	Line 1202 \| Line 1433 \| static bool sparc_skip_instruction(unsig
1433		return false;
1434		}
1435
1205	–	// Zero target register in case of a load operation
1436		const int reg = (opcode >> 25) & 0x1f;
1437	+
1438	+	#if DEBUG
1439	+	static const char * reg_names[] = {
1440	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1441	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1442	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1443	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1444	+	};
1445	+	printf("%s %s register %s\n",
1446	+	transfer_size == SIZE_BYTE ? "byte" :
1447	+	transfer_size == SIZE_WORD ? "word" :
1448	+	transfer_size == SIZE_LONG ? "long" :
1449	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1450	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1451	+	reg_names[reg]);
1452	+	#endif
1453	+
1454	+	// Zero target register in case of a load operation
1455		if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1456		// FIXME: code to handle local & input registers is not tested
1457	<	if (reg >= 1 && reg <= 7) {
1457	>	if (reg >= 1 && reg < 8) {
1458		// global registers
1459		regs[reg - 1 + SPARC_REG_G1] = 0;
1460		}
1461	<	else if (reg >= 8 && reg <= 15) {
1461	>	else if (reg >= 8 && reg < 16) {
1462		// output registers
1463		regs[reg - 8 + SPARC_REG_O0] = 0;
1464		}
1465	<	else if (reg >= 16 && reg <= 23) {
1465	>	else if (reg >= 16 && reg < 24) {
1466		// local registers (in register windows)
1467		if (gwins)
1468		gwins->wbuf->rw_local[reg - 16] = 0;
#	Line 1230 \| Line 1478 \| static bool sparc_skip_instruction(unsig
1478		}
1479		}
1480
1481	+	regs[SPARC_REG_PC] += 4;
1482	+	regs[SPARC_REG_nPC] += 4;
1483	+	return true;
1484	+	}
1485	+	#endif
1486	+	#endif
1487	+
1488	+	// Decode and skip ARM instruction
1489	+	#if (defined(arm) \|\| defined(__arm__))
1490	+	enum {
1491	+	#if (defined(__linux__))
1492	+	ARM_REG_PC = 15,
1493	+	ARM_REG_CPSR = 16
1494	+	#endif
1495	+	};
1496	+	static bool arm_skip_instruction(unsigned long * regs)
1497	+	{
1498	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
1499	+
1500	+	if (pc == 0)
1501	+	return false;
1502	+
1503	+	#if DEBUG
1504	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1505	+	#endif
1506	+
1507	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1508	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1509	+	enum { op_sdt = 1, op_sdth = 2 };
1510	+	int op = 0;
1511	+
1512	+	// Handle load/store instructions only
1513	+	const unsigned int opcode = pc[0];
1514	+	switch ((opcode >> 25) & 7) {
1515	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
1516	+	op = op_sdth;
1517	+	// Determine transfer size (S/H bits)
1518	+	switch ((opcode >> 5) & 3) {
1519	+	case 0: // SWP instruction
1520	+	break;
1521	+	case 1: // Unsigned halfwords
1522	+	case 3: // Signed halfwords
1523	+	transfer_size = SIZE_WORD;
1524	+	break;
1525	+	case 2: // Signed byte
1526	+	transfer_size = SIZE_BYTE;
1527	+	break;
1528	+	}
1529	+	break;
1530	+	case 2:
1531	+	case 3: // Single Data Transfer (LDR, STR)
1532	+	op = op_sdt;
1533	+	// Determine transfer size (B bit)
1534	+	if (((opcode >> 22) & 1) == 1)
1535	+	transfer_size = SIZE_BYTE;
1536	+	else
1537	+	transfer_size = SIZE_LONG;
1538	+	break;
1539	+	default:
1540	+	// FIXME: support load/store mutliple?
1541	+	return false;
1542	+	}
1543	+
1544	+	// Check for invalid transfer size (SWP instruction?)
1545	+	if (transfer_size == SIZE_UNKNOWN)
1546	+	return false;
1547	+
1548	+	// Determine transfer type (L bit)
1549	+	if (((opcode >> 20) & 1) == 1)
1550	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1551	+	else
1552	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1553	+
1554	+	// Compute offset
1555	+	int offset;
1556	+	if (((opcode >> 25) & 1) == 0) {
1557	+	if (op == op_sdt)
1558	+	offset = opcode & 0xfff;
1559	+	else if (op == op_sdth) {
1560	+	int rm = opcode & 0xf;
1561	+	if (((opcode >> 22) & 1) == 0) {
1562	+	// register offset
1563	+	offset = regs[rm];
1564	+	}
1565	+	else {
1566	+	// immediate offset
1567	+	offset = ((opcode >> 4) & 0xf0) \| (opcode & 0x0f);
1568	+	}
1569	+	}
1570	+	}
1571	+	else {
1572	+	const int rm = opcode & 0xf;
1573	+	const int sh = (opcode >> 7) & 0x1f;
1574	+	if (((opcode >> 4) & 1) == 1) {
1575	+	// we expect only legal load/store instructions
1576	+	printf("FATAL: invalid shift operand\n");
1577	+	return false;
1578	+	}
1579	+	const unsigned int v = regs[rm];
1580	+	switch ((opcode >> 5) & 3) {
1581	+	case 0: // logical shift left
1582	+	offset = sh ? v << sh : v;
1583	+	break;
1584	+	case 1: // logical shift right
1585	+	offset = sh ? v >> sh : 0;
1586	+	break;
1587	+	case 2: // arithmetic shift right
1588	+	if (sh)
1589	+	offset = ((signed int)v) >> sh;
1590	+	else
1591	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
1592	+	break;
1593	+	case 3: // rotate right
1594	+	if (sh)
1595	+	offset = (v >> sh) \| (v << (32 - sh));
1596	+	else
1597	+	offset = (v >> 1) \| ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
1598	+	break;
1599	+	}
1600	+	}
1601	+	if (((opcode >> 23) & 1) == 0)
1602	+	offset = -offset;
1603	+
1604	+	int rd = (opcode >> 12) & 0xf;
1605	+	int rn = (opcode >> 16) & 0xf;
1606		#if DEBUG
1607		static const char * reg_names[] = {
1608	<	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1609	<	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1237	<	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1238	<	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1608	>	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1609	>	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
1610		};
1611		printf("%s %s register %s\n",
1612		transfer_size == SIZE_BYTE ? "byte" :
1613		transfer_size == SIZE_WORD ? "word" :
1614	<	transfer_size == SIZE_LONG ? "long" :
1244	<	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1614	>	transfer_size == SIZE_LONG ? "long" : "unknown",
1615		transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1616	<	reg_names[reg]);
1616	>	reg_names[rd]);
1617		#endif
1618
1619	<	regs[SPARC_REG_PC] += 4;
1619	>	unsigned int base = regs[rn];
1620	>	if (((opcode >> 24) & 1) == 1)
1621	>	base += offset;
1622	>
1623	>	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
1624	>	regs[rd] = 0;
1625	>
1626	>	if (((opcode >> 24) & 1) == 0) // post-index addressing
1627	>	regs[rn] += offset;
1628	>	else if (((opcode >> 21) & 1) == 1) // write-back address into base
1629	>	regs[rn] = base;
1630	>
1631	>	regs[ARM_REG_PC] += 4;
1632		return true;
1633		}
1634		#endif
1635	<	#endif
1635	>
1636
1637		// Fallbacks
1638		#ifndef SIGSEGV_FAULT_INSTRUCTION
#	Line 1273 \| Line 1655 \| static bool sparc_skip_instruction(unsig
1655		* SIGSEGV global handler
1656		*/
1657
1276	–	#if defined(HAVE_SIGSEGV_RECOVERY) \|\| defined(HAVE_MACH_EXCEPTIONS)
1658		// This function handles the badaccess to memory.
1659		// It is called from the signal handler or the exception handler.
1660		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
1661		{
1662	+	#ifdef HAVE_MACH_EXCEPTIONS
1663	+	// We must match the initial count when writing back the CPU state registers
1664	+	kern_return_t krc;
1665	+	mach_msg_type_number_t count;
1666	+	SIGSEGV_THREAD_STATE_TYPE state;
1667	+
1668	+	count = SIGSEGV_THREAD_STATE_COUNT;
1669	+	krc = thread_get_state(thread, SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)&state, &count);
1670	+	MACH_CHECK_ERROR (thread_get_state, krc);
1671	+	#endif
1672	+
1673		sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
1674		sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
1675
#	Line 1296 \| Line 1688 \| static bool handle_badaccess(SIGSEGV_FAU
1688		// is modified off of the stack, in Mach we
1689		// need to actually call thread_set_state to
1690		// have the register values updated.
1299	–	kern_return_t krc;
1300	–
1691		krc = thread_set_state(thread,
1692	<	MACHINE_THREAD_STATE, (thread_state_t)state,
1693	<	MACHINE_THREAD_STATE_COUNT);
1694	<	MACH_CHECK_ERROR (thread_get_state, krc);
1692	>	SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)&state,
1693	>	count);
1694	>	MACH_CHECK_ERROR (thread_set_state, krc);
1695		#endif
1696		return true;
1697		}
1698		break;
1699		#endif
1700	+	case SIGSEGV_RETURN_FAILURE:
1701	+	// We can't do anything with the fault_address, dump state?
1702	+	if (sigsegv_state_dumper != 0)
1703	+	sigsegv_state_dumper(fault_address, fault_instruction);
1704	+	break;
1705		}
1311	–
1312	–	// We can't do anything with the fault_address, dump state?
1313	–	if (sigsegv_state_dumper != 0)
1314	–	sigsegv_state_dumper(fault_address, fault_instruction);
1706
1707		return false;
1708		}
1318	–	#endif
1709
1710
1711		/*
#	Line 1352 \| Line 1742 \| forward_exception(mach_port_t thread_por
1742		mach_port_t port;
1743		exception_behavior_t behavior;
1744		thread_state_flavor_t flavor;
1745	<	thread_state_t thread_state;
1745	>	thread_state_data_t thread_state;
1746		mach_msg_type_number_t thread_state_count;
1747
1748		for (portIndex = 0; portIndex < oldExceptionPorts->maskCount; portIndex++) {
#	Line 1371 \| Line 1761 \| forward_exception(mach_port_t thread_por
1761		behavior = oldExceptionPorts->behaviors[portIndex];
1762		flavor = oldExceptionPorts->flavors[portIndex];
1763
1764	+	if (!VALID_THREAD_STATE_FLAVOR(flavor)) {
1765	+	fprintf(stderr, "Invalid thread_state flavor = %d. Not forwarding\n", flavor);
1766	+	return KERN_FAILURE;
1767	+	}
1768	+
1769		/*
1770		fprintf(stderr, "forwarding exception, port = 0x%x, behaviour = %d, flavor = %d\n", port, behavior, flavor);
1771		*/
1772
1773		if (behavior != EXCEPTION_DEFAULT) {
1774		thread_state_count = THREAD_STATE_MAX;
1775	<	kret = thread_get_state (thread_port, flavor, thread_state,
1775	>	kret = thread_get_state (thread_port, flavor, (natural_t *)&thread_state,
1776		&thread_state_count);
1777		MACH_CHECK_ERROR (thread_get_state, kret);
1778		}
#	Line 1393 \| Line 1788 \| forward_exception(mach_port_t thread_por
1788		// fprintf(stderr, "forwarding to exception_raise_state\n");
1789		kret = exception_raise_state(port, exception_type, exception_data,
1790		data_count, &flavor,
1791	<	thread_state, thread_state_count,
1792	<	thread_state, &thread_state_count);
1791	>	(natural_t *)&thread_state, thread_state_count,
1792	>	(natural_t *)&thread_state, &thread_state_count);
1793		MACH_CHECK_ERROR (exception_raise_state, kret);
1794		break;
1795		case EXCEPTION_STATE_IDENTITY:
#	Line 1402 \| Line 1797 \| forward_exception(mach_port_t thread_por
1797		kret = exception_raise_state_identity(port, thread_port, task_port,
1798		exception_type, exception_data,
1799		data_count, &flavor,
1800	<	thread_state, thread_state_count,
1801	<	thread_state, &thread_state_count);
1800	>	(natural_t *)&thread_state, thread_state_count,
1801	>	(natural_t *)&thread_state, &thread_state_count);
1802		MACH_CHECK_ERROR (exception_raise_state_identity, kret);
1803		break;
1804		default:
1805		fprintf(stderr, "forward_exception got unknown behavior\n");
1806	+	kret = KERN_FAILURE;
1807		break;
1808		}
1809
1810		if (behavior != EXCEPTION_DEFAULT) {
1811	<	kret = thread_set_state (thread_port, flavor, thread_state,
1811	>	kret = thread_set_state (thread_port, flavor, (natural_t *)&thread_state,
1812		thread_state_count);
1813		MACH_CHECK_ERROR (thread_set_state, kret);
1814		}
1815
1816	<	return KERN_SUCCESS;
1816	>	return kret;
1817		}
1818
1819		/*
#	Line 1445 \| Line 1841 \| catch_exception_raise(mach_port_t except
1841		mach_port_t task,
1842		exception_type_t exception,
1843		exception_data_t code,
1844	<	mach_msg_type_number_t codeCount)
1844	>	mach_msg_type_number_t code_count)
1845		{
1450	–	ppc_thread_state_t state;
1846		kern_return_t krc;
1847
1848	<	if ((exception == EXC_BAD_ACCESS) && (codeCount >= 2)) {
1849	<	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
1850	<	return KERN_SUCCESS;
1848	>	if (exception == EXC_BAD_ACCESS) {
1849	>	switch (code[0]) {
1850	>	case KERN_PROTECTION_FAILURE:
1851	>	case KERN_INVALID_ADDRESS:
1852	>	{
1853	>	#ifdef SIGSEGV_EXCEPTION_STATE_TYPE
1854	>	SIGSEGV_EXCEPTION_STATE_TYPE exc_state;
1855	>	mach_msg_type_number_t exc_state_count;
1856	>	exc_state_count = SIGSEGV_EXCEPTION_STATE_COUNT;
1857	>	krc = thread_get_state(thread, SIGSEGV_EXCEPTION_STATE_FLAVOR, (natural_t *)&exc_state, &exc_state_count);
1858	>	MACH_CHECK_ERROR (thread_get_state, krc);
1859	>	#endif
1860	>
1861	>	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
1862	>	return KERN_SUCCESS;
1863	>	break;
1864	>	}
1865	>	}
1866		}
1867
1868		// In Mach we do not need to remove the exception handler.
1869		// If we forward the exception, eventually some exception handler
1870		// will take care of this exception.
1871	<	krc = forward_exception(thread, task, exception, code, codeCount, &ports);
1871	>	krc = forward_exception(thread, task, exception, code, code_count, &ports);
1872
1873		return krc;
1874		}
#	Line 1586 \| Line 1996 \| static bool sigsegv_do_install_handler(s
1996		// addressing modes) used in PPC instructions, you will need the
1997		// GPR state anyway.
1998		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
1999	<	EXCEPTION_DEFAULT, MACHINE_THREAD_STATE);
1999	>	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
2000		if (krc != KERN_SUCCESS) {
2001		mach_error("thread_set_exception_ports", krc);
2002		return false;
#	Line 1609 \| Line 2019 \| static bool sigsegv_do_install_handler(s
2019		}
2020		#endif
2021
2022	+	#ifdef HAVE_WIN32_EXCEPTIONS
2023	+	static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo)
2024	+	{
2025	+	if (sigsegv_fault_handler != NULL
2026	+	&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
2027	+	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
2028	+	&& handle_badaccess(ExceptionInfo))
2029	+	return EXCEPTION_CONTINUE_EXECUTION;
2030	+
2031	+	return EXCEPTION_CONTINUE_SEARCH;
2032	+	}
2033	+
2034	+	#if defined __CYGWIN__ && defined __i386__
2035	+	/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin
2036	+	installs a global exception handler. We have to dig deep in order to install
2037	+	our main_exception_filter. */
2038	+
2039	+	/* Data structures for the current thread's exception handler chain.
2040	+	On the x86 Windows uses register fs, offset 0 to point to the current
2041	+	exception handler; Cygwin mucks with it, so we must do the same... :-/ */
2042	+
2043	+	/* Magic taken from winsup/cygwin/include/exceptions.h. */
2044	+
2045	+	struct exception_list {
2046	+	struct exception_list *prev;
2047	+	int (handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
2048	+	};
2049	+	typedef struct exception_list exception_list;
2050	+
2051	+	/* Magic taken from winsup/cygwin/exceptions.cc. */
2052	+
2053	+	__asm__ (".equ __except_list,0");
2054	+
2055	+	extern exception_list *_except_list __asm__ ("%fs:__except_list");
2056	+
2057	+	/* For debugging. _except_list is not otherwise accessible from gdb. */
2058	+	static exception_list *
2059	+	debug_get_except_list ()
2060	+	{
2061	+	return _except_list;
2062	+	}
2063	+
2064	+	/* Cygwin's original exception handler. */
2065	+	static int (cygwin_exception_handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
2066	+
2067	+	/* Our exception handler. */
2068	+	static int
2069	+	libsigsegv_exception_handler (EXCEPTION_RECORD exception, void frame, CONTEXT context, void dispatch)
2070	+	{
2071	+	EXCEPTION_POINTERS ExceptionInfo;
2072	+	ExceptionInfo.ExceptionRecord = exception;
2073	+	ExceptionInfo.ContextRecord = context;
2074	+	if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH)
2075	+	return cygwin_exception_handler (exception, frame, context, dispatch);
2076	+	else
2077	+	return 0;
2078	+	}
2079	+
2080	+	static void
2081	+	do_install_main_exception_filter ()
2082	+	{
2083	+	/* We cannot insert any handler into the chain, because such handlers
2084	+	must lie on the stack (?). Instead, we have to replace(!) Cygwin's
2085	+	global exception handler. */
2086	+	cygwin_exception_handler = _except_list->handler;
2087	+	_except_list->handler = libsigsegv_exception_handler;
2088	+	}
2089	+
2090	+	#else
2091	+
2092	+	static void
2093	+	do_install_main_exception_filter ()
2094	+	{
2095	+	SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter);
2096	+	}
2097	+	#endif
2098	+
2099	+	static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler)
2100	+	{
2101	+	static bool main_exception_filter_installed = false;
2102	+	if (!main_exception_filter_installed) {
2103	+	do_install_main_exception_filter();
2104	+	main_exception_filter_installed = true;
2105	+	}
2106	+	sigsegv_fault_handler = handler;
2107	+	return true;
2108	+	}
2109	+	#endif
2110	+
2111		bool sigsegv_install_handler(sigsegv_fault_handler_t handler)
2112		{
2113		#if defined(HAVE_SIGSEGV_RECOVERY)
#	Line 1619 \| Line 2118 \| bool sigsegv_install_handler(sigsegv_fau
2118		if (success)
2119		sigsegv_fault_handler = handler;
2120		return success;
2121	<	#elif defined(HAVE_MACH_EXCEPTIONS)
2121	>	#elif defined(HAVE_MACH_EXCEPTIONS) \|\| defined(HAVE_WIN32_EXCEPTIONS)
2122		return sigsegv_do_install_handler(handler);
2123		#else
2124		// FAIL: no siginfo_t nor sigcontext subterfuge is available
#	Line 1645 \| Line 2144 \| void sigsegv_deinstall_handler(void)
2144		SIGSEGV_ALL_SIGNALS
2145		#undef FAULT_HANDLER
2146		#endif
2147	+	#ifdef HAVE_WIN32_EXCEPTIONS
2148	+	sigsegv_fault_handler = NULL;
2149	+	#endif
2150		}
2151
2152
#	Line 1666 \| Line 2168 \| void sigsegv_set_dump_state(sigsegv_stat
2168		#include <stdio.h>
2169		#include <stdlib.h>
2170		#include <fcntl.h>
2171	+	#ifdef HAVE_SYS_MMAN_H
2172		#include <sys/mman.h>
2173	+	#endif
2174		#include "vm_alloc.h"
2175
2176		const int REF_INDEX = 123;
#	Line 1676 \| Line 2180 \| static int page_size;
2180		static volatile char * page = 0;
2181		static volatile int handler_called = 0;
2182
2183	+	/* Barriers */
2184	+	#ifdef __GNUC__
2185	+	#define BARRIER() asm volatile ("" : : : "memory")
2186	+	#else
2187	+	#define BARRIER() /* nothing */
2188	+	#endif
2189	+
2190		#ifdef __GNUC__
2191		// Code range where we expect the fault to come from
2192		static void b_region, e_region;
#	Line 1709 \| Line 2220 \| static sigsegv_return_t sigsegv_test_han
2220		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
2221		static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2222		{
2223	+	#if DEBUG
2224	+	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
2225	+	#endif
2226		if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
2227		#ifdef __GNUC__
2228		// Make sure reported fault instruction address falls into
#	Line 1764 \| Line 2278 \| static bool arch_insn_skipper_tests()
2278		0x4c, 0x89, 0x18, // mov %r11,(%rax)
2279		0x4a, 0x89, 0x0c, 0x10, // mov %rcx,(%rax,%r10,1)
2280		0x4e, 0x89, 0x1c, 0x10, // mov %r11,(%rax,%r10,1)
2281	+	0x63, 0x47, 0x04, // movslq 4(%rdi),%eax
2282	+	0x48, 0x63, 0x47, 0x04, // movslq 4(%rdi),%rax
2283		#endif
2284		0 // end
2285		};
#	Line 1787 \| Line 2303 \| int main(void)
2303		if (vm_init() < 0)
2304		return 1;
2305
2306	<	page_size = getpagesize();
2306	>	page_size = vm_get_page_size();
2307		if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED)
2308		return 2;
2309
#	Line 1807 \| Line 2323 \| int main(void)
2323		if (page[REF_INDEX] != REF_VALUE)
2324		exit(20);
2325		page[REF_INDEX] = REF_VALUE;
2326	+	BARRIER();
2327		L_e_region1:
2328
2329		if (handler_called != 1)
#	Line 1843 \| Line 2360 \| int main(void)
2360		TEST_SKIP_INSTRUCTION(unsigned short);
2361		TEST_SKIP_INSTRUCTION(unsigned int);
2362		TEST_SKIP_INSTRUCTION(unsigned long);
2363	+	TEST_SKIP_INSTRUCTION(signed char);
2364	+	TEST_SKIP_INSTRUCTION(signed short);
2365	+	TEST_SKIP_INSTRUCTION(signed int);
2366	+	TEST_SKIP_INSTRUCTION(signed long);
2367	+	BARRIER();
2368		L_e_region2:
2369
2370		if (!arch_insn_skipper_tests())

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.42 by gbeauche, 2004-01-19T16:59:13Z vs. Revision 1.66 by gbeauche, 2007-06-16T06:21:57Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.42 by gbeauche, 2004-01-19T16:59:13Z vs.
Revision 1.66 by gbeauche, 2007-06-16T06:21:57Z