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root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.42 by gbeauche, 2004-01-19T16:59:13Z vs.
Revision 1.60 by gbeauche, 2006-01-24T21:33:26Z

#	Line 10 | Line 10
10		*    tjw@omnigroup.com Sun, 4 Jun 2000
11		*    www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	*  Basilisk II (C) 1997-2004 Christian Bauer
13	>	*  Basilisk II (C) 1997-2005 Christian Bauer
14		*
15		*  This program is free software; you can redistribute it and/or modify
16		*  it under the terms of the GNU General Public License as published by
#	Line 97 | Line 97 | struct instruction_t {
97		char                            ra, rd;
98		};
99
100	<	static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned int * gpr)
100	>	static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned long * gpr)
101		{
102		// Get opcode and divide into fields
103	<	unsigned int opcode = *((unsigned int *)nip);
103	>	unsigned int opcode = *((unsigned int *)(unsigned long)nip);
104		unsigned int primop = opcode >> 26;
105		unsigned int exop = (opcode >> 1) & 0x3ff;
106		unsigned int ra = (opcode >> 16) & 0x1f;
#	Line 174 | Line 174 | static void powerpc_decode_instruction(i
174		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break;
175		case 45:        // sthu
176		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break;
177	+	case 58:        // ld, ldu, lwa
178	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
179	+	transfer_size = SIZE_QUAD;
180	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
181	+	imm &= ~3;
182	+	break;
183	+	case 62:        // std, stdu, stq
184	+	transfer_type = SIGSEGV_TRANSFER_STORE;
185	+	transfer_size = SIZE_QUAD;
186	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
187	+	imm &= ~3;
188	+	break;
189		}
190
191		// Calculate effective address
#	Line 214 | Line 226 | static void powerpc_decode_instruction(i
226
227		#if HAVE_SIGINFO_T
228		// Generic extended signal handler
229	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
229	>	#if defined(__FreeBSD__)
230		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
231		#else
232		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
#	Line 244 | Line 256 | static void powerpc_decode_instruction(i
256		#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
257		#define SIGSEGV_SKIP_INSTRUCTION                sparc_skip_instruction
258		#endif
259	+	#if defined(__i386__)
260	+	#include <sys/regset.h>
261	+	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
262	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[EIP]
263	+	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
264	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
265		#endif
266	<	#if defined(__FreeBSD__)
266	>	#endif
267	>	#if defined(__FreeBSD__) || defined(__OpenBSD__)
268		#if (defined(i386) || defined(__i386__))
269		#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_eip)
270		#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
271		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
272		#endif
273		#endif
274	+	#if defined(__NetBSD__)
275	+	#if (defined(i386) || defined(__i386__))
276	+	#include <sys/ucontext.h>
277	+	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.__gregs)
278	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[_REG_EIP]
279	+	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
280	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
281	+	#endif
282	+	#if (defined(powerpc) || defined(__powerpc__))
283	+	#include <sys/ucontext.h>
284	+	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.__gregs)
285	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[_REG_PC]
286	+	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_PC], (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_R0]
287	+	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
288	+	#endif
289	+	#endif
290		#if defined(__linux__)
291		#if (defined(i386) || defined(__i386__))
292		#include <sys/ucontext.h>
#	Line 274 | Line 309 | static void powerpc_decode_instruction(i
309		#include <sys/ucontext.h>
310		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.regs)
311		#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS->nip)
312	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned int *)(SIGSEGV_CONTEXT_REGS->gpr)
312	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned long *)(SIGSEGV_CONTEXT_REGS->gpr)
313		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
314		#endif
315		#if (defined(hppa) || defined(__hppa__))
#	Line 285 | Line 320 | static void powerpc_decode_instruction(i
320		#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
321		#define SIGSEGV_CONTEXT_REGS                    (((struct ucontext *)scp)->uc_mcontext)
322		#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS.arm_pc)
323	+	#define SIGSEGV_REGISTER_FILE                   (&SIGSEGV_CONTEXT_REGS.arm_r0)
324	+	#define SIGSEGV_SKIP_INSTRUCTION                arm_skip_instruction
325		#endif
326		#endif
327		#endif
#	Line 315 | Line 352 | static void powerpc_decode_instruction(i
352		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, scp
353		#define SIGSEGV_FAULT_ADDRESS                   scp->regs->dar
354		#define SIGSEGV_FAULT_INSTRUCTION               scp->regs->nip
355	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&scp->regs->nip, (unsigned int *)(scp->regs->gpr)
355	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&scp->regs->nip, (unsigned long *)(scp->regs->gpr)
356		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
357		#endif
358		#if (defined(alpha) || defined(__alpha__))
#	Line 331 | Line 368 | static void powerpc_decode_instruction(i
368		#define SIGSEGV_FAULT_HANDLER_ARGS              &sc
369		#define SIGSEGV_FAULT_ADDRESS                   scp->fault_address
370		#define SIGSEGV_FAULT_INSTRUCTION               scp->arm_pc
371	+	#define SIGSEGV_REGISTER_FILE                   &scp->arm_r0
372	+	#define SIGSEGV_SKIP_INSTRUCTION                arm_skip_instruction
373		#endif
374		#endif
375
#	Line 477 | Line 516 | static sigsegv_address_t get_fault_addre
516		#endif
517		#endif
518
519	+	#if HAVE_WIN32_EXCEPTIONS
520	+	#define WIN32_LEAN_AND_MEAN /* avoid including junk */
521	+	#include <windows.h>
522	+	#include <winerror.h>
523	+
524	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
525	+	#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
526	+	#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
527	+	#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
528	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Eip
529	+	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
530	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
531	+	#endif
532	+
533		#if HAVE_MACH_EXCEPTIONS
534
535		// This can easily be extended to other Mach systems, but really who
#	Line 537 | Line 590 | if (ret != KERN_SUCCESS) { \
590		exit (1); \
591		}
592
593	+	#ifdef __ppc__
594	+	#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state_t
595	+	#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE
596	+	#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE_COUNT
597	+	#define SIGSEGV_FAULT_INSTRUCTION               state->srr0
598	+	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
599	+	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&state->srr0, (unsigned long *)&state->r0
600	+	#endif
601	+	#ifdef __i386__
602	+	#ifdef i386_SAVED_STATE
603	+	#define SIGSEGV_THREAD_STATE_TYPE               struct i386_saved_state
604	+	#define SIGSEGV_THREAD_STATE_FLAVOR             i386_SAVED_STATE
605	+	#define SIGSEGV_THREAD_STATE_COUNT              i386_SAVED_STATE_COUNT
606	+	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&state->edi) /* EDI is the first GPR we consider */
607	+	#else
608	+	#define SIGSEGV_THREAD_STATE_TYPE               struct i386_thread_state
609	+	#define SIGSEGV_THREAD_STATE_FLAVOR             i386_THREAD_STATE
610	+	#define SIGSEGV_THREAD_STATE_COUNT              i386_THREAD_STATE_COUNT
611	+	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&state->eax) /* EAX is the first GPR we consider */
612	+	#endif
613	+	#define SIGSEGV_FAULT_INSTRUCTION               state->eip
614	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
615	+	#endif
616		#define SIGSEGV_FAULT_ADDRESS                   code[1]
541	–	#define SIGSEGV_FAULT_INSTRUCTION               get_fault_instruction(thread, state)
617		#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP)  ((code[0] == KERN_PROTECTION_FAILURE) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE)
618	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code, ppc_thread_state_t *state
618	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code, SIGSEGV_THREAD_STATE_TYPE *state
619		#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code, &state
545	–	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
546	–	#define SIGSEGV_REGISTER_FILE                   &state->srr0, &state->r0
547	–
548	–	// Given a suspended thread, stuff the current instruction and
549	–	// registers into state.
550	–	//
551	–	// It would have been nice to have this be ppc/x86 independant which
552	–	// could have been done easily with a thread_state_t instead of
553	–	// ppc_thread_state_t, but because of the way this is called it is
554	–	// easier to do it this way.
555	–	#if (defined(ppc) || defined(__ppc__))
556	–	static inline sigsegv_address_t get_fault_instruction(mach_port_t thread, ppc_thread_state_t *state)
557	–	{
558	–	kern_return_t krc;
559	–	mach_msg_type_number_t count;
560	–
561	–	count = MACHINE_THREAD_STATE_COUNT;
562	–	krc = thread_get_state(thread, MACHINE_THREAD_STATE, (thread_state_t)state, &count);
563	–	MACH_CHECK_ERROR (thread_get_state, krc);
564	–
565	–	return (sigsegv_address_t)state->srr0;
566	–	}
567	–	#endif
620
621		// Since there can only be one exception thread running at any time
622		// this is not a problem.
#	Line 654 | Line 706 | enum {
706		#endif
707		};
708		#endif
709	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
709	>	#if defined(__NetBSD__)
710	>	enum {
711	>	#if (defined(i386) || defined(__i386__))
712	>	X86_REG_EIP = _REG_EIP,
713	>	X86_REG_EAX = _REG_EAX,
714	>	X86_REG_ECX = _REG_ECX,
715	>	X86_REG_EDX = _REG_EDX,
716	>	X86_REG_EBX = _REG_EBX,
717	>	X86_REG_ESP = _REG_ESP,
718	>	X86_REG_EBP = _REG_EBP,
719	>	X86_REG_ESI = _REG_ESI,
720	>	X86_REG_EDI = _REG_EDI
721	>	#endif
722	>	};
723	>	#endif
724	>	#if defined(__FreeBSD__)
725		enum {
726		#if (defined(i386) || defined(__i386__))
727		X86_REG_EIP = 10,
#	Line 669 | Line 736 | enum {
736		#endif
737		};
738		#endif
739	+	#if defined(__OpenBSD__)
740	+	enum {
741	+	#if defined(__i386__)
742	+	// EDI is the first register we consider
743	+	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
744	+	#define DREG(REG) ((OREG(REG) - OREG(edi)) / 4)
745	+	X86_REG_EIP = DREG(eip), // 7
746	+	X86_REG_EAX = DREG(eax), // 6
747	+	X86_REG_ECX = DREG(ecx), // 5
748	+	X86_REG_EDX = DREG(edx), // 4
749	+	X86_REG_EBX = DREG(ebx), // 3
750	+	X86_REG_ESP = DREG(esp), // 10
751	+	X86_REG_EBP = DREG(ebp), // 2
752	+	X86_REG_ESI = DREG(esi), // 1
753	+	X86_REG_EDI = DREG(edi)  // 0
754	+	#undef DREG
755	+	#undef OREG
756	+	#endif
757	+	};
758	+	#endif
759	+	#if defined(__sun__)
760	+	// Same as for Linux, need to check for x86-64
761	+	enum {
762	+	#if defined(__i386__)
763	+	X86_REG_EIP = EIP,
764	+	X86_REG_EAX = EAX,
765	+	X86_REG_ECX = ECX,
766	+	X86_REG_EDX = EDX,
767	+	X86_REG_EBX = EBX,
768	+	X86_REG_ESP = ESP,
769	+	X86_REG_EBP = EBP,
770	+	X86_REG_ESI = ESI,
771	+	X86_REG_EDI = EDI
772	+	#endif
773	+	};
774	+	#endif
775	+	#if defined(__APPLE__) && defined(__MACH__)
776	+	enum {
777	+	#ifdef i386_SAVED_STATE
778	+	// same as FreeBSD (in Open Darwin 8.0.1)
779	+	X86_REG_EIP = 10,
780	+	X86_REG_EAX = 7,
781	+	X86_REG_ECX = 6,
782	+	X86_REG_EDX = 5,
783	+	X86_REG_EBX = 4,
784	+	X86_REG_ESP = 13,
785	+	X86_REG_EBP = 2,
786	+	X86_REG_ESI = 1,
787	+	X86_REG_EDI = 0
788	+	#else
789	+	// new layout (MacOS X 10.4.4 for x86)
790	+	X86_REG_EIP = 10,
791	+	X86_REG_EAX = 0,
792	+	X86_REG_ECX = 2,
793	+	X86_REG_EDX = 4,
794	+	X86_REG_EBX = 1,
795	+	X86_REG_ESP = 7,
796	+	X86_REG_EBP = 6,
797	+	X86_REG_ESI = 5,
798	+	X86_REG_EDI = 4
799	+	#endif
800	+	};
801	+	#endif
802	+	#if defined(_WIN32)
803	+	enum {
804	+	#if (defined(i386) || defined(__i386__))
805	+	X86_REG_EIP = 7,
806	+	X86_REG_EAX = 5,
807	+	X86_REG_ECX = 4,
808	+	X86_REG_EDX = 3,
809	+	X86_REG_EBX = 2,
810	+	X86_REG_ESP = 10,
811	+	X86_REG_EBP = 6,
812	+	X86_REG_ESI = 1,
813	+	X86_REG_EDI = 0
814	+	#endif
815	+	};
816	+	#endif
817		// FIXME: this is partly redundant with the instruction decoding phase
818		// to discover transfer type and register number
819		static inline int ix86_step_over_modrm(unsigned char * p)
#	Line 709 | Line 854 | static bool ix86_skip_instruction(unsign
854
855		if (eip == 0)
856		return false;
857	+	#ifdef _WIN32
858	+	if (IsBadCodePtr((FARPROC)eip))
859	+	return false;
860	+	#endif
861
862		transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
863		transfer_size_t transfer_size = SIZE_LONG;
#	Line 762 | Line 911 | static bool ix86_skip_instruction(unsign
911		#endif
912
913		// Decode instruction
914	+	int target_size = SIZE_UNKNOWN;
915		switch (eip[0]) {
916		case 0x0f:
917	+	target_size = transfer_size;
918		switch (eip[1]) {
919	+	case 0xbe: // MOVSX r32, r/m8
920		case 0xb6: // MOVZX r32, r/m8
921	+	transfer_size = SIZE_BYTE;
922	+	goto do_mov_extend;
923	+	case 0xbf: // MOVSX r32, r/m16
924		case 0xb7: // MOVZX r32, r/m16
925	<	switch (eip[2] & 0xc0) {
926	<	case 0x80:
927	<	reg = (eip[2] >> 3) & 7;
928	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
929	<	break;
930	<	case 0x40:
931	<	reg = (eip[2] >> 3) & 7;
932	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
933	<	break;
934	<	case 0x00:
935	<	reg = (eip[2] >> 3) & 7;
936	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
937	<	break;
938	<	}
939	<	len += 3 + ix86_step_over_modrm(eip + 2);
940	<	break;
925	>	transfer_size = SIZE_WORD;
926	>	goto do_mov_extend;
927	>	do_mov_extend:
928	>	switch (eip[2] & 0xc0) {
929	>	case 0x80:
930	>	reg = (eip[2] >> 3) & 7;
931	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
932	>	break;
933	>	case 0x40:
934	>	reg = (eip[2] >> 3) & 7;
935	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
936	>	break;
937	>	case 0x00:
938	>	reg = (eip[2] >> 3) & 7;
939	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
940	>	break;
941	>	}
942	>	len += 3 + ix86_step_over_modrm(eip + 2);
943	>	break;
944		}
945		break;
946		case 0x8a: // MOV r8, r/m8
#	Line 824 | Line 982 | static bool ix86_skip_instruction(unsign
982		len += 2 + ix86_step_over_modrm(eip + 1);
983		break;
984		}
985	+	if (target_size == SIZE_UNKNOWN)
986	+	target_size = transfer_size;
987
988		if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
989		// Unknown machine code, let it crash. Then patch the decoder
#	Line 851 | Line 1011 | static bool ix86_skip_instruction(unsign
1011		// Set 0 to the relevant register part
1012		// NOTE: this is only valid for MOV alike instructions
1013		int rloc = x86_reg_map[reg];
1014	<	switch (transfer_size) {
1014	>	switch (target_size) {
1015		case SIZE_BYTE:
1016		if (has_rex || reg < 4)
1017		regs[rloc] = (regs[rloc] & ~0x00ffL);
#	Line 905 | Line 1065 | static bool ix86_skip_instruction(unsign
1065		"r12", "r13", "r14", "r15",
1066		};
1067		const char * reg_str = NULL;
1068	<	switch (transfer_size) {
1068	>	switch (target_size) {
1069		case SIZE_BYTE:
1070		reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
1071		break;
#	Line 928 | Line 1088 | static bool ix86_skip_instruction(unsign
1088
1089		// Decode and skip PPC instruction
1090		#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__))
1091	<	static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs)
1091	>	static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
1092		{
1093		instruction_t instr;
1094		powerpc_decode_instruction(&instr, *nip_p, regs);
#	Line 940 | Line 1100 | static bool powerpc_skip_instruction(uns
1100
1101		#if DEBUG
1102		printf("%08x: %s %s access", *nip_p,
1103	<	instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long",
1103	>	instr.transfer_size == SIZE_BYTE ? "byte" :
1104	>	instr.transfer_size == SIZE_WORD ? "word" :
1105	>	instr.transfer_size == SIZE_LONG ? "long" : "quad",
1106		instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1107
1108		if (instr.addr_mode == MODE_U || instr.addr_mode == MODE_UX)
#	Line 1129 | Line 1291 | enum {
1291		SPARC_REG_G1 = REG_G1,
1292		SPARC_REG_O0 = REG_O0,
1293		SPARC_REG_PC = REG_PC,
1294	+	SPARC_REG_nPC = REG_nPC
1295		#endif
1296		};
1297		static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
#	Line 1192 | Line 1355 | static bool sparc_skip_instruction(unsig
1355		break;
1356		case 7: // Store Doubleword
1357		transfer_type = SIGSEGV_TRANSFER_STORE;
1358	<	transfer_size = SIZE_WORD;
1358	>	transfer_size = SIZE_LONG;
1359		register_pair = true;
1360		break;
1361		}
#	Line 1202 | Line 1365 | static bool sparc_skip_instruction(unsig
1365		return false;
1366		}
1367
1205	–	// Zero target register in case of a load operation
1368		const int reg = (opcode >> 25) & 0x1f;
1369	+
1370	+	#if DEBUG
1371	+	static const char * reg_names[] = {
1372	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1373	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1374	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1375	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1376	+	};
1377	+	printf("%s %s register %s\n",
1378	+	transfer_size == SIZE_BYTE ? "byte" :
1379	+	transfer_size == SIZE_WORD ? "word" :
1380	+	transfer_size == SIZE_LONG ? "long" :
1381	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1382	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1383	+	reg_names[reg]);
1384	+	#endif
1385	+
1386	+	// Zero target register in case of a load operation
1387		if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1388		// FIXME: code to handle local & input registers is not tested
1389	<	if (reg >= 1 && reg <= 7) {
1389	>	if (reg >= 1 && reg < 8) {
1390		// global registers
1391		regs[reg - 1 + SPARC_REG_G1] = 0;
1392		}
1393	<	else if (reg >= 8 && reg <= 15) {
1393	>	else if (reg >= 8 && reg < 16) {
1394		// output registers
1395		regs[reg - 8 + SPARC_REG_O0] = 0;
1396		}
1397	<	else if (reg >= 16 && reg <= 23) {
1397	>	else if (reg >= 16 && reg < 24) {
1398		// local registers (in register windows)
1399		if (gwins)
1400		gwins->wbuf->rw_local[reg - 16] = 0;
#	Line 1230 | Line 1410 | static bool sparc_skip_instruction(unsig
1410		}
1411		}
1412
1413	+	regs[SPARC_REG_PC] += 4;
1414	+	regs[SPARC_REG_nPC] += 4;
1415	+	return true;
1416	+	}
1417	+	#endif
1418	+	#endif
1419	+
1420	+	// Decode and skip ARM instruction
1421	+	#if (defined(arm) || defined(__arm__))
1422	+	enum {
1423	+	#if (defined(__linux__))
1424	+	ARM_REG_PC = 15,
1425	+	ARM_REG_CPSR = 16
1426	+	#endif
1427	+	};
1428	+	static bool arm_skip_instruction(unsigned long * regs)
1429	+	{
1430	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
1431	+
1432	+	if (pc == 0)
1433	+	return false;
1434	+
1435	+	#if DEBUG
1436	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1437	+	#endif
1438	+
1439	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1440	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1441	+	enum { op_sdt = 1, op_sdth = 2 };
1442	+	int op = 0;
1443	+
1444	+	// Handle load/store instructions only
1445	+	const unsigned int opcode = pc[0];
1446	+	switch ((opcode >> 25) & 7) {
1447	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
1448	+	op = op_sdth;
1449	+	// Determine transfer size (S/H bits)
1450	+	switch ((opcode >> 5) & 3) {
1451	+	case 0: // SWP instruction
1452	+	break;
1453	+	case 1: // Unsigned halfwords
1454	+	case 3: // Signed halfwords
1455	+	transfer_size = SIZE_WORD;
1456	+	break;
1457	+	case 2: // Signed byte
1458	+	transfer_size = SIZE_BYTE;
1459	+	break;
1460	+	}
1461	+	break;
1462	+	case 2:
1463	+	case 3: // Single Data Transfer (LDR, STR)
1464	+	op = op_sdt;
1465	+	// Determine transfer size (B bit)
1466	+	if (((opcode >> 22) & 1) == 1)
1467	+	transfer_size = SIZE_BYTE;
1468	+	else
1469	+	transfer_size = SIZE_LONG;
1470	+	break;
1471	+	default:
1472	+	// FIXME: support load/store mutliple?
1473	+	return false;
1474	+	}
1475	+
1476	+	// Check for invalid transfer size (SWP instruction?)
1477	+	if (transfer_size == SIZE_UNKNOWN)
1478	+	return false;
1479	+
1480	+	// Determine transfer type (L bit)
1481	+	if (((opcode >> 20) & 1) == 1)
1482	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1483	+	else
1484	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1485	+
1486	+	// Compute offset
1487	+	int offset;
1488	+	if (((opcode >> 25) & 1) == 0) {
1489	+	if (op == op_sdt)
1490	+	offset = opcode & 0xfff;
1491	+	else if (op == op_sdth) {
1492	+	int rm = opcode & 0xf;
1493	+	if (((opcode >> 22) & 1) == 0) {
1494	+	// register offset
1495	+	offset = regs[rm];
1496	+	}
1497	+	else {
1498	+	// immediate offset
1499	+	offset = ((opcode >> 4) & 0xf0) | (opcode & 0x0f);
1500	+	}
1501	+	}
1502	+	}
1503	+	else {
1504	+	const int rm = opcode & 0xf;
1505	+	const int sh = (opcode >> 7) & 0x1f;
1506	+	if (((opcode >> 4) & 1) == 1) {
1507	+	// we expect only legal load/store instructions
1508	+	printf("FATAL: invalid shift operand\n");
1509	+	return false;
1510	+	}
1511	+	const unsigned int v = regs[rm];
1512	+	switch ((opcode >> 5) & 3) {
1513	+	case 0: // logical shift left
1514	+	offset = sh ? v << sh : v;
1515	+	break;
1516	+	case 1: // logical shift right
1517	+	offset = sh ? v >> sh : 0;
1518	+	break;
1519	+	case 2: // arithmetic shift right
1520	+	if (sh)
1521	+	offset = ((signed int)v) >> sh;
1522	+	else
1523	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
1524	+	break;
1525	+	case 3: // rotate right
1526	+	if (sh)
1527	+	offset = (v >> sh) | (v << (32 - sh));
1528	+	else
1529	+	offset = (v >> 1) | ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
1530	+	break;
1531	+	}
1532	+	}
1533	+	if (((opcode >> 23) & 1) == 0)
1534	+	offset = -offset;
1535	+
1536	+	int rd = (opcode >> 12) & 0xf;
1537	+	int rn = (opcode >> 16) & 0xf;
1538		#if DEBUG
1539		static const char * reg_names[] = {
1540	<	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1541	<	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1237	<	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1238	<	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1540	>	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1541	>	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
1542		};
1543		printf("%s %s register %s\n",
1544		transfer_size == SIZE_BYTE ? "byte" :
1545		transfer_size == SIZE_WORD ? "word" :
1546	<	transfer_size == SIZE_LONG ? "long" :
1244	<	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1546	>	transfer_size == SIZE_LONG ? "long" : "unknown",
1547		transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1548	<	reg_names[reg]);
1548	>	reg_names[rd]);
1549		#endif
1550
1551	<	regs[SPARC_REG_PC] += 4;
1551	>	unsigned int base = regs[rn];
1552	>	if (((opcode >> 24) & 1) == 1)
1553	>	base += offset;
1554	>
1555	>	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
1556	>	regs[rd] = 0;
1557	>
1558	>	if (((opcode >> 24) & 1) == 0)                // post-index addressing
1559	>	regs[rn] += offset;
1560	>	else if (((opcode >> 21) & 1) == 1)   // write-back address into base
1561	>	regs[rn] = base;
1562	>
1563	>	regs[ARM_REG_PC] += 4;
1564		return true;
1565		}
1566		#endif
1567	<	#endif
1567	>
1568
1569		// Fallbacks
1570		#ifndef SIGSEGV_FAULT_INSTRUCTION
#	Line 1273 | Line 1587 | static bool sparc_skip_instruction(unsig
1587		*  SIGSEGV global handler
1588		*/
1589
1276	–	#if defined(HAVE_SIGSEGV_RECOVERY) || defined(HAVE_MACH_EXCEPTIONS)
1590		// This function handles the badaccess to memory.
1591		// It is called from the signal handler or the exception handler.
1592		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
1593		{
1594	+	#ifdef HAVE_MACH_EXCEPTIONS
1595	+	// We must match the initial count when writing back the CPU state registers
1596	+	kern_return_t krc;
1597	+	mach_msg_type_number_t count;
1598	+
1599	+	count = SIGSEGV_THREAD_STATE_COUNT;
1600	+	krc = thread_get_state(thread, SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state, &count);
1601	+	MACH_CHECK_ERROR (thread_get_state, krc);
1602	+	#endif
1603	+
1604		sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
1605		sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
1606
#	Line 1296 | Line 1619 | static bool handle_badaccess(SIGSEGV_FAU
1619		// is modified off of the stack, in Mach we
1620		// need to actually call thread_set_state to
1621		// have the register values updated.
1299	–	kern_return_t krc;
1300	–
1622		krc = thread_set_state(thread,
1623	<	MACHINE_THREAD_STATE, (thread_state_t)state,
1624	<	MACHINE_THREAD_STATE_COUNT);
1625	<	MACH_CHECK_ERROR (thread_get_state, krc);
1623	>	SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state,
1624	>	count);
1625	>	MACH_CHECK_ERROR (thread_set_state, krc);
1626		#endif
1627		return true;
1628		}
1629		break;
1630		#endif
1631	+	case SIGSEGV_RETURN_FAILURE:
1632	+	// We can't do anything with the fault_address, dump state?
1633	+	if (sigsegv_state_dumper != 0)
1634	+	sigsegv_state_dumper(fault_address, fault_instruction);
1635	+	break;
1636		}
1311	–
1312	–	// We can't do anything with the fault_address, dump state?
1313	–	if (sigsegv_state_dumper != 0)
1314	–	sigsegv_state_dumper(fault_address, fault_instruction);
1637
1638		return false;
1639		}
1318	–	#endif
1640
1641
1642		/*
#	Line 1352 | Line 1673 | forward_exception(mach_port_t thread_por
1673		mach_port_t port;
1674		exception_behavior_t behavior;
1675		thread_state_flavor_t flavor;
1676	<	thread_state_t thread_state;
1676	>	thread_state_data_t thread_state;
1677		mach_msg_type_number_t thread_state_count;
1678
1679		for (portIndex = 0; portIndex < oldExceptionPorts->maskCount; portIndex++) {
#	Line 1377 | Line 1698 | forward_exception(mach_port_t thread_por
1698
1699		if (behavior != EXCEPTION_DEFAULT) {
1700		thread_state_count = THREAD_STATE_MAX;
1701	<	kret = thread_get_state (thread_port, flavor, thread_state,
1701	>	kret = thread_get_state (thread_port, flavor, (natural_t *)&thread_state,
1702		&thread_state_count);
1703		MACH_CHECK_ERROR (thread_get_state, kret);
1704		}
#	Line 1393 | Line 1714 | forward_exception(mach_port_t thread_por
1714		// fprintf(stderr, "forwarding to exception_raise_state\n");
1715		kret = exception_raise_state(port, exception_type, exception_data,
1716		data_count, &flavor,
1717	<	thread_state, thread_state_count,
1718	<	thread_state, &thread_state_count);
1717	>	(natural_t *)&thread_state, thread_state_count,
1718	>	(natural_t *)&thread_state, &thread_state_count);
1719		MACH_CHECK_ERROR (exception_raise_state, kret);
1720		break;
1721		case EXCEPTION_STATE_IDENTITY:
#	Line 1402 | Line 1723 | forward_exception(mach_port_t thread_por
1723		kret = exception_raise_state_identity(port, thread_port, task_port,
1724		exception_type, exception_data,
1725		data_count, &flavor,
1726	<	thread_state, thread_state_count,
1727	<	thread_state, &thread_state_count);
1726	>	(natural_t *)&thread_state, thread_state_count,
1727	>	(natural_t *)&thread_state, &thread_state_count);
1728		MACH_CHECK_ERROR (exception_raise_state_identity, kret);
1729		break;
1730		default:
#	Line 1412 | Line 1733 | forward_exception(mach_port_t thread_por
1733		}
1734
1735		if (behavior != EXCEPTION_DEFAULT) {
1736	<	kret = thread_set_state (thread_port, flavor, thread_state,
1736	>	kret = thread_set_state (thread_port, flavor, (natural_t *)&thread_state,
1737		thread_state_count);
1738		MACH_CHECK_ERROR (thread_set_state, kret);
1739		}
#	Line 1447 | Line 1768 | catch_exception_raise(mach_port_t except
1768		exception_data_t code,
1769		mach_msg_type_number_t codeCount)
1770		{
1771	<	ppc_thread_state_t state;
1771	>	SIGSEGV_THREAD_STATE_TYPE state;
1772		kern_return_t krc;
1773
1774		if ((exception == EXC_BAD_ACCESS)  && (codeCount >= 2)) {
#	Line 1586 | Line 1907 | static bool sigsegv_do_install_handler(s
1907		// addressing modes) used in PPC instructions, you will need the
1908		// GPR state anyway.
1909		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
1910	<	EXCEPTION_DEFAULT, MACHINE_THREAD_STATE);
1910	>	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
1911		if (krc != KERN_SUCCESS) {
1912		mach_error("thread_set_exception_ports", krc);
1913		return false;
#	Line 1609 | Line 1930 | static bool sigsegv_do_install_handler(s
1930		}
1931		#endif
1932
1933	+	#ifdef HAVE_WIN32_EXCEPTIONS
1934	+	static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo)
1935	+	{
1936	+	if (sigsegv_fault_handler != NULL
1937	+	&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
1938	+	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
1939	+	&& handle_badaccess(ExceptionInfo))
1940	+	return EXCEPTION_CONTINUE_EXECUTION;
1941	+
1942	+	return EXCEPTION_CONTINUE_SEARCH;
1943	+	}
1944	+
1945	+	#if defined __CYGWIN__ && defined __i386__
1946	+	/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin
1947	+	installs a global exception handler.  We have to dig deep in order to install
1948	+	our main_exception_filter.  */
1949	+
1950	+	/* Data structures for the current thread's exception handler chain.
1951	+	On the x86 Windows uses register fs, offset 0 to point to the current
1952	+	exception handler; Cygwin mucks with it, so we must do the same... :-/ */
1953	+
1954	+	/* Magic taken from winsup/cygwin/include/exceptions.h.  */
1955	+
1956	+	struct exception_list {
1957	+	struct exception_list *prev;
1958	+	int (*handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *);
1959	+	};
1960	+	typedef struct exception_list exception_list;
1961	+
1962	+	/* Magic taken from winsup/cygwin/exceptions.cc.  */
1963	+
1964	+	__asm__ (".equ __except_list,0");
1965	+
1966	+	extern exception_list *_except_list __asm__ ("%fs:__except_list");
1967	+
1968	+	/* For debugging.  _except_list is not otherwise accessible from gdb.  */
1969	+	static exception_list *
1970	+	debug_get_except_list ()
1971	+	{
1972	+	return _except_list;
1973	+	}
1974	+
1975	+	/* Cygwin's original exception handler.  */
1976	+	static int (*cygwin_exception_handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *);
1977	+
1978	+	/* Our exception handler.  */
1979	+	static int
1980	+	libsigsegv_exception_handler (EXCEPTION_RECORD *exception, void *frame, CONTEXT *context, void *dispatch)
1981	+	{
1982	+	EXCEPTION_POINTERS ExceptionInfo;
1983	+	ExceptionInfo.ExceptionRecord = exception;
1984	+	ExceptionInfo.ContextRecord = context;
1985	+	if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH)
1986	+	return cygwin_exception_handler (exception, frame, context, dispatch);
1987	+	else
1988	+	return 0;
1989	+	}
1990	+
1991	+	static void
1992	+	do_install_main_exception_filter ()
1993	+	{
1994	+	/* We cannot insert any handler into the chain, because such handlers
1995	+	must lie on the stack (?).  Instead, we have to replace(!) Cygwin's
1996	+	global exception handler.  */
1997	+	cygwin_exception_handler = _except_list->handler;
1998	+	_except_list->handler = libsigsegv_exception_handler;
1999	+	}
2000	+
2001	+	#else
2002	+
2003	+	static void
2004	+	do_install_main_exception_filter ()
2005	+	{
2006	+	SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter);
2007	+	}
2008	+	#endif
2009	+
2010	+	static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler)
2011	+	{
2012	+	static bool main_exception_filter_installed = false;
2013	+	if (!main_exception_filter_installed) {
2014	+	do_install_main_exception_filter();
2015	+	main_exception_filter_installed = true;
2016	+	}
2017	+	sigsegv_fault_handler = handler;
2018	+	return true;
2019	+	}
2020	+	#endif
2021	+
2022		bool sigsegv_install_handler(sigsegv_fault_handler_t handler)
2023		{
2024		#if defined(HAVE_SIGSEGV_RECOVERY)
#	Line 1619 | Line 2029 | bool sigsegv_install_handler(sigsegv_fau
2029		if (success)
2030		sigsegv_fault_handler = handler;
2031		return success;
2032	<	#elif defined(HAVE_MACH_EXCEPTIONS)
2032	>	#elif defined(HAVE_MACH_EXCEPTIONS) || defined(HAVE_WIN32_EXCEPTIONS)
2033		return sigsegv_do_install_handler(handler);
2034		#else
2035		// FAIL: no siginfo_t nor sigcontext subterfuge is available
#	Line 1645 | Line 2055 | void sigsegv_deinstall_handler(void)
2055		SIGSEGV_ALL_SIGNALS
2056		#undef FAULT_HANDLER
2057		#endif
2058	+	#ifdef HAVE_WIN32_EXCEPTIONS
2059	+	sigsegv_fault_handler = NULL;
2060	+	#endif
2061		}
2062
2063
#	Line 1666 | Line 2079 | void sigsegv_set_dump_state(sigsegv_stat
2079		#include <stdio.h>
2080		#include <stdlib.h>
2081		#include <fcntl.h>
2082	+	#ifdef HAVE_SYS_MMAN_H
2083		#include <sys/mman.h>
2084	+	#endif
2085		#include "vm_alloc.h"
2086
2087		const int REF_INDEX = 123;
#	Line 1709 | Line 2124 | static sigsegv_return_t sigsegv_test_han
2124		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
2125		static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2126		{
2127	+	#if DEBUG
2128	+	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
2129	+	#endif
2130		if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
2131		#ifdef __GNUC__
2132		// Make sure reported fault instruction address falls into
#	Line 1787 | Line 2205 | int main(void)
2205		if (vm_init() < 0)
2206		return 1;
2207
2208	<	page_size = getpagesize();
2208	>	page_size = vm_get_page_size();
2209		if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED)
2210		return 2;
2211
#	Line 1843 | Line 2261 | int main(void)
2261		TEST_SKIP_INSTRUCTION(unsigned short);
2262		TEST_SKIP_INSTRUCTION(unsigned int);
2263		TEST_SKIP_INSTRUCTION(unsigned long);
2264	+	TEST_SKIP_INSTRUCTION(signed char);
2265	+	TEST_SKIP_INSTRUCTION(signed short);
2266	+	TEST_SKIP_INSTRUCTION(signed int);
2267	+	TEST_SKIP_INSTRUCTION(signed long);
2268		L_e_region2:
2269
2270		if (!arch_insn_skipper_tests())

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