[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.37 by gbeauche, 2003-12-20T07:43:56Z vs.
Revision 1.40 by gbeauche, 2003-12-20T23:22:25Z

+#endif
+#include <list>
-+
+#include <stdio.h>
+#include <signal.h>
+#include "sigsegv.h"
+#include <ucontext.h>
+#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
+#define SIGSEGV_FAULT_INSTRUCTION               (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
-+
+#if (defined(mips) || defined(__mips))
-+
+#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
-+
+#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
-+
+#endif
+#endif
+#if defined(__sun__)
+#if (defined(sparc) || defined(__sparc__))
-+
+#include <sys/stack.h>
-+
+#include <sys/regset.h>
+#include <sys/ucontext.h>
+#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
+#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[REG_PC]
-+
+#define SIGSEGV_SPARC_GWINDOWS                  (((ucontext_t *)scp)->uc_mcontext.gwins)
-+
+#define SIGSEGV_SPARC_RWINDOW                   (struct rwindow *)((char *)SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
-+
+#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
-+
+#define SIGSEGV_SKIP_INSTRUCTION                sparc_skip_instruction
+#endif
+#endif
+#if defined(__FreeBSD__)
+#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned int *)(SIGSEGV_CONTEXT_REGS->gpr)
+#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
+#endif
-+
+#if (defined(hppa) || defined(__hppa__))
-+
+#undef  SIGSEGV_FAULT_ADDRESS
-+
+#define SIGSEGV_FAULT_ADDRESS                   sip->si_ptr
-+
+#endif
+#endif
+#endif
+#endif
+#endif
+#if defined(__FreeBSD__)
-–
+#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
+#if (defined(i386) || defined(__i386__))
-+
+#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
+#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp, char *addr
+#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp, addr
+#define SIGSEGV_FAULT_ADDRESS                   addr
+#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&scp->sc_edi)
+#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
+#endif
-+
+#if (defined(alpha) || defined(__alpha__))
-+
+#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
-+
+#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, char *addr, struct sigcontext *scp
-+
+#define SIGSEGV_FAULT_HANDLER_ARGS              sig, addr, scp
-+
+#define SIGSEGV_FAULT_ADDRESS                   addr
-+
+#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_pc
-+
+#endif
+#endif
+// Extract fault address out of a sigcontext
+        return true;
+#endif
-+
-+
+// Decode and skip MIPS instruction
-+
+#if (defined(mips) || defined(__mips))
-+
+enum {
-+
+#if (defined(sgi) || defined(__sgi))
-+
+  MIPS_REG_EPC = 35,
-+
+#endif
-+
+};
-+
+static bool mips_skip_instruction(greg_t * regs)
-+
+{
-+
+  unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC];
-+
-+
+  if (epc == 0)
-+
+        return false;
-+
-+
+#if DEBUG
-+
+  printf("IP: %p [%08x]\n", epc, epc[0]);
-+
+#endif
-+
-+
+  transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
-+
+  transfer_size_t transfer_size = SIZE_LONG;
-+
+  int direction = 0;
-+
-+
+  const unsigned int opcode = epc[0];
-+
+  switch (opcode >> 26) {
-+
+  case 32: // Load Byte
-+
+  case 36: // Load Byte Unsigned
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_BYTE;
-+
+        break;
-+
+  case 33: // Load Halfword
-+
+  case 37: // Load Halfword Unsigned
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_WORD;
-+
+        break;
-+
+  case 35: // Load Word
-+
+  case 39: // Load Word Unsigned
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_LONG;
-+
+        break;
-+
+  case 34: // Load Word Left
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_LONG;
-+
+        direction = -1;
-+
+        break;
-+
+  case 38: // Load Word Right
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_LONG;
-+
+        direction = 1;
-+
+        break;
-+
+  case 55: // Load Doubleword
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_QUAD;
-+
+        break;
-+
+  case 26: // Load Doubleword Left
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_QUAD;
-+
+        direction = -1;
-+
+        break;
-+
+  case 27: // Load Doubleword Right
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_QUAD;
-+
+        direction = 1;
-+
+        break;
-+
+  case 40: // Store Byte
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_BYTE;
-+
+        break;
-+
+  case 41: // Store Halfword
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_WORD;
-+
+        break;
-+
+  case 43: // Store Word
-+
+  case 42: // Store Word Left
-+
+  case 46: // Store Word Right
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_LONG;
-+
+        break;
-+
+  case 63: // Store Doubleword
-+
+  case 44: // Store Doubleword Left
-+
+  case 45: // Store Doubleword Right
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_QUAD;
-+
+        break;
-+
+  /* Misc instructions unlikely to be used within CPU emulators */
-+
+  case 48: // Load Linked Word
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_LONG;
-+
+        break;
-+
+  case 52: // Load Linked Doubleword
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_QUAD;
-+
+        break;
-+
+  case 56: // Store Conditional Word
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_LONG;
-+
+        break;
-+
+  case 60: // Store Conditional Doubleword
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_QUAD;
-+
+        break;
-+
+  }
-+
-+
+  if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
-+
+        // Unknown machine code, let it crash. Then patch the decoder
-+
+        return false;
-+
+  }
-+
-+
+  // Zero target register in case of a load operation
-+
+  const int reg = (opcode >> 16) & 0x1f;
-+
+  if (transfer_type == SIGSEGV_TRANSFER_LOAD) {
-+
+        if (direction == 0)
-+
+          regs[reg] = 0;
-+
+        else {
-+
+          // FIXME: untested code
-+
+          unsigned long ea = regs[(opcode >> 21) & 0x1f];
-+
+          ea += (signed long)(signed int)(signed short)(opcode & 0xffff);
-+
+          const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7);
-+
+          unsigned long value;
-+
+          if (direction > 0) {
-+
+                const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1);
-+
+                value = regs[reg] & rmask;
-+
+          }
-+
+          else {
-+
+                const unsigned long lmask = (1L << (offset * 8)) - 1;
-+
+                value = regs[reg] & lmask;
-+
+          }
-+
+          // restore most significant bits
-+
+          if (transfer_size == SIZE_LONG)
-+
+                value = (signed long)(signed int)value;
-+
+          regs[reg] = value;
-+
+        }
-+
+  }
-+
-+
+#if DEBUG
-+
+#if (defined(_ABIN32) || defined(_ABI64))
-+
+  static const char * mips_gpr_names[32] = {
-+
+        "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
-+
+        "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
-+
+        "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
-+
+        "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
-+
+  };
-+
+#else
-+
+  static const char * mips_gpr_names[32] = {
-+
+        "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
-+
+        "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
-+
+        "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
-+
+        "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
-+
+  };
-+
+#endif
-+
+  printf("%s %s register %s\n",
-+
+                 transfer_size == SIZE_BYTE ? "byte" :
-+
+                 transfer_size == SIZE_WORD ? "word" :
-+
+                 transfer_size == SIZE_LONG ? "long" :
-+
+                 transfer_size == SIZE_QUAD ? "quad" : "unknown",
-+
+                 transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
-+
+                 mips_gpr_names[reg]);
-+
+#endif
-+
-+
+  regs[MIPS_REG_EPC] += 4;
-+
+  return true;
-+
+}
-+
+#endif
-+
-+
+// Decode and skip SPARC instruction
-+
+#if (defined(sparc) || defined(__sparc__))
-+
+enum {
-+
+#if (defined(__sun__))
-+
+  SPARC_REG_G1 = REG_G1,
-+
+  SPARC_REG_O0 = REG_O0,
-+
+  SPARC_REG_PC = REG_PC,
-+
+#endif
-+
+};
-+
+static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
-+
+{
-+
+  unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
-+
-+
+  if (pc == 0)
-+
+        return false;
-+
-+
+#if DEBUG
-+
+  printf("IP: %p [%08x]\n", pc, pc[0]);
-+
+#endif
-+
-+
+  transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
-+
+  transfer_size_t transfer_size = SIZE_LONG;
-+
+  bool register_pair = false;
-+
-+
+  const unsigned int opcode = pc[0];
-+
+  if ((opcode >> 30) != 3)
-+
+        return false;
-+
+  switch ((opcode >> 19) & 0x3f) {
-+
+  case 9: // Load Signed Byte
-+
+  case 1: // Load Unsigned Byte
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_BYTE;
-+
+        break;
-+
+  case 10:// Load Signed Halfword
-+
+  case 2: // Load Unsigned Word
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_WORD;
-+
+        break;
-+
+  case 8: // Load Word
-+
+  case 0: // Load Unsigned Word
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_LONG;
-+
+        break;
-+
+  case 11:// Load Extended Word
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_QUAD;
-+
+        break;
-+
+  case 3: // Load Doubleword
-+
+        transfer_type = SIGSEGV_TRANSFER_LOAD;
-+
+        transfer_size = SIZE_LONG;
-+
+        register_pair = true;
-+
+        break;
-+
+  case 5: // Store Byte
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_BYTE;
-+
+        break;
-+
+  case 6: // Store Halfword
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_WORD;
-+
+        break;
-+
+  case 4: // Store Word
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_LONG;
-+
+        break;
-+
+  case 14:// Store Extended Word
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_QUAD;
-+
+        break;
-+
+  case 7: // Store Doubleword
-+
+        transfer_type = SIGSEGV_TRANSFER_STORE;
-+
+        transfer_size = SIZE_WORD;
-+
+        register_pair = true;
-+
+        break;
-+
+  }
-+
-+
+  if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
-+
+        // Unknown machine code, let it crash. Then patch the decoder
-+
+        return false;
-+
+  }
-+
-+
+  // Zero target register in case of a load operation
-+
+  const int reg = (opcode >> 25) & 0x1f;
-+
+  if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
-+
+        // FIXME: code to handle local & input registers is not tested
-+
+        if (reg >= 1 && reg <= 7) {
-+
+          // global registers
-+
+          regs[reg - 1 + SPARC_REG_G1] = 0;
-+
+        }
-+
+        else if (reg >= 8 && reg <= 15) {
-+
+          // output registers
-+
+          regs[reg - 8 + SPARC_REG_O0] = 0;
-+
+        }
-+
+        else if (reg >= 16 && reg <= 23) {
-+
+          // local registers (in register windows)
-+
+          if (gwins)
-+
+                gwins->wbuf->rw_local[reg - 16] = 0;
-+
+          else
-+
+                rwin->rw_local[reg - 16] = 0;
-+
+        }
-+
+        else {
-+
+          // input registers (in register windows)
-+
+          if (gwins)
-+
+                gwins->wbuf->rw_in[reg - 24] = 0;
-+
+          else
-+
+                rwin->rw_in[reg - 24] = 0;
-+
+        }
-+
+  }
-+
-+
+#if DEBUG
-+
+  static const char * reg_names[] = {
-+
+        "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
-+
+        "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
-+
+        "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
-+
+        "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
-+
+  };
-+
+  printf("%s %s register %s\n",
-+
+                 transfer_size == SIZE_BYTE ? "byte" :
-+
+                 transfer_size == SIZE_WORD ? "word" :
-+
+                 transfer_size == SIZE_LONG ? "long" :
-+
+                 transfer_size == SIZE_QUAD ? "quad" : "unknown",
-+
+                 transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
-+
+                 reg_names[reg]);
-+
+#endif
-+
-+
+  regs[SPARC_REG_PC] += 4;
-+
+  return true;
-+
+}
-+
+#endif
+#endif
+// Fallbacks
+static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
-+
+#if DEBUG
-+
+        printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
-+
+        printf("expected fault at %p\n", page + REF_INDEX);
-+
+#ifdef __GNUC__
-+
+        printf("expected instruction address range: %p-%p\n", b_region, e_region);
-+
+#endif
-+
+#endif
+        handler_called++;
+        if ((fault_address - REF_INDEX) != page)
+                exit(10);

Diff Legend

-–
+Removed lines
-+
+Added lines
-<
+Changed lines
->
+Changed lines

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.37 by gbeauche, 2003-12-20T07:43:56Z vs. Revision 1.40 by gbeauche, 2003-12-20T23:22:25Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.37 by gbeauche, 2003-12-20T07:43:56Z vs.
Revision 1.40 by gbeauche, 2003-12-20T23:22:25Z