[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.33 by gbeauche, 2003-10-21T23:10:19Z vs.
Revision 1.44 by gbeauche, 2004-01-21T23:14:28Z

#	Line 10 \| Line 10
10		* tjw@omnigroup.com Sun, 4 Jun 2000
11		* www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	* Basilisk II (C) 1997-2002 Christian Bauer
13	>	* Basilisk II (C) 1997-2004 Christian Bauer
14		*
15		* This program is free software; you can redistribute it and/or modify
16		* it under the terms of the GNU General Public License as published by
#	Line 36 \| Line 36
36		#endif
37
38		#include <list>
39	+	#include <stdio.h>
40		#include <signal.h>
41		#include "sigsegv.h"
42
#	Line 69 \| Line 70 \| static bool sigsegv_do_install_handler(i
70		enum transfer_size_t {
71		SIZE_UNKNOWN,
72		SIZE_BYTE,
73	<	SIZE_WORD,
74	<	SIZE_LONG
73	>	SIZE_WORD, // 2 bytes
74	>	SIZE_LONG, // 4 bytes
75	>	SIZE_QUAD, // 8 bytes
76		};
77
78		// Transfer type
#	Line 221 \| Line 223 \| static void powerpc_decode_instruction(i
223		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t sip, void scp
224		#define SIGSEGV_FAULT_HANDLER_ARGS sip, scp
225		#define SIGSEGV_FAULT_ADDRESS sip->si_addr
226	+	#if (defined(sgi) \|\| defined(__sgi))
227	+	#include <ucontext.h>
228	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
229	+	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
230	+	#if (defined(mips) \|\| defined(__mips))
231	+	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
232	+	#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
233	+	#endif
234	+	#endif
235		#if defined(__sun__)
236		#if (defined(sparc) \|\| defined(__sparc__))
237	+	#include <sys/stack.h>
238	+	#include <sys/regset.h>
239		#include <sys/ucontext.h>
240		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
241		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[REG_PC]
242	+	#define SIGSEGV_SPARC_GWINDOWS (((ucontext_t *)scp)->uc_mcontext.gwins)
243	+	#define SIGSEGV_SPARC_RWINDOW (struct rwindow )((char )SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
244	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
245	+	#define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction
246		#endif
247		#endif
248		#if defined(__FreeBSD__)
249		#if (defined(i386) \|\| defined(__i386__))
250		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
251	<	#define SIGSEGV_REGISTER_FILE ((unsigned int )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
251	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
252		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
253		#endif
254		#endif
#	Line 240 \| Line 257 \| static void powerpc_decode_instruction(i
257		#include <sys/ucontext.h>
258		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
259		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
260	<	#define SIGSEGV_REGISTER_FILE (unsigned int *)SIGSEGV_CONTEXT_REGS
260	>	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
261		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
262		#endif
263		#if (defined(x86_64) \|\| defined(__x86_64__))
#	Line 248 \| Line 265 \| static void powerpc_decode_instruction(i
265		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
266		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
267		#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
268	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
269		#endif
270		#if (defined(ia64) \|\| defined(__ia64__))
271		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext )scp)->sc_ip & ~0x3ULL) / slot number is in bits 0 and 1 */
#	Line 259 \| Line 277 \| static void powerpc_decode_instruction(i
277		#define SIGSEGV_REGISTER_FILE (unsigned int )&SIGSEGV_CONTEXT_REGS->nip, (unsigned int )(SIGSEGV_CONTEXT_REGS->gpr)
278		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
279		#endif
280	+	#if (defined(hppa) \|\| defined(__hppa__))
281	+	#undef SIGSEGV_FAULT_ADDRESS
282	+	#define SIGSEGV_FAULT_ADDRESS sip->si_ptr
283	+	#endif
284	+	#if (defined(arm) \|\| defined(__arm__))
285	+	#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
286	+	#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext)
287	+	#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.arm_pc)
288	+	#define SIGSEGV_REGISTER_FILE (&SIGSEGV_CONTEXT_REGS.arm_r0)
289	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
290	+	#endif
291		#endif
292		#endif
293
#	Line 273 \| Line 302 \| static void powerpc_decode_instruction(i
302		#define SIGSEGV_FAULT_HANDLER_ARGS &scs
303		#define SIGSEGV_FAULT_ADDRESS scp->cr2
304		#define SIGSEGV_FAULT_INSTRUCTION scp->eip
305	<	#define SIGSEGV_REGISTER_FILE (unsigned int *)scp
305	>	#define SIGSEGV_REGISTER_FILE (unsigned long *)scp
306		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
307		#endif
308		#if (defined(sparc) \|\| defined(__sparc__))
#	Line 298 \| Line 327 \| static void powerpc_decode_instruction(i
327		#define SIGSEGV_FAULT_ADDRESS get_fault_address(scp)
328		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
329		#endif
330	+	#if (defined(arm) \|\| defined(__arm__))
331	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int r1, int r2, int r3, struct sigcontext sc
332	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp
333	+	#define SIGSEGV_FAULT_HANDLER_ARGS &sc
334	+	#define SIGSEGV_FAULT_ADDRESS scp->fault_address
335	+	#define SIGSEGV_FAULT_INSTRUCTION scp->arm_pc
336	+	#define SIGSEGV_REGISTER_FILE &scp->arm_r0
337	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
338	+	#endif
339		#endif
340
341		// Irix 5 or 6 on MIPS
342	<	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(__SYSTYPE_SVR4))
342	>	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(_SYSTYPE_SVR4))
343		#include <ucontext.h>
344		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp
345		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp
346	<	#define SIGSEGV_FAULT_ADDRESS scp->sc_badvaddr
346	>	#define SIGSEGV_FAULT_ADDRESS (unsigned long)scp->sc_badvaddr
347	>	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)scp->sc_pc
348		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
349		#endif
350
#	Line 378 \| Line 417 \| static sigsegv_address_t get_fault_addre
417		#endif
418		#endif
419		#if defined(__FreeBSD__)
381	–	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
420		#if (defined(i386) \|\| defined(__i386__))
421	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
422		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext scp, char addr
423		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr
424		#define SIGSEGV_FAULT_ADDRESS addr
425		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_eip
426	<	#define SIGSEGV_REGISTER_FILE ((unsigned int *)&scp->sc_edi)
426	>	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi)
427		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
428		#endif
429	+	#if (defined(alpha) \|\| defined(__alpha__))
430	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
431	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, char addr, struct sigcontext scp
432	+	#define SIGSEGV_FAULT_HANDLER_ARGS sig, addr, scp
433	+	#define SIGSEGV_FAULT_ADDRESS addr
434	+	#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
435	+	#endif
436		#endif
437
438		// Extract fault address out of a sigcontext
#	Line 577 \| Line 623 \| *handleExceptions(void priv)**
623
624		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
625		// Decode and skip X86 instruction
626	<	#if (defined(i386) \|\| defined(__i386__))
626	>	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
627		#if defined(__linux__)
628		enum {
629	+	#if (defined(i386) \|\| defined(__i386__))
630		X86_REG_EIP = 14,
631		X86_REG_EAX = 11,
632		X86_REG_ECX = 10,
#	Line 589 \| Line 636 \| enum {
636		X86_REG_EBP = 6,
637		X86_REG_ESI = 5,
638		X86_REG_EDI = 4
639	+	#endif
640	+	#if defined(__x86_64__)
641	+	X86_REG_R8 = 0,
642	+	X86_REG_R9 = 1,
643	+	X86_REG_R10 = 2,
644	+	X86_REG_R11 = 3,
645	+	X86_REG_R12 = 4,
646	+	X86_REG_R13 = 5,
647	+	X86_REG_R14 = 6,
648	+	X86_REG_R15 = 7,
649	+	X86_REG_EDI = 8,
650	+	X86_REG_ESI = 9,
651	+	X86_REG_EBP = 10,
652	+	X86_REG_EBX = 11,
653	+	X86_REG_EDX = 12,
654	+	X86_REG_EAX = 13,
655	+	X86_REG_ECX = 14,
656	+	X86_REG_ESP = 15,
657	+	X86_REG_EIP = 16
658	+	#endif
659		};
660		#endif
661		#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
662		enum {
663	+	#if (defined(i386) \|\| defined(__i386__))
664		X86_REG_EIP = 10,
665		X86_REG_EAX = 7,
666		X86_REG_ECX = 6,
#	Line 602 \| Line 670 \| enum {
670		X86_REG_EBP = 2,
671		X86_REG_ESI = 1,
672		X86_REG_EDI = 0
673	+	#endif
674		};
675		#endif
676		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 638 \| Line 707 \| static inline int ix86_step_over_modrm(u
707		return offset;
708		}
709
710	<	static bool ix86_skip_instruction(unsigned int * regs)
710	>	static bool ix86_skip_instruction(unsigned long * regs)
711		{
712		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
713
#	Line 650 \| Line 719 \| static bool ix86_skip_instruction(unsign
719
720		int reg = -1;
721		int len = 0;
722	<
722	>
723	>	#if DEBUG
724	>	printf("IP: %p [%02x %02x %02x %02x...]\n",
725	>	eip, eip[0], eip[1], eip[2], eip[3]);
726	>	#endif
727	>
728		// Operand size prefix
729		if (*eip == 0x66) {
730		eip++;
#	Line 658 \| Line 732 \| static bool ix86_skip_instruction(unsign
732		transfer_size = SIZE_WORD;
733		}
734
735	+	// REX prefix
736	+	#if defined(__x86_64__)
737	+	struct rex_t {
738	+	unsigned char W;
739	+	unsigned char R;
740	+	unsigned char X;
741	+	unsigned char B;
742	+	};
743	+	rex_t rex = { 0, 0, 0, 0 };
744	+	bool has_rex = false;
745	+	if ((*eip & 0xf0) == 0x40) {
746	+	has_rex = true;
747	+	const unsigned char b = *eip;
748	+	rex.W = b & (1 << 3);
749	+	rex.R = b & (1 << 2);
750	+	rex.X = b & (1 << 1);
751	+	rex.B = b & (1 << 0);
752	+	#if DEBUG
753	+	printf("REX: %c,%c,%c,%c\n",
754	+	rex.W ? 'W' : '_',
755	+	rex.R ? 'R' : '_',
756	+	rex.X ? 'X' : '_',
757	+	rex.B ? 'B' : '_');
758	+	#endif
759	+	eip++;
760	+	len++;
761	+	if (rex.W)
762	+	transfer_size = SIZE_QUAD;
763	+	}
764	+	#else
765	+	const bool has_rex = false;
766	+	#endif
767	+
768		// Decode instruction
769		switch (eip[0]) {
770		case 0x0f:
#	Line 727 \| Line 834 \| static bool ix86_skip_instruction(unsign
834		return false;
835		}
836
837	+	#if defined(__x86_64__)
838	+	if (rex.R)
839	+	reg += 8;
840	+	#endif
841	+
842		if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
843	<	static const int x86_reg_map[8] = {
843	>	static const int x86_reg_map[] = {
844		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
845	<	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI
845	>	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
846	>	#if defined(__x86_64__)
847	>	X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
848	>	X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
849	>	#endif
850		};
851
852	<	if (reg < 0 \|\| reg >= 8)
852	>	if (reg < 0 \|\| reg >= (sizeof(x86_reg_map)/sizeof(x86_reg_map[0]) - 1))
853		return false;
854
855	+	// Set 0 to the relevant register part
856	+	// NOTE: this is only valid for MOV alike instructions
857		int rloc = x86_reg_map[reg];
858		switch (transfer_size) {
859		case SIZE_BYTE:
860	<	regs[rloc] = (regs[rloc] & ~0xff);
860	>	if (has_rex \|\| reg < 4)
861	>	regs[rloc] = (regs[rloc] & ~0x00ffL);
862	>	else {
863	>	rloc = x86_reg_map[reg - 4];
864	>	regs[rloc] = (regs[rloc] & ~0xff00L);
865	>	}
866		break;
867		case SIZE_WORD:
868	<	regs[rloc] = (regs[rloc] & ~0xffff);
868	>	regs[rloc] = (regs[rloc] & ~0xffffL);
869		break;
870		case SIZE_LONG:
871	+	case SIZE_QUAD: // zero-extension
872		regs[rloc] = 0;
873		break;
874		}
#	Line 752 \| Line 876 \| static bool ix86_skip_instruction(unsign
876
877		#if DEBUG
878		printf("%08x: %s %s access", regs[X86_REG_EIP],
879	<	transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : "long",
879	>	transfer_size == SIZE_BYTE ? "byte" :
880	>	transfer_size == SIZE_WORD ? "word" :
881	>	transfer_size == SIZE_LONG ? "long" :
882	>	transfer_size == SIZE_QUAD ? "quad" : "unknown",
883		transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
884
885		if (reg != -1) {
886	<	static const char * x86_reg_str_map[8] = {
887	<	"eax", "ecx", "edx", "ebx",
888	<	"esp", "ebp", "esi", "edi"
886	>	static const char * x86_byte_reg_str_map[] = {
887	>	"al", "cl", "dl", "bl",
888	>	"spl", "bpl", "sil", "dil",
889	>	"r8b", "r9b", "r10b", "r11b",
890	>	"r12b", "r13b", "r14b", "r15b",
891	>	"ah", "ch", "dh", "bh",
892	>	};
893	>	static const char * x86_word_reg_str_map[] = {
894	>	"ax", "cx", "dx", "bx",
895	>	"sp", "bp", "si", "di",
896	>	"r8w", "r9w", "r10w", "r11w",
897	>	"r12w", "r13w", "r14w", "r15w",
898	>	};
899	>	static const char *x86_long_reg_str_map[] = {
900	>	"eax", "ecx", "edx", "ebx",
901	>	"esp", "ebp", "esi", "edi",
902	>	"r8d", "r9d", "r10d", "r11d",
903	>	"r12d", "r13d", "r14d", "r15d",
904		};
905	<	printf(" %s register %%%s", transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from", x86_reg_str_map[reg]);
905	>	static const char *x86_quad_reg_str_map[] = {
906	>	"rax", "rcx", "rdx", "rbx",
907	>	"rsp", "rbp", "rsi", "rdi",
908	>	"r8", "r9", "r10", "r11",
909	>	"r12", "r13", "r14", "r15",
910	>	};
911	>	const char * reg_str = NULL;
912	>	switch (transfer_size) {
913	>	case SIZE_BYTE:
914	>	reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
915	>	break;
916	>	case SIZE_WORD: reg_str = x86_word_reg_str_map[reg]; break;
917	>	case SIZE_LONG: reg_str = x86_long_reg_str_map[reg]; break;
918	>	case SIZE_QUAD: reg_str = x86_quad_reg_str_map[reg]; break;
919	>	}
920	>	if (reg_str)
921	>	printf(" %s register %%%s",
922	>	transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from",
923	>	reg_str);
924		}
925		printf(", %d bytes instruction\n", len);
926		#endif
#	Line 802 \| Line 962 \| static bool powerpc_skip_instruction(uns
962		return true;
963		}
964		#endif
965	+
966	+	// Decode and skip MIPS instruction
967	+	#if (defined(mips) \|\| defined(__mips))
968	+	enum {
969	+	#if (defined(sgi) \|\| defined(__sgi))
970	+	MIPS_REG_EPC = 35,
971	+	#endif
972	+	};
973	+	static bool mips_skip_instruction(greg_t * regs)
974	+	{
975	+	unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC];
976	+
977	+	if (epc == 0)
978	+	return false;
979	+
980	+	#if DEBUG
981	+	printf("IP: %p [%08x]\n", epc, epc[0]);
982	+	#endif
983	+
984	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
985	+	transfer_size_t transfer_size = SIZE_LONG;
986	+	int direction = 0;
987	+
988	+	const unsigned int opcode = epc[0];
989	+	switch (opcode >> 26) {
990	+	case 32: // Load Byte
991	+	case 36: // Load Byte Unsigned
992	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
993	+	transfer_size = SIZE_BYTE;
994	+	break;
995	+	case 33: // Load Halfword
996	+	case 37: // Load Halfword Unsigned
997	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
998	+	transfer_size = SIZE_WORD;
999	+	break;
1000	+	case 35: // Load Word
1001	+	case 39: // Load Word Unsigned
1002	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1003	+	transfer_size = SIZE_LONG;
1004	+	break;
1005	+	case 34: // Load Word Left
1006	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1007	+	transfer_size = SIZE_LONG;
1008	+	direction = -1;
1009	+	break;
1010	+	case 38: // Load Word Right
1011	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1012	+	transfer_size = SIZE_LONG;
1013	+	direction = 1;
1014	+	break;
1015	+	case 55: // Load Doubleword
1016	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1017	+	transfer_size = SIZE_QUAD;
1018	+	break;
1019	+	case 26: // Load Doubleword Left
1020	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1021	+	transfer_size = SIZE_QUAD;
1022	+	direction = -1;
1023	+	break;
1024	+	case 27: // Load Doubleword Right
1025	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1026	+	transfer_size = SIZE_QUAD;
1027	+	direction = 1;
1028	+	break;
1029	+	case 40: // Store Byte
1030	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1031	+	transfer_size = SIZE_BYTE;
1032	+	break;
1033	+	case 41: // Store Halfword
1034	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1035	+	transfer_size = SIZE_WORD;
1036	+	break;
1037	+	case 43: // Store Word
1038	+	case 42: // Store Word Left
1039	+	case 46: // Store Word Right
1040	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1041	+	transfer_size = SIZE_LONG;
1042	+	break;
1043	+	case 63: // Store Doubleword
1044	+	case 44: // Store Doubleword Left
1045	+	case 45: // Store Doubleword Right
1046	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1047	+	transfer_size = SIZE_QUAD;
1048	+	break;
1049	+	/* Misc instructions unlikely to be used within CPU emulators */
1050	+	case 48: // Load Linked Word
1051	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1052	+	transfer_size = SIZE_LONG;
1053	+	break;
1054	+	case 52: // Load Linked Doubleword
1055	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1056	+	transfer_size = SIZE_QUAD;
1057	+	break;
1058	+	case 56: // Store Conditional Word
1059	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1060	+	transfer_size = SIZE_LONG;
1061	+	break;
1062	+	case 60: // Store Conditional Doubleword
1063	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1064	+	transfer_size = SIZE_QUAD;
1065	+	break;
1066	+	}
1067	+
1068	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1069	+	// Unknown machine code, let it crash. Then patch the decoder
1070	+	return false;
1071	+	}
1072	+
1073	+	// Zero target register in case of a load operation
1074	+	const int reg = (opcode >> 16) & 0x1f;
1075	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD) {
1076	+	if (direction == 0)
1077	+	regs[reg] = 0;
1078	+	else {
1079	+	// FIXME: untested code
1080	+	unsigned long ea = regs[(opcode >> 21) & 0x1f];
1081	+	ea += (signed long)(signed int)(signed short)(opcode & 0xffff);
1082	+	const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7);
1083	+	unsigned long value;
1084	+	if (direction > 0) {
1085	+	const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1);
1086	+	value = regs[reg] & rmask;
1087	+	}
1088	+	else {
1089	+	const unsigned long lmask = (1L << (offset * 8)) - 1;
1090	+	value = regs[reg] & lmask;
1091	+	}
1092	+	// restore most significant bits
1093	+	if (transfer_size == SIZE_LONG)
1094	+	value = (signed long)(signed int)value;
1095	+	regs[reg] = value;
1096	+	}
1097	+	}
1098	+
1099	+	#if DEBUG
1100	+	#if (defined(_ABIN32) \|\| defined(_ABI64))
1101	+	static const char * mips_gpr_names[32] = {
1102	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1103	+	"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1104	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1105	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1106	+	};
1107	+	#else
1108	+	static const char * mips_gpr_names[32] = {
1109	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1110	+	"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
1111	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1112	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1113	+	};
1114	+	#endif
1115	+	printf("%s %s register %s\n",
1116	+	transfer_size == SIZE_BYTE ? "byte" :
1117	+	transfer_size == SIZE_WORD ? "word" :
1118	+	transfer_size == SIZE_LONG ? "long" :
1119	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1120	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1121	+	mips_gpr_names[reg]);
1122	+	#endif
1123	+
1124	+	regs[MIPS_REG_EPC] += 4;
1125	+	return true;
1126	+	}
1127	+	#endif
1128	+
1129	+	// Decode and skip SPARC instruction
1130	+	#if (defined(sparc) \|\| defined(__sparc__))
1131	+	enum {
1132	+	#if (defined(__sun__))
1133	+	SPARC_REG_G1 = REG_G1,
1134	+	SPARC_REG_O0 = REG_O0,
1135	+	SPARC_REG_PC = REG_PC,
1136	+	#endif
1137	+	};
1138	+	static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
1139	+	{
1140	+	unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
1141	+
1142	+	if (pc == 0)
1143	+	return false;
1144	+
1145	+	#if DEBUG
1146	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1147	+	#endif
1148	+
1149	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1150	+	transfer_size_t transfer_size = SIZE_LONG;
1151	+	bool register_pair = false;
1152	+
1153	+	const unsigned int opcode = pc[0];
1154	+	if ((opcode >> 30) != 3)
1155	+	return false;
1156	+	switch ((opcode >> 19) & 0x3f) {
1157	+	case 9: // Load Signed Byte
1158	+	case 1: // Load Unsigned Byte
1159	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1160	+	transfer_size = SIZE_BYTE;
1161	+	break;
1162	+	case 10:// Load Signed Halfword
1163	+	case 2: // Load Unsigned Word
1164	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1165	+	transfer_size = SIZE_WORD;
1166	+	break;
1167	+	case 8: // Load Word
1168	+	case 0: // Load Unsigned Word
1169	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1170	+	transfer_size = SIZE_LONG;
1171	+	break;
1172	+	case 11:// Load Extended Word
1173	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1174	+	transfer_size = SIZE_QUAD;
1175	+	break;
1176	+	case 3: // Load Doubleword
1177	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1178	+	transfer_size = SIZE_LONG;
1179	+	register_pair = true;
1180	+	break;
1181	+	case 5: // Store Byte
1182	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1183	+	transfer_size = SIZE_BYTE;
1184	+	break;
1185	+	case 6: // Store Halfword
1186	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1187	+	transfer_size = SIZE_WORD;
1188	+	break;
1189	+	case 4: // Store Word
1190	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1191	+	transfer_size = SIZE_LONG;
1192	+	break;
1193	+	case 14:// Store Extended Word
1194	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1195	+	transfer_size = SIZE_QUAD;
1196	+	break;
1197	+	case 7: // Store Doubleword
1198	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1199	+	transfer_size = SIZE_WORD;
1200	+	register_pair = true;
1201	+	break;
1202	+	}
1203	+
1204	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1205	+	// Unknown machine code, let it crash. Then patch the decoder
1206	+	return false;
1207	+	}
1208	+
1209	+	// Zero target register in case of a load operation
1210	+	const int reg = (opcode >> 25) & 0x1f;
1211	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1212	+	// FIXME: code to handle local & input registers is not tested
1213	+	if (reg >= 1 && reg <= 7) {
1214	+	// global registers
1215	+	regs[reg - 1 + SPARC_REG_G1] = 0;
1216	+	}
1217	+	else if (reg >= 8 && reg <= 15) {
1218	+	// output registers
1219	+	regs[reg - 8 + SPARC_REG_O0] = 0;
1220	+	}
1221	+	else if (reg >= 16 && reg <= 23) {
1222	+	// local registers (in register windows)
1223	+	if (gwins)
1224	+	gwins->wbuf->rw_local[reg - 16] = 0;
1225	+	else
1226	+	rwin->rw_local[reg - 16] = 0;
1227	+	}
1228	+	else {
1229	+	// input registers (in register windows)
1230	+	if (gwins)
1231	+	gwins->wbuf->rw_in[reg - 24] = 0;
1232	+	else
1233	+	rwin->rw_in[reg - 24] = 0;
1234	+	}
1235	+	}
1236	+
1237	+	#if DEBUG
1238	+	static const char * reg_names[] = {
1239	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1240	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1241	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1242	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1243	+	};
1244	+	printf("%s %s register %s\n",
1245	+	transfer_size == SIZE_BYTE ? "byte" :
1246	+	transfer_size == SIZE_WORD ? "word" :
1247	+	transfer_size == SIZE_LONG ? "long" :
1248	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1249	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1250	+	reg_names[reg]);
1251	+	#endif
1252	+
1253	+	regs[SPARC_REG_PC] += 4;
1254	+	return true;
1255	+	}
1256	+	#endif
1257		#endif
1258
1259	+	// Decode and skip ARM instruction
1260	+	#if (defined(arm) \|\| defined(__arm__))
1261	+	enum {
1262	+	#if (defined(__linux__))
1263	+	ARM_REG_PC = 15,
1264	+	ARM_REG_CPSR = 16
1265	+	#endif
1266	+	};
1267	+	static bool arm_skip_instruction(unsigned long * regs)
1268	+	{
1269	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
1270	+
1271	+	if (pc == 0)
1272	+	return false;
1273	+
1274	+	#if DEBUG
1275	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1276	+	#endif
1277	+
1278	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1279	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1280	+	enum { op_sdt = 1, op_sdth = 2 };
1281	+	int op = 0;
1282	+
1283	+	// Handle load/store instructions only
1284	+	const unsigned int opcode = pc[0];
1285	+	switch ((opcode >> 25) & 7) {
1286	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
1287	+	op = op_sdth;
1288	+	// Determine transfer size (S/H bits)
1289	+	switch ((opcode >> 5) & 3) {
1290	+	case 0: // SWP instruction
1291	+	break;
1292	+	case 1: // Unsigned halfwords
1293	+	case 3: // Signed halfwords
1294	+	transfer_size = SIZE_WORD;
1295	+	break;
1296	+	case 2: // Signed byte
1297	+	transfer_size = SIZE_BYTE;
1298	+	break;
1299	+	}
1300	+	break;
1301	+	case 2:
1302	+	case 3: // Single Data Transfer (LDR, STR)
1303	+	op = op_sdt;
1304	+	// Determine transfer size (B bit)
1305	+	if (((opcode >> 22) & 1) == 1)
1306	+	transfer_size = SIZE_BYTE;
1307	+	else
1308	+	transfer_size = SIZE_LONG;
1309	+	break;
1310	+	default:
1311	+	// FIXME: support load/store mutliple?
1312	+	return false;
1313	+	}
1314	+
1315	+	// Check for invalid transfer size (SWP instruction?)
1316	+	if (transfer_size == SIZE_UNKNOWN)
1317	+	return false;
1318	+
1319	+	// Determine transfer type (L bit)
1320	+	if (((opcode >> 20) & 1) == 1)
1321	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1322	+	else
1323	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1324	+
1325	+	// Compute offset
1326	+	int offset;
1327	+	if (((opcode >> 25) & 1) == 0) {
1328	+	if (op == op_sdt)
1329	+	offset = opcode & 0xfff;
1330	+	else if (op == op_sdth) {
1331	+	int rm = opcode & 0xf;
1332	+	if (((opcode >> 22) & 1) == 0) {
1333	+	// register offset
1334	+	offset = regs[rm];
1335	+	}
1336	+	else {
1337	+	// immediate offset
1338	+	offset = ((opcode >> 4) & 0xf0) \| (opcode & 0x0f);
1339	+	}
1340	+	}
1341	+	}
1342	+	else {
1343	+	const int rm = opcode & 0xf;
1344	+	const int sh = (opcode >> 7) & 0x1f;
1345	+	if (((opcode >> 4) & 1) == 1) {
1346	+	// we expect only legal load/store instructions
1347	+	printf("FATAL: invalid shift operand\n");
1348	+	return false;
1349	+	}
1350	+	const unsigned int v = regs[rm];
1351	+	switch ((opcode >> 5) & 3) {
1352	+	case 0: // logical shift left
1353	+	offset = sh ? v << sh : v;
1354	+	break;
1355	+	case 1: // logical shift right
1356	+	offset = sh ? v >> sh : 0;
1357	+	break;
1358	+	case 2: // arithmetic shift right
1359	+	if (sh)
1360	+	offset = ((signed int)v) >> sh;
1361	+	else
1362	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
1363	+	break;
1364	+	case 3: // rotate right
1365	+	if (sh)
1366	+	offset = (v >> sh) \| (v << (32 - sh));
1367	+	else
1368	+	offset = (v >> 1) \| ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
1369	+	break;
1370	+	}
1371	+	}
1372	+	if (((opcode >> 23) & 1) == 0)
1373	+	offset = -offset;
1374	+
1375	+	int rd = (opcode >> 12) & 0xf;
1376	+	int rn = (opcode >> 16) & 0xf;
1377	+	#if DEBUG
1378	+	static const char * reg_names[] = {
1379	+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1380	+	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
1381	+	};
1382	+	printf("%s %s register %s\n",
1383	+	transfer_size == SIZE_BYTE ? "byte" :
1384	+	transfer_size == SIZE_WORD ? "word" :
1385	+	transfer_size == SIZE_LONG ? "long" : "unknown",
1386	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1387	+	reg_names[rd]);
1388	+	#endif
1389	+
1390	+	unsigned int base = regs[rn];
1391	+	if (((opcode >> 24) & 1) == 1)
1392	+	base += offset;
1393	+
1394	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
1395	+	regs[rd] = 0;
1396	+
1397	+	if (((opcode >> 24) & 1) == 0) // post-index addressing
1398	+	regs[rn] += offset;
1399	+	else if (((opcode >> 21) & 1) == 1) // write-back address into base
1400	+	regs[rn] = base;
1401	+
1402	+	regs[ARM_REG_PC] += 4;
1403	+	return true;
1404	+	}
1405	+	#endif
1406	+
1407	+
1408		// Fallbacks
1409		#ifndef SIGSEGV_FAULT_INSTRUCTION
1410		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_INVALID_PC
#	Line 859 \| Line 1460 \| static bool handle_badaccess(SIGSEGV_FAU
1460		}
1461		break;
1462		#endif
1463	+	case SIGSEGV_RETURN_FAILURE:
1464	+	return false;
1465		}
1466
1467		// We can't do anything with the fault_address, dump state?
#	Line 1235 \| Line 1838 \| *static void b_region, e_region;*
1838
1839		static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
1840		{
1841	+	#if DEBUG
1842	+	printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
1843	+	printf("expected fault at %p\n", page + REF_INDEX);
1844	+	#ifdef __GNUC__
1845	+	printf("expected instruction address range: %p-%p\n", b_region, e_region);
1846	+	#endif
1847	+	#endif
1848		handler_called++;
1849		if ((fault_address - REF_INDEX) != page)
1850		exit(10);
#	Line 1254 \| Line 1864 \| static sigsegv_return_t sigsegv_test_han
1864		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
1865		static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
1866		{
1867	+	#if DEBUG
1868	+	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
1869	+	#endif
1870		if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
1871		#ifdef __GNUC__
1872		// Make sure reported fault instruction address falls into
#	Line 1268 \| Line 1881 \| static sigsegv_return_t sigsegv_insn_han
1881
1882		return SIGSEGV_RETURN_FAILURE;
1883		}
1884	+
1885	+	// More sophisticated tests for instruction skipper
1886	+	static bool arch_insn_skipper_tests()
1887	+	{
1888	+	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
1889	+	static const unsigned char code[] = {
1890	+	0x8a, 0x00, // mov (%eax),%al
1891	+	0x8a, 0x2c, 0x18, // mov (%eax,%ebx,1),%ch
1892	+	0x88, 0x20, // mov %ah,(%eax)
1893	+	0x88, 0x08, // mov %cl,(%eax)
1894	+	0x66, 0x8b, 0x00, // mov (%eax),%ax
1895	+	0x66, 0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%cx
1896	+	0x66, 0x89, 0x00, // mov %ax,(%eax)
1897	+	0x66, 0x89, 0x0c, 0x18, // mov %cx,(%eax,%ebx,1)
1898	+	0x8b, 0x00, // mov (%eax),%eax
1899	+	0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%ecx
1900	+	0x89, 0x00, // mov %eax,(%eax)
1901	+	0x89, 0x0c, 0x18, // mov %ecx,(%eax,%ebx,1)
1902	+	#if defined(__x86_64__)
1903	+	0x44, 0x8a, 0x00, // mov (%rax),%r8b
1904	+	0x44, 0x8a, 0x20, // mov (%rax),%r12b
1905	+	0x42, 0x8a, 0x3c, 0x10, // mov (%rax,%r10,1),%dil
1906	+	0x44, 0x88, 0x00, // mov %r8b,(%rax)
1907	+	0x44, 0x88, 0x20, // mov %r12b,(%rax)
1908	+	0x42, 0x88, 0x3c, 0x10, // mov %dil,(%rax,%r10,1)
1909	+	0x66, 0x44, 0x8b, 0x00, // mov (%rax),%r8w
1910	+	0x66, 0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%cx
1911	+	0x66, 0x44, 0x89, 0x00, // mov %r8w,(%rax)
1912	+	0x66, 0x42, 0x89, 0x0c, 0x10, // mov %cx,(%rax,%r10,1)
1913	+	0x44, 0x8b, 0x00, // mov (%rax),%r8d
1914	+	0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%ecx
1915	+	0x44, 0x89, 0x00, // mov %r8d,(%rax)
1916	+	0x42, 0x89, 0x0c, 0x10, // mov %ecx,(%rax,%r10,1)
1917	+	0x48, 0x8b, 0x08, // mov (%rax),%rcx
1918	+	0x4c, 0x8b, 0x18, // mov (%rax),%r11
1919	+	0x4a, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%rcx
1920	+	0x4e, 0x8b, 0x1c, 0x10, // mov (%rax,%r10,1),%r11
1921	+	0x48, 0x89, 0x08, // mov %rcx,(%rax)
1922	+	0x4c, 0x89, 0x18, // mov %r11,(%rax)
1923	+	0x4a, 0x89, 0x0c, 0x10, // mov %rcx,(%rax,%r10,1)
1924	+	0x4e, 0x89, 0x1c, 0x10, // mov %r11,(%rax,%r10,1)
1925	+	#endif
1926	+	0 // end
1927	+	};
1928	+	const int N_REGS = 20;
1929	+	unsigned long regs[N_REGS];
1930	+	for (int i = 0; i < N_REGS; i++)
1931	+	regs[i] = i;
1932	+	const unsigned long start_code = (unsigned long)&code;
1933	+	regs[X86_REG_EIP] = start_code;
1934	+	while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
1935	+	&& ix86_skip_instruction(regs))
1936	+	; /* simply iterate */
1937	+	return (regs[X86_REG_EIP] - start_code) == (sizeof(code) - 1);
1938	+	#endif
1939	+	return true;
1940	+	}
1941		#endif
1942
1943		int main(void)
#	Line 1314 \| Line 1984 \| int main(void)
1984		return 8;
1985
1986		#define TEST_SKIP_INSTRUCTION(TYPE) do { \
1987	<	const unsigned int TAG = 0x12345678; \
1987	>	const unsigned long TAG = 0x12345678 \| \
1988	>	(sizeof(long) == 8 ? 0x9abcdef0UL << 31 : 0); \
1989		TYPE data = ((TYPE )(page + sizeof(TYPE))); \
1990	<	volatile unsigned int effect = data + TAG; \
1990	>	volatile unsigned long effect = data + TAG; \
1991		if (effect != TAG) \
1992		return 9; \
1993		} while (0)
#	Line 1329 \| Line 2000 \| int main(void)
2000		TEST_SKIP_INSTRUCTION(unsigned char);
2001		TEST_SKIP_INSTRUCTION(unsigned short);
2002		TEST_SKIP_INSTRUCTION(unsigned int);
2003	+	TEST_SKIP_INSTRUCTION(unsigned long);
2004	+	TEST_SKIP_INSTRUCTION(signed char);
2005	+	TEST_SKIP_INSTRUCTION(signed short);
2006	+	TEST_SKIP_INSTRUCTION(signed int);
2007	+	TEST_SKIP_INSTRUCTION(signed long);
2008		L_e_region2:
2009	+
2010	+	if (!arch_insn_skipper_tests())
2011	+	return 20;
2012		#endif
2013
2014		vm_exit();
2015		return 0;
2016		}
2017		#endif
1339	–
1340	–
1341	–
1342	–
1343	–
1344	–
1345	–
1346	–
1347	–
1348	–
1349	–
1350	–
1351	–
1352	–
1353	–

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.33 by gbeauche, 2003-10-21T23:10:19Z vs. Revision 1.44 by gbeauche, 2004-01-21T23:14:28Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.33 by gbeauche, 2003-10-21T23:10:19Z vs.
Revision 1.44 by gbeauche, 2004-01-21T23:14:28Z