[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.33 by gbeauche, 2003-10-21T23:10:19Z vs.
Revision 1.42 by gbeauche, 2004-01-19T16:59:13Z

#	Line 10 \| Line 10
10		* tjw@omnigroup.com Sun, 4 Jun 2000
11		* www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	* Basilisk II (C) 1997-2002 Christian Bauer
13	>	* Basilisk II (C) 1997-2004 Christian Bauer
14		*
15		* This program is free software; you can redistribute it and/or modify
16		* it under the terms of the GNU General Public License as published by
#	Line 36 \| Line 36
36		#endif
37
38		#include <list>
39	+	#include <stdio.h>
40		#include <signal.h>
41		#include "sigsegv.h"
42
#	Line 69 \| Line 70 \| static bool sigsegv_do_install_handler(i
70		enum transfer_size_t {
71		SIZE_UNKNOWN,
72		SIZE_BYTE,
73	<	SIZE_WORD,
74	<	SIZE_LONG
73	>	SIZE_WORD, // 2 bytes
74	>	SIZE_LONG, // 4 bytes
75	>	SIZE_QUAD, // 8 bytes
76		};
77
78		// Transfer type
#	Line 221 \| Line 223 \| static void powerpc_decode_instruction(i
223		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t sip, void scp
224		#define SIGSEGV_FAULT_HANDLER_ARGS sip, scp
225		#define SIGSEGV_FAULT_ADDRESS sip->si_addr
226	+	#if (defined(sgi) \|\| defined(__sgi))
227	+	#include <ucontext.h>
228	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
229	+	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
230	+	#if (defined(mips) \|\| defined(__mips))
231	+	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
232	+	#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
233	+	#endif
234	+	#endif
235		#if defined(__sun__)
236		#if (defined(sparc) \|\| defined(__sparc__))
237	+	#include <sys/stack.h>
238	+	#include <sys/regset.h>
239		#include <sys/ucontext.h>
240		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
241		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[REG_PC]
242	+	#define SIGSEGV_SPARC_GWINDOWS (((ucontext_t *)scp)->uc_mcontext.gwins)
243	+	#define SIGSEGV_SPARC_RWINDOW (struct rwindow )((char )SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
244	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
245	+	#define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction
246		#endif
247		#endif
248		#if defined(__FreeBSD__)
249		#if (defined(i386) \|\| defined(__i386__))
250		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
251	<	#define SIGSEGV_REGISTER_FILE ((unsigned int )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
251	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
252		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
253		#endif
254		#endif
#	Line 240 \| Line 257 \| static void powerpc_decode_instruction(i
257		#include <sys/ucontext.h>
258		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
259		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
260	<	#define SIGSEGV_REGISTER_FILE (unsigned int *)SIGSEGV_CONTEXT_REGS
260	>	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
261		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
262		#endif
263		#if (defined(x86_64) \|\| defined(__x86_64__))
#	Line 248 \| Line 265 \| static void powerpc_decode_instruction(i
265		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
266		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
267		#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
268	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
269		#endif
270		#if (defined(ia64) \|\| defined(__ia64__))
271		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext )scp)->sc_ip & ~0x3ULL) / slot number is in bits 0 and 1 */
#	Line 259 \| Line 277 \| static void powerpc_decode_instruction(i
277		#define SIGSEGV_REGISTER_FILE (unsigned int )&SIGSEGV_CONTEXT_REGS->nip, (unsigned int )(SIGSEGV_CONTEXT_REGS->gpr)
278		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
279		#endif
280	+	#if (defined(hppa) \|\| defined(__hppa__))
281	+	#undef SIGSEGV_FAULT_ADDRESS
282	+	#define SIGSEGV_FAULT_ADDRESS sip->si_ptr
283	+	#endif
284	+	#if (defined(arm) \|\| defined(__arm__))
285	+	#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
286	+	#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext)
287	+	#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.arm_pc)
288	+	#endif
289		#endif
290		#endif
291
#	Line 273 \| Line 300 \| static void powerpc_decode_instruction(i
300		#define SIGSEGV_FAULT_HANDLER_ARGS &scs
301		#define SIGSEGV_FAULT_ADDRESS scp->cr2
302		#define SIGSEGV_FAULT_INSTRUCTION scp->eip
303	<	#define SIGSEGV_REGISTER_FILE (unsigned int *)scp
303	>	#define SIGSEGV_REGISTER_FILE (unsigned long *)scp
304		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
305		#endif
306		#if (defined(sparc) \|\| defined(__sparc__))
#	Line 298 \| Line 325 \| static void powerpc_decode_instruction(i
325		#define SIGSEGV_FAULT_ADDRESS get_fault_address(scp)
326		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
327		#endif
328	+	#if (defined(arm) \|\| defined(__arm__))
329	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int r1, int r2, int r3, struct sigcontext sc
330	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp
331	+	#define SIGSEGV_FAULT_HANDLER_ARGS &sc
332	+	#define SIGSEGV_FAULT_ADDRESS scp->fault_address
333	+	#define SIGSEGV_FAULT_INSTRUCTION scp->arm_pc
334	+	#endif
335		#endif
336
337		// Irix 5 or 6 on MIPS
338	<	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(__SYSTYPE_SVR4))
338	>	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(_SYSTYPE_SVR4))
339		#include <ucontext.h>
340		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp
341		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp
342	<	#define SIGSEGV_FAULT_ADDRESS scp->sc_badvaddr
342	>	#define SIGSEGV_FAULT_ADDRESS (unsigned long)scp->sc_badvaddr
343	>	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)scp->sc_pc
344		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
345		#endif
346
#	Line 378 \| Line 413 \| static sigsegv_address_t get_fault_addre
413		#endif
414		#endif
415		#if defined(__FreeBSD__)
381	–	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
416		#if (defined(i386) \|\| defined(__i386__))
417	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
418		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext scp, char addr
419		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr
420		#define SIGSEGV_FAULT_ADDRESS addr
421		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_eip
422	<	#define SIGSEGV_REGISTER_FILE ((unsigned int *)&scp->sc_edi)
422	>	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi)
423		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
424		#endif
425	+	#if (defined(alpha) \|\| defined(__alpha__))
426	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
427	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, char addr, struct sigcontext scp
428	+	#define SIGSEGV_FAULT_HANDLER_ARGS sig, addr, scp
429	+	#define SIGSEGV_FAULT_ADDRESS addr
430	+	#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
431	+	#endif
432		#endif
433
434		// Extract fault address out of a sigcontext
#	Line 577 \| Line 619 \| *handleExceptions(void priv)**
619
620		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
621		// Decode and skip X86 instruction
622	<	#if (defined(i386) \|\| defined(__i386__))
622	>	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
623		#if defined(__linux__)
624		enum {
625	+	#if (defined(i386) \|\| defined(__i386__))
626		X86_REG_EIP = 14,
627		X86_REG_EAX = 11,
628		X86_REG_ECX = 10,
#	Line 589 \| Line 632 \| enum {
632		X86_REG_EBP = 6,
633		X86_REG_ESI = 5,
634		X86_REG_EDI = 4
635	+	#endif
636	+	#if defined(__x86_64__)
637	+	X86_REG_R8 = 0,
638	+	X86_REG_R9 = 1,
639	+	X86_REG_R10 = 2,
640	+	X86_REG_R11 = 3,
641	+	X86_REG_R12 = 4,
642	+	X86_REG_R13 = 5,
643	+	X86_REG_R14 = 6,
644	+	X86_REG_R15 = 7,
645	+	X86_REG_EDI = 8,
646	+	X86_REG_ESI = 9,
647	+	X86_REG_EBP = 10,
648	+	X86_REG_EBX = 11,
649	+	X86_REG_EDX = 12,
650	+	X86_REG_EAX = 13,
651	+	X86_REG_ECX = 14,
652	+	X86_REG_ESP = 15,
653	+	X86_REG_EIP = 16
654	+	#endif
655		};
656		#endif
657		#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
658		enum {
659	+	#if (defined(i386) \|\| defined(__i386__))
660		X86_REG_EIP = 10,
661		X86_REG_EAX = 7,
662		X86_REG_ECX = 6,
#	Line 602 \| Line 666 \| enum {
666		X86_REG_EBP = 2,
667		X86_REG_ESI = 1,
668		X86_REG_EDI = 0
669	+	#endif
670		};
671		#endif
672		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 638 \| Line 703 \| static inline int ix86_step_over_modrm(u
703		return offset;
704		}
705
706	<	static bool ix86_skip_instruction(unsigned int * regs)
706	>	static bool ix86_skip_instruction(unsigned long * regs)
707		{
708		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
709
#	Line 650 \| Line 715 \| static bool ix86_skip_instruction(unsign
715
716		int reg = -1;
717		int len = 0;
718	<
718	>
719	>	#if DEBUG
720	>	printf("IP: %p [%02x %02x %02x %02x...]\n",
721	>	eip, eip[0], eip[1], eip[2], eip[3]);
722	>	#endif
723	>
724		// Operand size prefix
725		if (*eip == 0x66) {
726		eip++;
#	Line 658 \| Line 728 \| static bool ix86_skip_instruction(unsign
728		transfer_size = SIZE_WORD;
729		}
730
731	+	// REX prefix
732	+	#if defined(__x86_64__)
733	+	struct rex_t {
734	+	unsigned char W;
735	+	unsigned char R;
736	+	unsigned char X;
737	+	unsigned char B;
738	+	};
739	+	rex_t rex = { 0, 0, 0, 0 };
740	+	bool has_rex = false;
741	+	if ((*eip & 0xf0) == 0x40) {
742	+	has_rex = true;
743	+	const unsigned char b = *eip;
744	+	rex.W = b & (1 << 3);
745	+	rex.R = b & (1 << 2);
746	+	rex.X = b & (1 << 1);
747	+	rex.B = b & (1 << 0);
748	+	#if DEBUG
749	+	printf("REX: %c,%c,%c,%c\n",
750	+	rex.W ? 'W' : '_',
751	+	rex.R ? 'R' : '_',
752	+	rex.X ? 'X' : '_',
753	+	rex.B ? 'B' : '_');
754	+	#endif
755	+	eip++;
756	+	len++;
757	+	if (rex.W)
758	+	transfer_size = SIZE_QUAD;
759	+	}
760	+	#else
761	+	const bool has_rex = false;
762	+	#endif
763	+
764		// Decode instruction
765		switch (eip[0]) {
766		case 0x0f:
#	Line 727 \| Line 830 \| static bool ix86_skip_instruction(unsign
830		return false;
831		}
832
833	+	#if defined(__x86_64__)
834	+	if (rex.R)
835	+	reg += 8;
836	+	#endif
837	+
838		if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
839	<	static const int x86_reg_map[8] = {
839	>	static const int x86_reg_map[] = {
840		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
841	<	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI
841	>	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
842	>	#if defined(__x86_64__)
843	>	X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
844	>	X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
845	>	#endif
846		};
847
848	<	if (reg < 0 \|\| reg >= 8)
848	>	if (reg < 0 \|\| reg >= (sizeof(x86_reg_map)/sizeof(x86_reg_map[0]) - 1))
849		return false;
850
851	+	// Set 0 to the relevant register part
852	+	// NOTE: this is only valid for MOV alike instructions
853		int rloc = x86_reg_map[reg];
854		switch (transfer_size) {
855		case SIZE_BYTE:
856	<	regs[rloc] = (regs[rloc] & ~0xff);
856	>	if (has_rex \|\| reg < 4)
857	>	regs[rloc] = (regs[rloc] & ~0x00ffL);
858	>	else {
859	>	rloc = x86_reg_map[reg - 4];
860	>	regs[rloc] = (regs[rloc] & ~0xff00L);
861	>	}
862		break;
863		case SIZE_WORD:
864	<	regs[rloc] = (regs[rloc] & ~0xffff);
864	>	regs[rloc] = (regs[rloc] & ~0xffffL);
865		break;
866		case SIZE_LONG:
867	+	case SIZE_QUAD: // zero-extension
868		regs[rloc] = 0;
869		break;
870		}
#	Line 752 \| Line 872 \| static bool ix86_skip_instruction(unsign
872
873		#if DEBUG
874		printf("%08x: %s %s access", regs[X86_REG_EIP],
875	<	transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : "long",
875	>	transfer_size == SIZE_BYTE ? "byte" :
876	>	transfer_size == SIZE_WORD ? "word" :
877	>	transfer_size == SIZE_LONG ? "long" :
878	>	transfer_size == SIZE_QUAD ? "quad" : "unknown",
879		transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
880
881		if (reg != -1) {
882	<	static const char * x86_reg_str_map[8] = {
883	<	"eax", "ecx", "edx", "ebx",
884	<	"esp", "ebp", "esi", "edi"
882	>	static const char * x86_byte_reg_str_map[] = {
883	>	"al", "cl", "dl", "bl",
884	>	"spl", "bpl", "sil", "dil",
885	>	"r8b", "r9b", "r10b", "r11b",
886	>	"r12b", "r13b", "r14b", "r15b",
887	>	"ah", "ch", "dh", "bh",
888	>	};
889	>	static const char * x86_word_reg_str_map[] = {
890	>	"ax", "cx", "dx", "bx",
891	>	"sp", "bp", "si", "di",
892	>	"r8w", "r9w", "r10w", "r11w",
893	>	"r12w", "r13w", "r14w", "r15w",
894	>	};
895	>	static const char *x86_long_reg_str_map[] = {
896	>	"eax", "ecx", "edx", "ebx",
897	>	"esp", "ebp", "esi", "edi",
898	>	"r8d", "r9d", "r10d", "r11d",
899	>	"r12d", "r13d", "r14d", "r15d",
900	>	};
901	>	static const char *x86_quad_reg_str_map[] = {
902	>	"rax", "rcx", "rdx", "rbx",
903	>	"rsp", "rbp", "rsi", "rdi",
904	>	"r8", "r9", "r10", "r11",
905	>	"r12", "r13", "r14", "r15",
906		};
907	<	printf(" %s register %%%s", transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from", x86_reg_str_map[reg]);
907	>	const char * reg_str = NULL;
908	>	switch (transfer_size) {
909	>	case SIZE_BYTE:
910	>	reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
911	>	break;
912	>	case SIZE_WORD: reg_str = x86_word_reg_str_map[reg]; break;
913	>	case SIZE_LONG: reg_str = x86_long_reg_str_map[reg]; break;
914	>	case SIZE_QUAD: reg_str = x86_quad_reg_str_map[reg]; break;
915	>	}
916	>	if (reg_str)
917	>	printf(" %s register %%%s",
918	>	transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from",
919	>	reg_str);
920		}
921		printf(", %d bytes instruction\n", len);
922		#endif
#	Line 802 \| Line 958 \| static bool powerpc_skip_instruction(uns
958		return true;
959		}
960		#endif
961	+
962	+	// Decode and skip MIPS instruction
963	+	#if (defined(mips) \|\| defined(__mips))
964	+	enum {
965	+	#if (defined(sgi) \|\| defined(__sgi))
966	+	MIPS_REG_EPC = 35,
967	+	#endif
968	+	};
969	+	static bool mips_skip_instruction(greg_t * regs)
970	+	{
971	+	unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC];
972	+
973	+	if (epc == 0)
974	+	return false;
975	+
976	+	#if DEBUG
977	+	printf("IP: %p [%08x]\n", epc, epc[0]);
978	+	#endif
979	+
980	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
981	+	transfer_size_t transfer_size = SIZE_LONG;
982	+	int direction = 0;
983	+
984	+	const unsigned int opcode = epc[0];
985	+	switch (opcode >> 26) {
986	+	case 32: // Load Byte
987	+	case 36: // Load Byte Unsigned
988	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
989	+	transfer_size = SIZE_BYTE;
990	+	break;
991	+	case 33: // Load Halfword
992	+	case 37: // Load Halfword Unsigned
993	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
994	+	transfer_size = SIZE_WORD;
995	+	break;
996	+	case 35: // Load Word
997	+	case 39: // Load Word Unsigned
998	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
999	+	transfer_size = SIZE_LONG;
1000	+	break;
1001	+	case 34: // Load Word Left
1002	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1003	+	transfer_size = SIZE_LONG;
1004	+	direction = -1;
1005	+	break;
1006	+	case 38: // Load Word Right
1007	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1008	+	transfer_size = SIZE_LONG;
1009	+	direction = 1;
1010	+	break;
1011	+	case 55: // Load Doubleword
1012	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1013	+	transfer_size = SIZE_QUAD;
1014	+	break;
1015	+	case 26: // Load Doubleword Left
1016	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1017	+	transfer_size = SIZE_QUAD;
1018	+	direction = -1;
1019	+	break;
1020	+	case 27: // Load Doubleword Right
1021	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1022	+	transfer_size = SIZE_QUAD;
1023	+	direction = 1;
1024	+	break;
1025	+	case 40: // Store Byte
1026	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1027	+	transfer_size = SIZE_BYTE;
1028	+	break;
1029	+	case 41: // Store Halfword
1030	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1031	+	transfer_size = SIZE_WORD;
1032	+	break;
1033	+	case 43: // Store Word
1034	+	case 42: // Store Word Left
1035	+	case 46: // Store Word Right
1036	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1037	+	transfer_size = SIZE_LONG;
1038	+	break;
1039	+	case 63: // Store Doubleword
1040	+	case 44: // Store Doubleword Left
1041	+	case 45: // Store Doubleword Right
1042	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1043	+	transfer_size = SIZE_QUAD;
1044	+	break;
1045	+	/* Misc instructions unlikely to be used within CPU emulators */
1046	+	case 48: // Load Linked Word
1047	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1048	+	transfer_size = SIZE_LONG;
1049	+	break;
1050	+	case 52: // Load Linked Doubleword
1051	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1052	+	transfer_size = SIZE_QUAD;
1053	+	break;
1054	+	case 56: // Store Conditional Word
1055	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1056	+	transfer_size = SIZE_LONG;
1057	+	break;
1058	+	case 60: // Store Conditional Doubleword
1059	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1060	+	transfer_size = SIZE_QUAD;
1061	+	break;
1062	+	}
1063	+
1064	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1065	+	// Unknown machine code, let it crash. Then patch the decoder
1066	+	return false;
1067	+	}
1068	+
1069	+	// Zero target register in case of a load operation
1070	+	const int reg = (opcode >> 16) & 0x1f;
1071	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD) {
1072	+	if (direction == 0)
1073	+	regs[reg] = 0;
1074	+	else {
1075	+	// FIXME: untested code
1076	+	unsigned long ea = regs[(opcode >> 21) & 0x1f];
1077	+	ea += (signed long)(signed int)(signed short)(opcode & 0xffff);
1078	+	const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7);
1079	+	unsigned long value;
1080	+	if (direction > 0) {
1081	+	const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1);
1082	+	value = regs[reg] & rmask;
1083	+	}
1084	+	else {
1085	+	const unsigned long lmask = (1L << (offset * 8)) - 1;
1086	+	value = regs[reg] & lmask;
1087	+	}
1088	+	// restore most significant bits
1089	+	if (transfer_size == SIZE_LONG)
1090	+	value = (signed long)(signed int)value;
1091	+	regs[reg] = value;
1092	+	}
1093	+	}
1094	+
1095	+	#if DEBUG
1096	+	#if (defined(_ABIN32) \|\| defined(_ABI64))
1097	+	static const char * mips_gpr_names[32] = {
1098	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1099	+	"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1100	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1101	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1102	+	};
1103	+	#else
1104	+	static const char * mips_gpr_names[32] = {
1105	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1106	+	"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
1107	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1108	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1109	+	};
1110	+	#endif
1111	+	printf("%s %s register %s\n",
1112	+	transfer_size == SIZE_BYTE ? "byte" :
1113	+	transfer_size == SIZE_WORD ? "word" :
1114	+	transfer_size == SIZE_LONG ? "long" :
1115	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1116	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1117	+	mips_gpr_names[reg]);
1118	+	#endif
1119	+
1120	+	regs[MIPS_REG_EPC] += 4;
1121	+	return true;
1122	+	}
1123	+	#endif
1124	+
1125	+	// Decode and skip SPARC instruction
1126	+	#if (defined(sparc) \|\| defined(__sparc__))
1127	+	enum {
1128	+	#if (defined(__sun__))
1129	+	SPARC_REG_G1 = REG_G1,
1130	+	SPARC_REG_O0 = REG_O0,
1131	+	SPARC_REG_PC = REG_PC,
1132	+	#endif
1133	+	};
1134	+	static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
1135	+	{
1136	+	unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
1137	+
1138	+	if (pc == 0)
1139	+	return false;
1140	+
1141	+	#if DEBUG
1142	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1143	+	#endif
1144	+
1145	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1146	+	transfer_size_t transfer_size = SIZE_LONG;
1147	+	bool register_pair = false;
1148	+
1149	+	const unsigned int opcode = pc[0];
1150	+	if ((opcode >> 30) != 3)
1151	+	return false;
1152	+	switch ((opcode >> 19) & 0x3f) {
1153	+	case 9: // Load Signed Byte
1154	+	case 1: // Load Unsigned Byte
1155	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1156	+	transfer_size = SIZE_BYTE;
1157	+	break;
1158	+	case 10:// Load Signed Halfword
1159	+	case 2: // Load Unsigned Word
1160	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1161	+	transfer_size = SIZE_WORD;
1162	+	break;
1163	+	case 8: // Load Word
1164	+	case 0: // Load Unsigned Word
1165	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1166	+	transfer_size = SIZE_LONG;
1167	+	break;
1168	+	case 11:// Load Extended Word
1169	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1170	+	transfer_size = SIZE_QUAD;
1171	+	break;
1172	+	case 3: // Load Doubleword
1173	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1174	+	transfer_size = SIZE_LONG;
1175	+	register_pair = true;
1176	+	break;
1177	+	case 5: // Store Byte
1178	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1179	+	transfer_size = SIZE_BYTE;
1180	+	break;
1181	+	case 6: // Store Halfword
1182	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1183	+	transfer_size = SIZE_WORD;
1184	+	break;
1185	+	case 4: // Store Word
1186	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1187	+	transfer_size = SIZE_LONG;
1188	+	break;
1189	+	case 14:// Store Extended Word
1190	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1191	+	transfer_size = SIZE_QUAD;
1192	+	break;
1193	+	case 7: // Store Doubleword
1194	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1195	+	transfer_size = SIZE_WORD;
1196	+	register_pair = true;
1197	+	break;
1198	+	}
1199	+
1200	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1201	+	// Unknown machine code, let it crash. Then patch the decoder
1202	+	return false;
1203	+	}
1204	+
1205	+	// Zero target register in case of a load operation
1206	+	const int reg = (opcode >> 25) & 0x1f;
1207	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1208	+	// FIXME: code to handle local & input registers is not tested
1209	+	if (reg >= 1 && reg <= 7) {
1210	+	// global registers
1211	+	regs[reg - 1 + SPARC_REG_G1] = 0;
1212	+	}
1213	+	else if (reg >= 8 && reg <= 15) {
1214	+	// output registers
1215	+	regs[reg - 8 + SPARC_REG_O0] = 0;
1216	+	}
1217	+	else if (reg >= 16 && reg <= 23) {
1218	+	// local registers (in register windows)
1219	+	if (gwins)
1220	+	gwins->wbuf->rw_local[reg - 16] = 0;
1221	+	else
1222	+	rwin->rw_local[reg - 16] = 0;
1223	+	}
1224	+	else {
1225	+	// input registers (in register windows)
1226	+	if (gwins)
1227	+	gwins->wbuf->rw_in[reg - 24] = 0;
1228	+	else
1229	+	rwin->rw_in[reg - 24] = 0;
1230	+	}
1231	+	}
1232	+
1233	+	#if DEBUG
1234	+	static const char * reg_names[] = {
1235	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1236	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1237	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1238	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1239	+	};
1240	+	printf("%s %s register %s\n",
1241	+	transfer_size == SIZE_BYTE ? "byte" :
1242	+	transfer_size == SIZE_WORD ? "word" :
1243	+	transfer_size == SIZE_LONG ? "long" :
1244	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1245	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1246	+	reg_names[reg]);
1247	+	#endif
1248	+
1249	+	regs[SPARC_REG_PC] += 4;
1250	+	return true;
1251	+	}
1252	+	#endif
1253		#endif
1254
1255		// Fallbacks
#	Line 1235 \| Line 1683 \| *static void b_region, e_region;*
1683
1684		static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
1685		{
1686	+	#if DEBUG
1687	+	printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
1688	+	printf("expected fault at %p\n", page + REF_INDEX);
1689	+	#ifdef __GNUC__
1690	+	printf("expected instruction address range: %p-%p\n", b_region, e_region);
1691	+	#endif
1692	+	#endif
1693		handler_called++;
1694		if ((fault_address - REF_INDEX) != page)
1695		exit(10);
#	Line 1268 \| Line 1723 \| static sigsegv_return_t sigsegv_insn_han
1723
1724		return SIGSEGV_RETURN_FAILURE;
1725		}
1726	+
1727	+	// More sophisticated tests for instruction skipper
1728	+	static bool arch_insn_skipper_tests()
1729	+	{
1730	+	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
1731	+	static const unsigned char code[] = {
1732	+	0x8a, 0x00, // mov (%eax),%al
1733	+	0x8a, 0x2c, 0x18, // mov (%eax,%ebx,1),%ch
1734	+	0x88, 0x20, // mov %ah,(%eax)
1735	+	0x88, 0x08, // mov %cl,(%eax)
1736	+	0x66, 0x8b, 0x00, // mov (%eax),%ax
1737	+	0x66, 0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%cx
1738	+	0x66, 0x89, 0x00, // mov %ax,(%eax)
1739	+	0x66, 0x89, 0x0c, 0x18, // mov %cx,(%eax,%ebx,1)
1740	+	0x8b, 0x00, // mov (%eax),%eax
1741	+	0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%ecx
1742	+	0x89, 0x00, // mov %eax,(%eax)
1743	+	0x89, 0x0c, 0x18, // mov %ecx,(%eax,%ebx,1)
1744	+	#if defined(__x86_64__)
1745	+	0x44, 0x8a, 0x00, // mov (%rax),%r8b
1746	+	0x44, 0x8a, 0x20, // mov (%rax),%r12b
1747	+	0x42, 0x8a, 0x3c, 0x10, // mov (%rax,%r10,1),%dil
1748	+	0x44, 0x88, 0x00, // mov %r8b,(%rax)
1749	+	0x44, 0x88, 0x20, // mov %r12b,(%rax)
1750	+	0x42, 0x88, 0x3c, 0x10, // mov %dil,(%rax,%r10,1)
1751	+	0x66, 0x44, 0x8b, 0x00, // mov (%rax),%r8w
1752	+	0x66, 0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%cx
1753	+	0x66, 0x44, 0x89, 0x00, // mov %r8w,(%rax)
1754	+	0x66, 0x42, 0x89, 0x0c, 0x10, // mov %cx,(%rax,%r10,1)
1755	+	0x44, 0x8b, 0x00, // mov (%rax),%r8d
1756	+	0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%ecx
1757	+	0x44, 0x89, 0x00, // mov %r8d,(%rax)
1758	+	0x42, 0x89, 0x0c, 0x10, // mov %ecx,(%rax,%r10,1)
1759	+	0x48, 0x8b, 0x08, // mov (%rax),%rcx
1760	+	0x4c, 0x8b, 0x18, // mov (%rax),%r11
1761	+	0x4a, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%rcx
1762	+	0x4e, 0x8b, 0x1c, 0x10, // mov (%rax,%r10,1),%r11
1763	+	0x48, 0x89, 0x08, // mov %rcx,(%rax)
1764	+	0x4c, 0x89, 0x18, // mov %r11,(%rax)
1765	+	0x4a, 0x89, 0x0c, 0x10, // mov %rcx,(%rax,%r10,1)
1766	+	0x4e, 0x89, 0x1c, 0x10, // mov %r11,(%rax,%r10,1)
1767	+	#endif
1768	+	0 // end
1769	+	};
1770	+	const int N_REGS = 20;
1771	+	unsigned long regs[N_REGS];
1772	+	for (int i = 0; i < N_REGS; i++)
1773	+	regs[i] = i;
1774	+	const unsigned long start_code = (unsigned long)&code;
1775	+	regs[X86_REG_EIP] = start_code;
1776	+	while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
1777	+	&& ix86_skip_instruction(regs))
1778	+	; /* simply iterate */
1779	+	return (regs[X86_REG_EIP] - start_code) == (sizeof(code) - 1);
1780	+	#endif
1781	+	return true;
1782	+	}
1783		#endif
1784
1785		int main(void)
#	Line 1314 \| Line 1826 \| int main(void)
1826		return 8;
1827
1828		#define TEST_SKIP_INSTRUCTION(TYPE) do { \
1829	<	const unsigned int TAG = 0x12345678; \
1829	>	const unsigned long TAG = 0x12345678 \| \
1830	>	(sizeof(long) == 8 ? 0x9abcdef0UL << 31 : 0); \
1831		TYPE data = ((TYPE )(page + sizeof(TYPE))); \
1832	<	volatile unsigned int effect = data + TAG; \
1832	>	volatile unsigned long effect = data + TAG; \
1833		if (effect != TAG) \
1834		return 9; \
1835		} while (0)
#	Line 1329 \| Line 1842 \| int main(void)
1842		TEST_SKIP_INSTRUCTION(unsigned char);
1843		TEST_SKIP_INSTRUCTION(unsigned short);
1844		TEST_SKIP_INSTRUCTION(unsigned int);
1845	+	TEST_SKIP_INSTRUCTION(unsigned long);
1846		L_e_region2:
1847	+
1848	+	if (!arch_insn_skipper_tests())
1849	+	return 20;
1850		#endif
1851
1852		vm_exit();
1853		return 0;
1854		}
1855		#endif
1339	–
1340	–
1341	–
1342	–
1343	–
1344	–
1345	–
1346	–
1347	–
1348	–
1349	–
1350	–
1351	–
1352	–
1353	–

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.33 by gbeauche, 2003-10-21T23:10:19Z vs. Revision 1.42 by gbeauche, 2004-01-19T16:59:13Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.33 by gbeauche, 2003-10-21T23:10:19Z vs.
Revision 1.42 by gbeauche, 2004-01-19T16:59:13Z