10 |
|
* tjw@omnigroup.com Sun, 4 Jun 2000 |
11 |
|
* www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html |
12 |
|
* |
13 |
< |
* Basilisk II (C) 1997-2002 Christian Bauer |
13 |
> |
* Basilisk II (C) 1997-2004 Christian Bauer |
14 |
|
* |
15 |
|
* This program is free software; you can redistribute it and/or modify |
16 |
|
* it under the terms of the GNU General Public License as published by |
36 |
|
#endif |
37 |
|
|
38 |
|
#include <list> |
39 |
+ |
#include <stdio.h> |
40 |
|
#include <signal.h> |
41 |
|
#include "sigsegv.h" |
42 |
|
|
223 |
|
#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t *sip, void *scp |
224 |
|
#define SIGSEGV_FAULT_HANDLER_ARGS sip, scp |
225 |
|
#define SIGSEGV_FAULT_ADDRESS sip->si_addr |
226 |
+ |
#if (defined(sgi) || defined(__sgi)) |
227 |
+ |
#include <ucontext.h> |
228 |
+ |
#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) |
229 |
+ |
#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC] |
230 |
+ |
#if (defined(mips) || defined(__mips)) |
231 |
+ |
#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS |
232 |
+ |
#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction |
233 |
+ |
#endif |
234 |
+ |
#endif |
235 |
|
#if defined(__sun__) |
236 |
|
#if (defined(sparc) || defined(__sparc__)) |
237 |
+ |
#include <sys/stack.h> |
238 |
+ |
#include <sys/regset.h> |
239 |
|
#include <sys/ucontext.h> |
240 |
|
#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) |
241 |
|
#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[REG_PC] |
242 |
+ |
#define SIGSEGV_SPARC_GWINDOWS (((ucontext_t *)scp)->uc_mcontext.gwins) |
243 |
+ |
#define SIGSEGV_SPARC_RWINDOW (struct rwindow *)((char *)SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS) |
244 |
+ |
#define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW |
245 |
+ |
#define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction |
246 |
|
#endif |
247 |
|
#endif |
248 |
|
#if defined(__FreeBSD__) |
277 |
|
#define SIGSEGV_REGISTER_FILE (unsigned int *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned int *)(SIGSEGV_CONTEXT_REGS->gpr) |
278 |
|
#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction |
279 |
|
#endif |
280 |
+ |
#if (defined(hppa) || defined(__hppa__)) |
281 |
+ |
#undef SIGSEGV_FAULT_ADDRESS |
282 |
+ |
#define SIGSEGV_FAULT_ADDRESS sip->si_ptr |
283 |
+ |
#endif |
284 |
|
#endif |
285 |
|
#endif |
286 |
|
|
323 |
|
#endif |
324 |
|
|
325 |
|
// Irix 5 or 6 on MIPS |
326 |
< |
#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(__SYSTYPE_SVR4)) |
326 |
> |
#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(_SYSTYPE_SVR4)) |
327 |
|
#include <ucontext.h> |
328 |
|
#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp |
329 |
|
#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp |
330 |
< |
#define SIGSEGV_FAULT_ADDRESS scp->sc_badvaddr |
330 |
> |
#define SIGSEGV_FAULT_ADDRESS (unsigned long)scp->sc_badvaddr |
331 |
> |
#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)scp->sc_pc |
332 |
|
#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) |
333 |
|
#endif |
334 |
|
|
401 |
|
#endif |
402 |
|
#endif |
403 |
|
#if defined(__FreeBSD__) |
383 |
– |
#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS) |
404 |
|
#if (defined(i386) || defined(__i386__)) |
405 |
+ |
#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS) |
406 |
|
#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp, char *addr |
407 |
|
#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr |
408 |
|
#define SIGSEGV_FAULT_ADDRESS addr |
410 |
|
#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi) |
411 |
|
#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction |
412 |
|
#endif |
413 |
+ |
#if (defined(alpha) || defined(__alpha__)) |
414 |
+ |
#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) |
415 |
+ |
#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, char *addr, struct sigcontext *scp |
416 |
+ |
#define SIGSEGV_FAULT_HANDLER_ARGS sig, addr, scp |
417 |
+ |
#define SIGSEGV_FAULT_ADDRESS addr |
418 |
+ |
#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc |
419 |
+ |
#endif |
420 |
|
#endif |
421 |
|
|
422 |
|
// Extract fault address out of a sigcontext |
841 |
|
int rloc = x86_reg_map[reg]; |
842 |
|
switch (transfer_size) { |
843 |
|
case SIZE_BYTE: |
844 |
< |
if (!has_rex && reg >= 4) |
845 |
< |
regs[rloc - 4] = (regs[rloc - 4] & ~0xff00L); |
846 |
< |
else |
847 |
< |
regs[rloc] = (regs[rloc] & ~0xffL); |
844 |
> |
if (has_rex || reg < 4) |
845 |
> |
regs[rloc] = (regs[rloc] & ~0x00ffL); |
846 |
> |
else { |
847 |
> |
rloc = x86_reg_map[reg - 4]; |
848 |
> |
regs[rloc] = (regs[rloc] & ~0xff00L); |
849 |
> |
} |
850 |
|
break; |
851 |
|
case SIZE_WORD: |
852 |
|
regs[rloc] = (regs[rloc] & ~0xffffL); |
946 |
|
return true; |
947 |
|
} |
948 |
|
#endif |
949 |
+ |
|
950 |
+ |
// Decode and skip MIPS instruction |
951 |
+ |
#if (defined(mips) || defined(__mips)) |
952 |
+ |
enum { |
953 |
+ |
#if (defined(sgi) || defined(__sgi)) |
954 |
+ |
MIPS_REG_EPC = 35, |
955 |
+ |
#endif |
956 |
+ |
}; |
957 |
+ |
static bool mips_skip_instruction(greg_t * regs) |
958 |
+ |
{ |
959 |
+ |
unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC]; |
960 |
+ |
|
961 |
+ |
if (epc == 0) |
962 |
+ |
return false; |
963 |
+ |
|
964 |
+ |
#if DEBUG |
965 |
+ |
printf("IP: %p [%08x]\n", epc, epc[0]); |
966 |
+ |
#endif |
967 |
+ |
|
968 |
+ |
transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN; |
969 |
+ |
transfer_size_t transfer_size = SIZE_LONG; |
970 |
+ |
int direction = 0; |
971 |
+ |
|
972 |
+ |
const unsigned int opcode = epc[0]; |
973 |
+ |
switch (opcode >> 26) { |
974 |
+ |
case 32: // Load Byte |
975 |
+ |
case 36: // Load Byte Unsigned |
976 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
977 |
+ |
transfer_size = SIZE_BYTE; |
978 |
+ |
break; |
979 |
+ |
case 33: // Load Halfword |
980 |
+ |
case 37: // Load Halfword Unsigned |
981 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
982 |
+ |
transfer_size = SIZE_WORD; |
983 |
+ |
break; |
984 |
+ |
case 35: // Load Word |
985 |
+ |
case 39: // Load Word Unsigned |
986 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
987 |
+ |
transfer_size = SIZE_LONG; |
988 |
+ |
break; |
989 |
+ |
case 34: // Load Word Left |
990 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
991 |
+ |
transfer_size = SIZE_LONG; |
992 |
+ |
direction = -1; |
993 |
+ |
break; |
994 |
+ |
case 38: // Load Word Right |
995 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
996 |
+ |
transfer_size = SIZE_LONG; |
997 |
+ |
direction = 1; |
998 |
+ |
break; |
999 |
+ |
case 55: // Load Doubleword |
1000 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1001 |
+ |
transfer_size = SIZE_QUAD; |
1002 |
+ |
break; |
1003 |
+ |
case 26: // Load Doubleword Left |
1004 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1005 |
+ |
transfer_size = SIZE_QUAD; |
1006 |
+ |
direction = -1; |
1007 |
+ |
break; |
1008 |
+ |
case 27: // Load Doubleword Right |
1009 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1010 |
+ |
transfer_size = SIZE_QUAD; |
1011 |
+ |
direction = 1; |
1012 |
+ |
break; |
1013 |
+ |
case 40: // Store Byte |
1014 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1015 |
+ |
transfer_size = SIZE_BYTE; |
1016 |
+ |
break; |
1017 |
+ |
case 41: // Store Halfword |
1018 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1019 |
+ |
transfer_size = SIZE_WORD; |
1020 |
+ |
break; |
1021 |
+ |
case 43: // Store Word |
1022 |
+ |
case 42: // Store Word Left |
1023 |
+ |
case 46: // Store Word Right |
1024 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1025 |
+ |
transfer_size = SIZE_LONG; |
1026 |
+ |
break; |
1027 |
+ |
case 63: // Store Doubleword |
1028 |
+ |
case 44: // Store Doubleword Left |
1029 |
+ |
case 45: // Store Doubleword Right |
1030 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1031 |
+ |
transfer_size = SIZE_QUAD; |
1032 |
+ |
break; |
1033 |
+ |
/* Misc instructions unlikely to be used within CPU emulators */ |
1034 |
+ |
case 48: // Load Linked Word |
1035 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1036 |
+ |
transfer_size = SIZE_LONG; |
1037 |
+ |
break; |
1038 |
+ |
case 52: // Load Linked Doubleword |
1039 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1040 |
+ |
transfer_size = SIZE_QUAD; |
1041 |
+ |
break; |
1042 |
+ |
case 56: // Store Conditional Word |
1043 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1044 |
+ |
transfer_size = SIZE_LONG; |
1045 |
+ |
break; |
1046 |
+ |
case 60: // Store Conditional Doubleword |
1047 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1048 |
+ |
transfer_size = SIZE_QUAD; |
1049 |
+ |
break; |
1050 |
+ |
} |
1051 |
+ |
|
1052 |
+ |
if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) { |
1053 |
+ |
// Unknown machine code, let it crash. Then patch the decoder |
1054 |
+ |
return false; |
1055 |
+ |
} |
1056 |
+ |
|
1057 |
+ |
// Zero target register in case of a load operation |
1058 |
+ |
const int reg = (opcode >> 16) & 0x1f; |
1059 |
+ |
if (transfer_type == SIGSEGV_TRANSFER_LOAD) { |
1060 |
+ |
if (direction == 0) |
1061 |
+ |
regs[reg] = 0; |
1062 |
+ |
else { |
1063 |
+ |
// FIXME: untested code |
1064 |
+ |
unsigned long ea = regs[(opcode >> 21) & 0x1f]; |
1065 |
+ |
ea += (signed long)(signed int)(signed short)(opcode & 0xffff); |
1066 |
+ |
const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7); |
1067 |
+ |
unsigned long value; |
1068 |
+ |
if (direction > 0) { |
1069 |
+ |
const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1); |
1070 |
+ |
value = regs[reg] & rmask; |
1071 |
+ |
} |
1072 |
+ |
else { |
1073 |
+ |
const unsigned long lmask = (1L << (offset * 8)) - 1; |
1074 |
+ |
value = regs[reg] & lmask; |
1075 |
+ |
} |
1076 |
+ |
// restore most significant bits |
1077 |
+ |
if (transfer_size == SIZE_LONG) |
1078 |
+ |
value = (signed long)(signed int)value; |
1079 |
+ |
regs[reg] = value; |
1080 |
+ |
} |
1081 |
+ |
} |
1082 |
+ |
|
1083 |
+ |
#if DEBUG |
1084 |
+ |
#if (defined(_ABIN32) || defined(_ABI64)) |
1085 |
+ |
static const char * mips_gpr_names[32] = { |
1086 |
+ |
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
1087 |
+ |
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
1088 |
+ |
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
1089 |
+ |
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" |
1090 |
+ |
}; |
1091 |
+ |
#else |
1092 |
+ |
static const char * mips_gpr_names[32] = { |
1093 |
+ |
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
1094 |
+ |
"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", |
1095 |
+ |
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
1096 |
+ |
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" |
1097 |
+ |
}; |
1098 |
+ |
#endif |
1099 |
+ |
printf("%s %s register %s\n", |
1100 |
+ |
transfer_size == SIZE_BYTE ? "byte" : |
1101 |
+ |
transfer_size == SIZE_WORD ? "word" : |
1102 |
+ |
transfer_size == SIZE_LONG ? "long" : |
1103 |
+ |
transfer_size == SIZE_QUAD ? "quad" : "unknown", |
1104 |
+ |
transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from", |
1105 |
+ |
mips_gpr_names[reg]); |
1106 |
+ |
#endif |
1107 |
+ |
|
1108 |
+ |
regs[MIPS_REG_EPC] += 4; |
1109 |
+ |
return true; |
1110 |
+ |
} |
1111 |
+ |
#endif |
1112 |
+ |
|
1113 |
+ |
// Decode and skip SPARC instruction |
1114 |
+ |
#if (defined(sparc) || defined(__sparc__)) |
1115 |
+ |
enum { |
1116 |
+ |
#if (defined(__sun__)) |
1117 |
+ |
SPARC_REG_G1 = REG_G1, |
1118 |
+ |
SPARC_REG_O0 = REG_O0, |
1119 |
+ |
SPARC_REG_PC = REG_PC, |
1120 |
+ |
#endif |
1121 |
+ |
}; |
1122 |
+ |
static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin) |
1123 |
+ |
{ |
1124 |
+ |
unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC]; |
1125 |
+ |
|
1126 |
+ |
if (pc == 0) |
1127 |
+ |
return false; |
1128 |
+ |
|
1129 |
+ |
#if DEBUG |
1130 |
+ |
printf("IP: %p [%08x]\n", pc, pc[0]); |
1131 |
+ |
#endif |
1132 |
+ |
|
1133 |
+ |
transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN; |
1134 |
+ |
transfer_size_t transfer_size = SIZE_LONG; |
1135 |
+ |
bool register_pair = false; |
1136 |
+ |
|
1137 |
+ |
const unsigned int opcode = pc[0]; |
1138 |
+ |
if ((opcode >> 30) != 3) |
1139 |
+ |
return false; |
1140 |
+ |
switch ((opcode >> 19) & 0x3f) { |
1141 |
+ |
case 9: // Load Signed Byte |
1142 |
+ |
case 1: // Load Unsigned Byte |
1143 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1144 |
+ |
transfer_size = SIZE_BYTE; |
1145 |
+ |
break; |
1146 |
+ |
case 10:// Load Signed Halfword |
1147 |
+ |
case 2: // Load Unsigned Word |
1148 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1149 |
+ |
transfer_size = SIZE_WORD; |
1150 |
+ |
break; |
1151 |
+ |
case 8: // Load Word |
1152 |
+ |
case 0: // Load Unsigned Word |
1153 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1154 |
+ |
transfer_size = SIZE_LONG; |
1155 |
+ |
break; |
1156 |
+ |
case 11:// Load Extended Word |
1157 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1158 |
+ |
transfer_size = SIZE_QUAD; |
1159 |
+ |
break; |
1160 |
+ |
case 3: // Load Doubleword |
1161 |
+ |
transfer_type = SIGSEGV_TRANSFER_LOAD; |
1162 |
+ |
transfer_size = SIZE_LONG; |
1163 |
+ |
register_pair = true; |
1164 |
+ |
break; |
1165 |
+ |
case 5: // Store Byte |
1166 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1167 |
+ |
transfer_size = SIZE_BYTE; |
1168 |
+ |
break; |
1169 |
+ |
case 6: // Store Halfword |
1170 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1171 |
+ |
transfer_size = SIZE_WORD; |
1172 |
+ |
break; |
1173 |
+ |
case 4: // Store Word |
1174 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1175 |
+ |
transfer_size = SIZE_LONG; |
1176 |
+ |
break; |
1177 |
+ |
case 14:// Store Extended Word |
1178 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1179 |
+ |
transfer_size = SIZE_QUAD; |
1180 |
+ |
break; |
1181 |
+ |
case 7: // Store Doubleword |
1182 |
+ |
transfer_type = SIGSEGV_TRANSFER_STORE; |
1183 |
+ |
transfer_size = SIZE_WORD; |
1184 |
+ |
register_pair = true; |
1185 |
+ |
break; |
1186 |
+ |
} |
1187 |
+ |
|
1188 |
+ |
if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) { |
1189 |
+ |
// Unknown machine code, let it crash. Then patch the decoder |
1190 |
+ |
return false; |
1191 |
+ |
} |
1192 |
+ |
|
1193 |
+ |
// Zero target register in case of a load operation |
1194 |
+ |
const int reg = (opcode >> 25) & 0x1f; |
1195 |
+ |
if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) { |
1196 |
+ |
// FIXME: code to handle local & input registers is not tested |
1197 |
+ |
if (reg >= 1 && reg <= 7) { |
1198 |
+ |
// global registers |
1199 |
+ |
regs[reg - 1 + SPARC_REG_G1] = 0; |
1200 |
+ |
} |
1201 |
+ |
else if (reg >= 8 && reg <= 15) { |
1202 |
+ |
// output registers |
1203 |
+ |
regs[reg - 8 + SPARC_REG_O0] = 0; |
1204 |
+ |
} |
1205 |
+ |
else if (reg >= 16 && reg <= 23) { |
1206 |
+ |
// local registers (in register windows) |
1207 |
+ |
if (gwins) |
1208 |
+ |
gwins->wbuf->rw_local[reg - 16] = 0; |
1209 |
+ |
else |
1210 |
+ |
rwin->rw_local[reg - 16] = 0; |
1211 |
+ |
} |
1212 |
+ |
else { |
1213 |
+ |
// input registers (in register windows) |
1214 |
+ |
if (gwins) |
1215 |
+ |
gwins->wbuf->rw_in[reg - 24] = 0; |
1216 |
+ |
else |
1217 |
+ |
rwin->rw_in[reg - 24] = 0; |
1218 |
+ |
} |
1219 |
+ |
} |
1220 |
+ |
|
1221 |
+ |
#if DEBUG |
1222 |
+ |
static const char * reg_names[] = { |
1223 |
+ |
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
1224 |
+ |
"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
1225 |
+ |
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
1226 |
+ |
"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7" |
1227 |
+ |
}; |
1228 |
+ |
printf("%s %s register %s\n", |
1229 |
+ |
transfer_size == SIZE_BYTE ? "byte" : |
1230 |
+ |
transfer_size == SIZE_WORD ? "word" : |
1231 |
+ |
transfer_size == SIZE_LONG ? "long" : |
1232 |
+ |
transfer_size == SIZE_QUAD ? "quad" : "unknown", |
1233 |
+ |
transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from", |
1234 |
+ |
reg_names[reg]); |
1235 |
+ |
#endif |
1236 |
+ |
|
1237 |
+ |
regs[SPARC_REG_PC] += 4; |
1238 |
+ |
return true; |
1239 |
+ |
} |
1240 |
+ |
#endif |
1241 |
|
#endif |
1242 |
|
|
1243 |
|
// Fallbacks |
1671 |
|
|
1672 |
|
static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address) |
1673 |
|
{ |
1674 |
+ |
#if DEBUG |
1675 |
+ |
printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address); |
1676 |
+ |
printf("expected fault at %p\n", page + REF_INDEX); |
1677 |
+ |
#ifdef __GNUC__ |
1678 |
+ |
printf("expected instruction address range: %p-%p\n", b_region, e_region); |
1679 |
+ |
#endif |
1680 |
+ |
#endif |
1681 |
|
handler_called++; |
1682 |
|
if ((fault_address - REF_INDEX) != page) |
1683 |
|
exit(10); |
1832 |
|
TEST_SKIP_INSTRUCTION(unsigned int); |
1833 |
|
TEST_SKIP_INSTRUCTION(unsigned long); |
1834 |
|
L_e_region2: |
1506 |
– |
#endif |
1835 |
|
|
1836 |
|
if (!arch_insn_skipper_tests()) |
1837 |
|
return 20; |
1838 |
+ |
#endif |
1839 |
|
|
1840 |
|
vm_exit(); |
1841 |
|
return 0; |