54 |
|
|
55 |
|
|
56 |
|
/* |
57 |
+ |
* Instruction decoding aids |
58 |
+ |
*/ |
59 |
+ |
|
60 |
+ |
// Transfer type |
61 |
+ |
enum transfer_type_t { |
62 |
+ |
TYPE_UNKNOWN, |
63 |
+ |
TYPE_LOAD, |
64 |
+ |
TYPE_STORE |
65 |
+ |
}; |
66 |
+ |
|
67 |
+ |
// Transfer size |
68 |
+ |
enum transfer_size_t { |
69 |
+ |
SIZE_UNKNOWN, |
70 |
+ |
SIZE_BYTE, |
71 |
+ |
SIZE_WORD, |
72 |
+ |
SIZE_LONG |
73 |
+ |
}; |
74 |
+ |
|
75 |
+ |
#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__)) |
76 |
+ |
// Addressing mode |
77 |
+ |
enum addressing_mode_t { |
78 |
+ |
MODE_UNKNOWN, |
79 |
+ |
MODE_NORM, |
80 |
+ |
MODE_U, |
81 |
+ |
MODE_X, |
82 |
+ |
MODE_UX |
83 |
+ |
}; |
84 |
+ |
|
85 |
+ |
// Decoded instruction |
86 |
+ |
struct instruction_t { |
87 |
+ |
transfer_type_t transfer_type; |
88 |
+ |
transfer_size_t transfer_size; |
89 |
+ |
addressing_mode_t addr_mode; |
90 |
+ |
unsigned int addr; |
91 |
+ |
char ra, rd; |
92 |
+ |
}; |
93 |
+ |
|
94 |
+ |
static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned int * gpr) |
95 |
+ |
{ |
96 |
+ |
// Get opcode and divide into fields |
97 |
+ |
unsigned int opcode = *((unsigned int *)nip); |
98 |
+ |
unsigned int primop = opcode >> 26; |
99 |
+ |
unsigned int exop = (opcode >> 1) & 0x3ff; |
100 |
+ |
unsigned int ra = (opcode >> 16) & 0x1f; |
101 |
+ |
unsigned int rb = (opcode >> 11) & 0x1f; |
102 |
+ |
unsigned int rd = (opcode >> 21) & 0x1f; |
103 |
+ |
signed int imm = (signed short)(opcode & 0xffff); |
104 |
+ |
|
105 |
+ |
// Analyze opcode |
106 |
+ |
transfer_type_t transfer_type = TYPE_UNKNOWN; |
107 |
+ |
transfer_size_t transfer_size = SIZE_UNKNOWN; |
108 |
+ |
addressing_mode_t addr_mode = MODE_UNKNOWN; |
109 |
+ |
switch (primop) { |
110 |
+ |
case 31: |
111 |
+ |
switch (exop) { |
112 |
+ |
case 23: // lwzx |
113 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_LONG; addr_mode = MODE_X; break; |
114 |
+ |
case 55: // lwzux |
115 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_LONG; addr_mode = MODE_UX; break; |
116 |
+ |
case 87: // lbzx |
117 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_BYTE; addr_mode = MODE_X; break; |
118 |
+ |
case 119: // lbzux |
119 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_BYTE; addr_mode = MODE_UX; break; |
120 |
+ |
case 151: // stwx |
121 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_LONG; addr_mode = MODE_X; break; |
122 |
+ |
case 183: // stwux |
123 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_LONG; addr_mode = MODE_UX; break; |
124 |
+ |
case 215: // stbx |
125 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_BYTE; addr_mode = MODE_X; break; |
126 |
+ |
case 247: // stbux |
127 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_BYTE; addr_mode = MODE_UX; break; |
128 |
+ |
case 279: // lhzx |
129 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_WORD; addr_mode = MODE_X; break; |
130 |
+ |
case 311: // lhzux |
131 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_WORD; addr_mode = MODE_UX; break; |
132 |
+ |
case 343: // lhax |
133 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_WORD; addr_mode = MODE_X; break; |
134 |
+ |
case 375: // lhaux |
135 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_WORD; addr_mode = MODE_UX; break; |
136 |
+ |
case 407: // sthx |
137 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_X; break; |
138 |
+ |
case 439: // sthux |
139 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_UX; break; |
140 |
+ |
} |
141 |
+ |
break; |
142 |
+ |
|
143 |
+ |
case 32: // lwz |
144 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_LONG; addr_mode = MODE_NORM; break; |
145 |
+ |
case 33: // lwzu |
146 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_LONG; addr_mode = MODE_U; break; |
147 |
+ |
case 34: // lbz |
148 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_BYTE; addr_mode = MODE_NORM; break; |
149 |
+ |
case 35: // lbzu |
150 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_BYTE; addr_mode = MODE_U; break; |
151 |
+ |
case 36: // stw |
152 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_LONG; addr_mode = MODE_NORM; break; |
153 |
+ |
case 37: // stwu |
154 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_LONG; addr_mode = MODE_U; break; |
155 |
+ |
case 38: // stb |
156 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_BYTE; addr_mode = MODE_NORM; break; |
157 |
+ |
case 39: // stbu |
158 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_BYTE; addr_mode = MODE_U; break; |
159 |
+ |
case 40: // lhz |
160 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break; |
161 |
+ |
case 41: // lhzu |
162 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_WORD; addr_mode = MODE_U; break; |
163 |
+ |
case 42: // lha |
164 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break; |
165 |
+ |
case 43: // lhau |
166 |
+ |
transfer_type = TYPE_LOAD; transfer_size = SIZE_WORD; addr_mode = MODE_U; break; |
167 |
+ |
case 44: // sth |
168 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break; |
169 |
+ |
case 45: // sthu |
170 |
+ |
transfer_type = TYPE_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break; |
171 |
+ |
} |
172 |
+ |
|
173 |
+ |
// Calculate effective address |
174 |
+ |
unsigned int addr = 0; |
175 |
+ |
switch (addr_mode) { |
176 |
+ |
case MODE_X: |
177 |
+ |
case MODE_UX: |
178 |
+ |
if (ra == 0) |
179 |
+ |
addr = gpr[rb]; |
180 |
+ |
else |
181 |
+ |
addr = gpr[ra] + gpr[rb]; |
182 |
+ |
break; |
183 |
+ |
case MODE_NORM: |
184 |
+ |
case MODE_U: |
185 |
+ |
if (ra == 0) |
186 |
+ |
addr = (signed int)(signed short)imm; |
187 |
+ |
else |
188 |
+ |
addr = gpr[ra] + (signed int)(signed short)imm; |
189 |
+ |
break; |
190 |
+ |
default: |
191 |
+ |
break; |
192 |
+ |
} |
193 |
+ |
|
194 |
+ |
// Commit decoded instruction |
195 |
+ |
instruction->addr = addr; |
196 |
+ |
instruction->addr_mode = addr_mode; |
197 |
+ |
instruction->transfer_type = transfer_type; |
198 |
+ |
instruction->transfer_size = transfer_size; |
199 |
+ |
instruction->ra = ra; |
200 |
+ |
instruction->rd = rd; |
201 |
+ |
} |
202 |
+ |
#endif |
203 |
+ |
|
204 |
+ |
|
205 |
+ |
/* |
206 |
|
* OS-dependant SIGSEGV signals support section |
207 |
|
*/ |
208 |
|
|
215 |
|
#endif |
216 |
|
#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, siginfo_t *sip, void *scp |
217 |
|
#define SIGSEGV_FAULT_ADDRESS sip->si_addr |
218 |
+ |
#if (defined(i386) || defined(__i386__)) |
219 |
+ |
#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip) |
220 |
+ |
#define SIGSEGV_REGISTER_FILE ((unsigned int *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */ |
221 |
+ |
/* (gb) Disable because this would hang configure script for some reason |
222 |
+ |
* though standalone testing gets it right. Any idea why? |
223 |
+ |
#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction |
224 |
+ |
*/ |
225 |
+ |
#endif |
226 |
|
#if defined(__linux__) |
227 |
|
#if (defined(i386) || defined(__i386__)) |
228 |
|
#include <sys/ucontext.h> |
229 |
< |
#define SIGSEGV_FAULT_INSTRUCTION (((ucontext_t *)scp)->uc_mcontext.gregs[14]) /* should use REG_EIP instead */ |
230 |
< |
#define SIGSEGV_REGISTER_FILE (unsigned long *)(((ucontext_t *)scp)->uc_mcontext.gregs) |
229 |
> |
#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs) |
230 |
> |
#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */ |
231 |
> |
#define SIGSEGV_REGISTER_FILE (unsigned int *)SIGSEGV_CONTEXT_REGS |
232 |
|
#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction |
233 |
|
#endif |
234 |
|
#if (defined(ia64) || defined(__ia64__)) |
236 |
|
#endif |
237 |
|
#if (defined(powerpc) || defined(__powerpc__)) |
238 |
|
#include <sys/ucontext.h> |
239 |
< |
#define SIGSEGV_FAULT_INSTRUCTION (((ucontext_t *)scp)->uc_mcontext.regs->nip) |
239 |
> |
#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.regs) |
240 |
> |
#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->nip) |
241 |
> |
#define SIGSEGV_REGISTER_FILE (unsigned int *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned int *)(SIGSEGV_CONTEXT_REGS->gpr) |
242 |
> |
#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction |
243 |
|
#endif |
244 |
|
#endif |
245 |
|
#endif |
253 |
|
#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, struct sigcontext scs |
254 |
|
#define SIGSEGV_FAULT_ADDRESS scs.cr2 |
255 |
|
#define SIGSEGV_FAULT_INSTRUCTION scs.eip |
256 |
< |
#define SIGSEGV_REGISTER_FILE (unsigned long *)(&scs) |
256 |
> |
#define SIGSEGV_REGISTER_FILE (unsigned int *)(&scs) |
257 |
|
#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction |
258 |
|
#endif |
259 |
|
#if (defined(sparc) || defined(__sparc__)) |
266 |
|
#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, struct sigcontext *scp |
267 |
|
#define SIGSEGV_FAULT_ADDRESS scp->regs->dar |
268 |
|
#define SIGSEGV_FAULT_INSTRUCTION scp->regs->nip |
269 |
+ |
#define SIGSEGV_REGISTER_FILE (unsigned int *)&scp->regs->nip, (unsigned int *)(scp->regs->gpr) |
270 |
+ |
#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction |
271 |
|
#endif |
272 |
|
#if (defined(alpha) || defined(__alpha__)) |
273 |
|
#include <asm/sigcontext.h> |
321 |
|
#if (defined(m68k) || defined(__m68k__)) |
322 |
|
#include <m68k/frame.h> |
323 |
|
#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp |
324 |
< |
#define SIGSEGV_FAULT_ADDRESS ({ \ |
162 |
< |
struct sigstate { \ |
163 |
< |
int ss_flags; \ |
164 |
< |
struct frame ss_frame; \ |
165 |
< |
}; \ |
166 |
< |
struct sigstate *state = (struct sigstate *)scp->sc_ap; \ |
167 |
< |
char *fault_addr; \ |
168 |
< |
switch (state->ss_frame.f_format) { \ |
169 |
< |
case 7: /* 68040 access error */ \ |
170 |
< |
/* "code" is sometimes unreliable (i.e. contains NULL or a bogus address), reason unknown */ \ |
171 |
< |
fault_addr = state->ss_frame.f_fmt7.f_fa; \ |
172 |
< |
break; \ |
173 |
< |
default: \ |
174 |
< |
fault_addr = (char *)code; \ |
175 |
< |
break; \ |
176 |
< |
} \ |
177 |
< |
fault_addr; \ |
178 |
< |
}) |
324 |
> |
#define SIGSEGV_FAULT_ADDRESS get_fault_address(scp) |
325 |
|
#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) |
326 |
+ |
|
327 |
+ |
// Use decoding scheme from BasiliskII/m68k native |
328 |
+ |
static sigsegv_address_t get_fault_address(struct sigcontext *scp) |
329 |
+ |
{ |
330 |
+ |
struct sigstate { |
331 |
+ |
int ss_flags; |
332 |
+ |
struct frame ss_frame; |
333 |
+ |
}; |
334 |
+ |
struct sigstate *state = (struct sigstate *)scp->sc_ap; |
335 |
+ |
char *fault_addr; |
336 |
+ |
switch (state->ss_frame.f_format) { |
337 |
+ |
case 7: /* 68040 access error */ |
338 |
+ |
/* "code" is sometimes unreliable (i.e. contains NULL or a bogus address), reason unknown */ |
339 |
+ |
fault_addr = state->ss_frame.f_fmt7.f_fa; |
340 |
+ |
break; |
341 |
+ |
default: |
342 |
+ |
fault_addr = (char *)code; |
343 |
+ |
break; |
344 |
+ |
} |
345 |
+ |
return (sigsegv_address_t)fault_addr; |
346 |
+ |
} |
347 |
|
#else |
348 |
|
#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, void *scp, char *addr |
349 |
|
#define SIGSEGV_FAULT_ADDRESS addr |
358 |
|
#define SIGSEGV_FAULT_ADDRESS get_fault_address(scp) |
359 |
|
#define SIGSEGV_FAULT_INSTRUCTION scp->sc_ir |
360 |
|
#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS) |
361 |
+ |
#define SIGSEGV_REGISTER_FILE (unsigned int *)&scp->sc_ir, &((unsigned int *) scp->sc_regs)[2] |
362 |
+ |
#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction |
363 |
|
|
364 |
< |
// From Boehm's GC 6.0alpha8 |
196 |
< |
#define EXTRACT_OP1(iw) (((iw) & 0xFC000000) >> 26) |
197 |
< |
#define EXTRACT_OP2(iw) (((iw) & 0x000007FE) >> 1) |
198 |
< |
#define EXTRACT_REGA(iw) (((iw) & 0x001F0000) >> 16) |
199 |
< |
#define EXTRACT_REGB(iw) (((iw) & 0x03E00000) >> 21) |
200 |
< |
#define EXTRACT_REGC(iw) (((iw) & 0x0000F800) >> 11) |
201 |
< |
#define EXTRACT_DISP(iw) ((short *) &(iw))[1] |
202 |
< |
|
364 |
> |
// Use decoding scheme from SheepShaver |
365 |
|
static sigsegv_address_t get_fault_address(struct sigcontext *scp) |
366 |
|
{ |
367 |
< |
unsigned int instr = *((unsigned int *) scp->sc_ir); |
368 |
< |
unsigned int * regs = &((unsigned int *) scp->sc_regs)[2]; |
369 |
< |
int disp = 0, tmp; |
370 |
< |
unsigned int baseA = 0, baseB = 0; |
371 |
< |
unsigned int addr, alignmask = 0xFFFFFFFF; |
372 |
< |
|
211 |
< |
switch(EXTRACT_OP1(instr)) { |
212 |
< |
case 38: /* stb */ |
213 |
< |
case 39: /* stbu */ |
214 |
< |
case 54: /* stfd */ |
215 |
< |
case 55: /* stfdu */ |
216 |
< |
case 52: /* stfs */ |
217 |
< |
case 53: /* stfsu */ |
218 |
< |
case 44: /* sth */ |
219 |
< |
case 45: /* sthu */ |
220 |
< |
case 47: /* stmw */ |
221 |
< |
case 36: /* stw */ |
222 |
< |
case 37: /* stwu */ |
223 |
< |
tmp = EXTRACT_REGA(instr); |
224 |
< |
if(tmp > 0) |
225 |
< |
baseA = regs[tmp]; |
226 |
< |
disp = EXTRACT_DISP(instr); |
227 |
< |
break; |
228 |
< |
case 31: |
229 |
< |
switch(EXTRACT_OP2(instr)) { |
230 |
< |
case 86: /* dcbf */ |
231 |
< |
case 54: /* dcbst */ |
232 |
< |
case 1014: /* dcbz */ |
233 |
< |
case 247: /* stbux */ |
234 |
< |
case 215: /* stbx */ |
235 |
< |
case 759: /* stfdux */ |
236 |
< |
case 727: /* stfdx */ |
237 |
< |
case 983: /* stfiwx */ |
238 |
< |
case 695: /* stfsux */ |
239 |
< |
case 663: /* stfsx */ |
240 |
< |
case 918: /* sthbrx */ |
241 |
< |
case 439: /* sthux */ |
242 |
< |
case 407: /* sthx */ |
243 |
< |
case 661: /* stswx */ |
244 |
< |
case 662: /* stwbrx */ |
245 |
< |
case 150: /* stwcx. */ |
246 |
< |
case 183: /* stwux */ |
247 |
< |
case 151: /* stwx */ |
248 |
< |
case 135: /* stvebx */ |
249 |
< |
case 167: /* stvehx */ |
250 |
< |
case 199: /* stvewx */ |
251 |
< |
case 231: /* stvx */ |
252 |
< |
case 487: /* stvxl */ |
253 |
< |
tmp = EXTRACT_REGA(instr); |
254 |
< |
if(tmp > 0) |
255 |
< |
baseA = regs[tmp]; |
256 |
< |
baseB = regs[EXTRACT_REGC(instr)]; |
257 |
< |
/* determine Altivec alignment mask */ |
258 |
< |
switch(EXTRACT_OP2(instr)) { |
259 |
< |
case 167: /* stvehx */ |
260 |
< |
alignmask = 0xFFFFFFFE; |
261 |
< |
break; |
262 |
< |
case 199: /* stvewx */ |
263 |
< |
alignmask = 0xFFFFFFFC; |
264 |
< |
break; |
265 |
< |
case 231: /* stvx */ |
266 |
< |
alignmask = 0xFFFFFFF0; |
267 |
< |
break; |
268 |
< |
case 487: /* stvxl */ |
269 |
< |
alignmask = 0xFFFFFFF0; |
270 |
< |
break; |
271 |
< |
} |
272 |
< |
break; |
273 |
< |
case 725: /* stswi */ |
274 |
< |
tmp = EXTRACT_REGA(instr); |
275 |
< |
if(tmp > 0) |
276 |
< |
baseA = regs[tmp]; |
277 |
< |
break; |
278 |
< |
default: /* ignore instruction */ |
279 |
< |
return 0; |
280 |
< |
break; |
281 |
< |
} |
282 |
< |
break; |
283 |
< |
default: /* ignore instruction */ |
284 |
< |
return 0; |
285 |
< |
break; |
286 |
< |
} |
287 |
< |
|
288 |
< |
addr = (baseA + baseB) + disp; |
289 |
< |
addr &= alignmask; |
290 |
< |
return (sigsegv_address_t)addr; |
367 |
> |
unsigned int nip = (unsigned int) scp->sc_ir; |
368 |
> |
unsigned int * gpr = &((unsigned int *) scp->sc_regs)[2]; |
369 |
> |
instruction_t instr; |
370 |
> |
|
371 |
> |
powerpc_decode_instruction(&instr, nip, gpr); |
372 |
> |
return (sigsegv_address_t)instr.addr; |
373 |
|
} |
374 |
|
#endif |
375 |
|
#endif |
376 |
|
#endif |
377 |
|
|
378 |
+ |
|
379 |
+ |
/* |
380 |
+ |
* Instruction skipping |
381 |
+ |
*/ |
382 |
+ |
|
383 |
|
#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION |
384 |
|
// Decode and skip X86 instruction |
385 |
|
#if (defined(i386) || defined(__i386__)) |
396 |
|
X86_REG_EDI = 4 |
397 |
|
}; |
398 |
|
#endif |
399 |
+ |
#if defined(__NetBSD__) || defined(__FreeBSD__) |
400 |
+ |
enum { |
401 |
+ |
X86_REG_EIP = 10, |
402 |
+ |
X86_REG_EAX = 7, |
403 |
+ |
X86_REG_ECX = 6, |
404 |
+ |
X86_REG_EDX = 5, |
405 |
+ |
X86_REG_EBX = 4, |
406 |
+ |
X86_REG_ESP = 13, |
407 |
+ |
X86_REG_EBP = 2, |
408 |
+ |
X86_REG_ESI = 1, |
409 |
+ |
X86_REG_EDI = 0 |
410 |
+ |
}; |
411 |
+ |
#endif |
412 |
|
// FIXME: this is partly redundant with the instruction decoding phase |
413 |
|
// to discover transfer type and register number |
414 |
|
static inline int ix86_step_over_modrm(unsigned char * p) |
443 |
|
return offset; |
444 |
|
} |
445 |
|
|
446 |
< |
static bool ix86_skip_instruction(sigsegv_address_t fault_instruction, unsigned long * regs) |
446 |
> |
static bool ix86_skip_instruction(unsigned int * regs) |
447 |
|
{ |
448 |
< |
unsigned char * eip = (unsigned char *)fault_instruction; |
448 |
> |
unsigned char * eip = (unsigned char *)regs[X86_REG_EIP]; |
449 |
|
|
450 |
|
if (eip == 0) |
451 |
|
return false; |
452 |
|
|
453 |
< |
// Transfer type |
454 |
< |
enum { |
355 |
< |
TYPE_UNKNOWN, |
356 |
< |
TYPE_LOAD, |
357 |
< |
TYPE_STORE |
358 |
< |
} transfer_type = TYPE_UNKNOWN; |
359 |
< |
|
360 |
< |
// Transfer size |
361 |
< |
enum { |
362 |
< |
SIZE_BYTE, |
363 |
< |
SIZE_WORD, |
364 |
< |
SIZE_LONG |
365 |
< |
} transfer_size = SIZE_LONG; |
453 |
> |
transfer_type_t transfer_type = TYPE_UNKNOWN; |
454 |
> |
transfer_size_t transfer_size = SIZE_LONG; |
455 |
|
|
456 |
|
int reg = -1; |
457 |
|
int len = 0; |
465 |
|
|
466 |
|
// Decode instruction |
467 |
|
switch (eip[0]) { |
468 |
+ |
case 0x0f: |
469 |
+ |
switch (eip[1]) { |
470 |
+ |
case 0xb6: // MOVZX r32, r/m8 |
471 |
+ |
case 0xb7: // MOVZX r32, r/m16 |
472 |
+ |
switch (eip[2] & 0xc0) { |
473 |
+ |
case 0x80: |
474 |
+ |
reg = (eip[2] >> 3) & 7; |
475 |
+ |
transfer_type = TYPE_LOAD; |
476 |
+ |
break; |
477 |
+ |
case 0x40: |
478 |
+ |
reg = (eip[2] >> 3) & 7; |
479 |
+ |
transfer_type = TYPE_LOAD; |
480 |
+ |
break; |
481 |
+ |
case 0x00: |
482 |
+ |
reg = (eip[2] >> 3) & 7; |
483 |
+ |
transfer_type = TYPE_LOAD; |
484 |
+ |
break; |
485 |
+ |
} |
486 |
+ |
len += 3 + ix86_step_over_modrm(eip + 2); |
487 |
+ |
break; |
488 |
+ |
} |
489 |
+ |
break; |
490 |
|
case 0x8a: // MOV r8, r/m8 |
491 |
|
transfer_size = SIZE_BYTE; |
492 |
|
case 0x8b: // MOV r32, r/m32 (or 16-bit operation) |
574 |
|
return true; |
575 |
|
} |
576 |
|
#endif |
577 |
+ |
|
578 |
+ |
// Decode and skip PPC instruction |
579 |
+ |
#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__)) |
580 |
+ |
static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs) |
581 |
+ |
{ |
582 |
+ |
instruction_t instr; |
583 |
+ |
powerpc_decode_instruction(&instr, *nip_p, regs); |
584 |
+ |
|
585 |
+ |
if (instr.transfer_type == TYPE_UNKNOWN) { |
586 |
+ |
// Unknown machine code, let it crash. Then patch the decoder |
587 |
+ |
return false; |
588 |
+ |
} |
589 |
+ |
|
590 |
+ |
#if DEBUG |
591 |
+ |
printf("%08x: %s %s access", *nip_p, |
592 |
+ |
instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long", |
593 |
+ |
instr.transfer_type == TYPE_LOAD ? "read" : "write"); |
594 |
+ |
|
595 |
+ |
if (instr.addr_mode == MODE_U || instr.addr_mode == MODE_UX) |
596 |
+ |
printf(" r%d (ra = %08x)\n", instr.ra, instr.addr); |
597 |
+ |
if (instr.transfer_type == TYPE_LOAD) |
598 |
+ |
printf(" r%d (rd = 0)\n", instr.rd); |
599 |
+ |
#endif |
600 |
+ |
|
601 |
+ |
if (instr.addr_mode == MODE_U || instr.addr_mode == MODE_UX) |
602 |
+ |
regs[instr.ra] = instr.addr; |
603 |
+ |
if (instr.transfer_type == TYPE_LOAD) |
604 |
+ |
regs[instr.rd] = 0; |
605 |
+ |
|
606 |
+ |
*nip_p += 4; |
607 |
+ |
return true; |
608 |
+ |
} |
609 |
+ |
#endif |
610 |
|
#endif |
611 |
|
|
612 |
|
// Fallbacks |
641 |
|
#if HAVE_SIGSEGV_SKIP_INSTRUCTION |
642 |
|
else if (sigsegv_ignore_fault) { |
643 |
|
// Call the instruction skipper with the register file available |
644 |
< |
if (SIGSEGV_SKIP_INSTRUCTION(fault_instruction, SIGSEGV_REGISTER_FILE)) |
644 |
> |
if (SIGSEGV_SKIP_INSTRUCTION(SIGSEGV_REGISTER_FILE)) |
645 |
|
fault_recovered = true; |
646 |
|
} |
647 |
|
#endif |
809 |
|
if (!sigsegv_install_handler(sigsegv_insn_handler)) |
810 |
|
return 1; |
811 |
|
|
812 |
< |
if (vm_protect((char *)page, page_size, VM_PAGE_WRITE) < 0) |
812 |
> |
if (vm_protect((char *)page, page_size, VM_PAGE_READ | VM_PAGE_WRITE) < 0) |
813 |
|
return 1; |
814 |
|
|
815 |
|
for (int i = 0; i < page_size; i++) |