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root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.80 by gbeauche, 2008-01-14T19:29:29Z vs.
Revision 1.89 by asvitkine, 2009-04-13T23:13:20Z

#	Line 52 | Line 52 | using std::list;
52		// Size of an unsigned integer large enough to hold all bits of a pointer
53		// NOTE: this can be different than SIGSEGV_REGISTER_TYPE. In
54		// particular, on ILP32 systems with a 64-bit kernel (HP-UX/ia64?)
55	<	#ifdef HAVE_WIN32_VM
55	>	#if defined(HAVE_WIN32_VM)
56		// Windows is either ILP32 or LLP64
57	+	#include <BaseTsd.h>
58		typedef UINT_PTR sigsegv_uintptr_t;
59		#else
60		// Other systems are sane enough to follow ILP32 or LP64 models
#	Line 243 | Line 244 | static void powerpc_decode_instruction(i
244		// Generic extended signal handler
245		#if defined(__FreeBSD__)
246		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
247	+	#elif defined(__hpux)
248	+	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV) FAULT_HANDLER(SIGBUS)
249		#else
250		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
251		#endif
#	Line 349 | Line 352 | static void powerpc_decode_instruction(i
352		#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
353		#endif
354		#endif
355	+	#if (defined(__hpux) || defined(__hpux__))
356	+	#if (defined(__hppa) || defined(__hppa__))
357	+	#define SIGSEGV_CONTEXT_REGS                    (&((ucontext_t *)scp)->uc_mcontext)
358	+	#define SIGSEGV_FAULT_INSTRUCTION_32    (SIGSEGV_CONTEXT_REGS->ss_narrow.ss_pcoq_head & ~3ul)
359	+	#define SIGSEGV_FAULT_INSTRUCTION_64    (SIGSEGV_CONTEXT_REGS->ss_wide.ss_64.ss_pcoq_head & ~3ull)
360	+	#if defined(__LP64__)
361	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_FAULT_INSTRUCTION_64
362	+	#else
363	+	#define SIGSEGV_FAULT_INSTRUCTION               ((SIGSEGV_CONTEXT_REGS->ss_flags & SS_WIDEREGS) ? \
364	+	(uint32_t)SIGSEGV_FAULT_INSTRUCTION_64 : \
365	+	SIGSEGV_FAULT_INSTRUCTION_32)
366	+	#endif
367	+	#endif
368	+	#if (defined(__ia64) || defined(__ia64__))
369	+	#include <sys/ucontext.h>
370	+	#define SIGSEGV_CONTEXT_REGS                    ((ucontext_t *)scp)
371	+	#define SIGSEGV_FAULT_INSTRUCTION               get_fault_instruction(SIGSEGV_CONTEXT_REGS)
372	+	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
373	+	#define SIGSEGV_SKIP_INSTRUCTION                ia64_skip_instruction
374	+
375	+	#include <sys/uc_access.h>
376	+	static inline sigsegv_address_t get_fault_instruction(const ucontext_t *ucp)
377	+	{
378	+	uint64_t ip;
379	+	if (__uc_get_ip(ucp, &ip) != 0)
380	+	return SIGSEGV_INVALID_ADDRESS;
381	+	return (sigsegv_address_t)(ip & ~3ULL);
382	+	}
383	+	#endif
384	+	#endif
385		#endif
386
387		#if HAVE_SIGCONTEXT_SUBTERFUGE
#	Line 518 | Line 551 | static sigsegv_address_t get_fault_addre
551		#ifndef HAVE_MACH_EXCEPTIONS
552		#if defined(__APPLE__) && defined(__MACH__)
553		#if (defined(ppc) || defined(__ppc__))
554	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
554	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct __darwin_sigcontext *scp
555		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
556		#define SIGSEGV_FAULT_ADDRESS                   get_fault_address(scp)
557	<	#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_ir
557	>	#define SIGSEGV_FAULT_INSTRUCTION               scp->MACH_FIELD_NAME(sc_ir)
558		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
559		#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&scp->sc_ir, &((unsigned int *) scp->sc_regs)[2]
560		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
#	Line 529 | Line 562 | static sigsegv_address_t get_fault_addre
562		// Use decoding scheme from SheepShaver
563		static sigsegv_address_t get_fault_address(struct sigcontext *scp)
564		{
565	<	unsigned int   nip = (unsigned int) scp->sc_ir;
566	<	unsigned int * gpr = &((unsigned int *) scp->sc_regs)[2];
565	>	unsigned int   nip = (unsigned int) scp->MACH_FIELD_NAME(sc_ir);
566	>	unsigned int * gpr = &((unsigned int *) scp->MACH_FIELD_NAME(sc_regs))[2];
567		instruction_t  instr;
568
569	<	powerpc_decode_instruction(&instr, nip, gpr);
569	>	powerpc_decode_instruction(&instr, nip, (long unsigned int*)gpr);
570		return (sigsegv_address_t)instr.addr;
571		}
572		#endif
#	Line 546 | Line 579 | static sigsegv_address_t get_fault_addre
579		#include <windows.h>
580		#include <winerror.h>
581
549	–	#if defined(_M_IX86)
582		#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
583		#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
584		#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
585		#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
586	+	#if defined(_M_IX86)
587		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Eip
588		#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi)
589		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
590		#endif
591		#if defined(_M_X64)
559	–	#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
560	–	#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
561	–	#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
562	–	#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
592		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Rip
593		#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax)
594		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
595		#endif
596	+	#if defined(_M_IA64)
597	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->StIIP
598	+	#endif
599		#endif
600
601		#if HAVE_MACH_EXCEPTIONS
#	Line 586 | Line 618 | extern "C" {
618		#include <mach/mach.h>
619		#include <mach/mach_error.h>
620
621	<	extern boolean_t exc_server(mach_msg_header_t *, mach_msg_header_t *);
622	<	extern kern_return_t catch_exception_raise(mach_port_t, mach_port_t,
623	<	mach_port_t, exception_type_t, exception_data_t, mach_msg_type_number_t);
624	<	extern kern_return_t exception_raise(mach_port_t, mach_port_t, mach_port_t,
625	<	exception_type_t, exception_data_t, mach_msg_type_number_t);
626	<	extern kern_return_t exception_raise_state(mach_port_t, exception_type_t,
627	<	exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
621	>	#ifndef HAVE_MACH64_VM
622	>
623	>	// Undefine this to prevent a preprocessor warning when compiling on a
624	>	// 32-bit machine with Mac OS X 10.5.
625	>	#undef  MACH_EXCEPTION_CODES
626	>
627	>	#define MACH_EXCEPTION_CODES                                    0
628	>	#define mach_exception_data_t                                   exception_data_t
629	>	#define mach_exception_data_type_t                              exception_data_type_t
630	>	#define mach_exc_server                                                 exc_server
631	>	#define catch_mach_exception_raise                              catch_exception_raise
632	>	#define mach_exception_raise                                    exception_raise
633	>	#define mach_exception_raise_state                              exception_raise_state
634	>	#define mach_exception_raise_state_identity             exception_raise_state_identity
635	>	#endif
636	>
637	>	extern boolean_t mach_exc_server(mach_msg_header_t *, mach_msg_header_t *);
638	>	extern kern_return_t catch_mach_exception_raise(mach_port_t, mach_port_t,
639	>	mach_port_t, exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
640	>	extern kern_return_t catch_mach_exception_raise_state(mach_port_t exception_port,
641	>	exception_type_t exception, mach_exception_data_t code, mach_msg_type_number_t code_count,
642	>	int *flavor,
643	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
644	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
645	>	extern kern_return_t catch_mach_exception_raise_state_identity(mach_port_t exception_port,
646	>	mach_port_t thread_port, mach_port_t task_port, exception_type_t exception,
647	>	mach_exception_data_t code, mach_msg_type_number_t code_count,
648	>	int *flavor,
649	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
650	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
651	>	extern kern_return_t mach_exception_raise(mach_port_t, mach_port_t, mach_port_t,
652	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
653	>	extern kern_return_t mach_exception_raise_state(mach_port_t, exception_type_t,
654	>	mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
655		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
656	<	extern kern_return_t exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
657	<	exception_type_t, exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
656	>	extern kern_return_t mach_exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
657	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
658		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
659		}
660
#	Line 626 | Line 685 | if (ret != KERN_SUCCESS) { \
685		exit (1); \
686		}
687
629	–	#ifdef __ppc__
630	–	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE
631	–	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
632	–	#endif
633	–	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state_t
634	–	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE
635	–	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE_COUNT
636	–	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
637	–	#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state_t
638	–	#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE
639	–	#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE_COUNT
640	–	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
641	–	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
642	–	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
643	–	#endif
644	–	#ifdef __ppc64__
645	–	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64
646	–	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
647	–	#endif
648	–	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state64_t
649	–	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE64
650	–	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE64_COUNT
651	–	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
652	–	#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state64_t
653	–	#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE64
654	–	#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE64_COUNT
655	–	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
656	–	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
657	–	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
658	–	#endif
659	–	#ifdef __i386__
660	–	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32
661	–	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
662	–	#endif
663	–	#define SIGSEGV_EXCEPTION_STATE_TYPE    i386_exception_state_t
664	–	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  i386_EXCEPTION_STATE
665	–	#define SIGSEGV_EXCEPTION_STATE_COUNT   i386_EXCEPTION_STATE_COUNT
666	–	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
667	–	#define SIGSEGV_THREAD_STATE_TYPE               i386_thread_state_t
668	–	#define SIGSEGV_THREAD_STATE_FLAVOR             i386_THREAD_STATE
669	–	#define SIGSEGV_THREAD_STATE_COUNT              i386_THREAD_STATE_COUNT
670	–	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(eip)
671	–	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
672	–	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(eax)) /* EAX is the first GPR we consider */
673	–	#endif
674	–	#ifdef __x86_64__
675	–	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64
676	–	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
677	–	#endif
678	–	#define SIGSEGV_EXCEPTION_STATE_TYPE    x86_exception_state64_t
679	–	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  x86_EXCEPTION_STATE64
680	–	#define SIGSEGV_EXCEPTION_STATE_COUNT   x86_EXCEPTION_STATE64_COUNT
681	–	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
682	–	#define SIGSEGV_THREAD_STATE_TYPE               x86_thread_state64_t
683	–	#define SIGSEGV_THREAD_STATE_FLAVOR             x86_THREAD_STATE64
684	–	#define SIGSEGV_THREAD_STATE_COUNT              x86_THREAD_STATE64_COUNT
685	–	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(rip)
686	–	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
687	–	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(rax)) /* RAX is the first GPR we consider */
688	–	#endif
689	–	#define SIGSEGV_FAULT_ADDRESS_FAST              code[1]
690	–	#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_INVALID_ADDRESS
691	–	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code
692	–	#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code
693	–
688		#ifndef MACH_FIELD_NAME
689		#define MACH_FIELD_NAME(X) X
690		#endif
#	Line 724 | Line 718 | handleExceptions(void *priv)
718		_exceptionPort, 0, MACH_PORT_NULL);
719		MACH_CHECK_ERROR(mach_msg, krc);
720
721	<	if (!exc_server(msg, reply)) {
721	>	if (!mach_exc_server(msg, reply)) {
722		fprintf(stderr, "exc_server hated the message\n");
723		exit(1);
724		}
#	Line 1225 | Line 1219 | static bool ix86_skip_instruction(SIGSEG
1219		#endif
1220
1221		// Decode and skip IA-64 instruction
1222	<	#if defined(__ia64__)
1222	>	#if defined(__ia64) || defined(__ia64__)
1223	>	typedef uint64_t ia64_bundle_t[2];
1224		#if defined(__linux__)
1225		// We can directly patch the slot number
1226	<	#define IA64_CAN_PATCH_IP_SLOT 1
1226	>	#define IA64_CAN_PATCH_IP_SLOT  1
1227		// Helper macros to access the machine context
1228		#define IA64_CONTEXT_TYPE               struct sigcontext *
1229		#define IA64_CONTEXT                    scp
#	Line 1236 | Line 1231 | static bool ix86_skip_instruction(SIGSEG
1231		#define IA64_SET_IP(V)                  (IA64_CONTEXT->sc_ip = (V))
1232		#define IA64_GET_PR(P)                  ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1233		#define IA64_GET_NAT(I)                 ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1239	–	#define IA64_SET_NAT(I,V)               (IA64_CONTEXT->sc_nat= (IA64_CONTEXT->sc_nat & ~(1ul << (I))) | (((unsigned long)!!(V)) << (I)))
1234		#define IA64_GET_GR(R)                  (IA64_CONTEXT->sc_gr[(R)])
1235	<	#define IA64_SET_GR(R,V)                (IA64_CONTEXT->sc_gr[(R)] = (V))
1235	>	#define _IA64_SET_GR(R,V)               (IA64_CONTEXT->sc_gr[(R)] = (V))
1236	>	#define _IA64_SET_NAT(I,V)              (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) | (((uint64_t)!!(V)) << (I)))
1237	>	#define IA64_SET_GR(R,V,N)              (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N))
1238	>
1239	>	// Load bundle (in little-endian)
1240	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1241	>	{
1242	>	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1243	>	bundle[0] = ip[0];
1244	>	bundle[1] = ip[1];
1245	>	}
1246	>	#endif
1247	>	#if defined(__hpux) || defined(__hpux__)
1248	>	// We can directly patch the slot number
1249	>	#define IA64_CAN_PATCH_IP_SLOT  1
1250	>	// Helper macros to access the machine context
1251	>	#define IA64_CONTEXT_TYPE               ucontext_t *
1252	>	#define IA64_CONTEXT                    ucp
1253	>	#define IA64_GET_IP()                   ia64_get_ip(IA64_CONTEXT)
1254	>	#define IA64_SET_IP(V)                  ia64_set_ip(IA64_CONTEXT, V)
1255	>	#define IA64_GET_PR(P)                  ia64_get_pr(IA64_CONTEXT, P)
1256	>	#define IA64_GET_NAT(I)                 ia64_get_nat(IA64_CONTEXT, I)
1257	>	#define IA64_GET_GR(R)                  ia64_get_gr(IA64_CONTEXT, R)
1258	>	#define IA64_SET_GR(R,V,N)              ia64_set_gr(IA64_CONTEXT, R, V, N)
1259	>	#define UC_ACCESS(FUNC,ARGS)    do { if (__uc_##FUNC ARGS != 0) abort(); } while (0)
1260	>
1261	>	static inline uint64_t ia64_get_ip(IA64_CONTEXT_TYPE IA64_CONTEXT)
1262	>	{ uint64_t v; UC_ACCESS(get_ip,(IA64_CONTEXT, &v)); return v; }
1263	>	static inline void ia64_set_ip(IA64_CONTEXT_TYPE IA64_CONTEXT, uint64_t v)
1264	>	{ UC_ACCESS(set_ip,(IA64_CONTEXT, v)); }
1265	>	static inline unsigned int ia64_get_pr(IA64_CONTEXT_TYPE IA64_CONTEXT, int pr)
1266	>	{ uint64_t v; UC_ACCESS(get_prs,(IA64_CONTEXT, &v)); return (v >> pr) & 1; }
1267	>	static inline unsigned int ia64_get_nat(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1268	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return (nat >> r) & 1; }
1269	>	static inline uint64_t ia64_get_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1270	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return v; }
1271	>
1272	>	static void ia64_set_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r, uint64_t v, unsigned int nat)
1273	>	{
1274	>	if (r == 0)
1275	>	return;
1276	>	if (r > 0 && r < 32)
1277	>	UC_ACCESS(set_grs,(IA64_CONTEXT, r, 1, &v, (!!nat) << r));
1278	>	else {
1279	>	uint64_t bsp, bspstore;
1280	>	UC_ACCESS(get_ar_bsp,(IA64_CONTEXT, &bsp));
1281	>	UC_ACCESS(get_ar_bspstore,(IA64_CONTEXT, &bspstore));
1282	>	abort(); /* XXX: use libunwind, this is not fun... */
1283	>	}
1284	>	}
1285	>
1286	>	// Byte-swapping
1287	>	#if defined(__GNUC__)
1288	>	#define BSWAP64(V) ({ uint64_t r; __asm__ __volatile__("mux1 %0=%1,@rev;;" : "=r" (r) : "r" (V)); r; })
1289	>	#elif defined (__HP_aCC)
1290	>	#define BSWAP64(V) _Asm_mux1(_MBTYPE_REV, V)
1291	>	#else
1292	>	#error "Define byte-swap instruction"
1293	>	#endif
1294	>
1295	>	// Load bundle (in little-endian)
1296	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1297	>	{
1298	>	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1299	>	bundle[0] = BSWAP64(ip[0]);
1300	>	bundle[1] = BSWAP64(ip[1]);
1301	>	}
1302		#endif
1303
1304		// Instruction operations
#	Line 1280 | Line 1340 | const int IA64_N_OPERANDS = 4;
1340
1341		// Decoded operand type
1342		struct ia64_operand_t {
1343	<	unsigned char commit;           // commit result of operation to register file?
1344	<	unsigned char valid;            // XXX: not really used, can be removed (debug)
1345	<	signed char index;                      // index of GPR, or -1 if immediate value
1346	<	unsigned char nat;                      // NaT state before operation
1347	<	unsigned long value;            // register contents or immediate value
1343	>	uint8_t commit;                         // commit result of operation to register file?
1344	>	uint8_t valid;                          // XXX: not really used, can be removed (debug)
1345	>	int8_t index;                           // index of GPR, or -1 if immediate value
1346	>	uint8_t nat;                            // NaT state before operation
1347	>	uint64_t value;                         // register contents or immediate value
1348		};
1349
1350		// Decoded instruction type
1351		struct ia64_instruction_t {
1352	<	unsigned char mnemo;            // operation to perform
1353	<	unsigned char pred;                     // predicate register to check
1354	<	unsigned char no_memory;        // used to emulated main fault instruction
1355	<	unsigned long inst;                     // the raw instruction bits (41-bit wide)
1352	>	uint8_t mnemo;                          // operation to perform
1353	>	uint8_t pred;                           // predicate register to check
1354	>	uint8_t no_memory;                      // used to emulated main fault instruction
1355	>	uint64_t inst;                          // the raw instruction bits (41-bit wide)
1356		ia64_operand_t operands[IA64_N_OPERANDS];
1357		};
1358
1359		// Get immediate sign-bit
1360	<	static inline int ia64_inst_get_sbit(unsigned long inst)
1360	>	static inline int ia64_inst_get_sbit(uint64_t inst)
1361		{
1362		return (inst >> 36) & 1;
1363		}
1364
1365		// Get 8-bit immediate value (A3, A8, I27, M30)
1366	<	static inline unsigned long ia64_inst_get_imm8(unsigned long inst)
1366	>	static inline uint64_t ia64_inst_get_imm8(uint64_t inst)
1367		{
1368	<	unsigned long value = (inst >> 13) & 0x7ful;
1368	>	uint64_t value = (inst >> 13) & 0x7full;
1369		if (ia64_inst_get_sbit(inst))
1370	<	value |= ~0x7ful;
1370	>	value |= ~0x7full;
1371		return value;
1372		}
1373
1374		// Get 9-bit immediate value (M3)
1375	<	static inline unsigned long ia64_inst_get_imm9b(unsigned long inst)
1375	>	static inline uint64_t ia64_inst_get_imm9b(uint64_t inst)
1376		{
1377	<	unsigned long value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f);
1377	>	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f);
1378		if (ia64_inst_get_sbit(inst))
1379	<	value |= ~0xfful;
1379	>	value |= ~0xffull;
1380		return value;
1381		}
1382
1383		// Get 9-bit immediate value (M5)
1384	<	static inline unsigned long ia64_inst_get_imm9a(unsigned long inst)
1384	>	static inline uint64_t ia64_inst_get_imm9a(uint64_t inst)
1385		{
1386	<	unsigned long value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f);
1386	>	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f);
1387		if (ia64_inst_get_sbit(inst))
1388	<	value |= ~0xfful;
1388	>	value |= ~0xffull;
1389		return value;
1390		}
1391
1392		// Get 14-bit immediate value (A4)
1393	<	static inline unsigned long ia64_inst_get_imm14(unsigned long inst)
1393	>	static inline uint64_t ia64_inst_get_imm14(uint64_t inst)
1394		{
1395	<	unsigned long value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f);
1395	>	uint64_t value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f);
1396		if (ia64_inst_get_sbit(inst))
1397	<	value |= ~0x1fful;
1397	>	value |= ~0x1ffull;
1398		return value;
1399		}
1400
1401		// Get 22-bit immediate value (A5)
1402	<	static inline unsigned long ia64_inst_get_imm22(unsigned long inst)
1402	>	static inline uint64_t ia64_inst_get_imm22(uint64_t inst)
1403		{
1404	<	unsigned long value = ((((inst >> 22) & 0x1f) << 16) |
1405	<	(((inst >> 27) & 0x1ff) << 7) |
1406	<	(inst & 0x7f));
1404	>	uint64_t value = ((((inst >> 22) & 0x1f) << 16) |
1405	>	(((inst >> 27) & 0x1ff) << 7) |
1406	>	(inst & 0x7f));
1407		if (ia64_inst_get_sbit(inst))
1408	<	value |= ~0x1ffffful;
1408	>	value |= ~0x1fffffull;
1409		return value;
1410		}
1411
1412		// Get 21-bit immediate value (I19)
1413	<	static inline unsigned long ia64_inst_get_imm21(unsigned long inst)
1413	>	static inline uint64_t ia64_inst_get_imm21(uint64_t inst)
1414		{
1415		return (((inst >> 36) & 1) << 20) | ((inst >> 6) & 0xfffff);
1416		}
1417
1418		// Get 2-bit count value (A2)
1419	<	static inline int ia64_inst_get_count2(unsigned long inst)
1419	>	static inline int ia64_inst_get_count2(uint64_t inst)
1420		{
1421		return (inst >> 27) & 0x3;
1422		}
1423
1424		// Get bundle template
1425	<	static inline unsigned int ia64_get_template(unsigned long raw_ip)
1425	>	static inline unsigned int ia64_get_template(uint64_t ip)
1426		{
1427	<	unsigned long *ip = (unsigned long *)(raw_ip & ~3ul);
1428	<	return ip[0] & 0x1f;
1427	>	ia64_bundle_t bundle;
1428	>	ia64_load_bundle(bundle, ip);
1429	>	return bundle[0] & 0x1f;
1430		}
1431
1432		// Get specified instruction in bundle
1433	<	static unsigned long ia64_get_instruction(unsigned long raw_ip, int slot)
1433	>	static uint64_t ia64_get_instruction(uint64_t ip, int slot)
1434		{
1435	<	unsigned long inst;
1436	<	unsigned long *ip = (unsigned long *)(raw_ip & ~3ul);
1435	>	uint64_t inst;
1436	>	ia64_bundle_t bundle;
1437	>	ia64_load_bundle(bundle, ip);
1438		#if DEBUG
1439	<	printf("Bundle: %016lx%016lx\n", ip[1], ip[0]);
1439	>	printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]);
1440		#endif
1441
1442		switch (slot) {
1443		case 0:
1444	<	inst = (ip[0] >> 5) & 0x1fffffffffful;
1444	>	inst = (bundle[0] >> 5) & 0x1ffffffffffull;
1445		break;
1446		case 1:
1447	<	inst = ((ip[1] & 0x7ffffful) << 18) | ((ip[0] >> 46) & 0x3fffful);
1447	>	inst = ((bundle[1] & 0x7fffffull) << 18) | ((bundle[0] >> 46) & 0x3ffffull);
1448		break;
1449		case 2:
1450	<	inst = (ip[1] >> 23) & 0x1fffffffffful;
1450	>	inst = (bundle[1] >> 23) & 0x1ffffffffffull;
1451		break;
1452		case 3:
1453		fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
#	Line 1394 | Line 1456 | static unsigned long ia64_get_instructio
1456		}
1457
1458		#if DEBUG
1459	<	printf(" Instruction %d: 0x%016lx\n", slot, inst);
1459	>	printf(" Instruction %d: 0x%016llx\n", slot, inst);
1460		#endif
1461		return inst;
1462		}
#	Line 1678 | Line 1740 | static bool ia64_emulate_instruction(ia6
1740		if (inst->pred && !IA64_GET_PR(inst->pred))
1741		return true;
1742
1743	<	unsigned char nat, nat2;
1744	<	unsigned long dst, dst2, src1, src2, src3;
1743	>	uint8_t nat, nat2;
1744	>	uint64_t dst, dst2, src1, src2, src3;
1745
1746		switch (inst->mnemo) {
1747		case IA64_INST_NOP:
#	Line 1716 | Line 1778 | static bool ia64_emulate_instruction(ia6
1778		case IA64_INST_ZXT4:
1779		src1 = inst->operands[1].value;
1780		switch (inst->mnemo) {
1781	<	case IA64_INST_SXT1: dst = (signed long)(signed char)src1;              break;
1782	<	case IA64_INST_SXT2: dst = (signed long)(signed short)src1;             break;
1783	<	case IA64_INST_SXT4: dst = (signed long)(signed int)src1;               break;
1784	<	case IA64_INST_ZXT1: dst = (unsigned char)src1;                                 break;
1785	<	case IA64_INST_ZXT2: dst = (unsigned short)src1;                                break;
1786	<	case IA64_INST_ZXT4: dst = (unsigned int)src1;                                  break;
1781	>	case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1;               break;
1782	>	case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1;              break;
1783	>	case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1;              break;
1784	>	case IA64_INST_ZXT1: dst = (uint8_t)src1;                               break;
1785	>	case IA64_INST_ZXT2: dst = (uint16_t)src1;                              break;
1786	>	case IA64_INST_ZXT4: dst = (uint32_t)src1;                              break;
1787		}
1788		inst->operands[0].commit = true;
1789		inst->operands[0].value  = dst;
#	Line 1744 | Line 1806 | static bool ia64_emulate_instruction(ia6
1806		dst = 0;
1807		else {
1808		switch (inst->mnemo) {
1809	<	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((unsigned char *)src1);  break;
1810	<	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((unsigned short *)src1); break;
1811	<	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((unsigned int *)src1);   break;
1812	<	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((unsigned long *)src1);  break;
1809	>	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((uint8_t *)src1);        break;
1810	>	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((uint16_t *)src1);       break;
1811	>	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((uint32_t *)src1);       break;
1812	>	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((uint64_t *)src1);       break;
1813		}
1814		}
1815		inst->operands[0].commit = true;
#	Line 1772 | Line 1834 | static bool ia64_emulate_instruction(ia6
1834		src1 = inst->operands[1].value;
1835		if (!inst->no_memory) {
1836		switch (inst->mnemo) {
1837	<	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((unsigned char *)dst) = src1;  break;
1838	<	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((unsigned short *)dst) = src1; break;
1839	<	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((unsigned int *)dst) = src1;   break;
1840	<	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((unsigned long *)dst) = src1;  break;
1837	>	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((uint8_t *)dst) = src1;        break;
1838	>	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((uint16_t *)dst) = src1;       break;
1839	>	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((uint32_t *)dst) = src1;       break;
1840	>	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((uint64_t *)dst) = src1;       break;
1841		}
1842		}
1843		inst->operands[0].value  = dst2;
#	Line 1791 | Line 1853 | static bool ia64_emulate_instruction(ia6
1853		continue;
1854		if (op.index == -1)
1855		return false; // XXX: internal error
1856	<	IA64_SET_GR(op.index, op.value);
1795	<	IA64_SET_NAT(op.index, op.nat);
1856	>	IA64_SET_GR(op.index, op.value, op.nat);
1857		}
1858		return true;
1859		}
1860
1861	<	static bool ia64_emulate_instruction(unsigned long raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1861	>	static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1862		{
1863		ia64_instruction_t inst;
1864		memset(&inst, 0, sizeof(inst));
#	Line 1809 | Line 1870 | static bool ia64_emulate_instruction(uns
1870
1871		static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1872		{
1873	<	unsigned long ip = IA64_GET_IP();
1873	>	uint64_t ip = IA64_GET_IP();
1874		#if DEBUG
1875	<	printf("IP: 0x%016lx\n", ip);
1875	>	printf("IP: 0x%016llx\n", ip);
1876		#if 0
1877		printf(" Template 0x%02x\n", ia64_get_template(ip));
1878		ia64_get_instruction(ip, 0);
#	Line 1929 | Line 1990 | static bool ia64_skip_instruction(IA64_C
1990
1991		#if IA64_CAN_PATCH_IP_SLOT
1992		if ((slot = ip & 3) < 2)
1993	<	IA64_SET_IP((ip & ~3ul) + (slot + 1));
1993	>	IA64_SET_IP((ip & ~3ull) + (slot + 1));
1994		else
1995		#endif
1996	<	IA64_SET_IP((ip & ~3ul) + 16);
1996	>	IA64_SET_IP((ip & ~3ull) + 16);
1997		#if DEBUG
1998	<	printf("IP: 0x%016lx\n", IA64_GET_IP());
1998	>	printf("IP: 0x%016llx\n", IA64_GET_IP());
1999		#endif
2000		return true;
2001		}
#	Line 2442 | Line 2503 | static bool arm_skip_instruction(unsigne
2503		*  SIGSEGV global handler
2504		*/
2505
2445	–	struct sigsegv_info_t {
2446	–	sigsegv_address_t addr;
2447	–	sigsegv_address_t pc;
2448	–	#ifdef HAVE_MACH_EXCEPTIONS
2449	–	mach_port_t thread;
2450	–	bool has_exc_state;
2451	–	SIGSEGV_EXCEPTION_STATE_TYPE exc_state;
2452	–	mach_msg_type_number_t exc_state_count;
2453	–	bool has_thr_state;
2454	–	SIGSEGV_THREAD_STATE_TYPE thr_state;
2455	–	mach_msg_type_number_t thr_state_count;
2456	–	#endif
2457	–	};
2458	–
2506		#ifdef HAVE_MACH_EXCEPTIONS
2507		static void mach_get_exception_state(sigsegv_info_t *SIP)
2508		{
#	Line 2493 | Line 2540 | static void mach_set_thread_state(sigseg
2540		sigsegv_address_t sigsegv_get_fault_address(sigsegv_info_t *SIP)
2541		{
2542		#ifdef HAVE_MACH_EXCEPTIONS
2543	+	#ifdef EMULATED_PPC
2544		static int use_fast_path = -1;
2545		if (use_fast_path != 1 && !SIP->has_exc_state) {
2546		mach_get_exception_state(SIP);
#	Line 2512 | Line 2560 | sigsegv_address_t sigsegv_get_fault_addr
2560		SIP->addr = addr;
2561		}
2562		#endif
2563	+	#endif
2564		return SIP->addr;
2565		}
2566
#	Line 2520 | Line 2569 | sigsegv_address_t sigsegv_get_fault_addr
2569		sigsegv_address_t sigsegv_get_fault_instruction_address(sigsegv_info_t *SIP)
2570		{
2571		#ifdef HAVE_MACH_EXCEPTIONS
2572	+	#ifdef EMULATED_PPC
2573		if (!SIP->has_thr_state) {
2574		mach_get_thread_state(SIP);
2575
2576		SIP->pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
2577		}
2578		#endif
2579	+	#endif
2580		return SIP->pc;
2581		}
2582
#	Line 2604 | Line 2655 | static inline kern_return_t
2655		forward_exception(mach_port_t thread_port,
2656		mach_port_t task_port,
2657		exception_type_t exception_type,
2658	<	exception_data_t exception_data,
2658	>	mach_exception_data_t exception_data,
2659		mach_msg_type_number_t data_count,
2660		ExceptionPorts *oldExceptionPorts)
2661		{
#	Line 2651 | Line 2702 | forward_exception(mach_port_t thread_por
2702		switch (behavior) {
2703		case EXCEPTION_DEFAULT:
2704		// fprintf(stderr, "forwarding to exception_raise\n");
2705	<	kret = exception_raise(port, thread_port, task_port, exception_type,
2706	<	exception_data, data_count);
2707	<	MACH_CHECK_ERROR (exception_raise, kret);
2705	>	kret = mach_exception_raise(port, thread_port, task_port, exception_type,
2706	>	exception_data, data_count);
2707	>	MACH_CHECK_ERROR (mach_exception_raise, kret);
2708		break;
2709		case EXCEPTION_STATE:
2710		// fprintf(stderr, "forwarding to exception_raise_state\n");
2711	<	kret = exception_raise_state(port, exception_type, exception_data,
2712	<	data_count, &flavor,
2713	<	(natural_t *)&thread_state, thread_state_count,
2714	<	(natural_t *)&thread_state, &thread_state_count);
2715	<	MACH_CHECK_ERROR (exception_raise_state, kret);
2711	>	kret = mach_exception_raise_state(port, exception_type, exception_data,
2712	>	data_count, &flavor,
2713	>	(natural_t *)&thread_state, thread_state_count,
2714	>	(natural_t *)&thread_state, &thread_state_count);
2715	>	MACH_CHECK_ERROR (mach_exception_raise_state, kret);
2716		break;
2717		case EXCEPTION_STATE_IDENTITY:
2718		// fprintf(stderr, "forwarding to exception_raise_state_identity\n");
2719	<	kret = exception_raise_state_identity(port, thread_port, task_port,
2720	<	exception_type, exception_data,
2721	<	data_count, &flavor,
2722	<	(natural_t *)&thread_state, thread_state_count,
2723	<	(natural_t *)&thread_state, &thread_state_count);
2724	<	MACH_CHECK_ERROR (exception_raise_state_identity, kret);
2719	>	kret = mach_exception_raise_state_identity(port, thread_port, task_port,
2720	>	exception_type, exception_data,
2721	>	data_count, &flavor,
2722	>	(natural_t *)&thread_state, thread_state_count,
2723	>	(natural_t *)&thread_state, &thread_state_count);
2724	>	MACH_CHECK_ERROR (mach_exception_raise_state_identity, kret);
2725		break;
2726		default:
2727		fprintf(stderr, "forward_exception got unknown behavior\n");
#	Line 2707 | Line 2758 | forward_exception(mach_port_t thread_por
2758		* linkage because that is what exc_server expects.
2759		*/
2760		kern_return_t
2761	<	catch_exception_raise(mach_port_t exception_port,
2762	<	mach_port_t thread,
2763	<	mach_port_t task,
2764	<	exception_type_t exception,
2765	<	exception_data_t code,
2766	<	mach_msg_type_number_t code_count)
2761	>	catch_mach_exception_raise(mach_port_t exception_port,
2762	>	mach_port_t thread,
2763	>	mach_port_t task,
2764	>	exception_type_t exception,
2765	>	mach_exception_data_t code,
2766	>	mach_msg_type_number_t code_count)
2767		{
2768		kern_return_t krc;
2769
#	Line 2733 | Line 2784 | catch_exception_raise(mach_port_t except
2784
2785		return krc;
2786		}
2787	+
2788	+	/* XXX: borrowed from launchd and gdb */
2789	+	kern_return_t
2790	+	catch_mach_exception_raise_state(mach_port_t exception_port,
2791	+	exception_type_t exception,
2792	+	mach_exception_data_t code,
2793	+	mach_msg_type_number_t code_count,
2794	+	int *flavor,
2795	+	thread_state_t old_state,
2796	+	mach_msg_type_number_t old_state_count,
2797	+	thread_state_t new_state,
2798	+	mach_msg_type_number_t *new_state_count)
2799	+	{
2800	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2801	+	*new_state_count = old_state_count;
2802	+	return KERN_SUCCESS;
2803	+	}
2804	+
2805	+	/* XXX: borrowed from launchd and gdb */
2806	+	kern_return_t
2807	+	catch_mach_exception_raise_state_identity(mach_port_t exception_port,
2808	+	mach_port_t thread_port,
2809	+	mach_port_t task_port,
2810	+	exception_type_t exception,
2811	+	mach_exception_data_t code,
2812	+	mach_msg_type_number_t code_count,
2813	+	int *flavor,
2814	+	thread_state_t old_state,
2815	+	mach_msg_type_number_t old_state_count,
2816	+	thread_state_t new_state,
2817	+	mach_msg_type_number_t *new_state_count)
2818	+	{
2819	+	kern_return_t kret;
2820	+
2821	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2822	+	*new_state_count = old_state_count;
2823	+
2824	+	kret = mach_port_deallocate(mach_task_self(), task_port);
2825	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2826	+	kret = mach_port_deallocate(mach_task_self(), thread_port);
2827	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2828	+
2829	+	return KERN_SUCCESS;
2830	+	}
2831		#endif
2832
2833		#ifdef HAVE_SIGSEGV_RECOVERY
#	Line 2857 | Line 2952 | static bool sigsegv_do_install_handler(s
2952		// addressing modes) used in PPC instructions, you will need the
2953		// GPR state anyway.
2954		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
2955	<	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
2955	>	EXCEPTION_DEFAULT | MACH_EXCEPTION_CODES, SIGSEGV_THREAD_STATE_FLAVOR);
2956		if (krc != KERN_SUCCESS) {
2957		mach_error("thread_set_exception_ports", krc);
2958		return false;
#	Line 2885 | Line 2980 | static LONG WINAPI main_exception_filter
2980		{
2981		if (sigsegv_fault_handler != NULL
2982		&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
2983	<	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
2983	>	&& ExceptionInfo->ExceptionRecord->NumberParameters >= 2
2984		&& handle_badaccess(ExceptionInfo))
2985		return EXCEPTION_CONTINUE_EXECUTION;
2986

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