[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.76 by gbeauche, 2008-01-06T16:36:00Z vs.
Revision 1.80 by gbeauche, 2008-01-14T19:29:29Z

#	Line 49 \| Line 49 \| using std::list;
49		#define RETSIGTYPE void
50		#endif
51
52	+	// Size of an unsigned integer large enough to hold all bits of a pointer
53	+	// NOTE: this can be different than SIGSEGV_REGISTER_TYPE. In
54	+	// particular, on ILP32 systems with a 64-bit kernel (HP-UX/ia64?)
55	+	#ifdef HAVE_WIN32_VM
56	+	// Windows is either ILP32 or LLP64
57	+	typedef UINT_PTR sigsegv_uintptr_t;
58	+	#else
59	+	// Other systems are sane enough to follow ILP32 or LP64 models
60	+	typedef unsigned long sigsegv_uintptr_t;
61	+	#endif
62	+
63		// Type of the system signal handler
64		typedef RETSIGTYPE (*signal_handler)(int);
65
#	Line 264 \| Line 275 \| static void powerpc_decode_instruction(i
275		#include <sys/regset.h>
276		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
277		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[EIP]
278	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
278	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
279		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
280		#endif
281		#endif
282		#if defined(__FreeBSD__) \|\| defined(__OpenBSD__)
283		#if (defined(i386) \|\| defined(__i386__))
284		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
285	<	#define SIGSEGV_REGISTER_FILE ((unsigned long )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
285	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
286		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
287		#endif
288		#endif
#	Line 280 \| Line 291 \| static void powerpc_decode_instruction(i
291		#include <sys/ucontext.h>
292		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
293		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP]
294	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
294	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
295		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
296		#endif
297		#if (defined(powerpc) \|\| defined(__powerpc__))
#	Line 296 \| Line 307 \| static void powerpc_decode_instruction(i
307		#include <sys/ucontext.h>
308		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
309		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
310	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
310	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
311		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
312		#endif
313		#if (defined(x86_64) \|\| defined(__x86_64__))
314		#include <sys/ucontext.h>
315		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
316		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
317	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
317	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
318		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
319		#endif
320		#if (defined(ia64) \|\| defined(__ia64__))
321		#define SIGSEGV_CONTEXT_REGS ((struct sigcontext *)scp)
322		#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
323	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
323	>	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
324		#define SIGSEGV_SKIP_INSTRUCTION ia64_skip_instruction
325		#endif
326		#if (defined(powerpc) \|\| defined(__powerpc__))
#	Line 351 \| Line 362 \| static void powerpc_decode_instruction(i
362		#define SIGSEGV_FAULT_HANDLER_ARGS &scs
363		#define SIGSEGV_FAULT_ADDRESS scp->cr2
364		#define SIGSEGV_FAULT_INSTRUCTION scp->eip
365	<	#define SIGSEGV_REGISTER_FILE (unsigned long *)scp
365	>	#define SIGSEGV_REGISTER_FILE (SIGSEGV_REGISTER_TYPE *)scp
366		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
367		#endif
368		#if (defined(sparc) \|\| defined(__sparc__))
#	Line 472 \| Line 483 \| static sigsegv_address_t get_fault_addre
483		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr
484		#define SIGSEGV_FAULT_ADDRESS addr
485		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_eip
486	<	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi)
486	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&scp->sc_edi)
487		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
488		#endif
489		#if (defined(alpha) \|\| defined(__alpha__))
#	Line 535 \| Line 546 \| static sigsegv_address_t get_fault_addre
546		#include <windows.h>
547		#include <winerror.h>
548
549	+	#if defined(_M_IX86)
550		#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo
551		#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo
552		#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
553		#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord
554		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip
555	<	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
555	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi)
556	>	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
557	>	#endif
558	>	#if defined(_M_X64)
559	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo
560	>	#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo
561	>	#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
562	>	#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord
563	>	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Rip
564	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax)
565		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
566		#endif
567	+	#endif
568
569		#if HAVE_MACH_EXCEPTIONS
570
#	Line 605 \| Line 627 \| if (ret != KERN_SUCCESS) { \
627		}
628
629		#ifdef __ppc__
630	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE
631	+	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
632	+	#endif
633		#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state_t
634		#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE
635		#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE_COUNT
636	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.dar
636	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar)
637		#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t
638		#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE
639		#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT
640	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.srr0
640	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0)
641		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
642	<	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.srr0, (unsigned long )&SIP->thr_state.r0
642	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(r0)
643		#endif
644		#ifdef __ppc64__
645	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64
646	+	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
647	+	#endif
648		#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state64_t
649		#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE64
650		#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE64_COUNT
651	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.dar
651	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar)
652		#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state64_t
653		#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE64
654		#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE64_COUNT
655	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.srr0
655	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0)
656		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
657	<	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.srr0, (unsigned long )&SIP->thr_state.r0
657	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(r0)
658		#endif
659		#ifdef __i386__
660	<	#define SIGSEGV_EXCEPTION_STATE_TYPE struct i386_exception_state
660	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32
661	>	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
662	>	#endif
663	>	#define SIGSEGV_EXCEPTION_STATE_TYPE i386_exception_state_t
664		#define SIGSEGV_EXCEPTION_STATE_FLAVOR i386_EXCEPTION_STATE
665		#define SIGSEGV_EXCEPTION_STATE_COUNT i386_EXCEPTION_STATE_COUNT
666	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.faultvaddr
667	<	#define SIGSEGV_THREAD_STATE_TYPE struct i386_thread_state
666	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
667	>	#define SIGSEGV_THREAD_STATE_TYPE i386_thread_state_t
668		#define SIGSEGV_THREAD_STATE_FLAVOR i386_THREAD_STATE
669		#define SIGSEGV_THREAD_STATE_COUNT i386_THREAD_STATE_COUNT
670	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.eip
670	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(eip)
671		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
672	<	#define SIGSEGV_REGISTER_FILE ((unsigned long )&SIP->thr_state.eax) / EAX is the first GPR we consider */
672	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.MACH_FIELD_NAME(eax)) / EAX is the first GPR we consider */
673		#endif
674		#ifdef __x86_64__
675	<	#define SIGSEGV_EXCEPTION_STATE_TYPE struct x86_exception_state64
675	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64
676	>	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
677	>	#endif
678	>	#define SIGSEGV_EXCEPTION_STATE_TYPE x86_exception_state64_t
679		#define SIGSEGV_EXCEPTION_STATE_FLAVOR x86_EXCEPTION_STATE64
680		#define SIGSEGV_EXCEPTION_STATE_COUNT x86_EXCEPTION_STATE64_COUNT
681	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.faultvaddr
682	<	#define SIGSEGV_THREAD_STATE_TYPE struct x86_thread_state64
681	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
682	>	#define SIGSEGV_THREAD_STATE_TYPE x86_thread_state64_t
683		#define SIGSEGV_THREAD_STATE_FLAVOR x86_THREAD_STATE64
684		#define SIGSEGV_THREAD_STATE_COUNT x86_THREAD_STATE64_COUNT
685	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.rip
685	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(rip)
686		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
687	<	#define SIGSEGV_REGISTER_FILE ((unsigned long )&SIP->thr_state.rax) / RAX is the first GPR we consider */
687	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.MACH_FIELD_NAME(rax)) / RAX is the first GPR we consider */
688		#endif
689		#define SIGSEGV_FAULT_ADDRESS_FAST code[1]
690		#define SIGSEGV_FAULT_INSTRUCTION_FAST SIGSEGV_INVALID_ADDRESS
691		#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code
692		#define SIGSEGV_FAULT_HANDLER_ARGS thread, code
693
694	+	#ifndef MACH_FIELD_NAME
695	+	#define MACH_FIELD_NAME(X) X
696	+	#endif
697	+
698		// Since there can only be one exception thread running at any time
699		// this is not a problem.
700		#define MSG_SIZE 512
#	Line 708 \| Line 746 \| *handleExceptions(void priv)**
746		* Instruction skipping
747		*/
748
749	+	#ifndef SIGSEGV_REGISTER_TYPE
750	+	#define SIGSEGV_REGISTER_TYPE sigsegv_uintptr_t
751	+	#endif
752	+
753		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
754		// Decode and skip X86 instruction
755	<	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
755	>	#if (defined(i386) \|\| defined(__i386__)) \|\| (defined(__x86_64__) \|\| defined(_M_X64))
756		#if defined(__linux__)
757		enum {
758		#if (defined(i386) \|\| defined(__i386__))
#	Line 861 \| Line 903 \| enum {
903		#endif
904		#if defined(_WIN32)
905		enum {
906	<	#if (defined(i386) \|\| defined(__i386__))
906	>	#if defined(_M_IX86)
907		X86_REG_EIP = 7,
908		X86_REG_EAX = 5,
909		X86_REG_ECX = 4,
#	Line 872 \| Line 914 \| enum {
914		X86_REG_ESI = 1,
915		X86_REG_EDI = 0
916		#endif
917	+	#if defined(_M_X64)
918	+	X86_REG_EAX = 0,
919	+	X86_REG_ECX = 1,
920	+	X86_REG_EDX = 2,
921	+	X86_REG_EBX = 3,
922	+	X86_REG_ESP = 4,
923	+	X86_REG_EBP = 5,
924	+	X86_REG_ESI = 6,
925	+	X86_REG_EDI = 7,
926	+	X86_REG_R8 = 8,
927	+	X86_REG_R9 = 9,
928	+	X86_REG_R10 = 10,
929	+	X86_REG_R11 = 11,
930	+	X86_REG_R12 = 12,
931	+	X86_REG_R13 = 13,
932	+	X86_REG_R14 = 14,
933	+	X86_REG_R15 = 15,
934	+	X86_REG_EIP = 16
935	+	#endif
936		};
937		#endif
938		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 908 \| Line 969 \| static inline int ix86_step_over_modrm(u
969		return offset;
970		}
971
972	<	static bool ix86_skip_instruction(unsigned long * regs)
972	>	static bool ix86_skip_instruction(SIGSEGV_REGISTER_TYPE * regs)
973		{
974		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
975
#	Line 944 \| Line 1005 \| static bool ix86_skip_instruction(unsign
1005		}
1006
1007		// REX prefix
1008	<	#if defined(__x86_64__)
1008	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1009		struct rex_t {
1010		unsigned char W;
1011		unsigned char R;
#	Line 996 \| Line 1057 \| static bool ix86_skip_instruction(unsign
1057		goto do_transfer_load;
1058		}
1059		break;
1060	<	#if defined(__x86_64__)
1060	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1061		case 0x63: // MOVSXD r64, r/m32
1062		if (has_rex && rex.W) {
1063		transfer_size = SIZE_LONG;
#	Line 1067 \| Line 1128 \| static bool ix86_skip_instruction(unsign
1128		return false;
1129		}
1130
1131	<	#if defined(__x86_64__)
1131	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1132		if (rex.R)
1133		reg += 8;
1134		#endif
#	Line 1076 \| Line 1137 \| static bool ix86_skip_instruction(unsign
1137		static const int x86_reg_map[] = {
1138		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
1139		X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
1140	<	#if defined(__x86_64__)
1140	>	#if defined(__x86_64__) \|\| defined(_M_X64)
1141		X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
1142		X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
1143		#endif
#	Line 1166 \| Line 1227 \| static bool ix86_skip_instruction(unsign
1227		// Decode and skip IA-64 instruction
1228		#if defined(__ia64__)
1229		#if defined(__linux__)
1230	<	// XXX: we assume everything is 8-byte aligned
1231	<	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
1171	<	#define IREG(REG) ((OREG(REG) - OREG(flags)) / 8)
1172	<	enum {
1173	<	IA64_REG_IP = IREG(ip),
1174	<	IA64_REG_NAT = IREG(nat),
1175	<	IA64_REG_PR = IREG(pr),
1176	<	IA64_REG_GR = IREG(gr)
1177	<	};
1178	<	#undef IREG
1179	<	#undef OREG
1180	<	#endif
1181	<
1230	>	// We can directly patch the slot number
1231	>	#define IA64_CAN_PATCH_IP_SLOT 1
1232		// Helper macros to access the machine context
1233	<	#define IA64_CONTEXT (ctx)
1234	<	#define IA64_GET_PR(P) ((IA64_CONTEXT[IA64_REG_PR] >> (P)) & 1)
1235	<	#define IA64_GET_NAT(I) ((IA64_CONTEXT[IA64_REG_NAT] >> (I)) & 1)
1236	<	#define IA64_SET_NAT(I,V) (IA64_CONTEXT[IA64_REG_NAT] = (IA64_CONTEXT[IA64_REG_NAT] & ~(1ul << (I))) \| (((unsigned long)!!(V)) << (I)))
1237	<	#define IA64_GET_GR(R) (IA64_CONTEXT[IA64_REG_GR + (R)])
1238	<	#define IA64_SET_GR(R,V) (IA64_CONTEXT[IA64_REG_GR + (R)] = (V))
1233	>	#define IA64_CONTEXT_TYPE struct sigcontext *
1234	>	#define IA64_CONTEXT scp
1235	>	#define IA64_GET_IP() (IA64_CONTEXT->sc_ip)
1236	>	#define IA64_SET_IP(V) (IA64_CONTEXT->sc_ip = (V))
1237	>	#define IA64_GET_PR(P) ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1238	>	#define IA64_GET_NAT(I) ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1239	>	#define IA64_SET_NAT(I,V) (IA64_CONTEXT->sc_nat= (IA64_CONTEXT->sc_nat & ~(1ul << (I))) \| (((unsigned long)!!(V)) << (I)))
1240	>	#define IA64_GET_GR(R) (IA64_CONTEXT->sc_gr[(R)])
1241	>	#define IA64_SET_GR(R,V) (IA64_CONTEXT->sc_gr[(R)] = (V))
1242	>	#endif
1243
1244		// Instruction operations
1245		enum {
#	Line 1346 \| Line 1400 \| static unsigned long ia64_get_instructio
1400		}
1401
1402		// Decode group 0 instructions
1403	<	static bool ia64_decode_instruction_0(ia64_instruction_t inst, unsigned long ctx)
1403	>	static bool ia64_decode_instruction_0(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1404		{
1405		const int r1 = (inst->inst >> 6) & 0x7f;
1406		const int r3 = (inst->inst >> 20) & 0x7f;
#	Line 1392 \| Line 1446 \| static bool ia64_decode_instruction_0(ia
1446		}
1447
1448		// Decode group 4 instructions (load/store instructions)
1449	<	static bool ia64_decode_instruction_4(ia64_instruction_t inst, unsigned long ctx)
1449	>	static bool ia64_decode_instruction_4(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1450		{
1451		const int r1 = (inst->inst >> 6) & 0x7f;
1452		const int r2 = (inst->inst >> 13) & 0x7f;
#	Line 1464 \| Line 1518 \| static bool ia64_decode_instruction_4(ia
1518		}
1519
1520		// Decode group 5 instructions (load/store instructions)
1521	<	static bool ia64_decode_instruction_5(ia64_instruction_t inst, unsigned long ctx)
1521	>	static bool ia64_decode_instruction_5(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1522		{
1523		const int r1 = (inst->inst >> 6) & 0x7f;
1524		const int r2 = (inst->inst >> 13) & 0x7f;
#	Line 1522 \| Line 1576 \| static bool ia64_decode_instruction_5(ia
1576		}
1577
1578		// Decode group 8 instructions (ALU integer)
1579	<	static bool ia64_decode_instruction_8(ia64_instruction_t inst, unsigned long ctx)
1579	>	static bool ia64_decode_instruction_8(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1580		{
1581		const int r1 = (inst->inst >> 6) & 0x7f;
1582		const int r2 = (inst->inst >> 13) & 0x7f;
#	Line 1595 \| Line 1649 \| static bool ia64_decode_instruction_8(ia
1649		}
1650
1651		// Decode instruction
1652	<	static bool ia64_decode_instruction(ia64_instruction_t inst, unsigned long ctx)
1652	>	static bool ia64_decode_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1653		{
1654		const int major = (inst->inst >> 37) & 0xf;
1655
#	Line 1604 \| Line 1658 \| static bool ia64_decode_instruction(ia64
1658		memset(&inst->operands[0], 0, sizeof(inst->operands));
1659
1660		switch (major) {
1661	<	case 0x0: return ia64_decode_instruction_0(inst, ctx);
1662	<	case 0x4: return ia64_decode_instruction_4(inst, ctx);
1663	<	case 0x5: return ia64_decode_instruction_5(inst, ctx);
1664	<	case 0x8: return ia64_decode_instruction_8(inst, ctx);
1661	>	case 0x0: return ia64_decode_instruction_0(inst, IA64_CONTEXT);
1662	>	case 0x4: return ia64_decode_instruction_4(inst, IA64_CONTEXT);
1663	>	case 0x5: return ia64_decode_instruction_5(inst, IA64_CONTEXT);
1664	>	case 0x8: return ia64_decode_instruction_8(inst, IA64_CONTEXT);
1665		}
1666		return false;
1667		}
1668
1669	<	static bool ia64_emulate_instruction(ia64_instruction_t inst, unsigned long ctx)
1669	>	static bool ia64_emulate_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1670		{
1671		// XXX: handle Register NaT Consumption fault?
1672		// XXX: this simple emulator assumes instructions in a bundle
#	Line 1743 \| Line 1797 \| static bool ia64_emulate_instruction(ia6
1797		return true;
1798		}
1799
1800	<	static bool ia64_emulate_instruction(unsigned long raw_inst, unsigned long *ctx)
1800	>	static bool ia64_emulate_instruction(unsigned long raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1801		{
1802		ia64_instruction_t inst;
1803		memset(&inst, 0, sizeof(inst));
1804		inst.inst = raw_inst;
1805	<	if (!ia64_decode_instruction(&inst, ctx))
1805	>	if (!ia64_decode_instruction(&inst, IA64_CONTEXT))
1806		return false;
1807	<	return ia64_emulate_instruction(&inst, ctx);
1807	>	return ia64_emulate_instruction(&inst, IA64_CONTEXT);
1808		}
1809
1810	<	static bool ia64_skip_instruction(unsigned long *ctx)
1810	>	static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1811		{
1812	<	unsigned long ip = ctx[IA64_REG_IP];
1812	>	unsigned long ip = IA64_GET_IP();
1813		#if DEBUG
1814		printf("IP: 0x%016lx\n", ip);
1815		#if 0
#	Line 1769 \| Line 1823 \| static bool ia64_skip_instruction(unsign
1823		// Select which decode switch to use
1824		ia64_instruction_t inst;
1825		inst.inst = ia64_get_instruction(ip, ip & 3);
1826	<	if (!ia64_decode_instruction(&inst, ctx)) {
1826	>	if (!ia64_decode_instruction(&inst, IA64_CONTEXT)) {
1827		fprintf(stderr, "ERROR: ia64_skip_instruction(): could not decode instruction\n");
1828		return false;
1829		}
#	Line 1840 \| Line 1894 \| static bool ia64_skip_instruction(unsign
1894		}
1895
1896		inst.no_memory = true;
1897	<	if (!ia64_emulate_instruction(&inst, ctx)) {
1897	>	if (!ia64_emulate_instruction(&inst, IA64_CONTEXT)) {
1898		fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate fault instruction\n");
1899		return false;
1900		}
#	Line 1863 \| Line 1917 \| static bool ia64_skip_instruction(unsign
1917		}
1918		break;
1919		}
1920	<	if (emulate_next) {
1920	>	if (emulate_next && !IA64_CAN_PATCH_IP_SLOT) {
1921		while (slot < 3) {
1922	<	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), ctx)) {
1922	>	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), IA64_CONTEXT)) {
1923		fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate instruction\n");
1924		return false;
1925		}
#	Line 1873 \| Line 1927 \| static bool ia64_skip_instruction(unsign
1927		}
1928		}
1929
1930	<	ctx[IA64_REG_IP] = (ip & ~3ul) + 16;
1930	>	#if IA64_CAN_PATCH_IP_SLOT
1931	>	if ((slot = ip & 3) < 2)
1932	>	IA64_SET_IP((ip & ~3ul) + (slot + 1));
1933	>	else
1934	>	#endif
1935	>	IA64_SET_IP((ip & ~3ul) + 16);
1936		#if DEBUG
1937	<	printf("IP: 0x%016lx\n", ctx[IA64_REG_IP]);
1937	>	printf("IP: 0x%016lx\n", IA64_GET_IP());
1938		#endif
1939		return true;
1940		}
#	Line 2439 \| Line 2498 \| sigsegv_address_t sigsegv_get_fault_addr
2498		mach_get_exception_state(SIP);
2499
2500		sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
2501	<	if (use_fast_path < 0)
2502	<	use_fast_path = addr == SIP->addr;
2501	>	if (use_fast_path < 0) {
2502	>	const char *machfault = getenv("SIGSEGV_MACH_FAULT");
2503	>	if (machfault) {
2504	>	if (strcmp(machfault, "fast") == 0)
2505	>	use_fast_path = 1;
2506	>	else if (strcmp(machfault, "slow") == 0)
2507	>	use_fast_path = 0;
2508	>	}
2509	>	if (use_fast_path < 0)
2510	>	use_fast_path = addr == SIP->addr;
2511	>	}
2512		SIP->addr = addr;
2513		}
2514		#endif
#	Line 2969 \| Line 3037 \| void sigsegv_set_dump_state(sigsegv_stat
3037		const int REF_INDEX = 123;
3038		const int REF_VALUE = 45;
3039
3040	<	static int page_size;
3040	>	static sigsegv_uintptr_t page_size;
3041		static volatile char * page = 0;
3042		static volatile int handler_called = 0;
3043
#	Line 3007 \| Line 3075 \| static sigsegv_return_t sigsegv_test_han
3075		(instruction_address >= (sigsegv_address_t)e_region)))
3076		exit(11);
3077		#endif
3078	<	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ \| VM_PAGE_WRITE) != 0)
3078	>	if (vm_protect((char *)((sigsegv_uintptr_t)fault_address & -page_size), page_size, VM_PAGE_READ \| VM_PAGE_WRITE) != 0)
3079		exit(12);
3080		return SIGSEGV_RETURN_SUCCESS;
3081		}
#	Line 3020 \| Line 3088 \| static sigsegv_return_t sigsegv_insn_han
3088		#if DEBUG
3089		printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
3090		#endif
3091	<	if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
3091	>	if (((sigsegv_uintptr_t)fault_address - (sigsegv_uintptr_t)page) < page_size) {
3092		#ifdef __GNUC__
3093		// Make sure reported fault instruction address falls into
3094		// expected code range
#	Line 3038 \| Line 3106 \| static sigsegv_return_t sigsegv_insn_han
3106		// More sophisticated tests for instruction skipper
3107		static bool arch_insn_skipper_tests()
3108		{
3109	<	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
3109	>	#if (defined(i386) \|\| defined(__i386__)) \|\| (defined(__x86_64__) \|\| defined(_M_X64))
3110		static const unsigned char code[] = {
3111		0x8a, 0x00, // mov (%eax),%al
3112		0x8a, 0x2c, 0x18, // mov (%eax,%ebx,1),%ch
#	Line 3052 \| Line 3120 \| static bool arch_insn_skipper_tests()
3120		0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%ecx
3121		0x89, 0x00, // mov %eax,(%eax)
3122		0x89, 0x0c, 0x18, // mov %ecx,(%eax,%ebx,1)
3123	<	#if defined(__x86_64__)
3123	>	#if defined(__x86_64__) \|\| defined(_M_X64)
3124		0x44, 0x8a, 0x00, // mov (%rax),%r8b
3125		0x44, 0x8a, 0x20, // mov (%rax),%r12b
3126		0x42, 0x8a, 0x3c, 0x10, // mov (%rax,%r10,1),%dil
#	Line 3081 \| Line 3149 \| static bool arch_insn_skipper_tests()
3149		0 // end
3150		};
3151		const int N_REGS = 20;
3152	<	unsigned long regs[N_REGS];
3152	>	SIGSEGV_REGISTER_TYPE regs[N_REGS];
3153		for (int i = 0; i < N_REGS; i++)
3154		regs[i] = i;
3155	<	const unsigned long start_code = (unsigned long)&code;
3155	>	const sigsegv_uintptr_t start_code = (sigsegv_uintptr_t)&code;
3156		regs[X86_REG_EIP] = start_code;
3157		while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
3158		&& ix86_skip_instruction(regs))

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.76 by gbeauche, 2008-01-06T16:36:00Z vs. Revision 1.80 by gbeauche, 2008-01-14T19:29:29Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.76 by gbeauche, 2008-01-06T16:36:00Z vs.
Revision 1.80 by gbeauche, 2008-01-14T19:29:29Z