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root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.79 by gbeauche, 2008-01-12T23:01:40Z vs.
Revision 1.86 by asvitkine, 2009-02-11T19:23:53Z

#	Line 243 | Line 243 | static void powerpc_decode_instruction(i
243		// Generic extended signal handler
244		#if defined(__FreeBSD__)
245		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
246	+	#elif defined(__hpux)
247	+	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV) FAULT_HANDLER(SIGBUS)
248		#else
249		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
250		#endif
#	Line 349 | Line 351 | static void powerpc_decode_instruction(i
351		#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
352		#endif
353		#endif
354	+	#if (defined(__hpux) || defined(__hpux__))
355	+	#if (defined(__hppa) || defined(__hppa__))
356	+	#define SIGSEGV_CONTEXT_REGS                    (&((ucontext_t *)scp)->uc_mcontext)
357	+	#define SIGSEGV_FAULT_INSTRUCTION_32    (SIGSEGV_CONTEXT_REGS->ss_narrow.ss_pcoq_head & ~3ul)
358	+	#define SIGSEGV_FAULT_INSTRUCTION_64    (SIGSEGV_CONTEXT_REGS->ss_wide.ss_64.ss_pcoq_head & ~3ull)
359	+	#if defined(__LP64__)
360	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_FAULT_INSTRUCTION_64
361	+	#else
362	+	#define SIGSEGV_FAULT_INSTRUCTION               ((SIGSEGV_CONTEXT_REGS->ss_flags & SS_WIDEREGS) ? \
363	+	(uint32_t)SIGSEGV_FAULT_INSTRUCTION_64 : \
364	+	SIGSEGV_FAULT_INSTRUCTION_32)
365	+	#endif
366	+	#endif
367	+	#if (defined(__ia64) || defined(__ia64__))
368	+	#include <sys/ucontext.h>
369	+	#define SIGSEGV_CONTEXT_REGS                    ((ucontext_t *)scp)
370	+	#define SIGSEGV_FAULT_INSTRUCTION               get_fault_instruction(SIGSEGV_CONTEXT_REGS)
371	+	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
372	+	#define SIGSEGV_SKIP_INSTRUCTION                ia64_skip_instruction
373	+
374	+	#include <sys/uc_access.h>
375	+	static inline sigsegv_address_t get_fault_instruction(const ucontext_t *ucp)
376	+	{
377	+	uint64_t ip;
378	+	if (__uc_get_ip(ucp, &ip) != 0)
379	+	return SIGSEGV_INVALID_ADDRESS;
380	+	return (sigsegv_address_t)(ip & ~3ULL);
381	+	}
382	+	#endif
383	+	#endif
384		#endif
385
386		#if HAVE_SIGCONTEXT_SUBTERFUGE
#	Line 518 | Line 550 | static sigsegv_address_t get_fault_addre
550		#ifndef HAVE_MACH_EXCEPTIONS
551		#if defined(__APPLE__) && defined(__MACH__)
552		#if (defined(ppc) || defined(__ppc__))
553	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
553	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct __darwin_sigcontext *scp
554		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
555		#define SIGSEGV_FAULT_ADDRESS                   get_fault_address(scp)
556	<	#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_ir
556	>	#define SIGSEGV_FAULT_INSTRUCTION               scp->MACH_FIELD_NAME(sc_ir)
557		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
558		#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&scp->sc_ir, &((unsigned int *) scp->sc_regs)[2]
559		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
#	Line 529 | Line 561 | static sigsegv_address_t get_fault_addre
561		// Use decoding scheme from SheepShaver
562		static sigsegv_address_t get_fault_address(struct sigcontext *scp)
563		{
564	<	unsigned int   nip = (unsigned int) scp->sc_ir;
565	<	unsigned int * gpr = &((unsigned int *) scp->sc_regs)[2];
564	>	unsigned int   nip = (unsigned int) scp->MACH_FIELD_NAME(sc_ir);
565	>	unsigned int * gpr = &((unsigned int *) scp->MACH_FIELD_NAME(sc_regs))[2];
566		instruction_t  instr;
567
568	<	powerpc_decode_instruction(&instr, nip, gpr);
568	>	powerpc_decode_instruction(&instr, nip, (long unsigned int*)gpr);
569		return (sigsegv_address_t)instr.addr;
570		}
571		#endif
#	Line 546 | Line 578 | static sigsegv_address_t get_fault_addre
578		#include <windows.h>
579		#include <winerror.h>
580
549	–	#if defined(_M_IX86)
581		#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
582		#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
583		#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
584		#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
585	+	#if defined(_M_IX86)
586		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Eip
587		#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi)
588		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
589		#endif
590		#if defined(_M_X64)
559	–	#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
560	–	#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
561	–	#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
562	–	#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
591		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Rip
592		#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax)
593		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
594		#endif
595	+	#if defined(_M_IA64)
596	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->StIIP
597	+	#endif
598		#endif
599
600		#if HAVE_MACH_EXCEPTIONS
#	Line 586 | Line 617 | extern "C" {
617		#include <mach/mach.h>
618		#include <mach/mach_error.h>
619
620	<	extern boolean_t exc_server(mach_msg_header_t *, mach_msg_header_t *);
621	<	extern kern_return_t catch_exception_raise(mach_port_t, mach_port_t,
622	<	mach_port_t, exception_type_t, exception_data_t, mach_msg_type_number_t);
623	<	extern kern_return_t exception_raise(mach_port_t, mach_port_t, mach_port_t,
624	<	exception_type_t, exception_data_t, mach_msg_type_number_t);
625	<	extern kern_return_t exception_raise_state(mach_port_t, exception_type_t,
626	<	exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
620	>	#ifndef HAVE_MACH64_VM
621	>
622	>	// Undefine this to prevent a preprocessor warning when compiling on a
623	>	// 32-bit machine with Mac OS X 10.5.
624	>	#undef  MACH_EXCEPTION_CODES
625	>
626	>	#define MACH_EXCEPTION_CODES                                    0
627	>	#define mach_exception_data_t                                   exception_data_t
628	>	#define mach_exception_data_type_t                              exception_data_type_t
629	>	#define mach_exc_server                                                 exc_server
630	>	#define catch_mach_exception_raise                              catch_exception_raise
631	>	#define mach_exception_raise                                    exception_raise
632	>	#define mach_exception_raise_state                              exception_raise_state
633	>	#define mach_exception_raise_state_identity             exception_raise_state_identity
634	>	#endif
635	>
636	>	extern boolean_t mach_exc_server(mach_msg_header_t *, mach_msg_header_t *);
637	>	extern kern_return_t catch_mach_exception_raise(mach_port_t, mach_port_t,
638	>	mach_port_t, exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
639	>	extern kern_return_t catch_mach_exception_raise_state(mach_port_t exception_port,
640	>	exception_type_t exception, mach_exception_data_t code, mach_msg_type_number_t code_count,
641	>	int *flavor,
642	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
643	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
644	>	extern kern_return_t catch_mach_exception_raise_state_identity(mach_port_t exception_port,
645	>	mach_port_t thread_port, mach_port_t task_port, exception_type_t exception,
646	>	mach_exception_data_t code, mach_msg_type_number_t code_count,
647	>	int *flavor,
648	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
649	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
650	>	extern kern_return_t mach_exception_raise(mach_port_t, mach_port_t, mach_port_t,
651	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
652	>	extern kern_return_t mach_exception_raise_state(mach_port_t, exception_type_t,
653	>	mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
654		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
655	<	extern kern_return_t exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
656	<	exception_type_t, exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
655	>	extern kern_return_t mach_exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
656	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
657		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
658		}
659
#	Line 627 | Line 685 | if (ret != KERN_SUCCESS) { \
685		}
686
687		#ifdef __ppc__
688	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE
689	+	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
690	+	#endif
691		#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state_t
692		#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE
693		#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE_COUNT
694	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.dar
694	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
695		#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state_t
696		#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE
697		#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE_COUNT
698	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.srr0
698	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
699		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
700	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.srr0, (unsigned long *)&SIP->thr_state.r0
700	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
701		#endif
702		#ifdef __ppc64__
703	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64
704	+	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
705	+	#endif
706		#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state64_t
707		#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE64
708		#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE64_COUNT
709	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.dar
709	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
710		#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state64_t
711		#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE64
712		#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE64_COUNT
713	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.srr0
713	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
714		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
715	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.srr0, (unsigned long *)&SIP->thr_state.r0
715	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
716		#endif
717		#ifdef __i386__
718	<	#define SIGSEGV_EXCEPTION_STATE_TYPE    struct i386_exception_state
718	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32
719	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
720	>	#endif
721	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    i386_exception_state_t
722		#define SIGSEGV_EXCEPTION_STATE_FLAVOR  i386_EXCEPTION_STATE
723		#define SIGSEGV_EXCEPTION_STATE_COUNT   i386_EXCEPTION_STATE_COUNT
724	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.faultvaddr
725	<	#define SIGSEGV_THREAD_STATE_TYPE               struct i386_thread_state
724	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
725	>	#define SIGSEGV_THREAD_STATE_TYPE               i386_thread_state_t
726		#define SIGSEGV_THREAD_STATE_FLAVOR             i386_THREAD_STATE
727		#define SIGSEGV_THREAD_STATE_COUNT              i386_THREAD_STATE_COUNT
728	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.eip
728	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(eip)
729		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
730	<	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.eax) /* EAX is the first GPR we consider */
730	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(eax)) /* EAX is the first GPR we consider */
731		#endif
732		#ifdef __x86_64__
733	<	#define SIGSEGV_EXCEPTION_STATE_TYPE    struct x86_exception_state64
733	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64
734	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
735	>	#endif
736	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    x86_exception_state64_t
737		#define SIGSEGV_EXCEPTION_STATE_FLAVOR  x86_EXCEPTION_STATE64
738		#define SIGSEGV_EXCEPTION_STATE_COUNT   x86_EXCEPTION_STATE64_COUNT
739	<	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.faultvaddr
740	<	#define SIGSEGV_THREAD_STATE_TYPE               struct x86_thread_state64
739	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
740	>	#define SIGSEGV_THREAD_STATE_TYPE               x86_thread_state64_t
741		#define SIGSEGV_THREAD_STATE_FLAVOR             x86_THREAD_STATE64
742		#define SIGSEGV_THREAD_STATE_COUNT              x86_THREAD_STATE64_COUNT
743	<	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.rip
743	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(rip)
744		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
745	<	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.rax) /* RAX is the first GPR we consider */
745	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(rax)) /* RAX is the first GPR we consider */
746		#endif
747		#define SIGSEGV_FAULT_ADDRESS_FAST              code[1]
748		#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_INVALID_ADDRESS
749	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code
749	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, mach_exception_data_t code
750		#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code
751
752	+	#ifndef MACH_FIELD_NAME
753	+	#define MACH_FIELD_NAME(X) X
754	+	#endif
755	+
756		// Since there can only be one exception thread running at any time
757		// this is not a problem.
758		#define MSG_SIZE 512
#	Line 708 | Line 782 | handleExceptions(void *priv)
782		_exceptionPort, 0, MACH_PORT_NULL);
783		MACH_CHECK_ERROR(mach_msg, krc);
784
785	<	if (!exc_server(msg, reply)) {
785	>	if (!mach_exc_server(msg, reply)) {
786		fprintf(stderr, "exc_server hated the message\n");
787		exit(1);
788		}
#	Line 1209 | Line 1283 | static bool ix86_skip_instruction(SIGSEG
1283		#endif
1284
1285		// Decode and skip IA-64 instruction
1286	<	#if defined(__ia64__)
1286	>	#if defined(__ia64) || defined(__ia64__)
1287	>	typedef uint64_t ia64_bundle_t[2];
1288		#if defined(__linux__)
1289		// We can directly patch the slot number
1290	<	#define IA64_CAN_PATCH_IP_SLOT 1
1290	>	#define IA64_CAN_PATCH_IP_SLOT  1
1291		// Helper macros to access the machine context
1292		#define IA64_CONTEXT_TYPE               struct sigcontext *
1293		#define IA64_CONTEXT                    scp
#	Line 1220 | Line 1295 | static bool ix86_skip_instruction(SIGSEG
1295		#define IA64_SET_IP(V)                  (IA64_CONTEXT->sc_ip = (V))
1296		#define IA64_GET_PR(P)                  ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1297		#define IA64_GET_NAT(I)                 ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1223	–	#define IA64_SET_NAT(I,V)               (IA64_CONTEXT->sc_nat= (IA64_CONTEXT->sc_nat & ~(1ul << (I))) | (((unsigned long)!!(V)) << (I)))
1298		#define IA64_GET_GR(R)                  (IA64_CONTEXT->sc_gr[(R)])
1299	<	#define IA64_SET_GR(R,V)                (IA64_CONTEXT->sc_gr[(R)] = (V))
1299	>	#define _IA64_SET_GR(R,V)               (IA64_CONTEXT->sc_gr[(R)] = (V))
1300	>	#define _IA64_SET_NAT(I,V)              (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) | (((uint64_t)!!(V)) << (I)))
1301	>	#define IA64_SET_GR(R,V,N)              (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N))
1302	>
1303	>	// Load bundle (in little-endian)
1304	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1305	>	{
1306	>	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1307	>	bundle[0] = ip[0];
1308	>	bundle[1] = ip[1];
1309	>	}
1310	>	#endif
1311	>	#if defined(__hpux) || defined(__hpux__)
1312	>	// We can directly patch the slot number
1313	>	#define IA64_CAN_PATCH_IP_SLOT  1
1314	>	// Helper macros to access the machine context
1315	>	#define IA64_CONTEXT_TYPE               ucontext_t *
1316	>	#define IA64_CONTEXT                    ucp
1317	>	#define IA64_GET_IP()                   ia64_get_ip(IA64_CONTEXT)
1318	>	#define IA64_SET_IP(V)                  ia64_set_ip(IA64_CONTEXT, V)
1319	>	#define IA64_GET_PR(P)                  ia64_get_pr(IA64_CONTEXT, P)
1320	>	#define IA64_GET_NAT(I)                 ia64_get_nat(IA64_CONTEXT, I)
1321	>	#define IA64_GET_GR(R)                  ia64_get_gr(IA64_CONTEXT, R)
1322	>	#define IA64_SET_GR(R,V,N)              ia64_set_gr(IA64_CONTEXT, R, V, N)
1323	>	#define UC_ACCESS(FUNC,ARGS)    do { if (__uc_##FUNC ARGS != 0) abort(); } while (0)
1324	>
1325	>	static inline uint64_t ia64_get_ip(IA64_CONTEXT_TYPE IA64_CONTEXT)
1326	>	{ uint64_t v; UC_ACCESS(get_ip,(IA64_CONTEXT, &v)); return v; }
1327	>	static inline void ia64_set_ip(IA64_CONTEXT_TYPE IA64_CONTEXT, uint64_t v)
1328	>	{ UC_ACCESS(set_ip,(IA64_CONTEXT, v)); }
1329	>	static inline unsigned int ia64_get_pr(IA64_CONTEXT_TYPE IA64_CONTEXT, int pr)
1330	>	{ uint64_t v; UC_ACCESS(get_prs,(IA64_CONTEXT, &v)); return (v >> pr) & 1; }
1331	>	static inline unsigned int ia64_get_nat(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1332	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return (nat >> r) & 1; }
1333	>	static inline uint64_t ia64_get_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1334	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return v; }
1335	>
1336	>	static void ia64_set_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r, uint64_t v, unsigned int nat)
1337	>	{
1338	>	if (r == 0)
1339	>	return;
1340	>	if (r > 0 && r < 32)
1341	>	UC_ACCESS(set_grs,(IA64_CONTEXT, r, 1, &v, (!!nat) << r));
1342	>	else {
1343	>	uint64_t bsp, bspstore;
1344	>	UC_ACCESS(get_ar_bsp,(IA64_CONTEXT, &bsp));
1345	>	UC_ACCESS(get_ar_bspstore,(IA64_CONTEXT, &bspstore));
1346	>	abort(); /* XXX: use libunwind, this is not fun... */
1347	>	}
1348	>	}
1349	>
1350	>	// Byte-swapping
1351	>	#if defined(__GNUC__)
1352	>	#define BSWAP64(V) ({ uint64_t r; __asm__ __volatile__("mux1 %0=%1,@rev;;" : "=r" (r) : "r" (V)); r; })
1353	>	#elif defined (__HP_aCC)
1354	>	#define BSWAP64(V) _Asm_mux1(_MBTYPE_REV, V)
1355	>	#else
1356	>	#error "Define byte-swap instruction"
1357	>	#endif
1358	>
1359	>	// Load bundle (in little-endian)
1360	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1361	>	{
1362	>	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1363	>	bundle[0] = BSWAP64(ip[0]);
1364	>	bundle[1] = BSWAP64(ip[1]);
1365	>	}
1366		#endif
1367
1368		// Instruction operations
#	Line 1264 | Line 1404 | const int IA64_N_OPERANDS = 4;
1404
1405		// Decoded operand type
1406		struct ia64_operand_t {
1407	<	unsigned char commit;           // commit result of operation to register file?
1408	<	unsigned char valid;            // XXX: not really used, can be removed (debug)
1409	<	signed char index;                      // index of GPR, or -1 if immediate value
1410	<	unsigned char nat;                      // NaT state before operation
1411	<	unsigned long value;            // register contents or immediate value
1407	>	uint8_t commit;                         // commit result of operation to register file?
1408	>	uint8_t valid;                          // XXX: not really used, can be removed (debug)
1409	>	int8_t index;                           // index of GPR, or -1 if immediate value
1410	>	uint8_t nat;                            // NaT state before operation
1411	>	uint64_t value;                         // register contents or immediate value
1412		};
1413
1414		// Decoded instruction type
1415		struct ia64_instruction_t {
1416	<	unsigned char mnemo;            // operation to perform
1417	<	unsigned char pred;                     // predicate register to check
1418	<	unsigned char no_memory;        // used to emulated main fault instruction
1419	<	unsigned long inst;                     // the raw instruction bits (41-bit wide)
1416	>	uint8_t mnemo;                          // operation to perform
1417	>	uint8_t pred;                           // predicate register to check
1418	>	uint8_t no_memory;                      // used to emulated main fault instruction
1419	>	uint64_t inst;                          // the raw instruction bits (41-bit wide)
1420		ia64_operand_t operands[IA64_N_OPERANDS];
1421		};
1422
1423		// Get immediate sign-bit
1424	<	static inline int ia64_inst_get_sbit(unsigned long inst)
1424	>	static inline int ia64_inst_get_sbit(uint64_t inst)
1425		{
1426		return (inst >> 36) & 1;
1427		}
1428
1429		// Get 8-bit immediate value (A3, A8, I27, M30)
1430	<	static inline unsigned long ia64_inst_get_imm8(unsigned long inst)
1430	>	static inline uint64_t ia64_inst_get_imm8(uint64_t inst)
1431		{
1432	<	unsigned long value = (inst >> 13) & 0x7ful;
1432	>	uint64_t value = (inst >> 13) & 0x7full;
1433		if (ia64_inst_get_sbit(inst))
1434	<	value |= ~0x7ful;
1434	>	value |= ~0x7full;
1435		return value;
1436		}
1437
1438		// Get 9-bit immediate value (M3)
1439	<	static inline unsigned long ia64_inst_get_imm9b(unsigned long inst)
1439	>	static inline uint64_t ia64_inst_get_imm9b(uint64_t inst)
1440		{
1441	<	unsigned long value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f);
1441	>	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f);
1442		if (ia64_inst_get_sbit(inst))
1443	<	value |= ~0xfful;
1443	>	value |= ~0xffull;
1444		return value;
1445		}
1446
1447		// Get 9-bit immediate value (M5)
1448	<	static inline unsigned long ia64_inst_get_imm9a(unsigned long inst)
1448	>	static inline uint64_t ia64_inst_get_imm9a(uint64_t inst)
1449		{
1450	<	unsigned long value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f);
1450	>	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f);
1451		if (ia64_inst_get_sbit(inst))
1452	<	value |= ~0xfful;
1452	>	value |= ~0xffull;
1453		return value;
1454		}
1455
1456		// Get 14-bit immediate value (A4)
1457	<	static inline unsigned long ia64_inst_get_imm14(unsigned long inst)
1457	>	static inline uint64_t ia64_inst_get_imm14(uint64_t inst)
1458		{
1459	<	unsigned long value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f);
1459	>	uint64_t value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f);
1460		if (ia64_inst_get_sbit(inst))
1461	<	value |= ~0x1fful;
1461	>	value |= ~0x1ffull;
1462		return value;
1463		}
1464
1465		// Get 22-bit immediate value (A5)
1466	<	static inline unsigned long ia64_inst_get_imm22(unsigned long inst)
1466	>	static inline uint64_t ia64_inst_get_imm22(uint64_t inst)
1467		{
1468	<	unsigned long value = ((((inst >> 22) & 0x1f) << 16) |
1469	<	(((inst >> 27) & 0x1ff) << 7) |
1470	<	(inst & 0x7f));
1468	>	uint64_t value = ((((inst >> 22) & 0x1f) << 16) |
1469	>	(((inst >> 27) & 0x1ff) << 7) |
1470	>	(inst & 0x7f));
1471		if (ia64_inst_get_sbit(inst))
1472	<	value |= ~0x1ffffful;
1472	>	value |= ~0x1fffffull;
1473		return value;
1474		}
1475
1476		// Get 21-bit immediate value (I19)
1477	<	static inline unsigned long ia64_inst_get_imm21(unsigned long inst)
1477	>	static inline uint64_t ia64_inst_get_imm21(uint64_t inst)
1478		{
1479		return (((inst >> 36) & 1) << 20) | ((inst >> 6) & 0xfffff);
1480		}
1481
1482		// Get 2-bit count value (A2)
1483	<	static inline int ia64_inst_get_count2(unsigned long inst)
1483	>	static inline int ia64_inst_get_count2(uint64_t inst)
1484		{
1485		return (inst >> 27) & 0x3;
1486		}
1487
1488		// Get bundle template
1489	<	static inline unsigned int ia64_get_template(unsigned long raw_ip)
1489	>	static inline unsigned int ia64_get_template(uint64_t ip)
1490		{
1491	<	unsigned long *ip = (unsigned long *)(raw_ip & ~3ul);
1492	<	return ip[0] & 0x1f;
1491	>	ia64_bundle_t bundle;
1492	>	ia64_load_bundle(bundle, ip);
1493	>	return bundle[0] & 0x1f;
1494		}
1495
1496		// Get specified instruction in bundle
1497	<	static unsigned long ia64_get_instruction(unsigned long raw_ip, int slot)
1497	>	static uint64_t ia64_get_instruction(uint64_t ip, int slot)
1498		{
1499	<	unsigned long inst;
1500	<	unsigned long *ip = (unsigned long *)(raw_ip & ~3ul);
1499	>	uint64_t inst;
1500	>	ia64_bundle_t bundle;
1501	>	ia64_load_bundle(bundle, ip);
1502		#if DEBUG
1503	<	printf("Bundle: %016lx%016lx\n", ip[1], ip[0]);
1503	>	printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]);
1504		#endif
1505
1506		switch (slot) {
1507		case 0:
1508	<	inst = (ip[0] >> 5) & 0x1fffffffffful;
1508	>	inst = (bundle[0] >> 5) & 0x1ffffffffffull;
1509		break;
1510		case 1:
1511	<	inst = ((ip[1] & 0x7ffffful) << 18) | ((ip[0] >> 46) & 0x3fffful);
1511	>	inst = ((bundle[1] & 0x7fffffull) << 18) | ((bundle[0] >> 46) & 0x3ffffull);
1512		break;
1513		case 2:
1514	<	inst = (ip[1] >> 23) & 0x1fffffffffful;
1514	>	inst = (bundle[1] >> 23) & 0x1ffffffffffull;
1515		break;
1516		case 3:
1517		fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
#	Line 1378 | Line 1520 | static unsigned long ia64_get_instructio
1520		}
1521
1522		#if DEBUG
1523	<	printf(" Instruction %d: 0x%016lx\n", slot, inst);
1523	>	printf(" Instruction %d: 0x%016llx\n", slot, inst);
1524		#endif
1525		return inst;
1526		}
#	Line 1662 | Line 1804 | static bool ia64_emulate_instruction(ia6
1804		if (inst->pred && !IA64_GET_PR(inst->pred))
1805		return true;
1806
1807	<	unsigned char nat, nat2;
1808	<	unsigned long dst, dst2, src1, src2, src3;
1807	>	uint8_t nat, nat2;
1808	>	uint64_t dst, dst2, src1, src2, src3;
1809
1810		switch (inst->mnemo) {
1811		case IA64_INST_NOP:
#	Line 1700 | Line 1842 | static bool ia64_emulate_instruction(ia6
1842		case IA64_INST_ZXT4:
1843		src1 = inst->operands[1].value;
1844		switch (inst->mnemo) {
1845	<	case IA64_INST_SXT1: dst = (signed long)(signed char)src1;              break;
1846	<	case IA64_INST_SXT2: dst = (signed long)(signed short)src1;             break;
1847	<	case IA64_INST_SXT4: dst = (signed long)(signed int)src1;               break;
1848	<	case IA64_INST_ZXT1: dst = (unsigned char)src1;                                 break;
1849	<	case IA64_INST_ZXT2: dst = (unsigned short)src1;                                break;
1850	<	case IA64_INST_ZXT4: dst = (unsigned int)src1;                                  break;
1845	>	case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1;               break;
1846	>	case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1;              break;
1847	>	case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1;              break;
1848	>	case IA64_INST_ZXT1: dst = (uint8_t)src1;                               break;
1849	>	case IA64_INST_ZXT2: dst = (uint16_t)src1;                              break;
1850	>	case IA64_INST_ZXT4: dst = (uint32_t)src1;                              break;
1851		}
1852		inst->operands[0].commit = true;
1853		inst->operands[0].value  = dst;
#	Line 1728 | Line 1870 | static bool ia64_emulate_instruction(ia6
1870		dst = 0;
1871		else {
1872		switch (inst->mnemo) {
1873	<	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((unsigned char *)src1);  break;
1874	<	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((unsigned short *)src1); break;
1875	<	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((unsigned int *)src1);   break;
1876	<	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((unsigned long *)src1);  break;
1873	>	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((uint8_t *)src1);        break;
1874	>	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((uint16_t *)src1);       break;
1875	>	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((uint32_t *)src1);       break;
1876	>	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((uint64_t *)src1);       break;
1877		}
1878		}
1879		inst->operands[0].commit = true;
#	Line 1756 | Line 1898 | static bool ia64_emulate_instruction(ia6
1898		src1 = inst->operands[1].value;
1899		if (!inst->no_memory) {
1900		switch (inst->mnemo) {
1901	<	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((unsigned char *)dst) = src1;  break;
1902	<	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((unsigned short *)dst) = src1; break;
1903	<	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((unsigned int *)dst) = src1;   break;
1904	<	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((unsigned long *)dst) = src1;  break;
1901	>	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((uint8_t *)dst) = src1;        break;
1902	>	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((uint16_t *)dst) = src1;       break;
1903	>	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((uint32_t *)dst) = src1;       break;
1904	>	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((uint64_t *)dst) = src1;       break;
1905		}
1906		}
1907		inst->operands[0].value  = dst2;
#	Line 1775 | Line 1917 | static bool ia64_emulate_instruction(ia6
1917		continue;
1918		if (op.index == -1)
1919		return false; // XXX: internal error
1920	<	IA64_SET_GR(op.index, op.value);
1779	<	IA64_SET_NAT(op.index, op.nat);
1920	>	IA64_SET_GR(op.index, op.value, op.nat);
1921		}
1922		return true;
1923		}
1924
1925	<	static bool ia64_emulate_instruction(unsigned long raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1925	>	static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1926		{
1927		ia64_instruction_t inst;
1928		memset(&inst, 0, sizeof(inst));
#	Line 1793 | Line 1934 | static bool ia64_emulate_instruction(uns
1934
1935		static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1936		{
1937	<	unsigned long ip = IA64_GET_IP();
1937	>	uint64_t ip = IA64_GET_IP();
1938		#if DEBUG
1939	<	printf("IP: 0x%016lx\n", ip);
1939	>	printf("IP: 0x%016llx\n", ip);
1940		#if 0
1941		printf(" Template 0x%02x\n", ia64_get_template(ip));
1942		ia64_get_instruction(ip, 0);
#	Line 1913 | Line 2054 | static bool ia64_skip_instruction(IA64_C
2054
2055		#if IA64_CAN_PATCH_IP_SLOT
2056		if ((slot = ip & 3) < 2)
2057	<	IA64_SET_IP((ip & ~3ul) + (slot + 1));
2057	>	IA64_SET_IP((ip & ~3ull) + (slot + 1));
2058		else
2059		#endif
2060	<	IA64_SET_IP((ip & ~3ul) + 16);
2060	>	IA64_SET_IP((ip & ~3ull) + 16);
2061		#if DEBUG
2062	<	printf("IP: 0x%016lx\n", IA64_GET_IP());
2062	>	printf("IP: 0x%016llx\n", IA64_GET_IP());
2063		#endif
2064		return true;
2065		}
#	Line 2477 | Line 2618 | static void mach_set_thread_state(sigseg
2618		sigsegv_address_t sigsegv_get_fault_address(sigsegv_info_t *SIP)
2619		{
2620		#ifdef HAVE_MACH_EXCEPTIONS
2621	+	#ifdef EMULATED_PPC
2622		static int use_fast_path = -1;
2623		if (use_fast_path != 1 && !SIP->has_exc_state) {
2624		mach_get_exception_state(SIP);
#	Line 2496 | Line 2638 | sigsegv_address_t sigsegv_get_fault_addr
2638		SIP->addr = addr;
2639		}
2640		#endif
2641	+	#endif
2642		return SIP->addr;
2643		}
2644
#	Line 2504 | Line 2647 | sigsegv_address_t sigsegv_get_fault_addr
2647		sigsegv_address_t sigsegv_get_fault_instruction_address(sigsegv_info_t *SIP)
2648		{
2649		#ifdef HAVE_MACH_EXCEPTIONS
2650	+	#ifdef EMULATED_PPC
2651		if (!SIP->has_thr_state) {
2652		mach_get_thread_state(SIP);
2653
2654		SIP->pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
2655		}
2656		#endif
2657	+	#endif
2658		return SIP->pc;
2659		}
2660
#	Line 2588 | Line 2733 | static inline kern_return_t
2733		forward_exception(mach_port_t thread_port,
2734		mach_port_t task_port,
2735		exception_type_t exception_type,
2736	<	exception_data_t exception_data,
2736	>	mach_exception_data_t exception_data,
2737		mach_msg_type_number_t data_count,
2738		ExceptionPorts *oldExceptionPorts)
2739		{
#	Line 2635 | Line 2780 | forward_exception(mach_port_t thread_por
2780		switch (behavior) {
2781		case EXCEPTION_DEFAULT:
2782		// fprintf(stderr, "forwarding to exception_raise\n");
2783	<	kret = exception_raise(port, thread_port, task_port, exception_type,
2784	<	exception_data, data_count);
2785	<	MACH_CHECK_ERROR (exception_raise, kret);
2783	>	kret = mach_exception_raise(port, thread_port, task_port, exception_type,
2784	>	exception_data, data_count);
2785	>	MACH_CHECK_ERROR (mach_exception_raise, kret);
2786		break;
2787		case EXCEPTION_STATE:
2788		// fprintf(stderr, "forwarding to exception_raise_state\n");
2789	<	kret = exception_raise_state(port, exception_type, exception_data,
2790	<	data_count, &flavor,
2791	<	(natural_t *)&thread_state, thread_state_count,
2792	<	(natural_t *)&thread_state, &thread_state_count);
2793	<	MACH_CHECK_ERROR (exception_raise_state, kret);
2789	>	kret = mach_exception_raise_state(port, exception_type, exception_data,
2790	>	data_count, &flavor,
2791	>	(natural_t *)&thread_state, thread_state_count,
2792	>	(natural_t *)&thread_state, &thread_state_count);
2793	>	MACH_CHECK_ERROR (mach_exception_raise_state, kret);
2794		break;
2795		case EXCEPTION_STATE_IDENTITY:
2796		// fprintf(stderr, "forwarding to exception_raise_state_identity\n");
2797	<	kret = exception_raise_state_identity(port, thread_port, task_port,
2798	<	exception_type, exception_data,
2799	<	data_count, &flavor,
2800	<	(natural_t *)&thread_state, thread_state_count,
2801	<	(natural_t *)&thread_state, &thread_state_count);
2802	<	MACH_CHECK_ERROR (exception_raise_state_identity, kret);
2797	>	kret = mach_exception_raise_state_identity(port, thread_port, task_port,
2798	>	exception_type, exception_data,
2799	>	data_count, &flavor,
2800	>	(natural_t *)&thread_state, thread_state_count,
2801	>	(natural_t *)&thread_state, &thread_state_count);
2802	>	MACH_CHECK_ERROR (mach_exception_raise_state_identity, kret);
2803		break;
2804		default:
2805		fprintf(stderr, "forward_exception got unknown behavior\n");
#	Line 2691 | Line 2836 | forward_exception(mach_port_t thread_por
2836		* linkage because that is what exc_server expects.
2837		*/
2838		kern_return_t
2839	<	catch_exception_raise(mach_port_t exception_port,
2840	<	mach_port_t thread,
2841	<	mach_port_t task,
2842	<	exception_type_t exception,
2843	<	exception_data_t code,
2844	<	mach_msg_type_number_t code_count)
2839	>	catch_mach_exception_raise(mach_port_t exception_port,
2840	>	mach_port_t thread,
2841	>	mach_port_t task,
2842	>	exception_type_t exception,
2843	>	mach_exception_data_t code,
2844	>	mach_msg_type_number_t code_count)
2845		{
2846		kern_return_t krc;
2847
#	Line 2717 | Line 2862 | catch_exception_raise(mach_port_t except
2862
2863		return krc;
2864		}
2865	+
2866	+	/* XXX: borrowed from launchd and gdb */
2867	+	kern_return_t
2868	+	catch_mach_exception_raise_state(mach_port_t exception_port,
2869	+	exception_type_t exception,
2870	+	mach_exception_data_t code,
2871	+	mach_msg_type_number_t code_count,
2872	+	int *flavor,
2873	+	thread_state_t old_state,
2874	+	mach_msg_type_number_t old_state_count,
2875	+	thread_state_t new_state,
2876	+	mach_msg_type_number_t *new_state_count)
2877	+	{
2878	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2879	+	*new_state_count = old_state_count;
2880	+	return KERN_SUCCESS;
2881	+	}
2882	+
2883	+	/* XXX: borrowed from launchd and gdb */
2884	+	kern_return_t
2885	+	catch_mach_exception_raise_state_identity(mach_port_t exception_port,
2886	+	mach_port_t thread_port,
2887	+	mach_port_t task_port,
2888	+	exception_type_t exception,
2889	+	mach_exception_data_t code,
2890	+	mach_msg_type_number_t code_count,
2891	+	int *flavor,
2892	+	thread_state_t old_state,
2893	+	mach_msg_type_number_t old_state_count,
2894	+	thread_state_t new_state,
2895	+	mach_msg_type_number_t *new_state_count)
2896	+	{
2897	+	kern_return_t kret;
2898	+
2899	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2900	+	*new_state_count = old_state_count;
2901	+
2902	+	kret = mach_port_deallocate(mach_task_self(), task_port);
2903	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2904	+	kret = mach_port_deallocate(mach_task_self(), thread_port);
2905	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2906	+
2907	+	return KERN_SUCCESS;
2908	+	}
2909		#endif
2910
2911		#ifdef HAVE_SIGSEGV_RECOVERY
#	Line 2841 | Line 3030 | static bool sigsegv_do_install_handler(s
3030		// addressing modes) used in PPC instructions, you will need the
3031		// GPR state anyway.
3032		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
3033	<	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
3033	>	EXCEPTION_DEFAULT | MACH_EXCEPTION_CODES, SIGSEGV_THREAD_STATE_FLAVOR);
3034		if (krc != KERN_SUCCESS) {
3035		mach_error("thread_set_exception_ports", krc);
3036		return false;
#	Line 2869 | Line 3058 | static LONG WINAPI main_exception_filter
3058		{
3059		if (sigsegv_fault_handler != NULL
3060		&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
3061	<	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
3061	>	&& ExceptionInfo->ExceptionRecord->NumberParameters >= 2
3062		&& handle_badaccess(ExceptionInfo))
3063		return EXCEPTION_CONTINUE_EXECUTION;
3064

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