[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.79 by gbeauche, 2008-01-12T23:01:40Z vs.
Revision 1.83 by gbeauche, 2008-01-20T00:39:51Z

#	Line 243 \| Line 243 \| static void powerpc_decode_instruction(i
243		// Generic extended signal handler
244		#if defined(__FreeBSD__)
245		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
246	+	#elif defined(__hpux)
247	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV) FAULT_HANDLER(SIGBUS)
248		#else
249		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
250		#endif
#	Line 349 \| Line 351 \| static void powerpc_decode_instruction(i
351		#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
352		#endif
353		#endif
354	+	#if (defined(__hpux) \|\| defined(__hpux__))
355	+	#if (defined(__hppa) \|\| defined(__hppa__))
356	+	#define SIGSEGV_CONTEXT_REGS (&((ucontext_t *)scp)->uc_mcontext)
357	+	#define SIGSEGV_FAULT_INSTRUCTION_32 (SIGSEGV_CONTEXT_REGS->ss_narrow.ss_pcoq_head & ~3ul)
358	+	#define SIGSEGV_FAULT_INSTRUCTION_64 (SIGSEGV_CONTEXT_REGS->ss_wide.ss_64.ss_pcoq_head & ~3ull)
359	+	#if defined(__LP64__)
360	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_FAULT_INSTRUCTION_64
361	+	#else
362	+	#define SIGSEGV_FAULT_INSTRUCTION ((SIGSEGV_CONTEXT_REGS->ss_flags & SS_WIDEREGS) ? \
363	+	(uint32_t)SIGSEGV_FAULT_INSTRUCTION_64 : \
364	+	SIGSEGV_FAULT_INSTRUCTION_32)
365	+	#endif
366	+	#endif
367	+	#if (defined(__ia64) \|\| defined(__ia64__))
368	+	#include <sys/ucontext.h>
369	+	#define SIGSEGV_CONTEXT_REGS ((ucontext_t *)scp)
370	+	#define SIGSEGV_FAULT_INSTRUCTION get_fault_instruction(SIGSEGV_CONTEXT_REGS)
371	+	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
372	+	#define SIGSEGV_SKIP_INSTRUCTION ia64_skip_instruction
373	+
374	+	#include <sys/uc_access.h>
375	+	static inline sigsegv_address_t get_fault_instruction(const ucontext_t *ucp)
376	+	{
377	+	uint64_t ip;
378	+	if (__uc_get_ip(ucp, &ip) != 0)
379	+	return SIGSEGV_INVALID_ADDRESS;
380	+	return (sigsegv_address_t)(ip & ~3ULL);
381	+	}
382	+	#endif
383	+	#endif
384		#endif
385
386		#if HAVE_SIGCONTEXT_SUBTERFUGE
#	Line 627 \| Line 659 \| if (ret != KERN_SUCCESS) { \
659		}
660
661		#ifdef __ppc__
662	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE
663	+	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
664	+	#endif
665		#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state_t
666		#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE
667		#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE_COUNT
668	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.dar
668	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar)
669		#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t
670		#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE
671		#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT
672	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.srr0
672	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0)
673		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
674	<	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.srr0, (unsigned long )&SIP->thr_state.r0
674	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(r0)
675		#endif
676		#ifdef __ppc64__
677	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64
678	+	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
679	+	#endif
680		#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state64_t
681		#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE64
682		#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE64_COUNT
683	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.dar
683	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(dar)
684		#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state64_t
685		#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE64
686		#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE64_COUNT
687	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.srr0
687	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(srr0)
688		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
689	<	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.srr0, (unsigned long )&SIP->thr_state.r0
689	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long )&SIP->thr_state.MACH_FIELD_NAME(r0)
690		#endif
691		#ifdef __i386__
692	<	#define SIGSEGV_EXCEPTION_STATE_TYPE struct i386_exception_state
692	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32
693	>	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
694	>	#endif
695	>	#define SIGSEGV_EXCEPTION_STATE_TYPE i386_exception_state_t
696		#define SIGSEGV_EXCEPTION_STATE_FLAVOR i386_EXCEPTION_STATE
697		#define SIGSEGV_EXCEPTION_STATE_COUNT i386_EXCEPTION_STATE_COUNT
698	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.faultvaddr
699	<	#define SIGSEGV_THREAD_STATE_TYPE struct i386_thread_state
698	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
699	>	#define SIGSEGV_THREAD_STATE_TYPE i386_thread_state_t
700		#define SIGSEGV_THREAD_STATE_FLAVOR i386_THREAD_STATE
701		#define SIGSEGV_THREAD_STATE_COUNT i386_THREAD_STATE_COUNT
702	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.eip
702	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(eip)
703		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
704	<	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.eax) / EAX is the first GPR we consider */
704	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.MACH_FIELD_NAME(eax)) / EAX is the first GPR we consider */
705		#endif
706		#ifdef __x86_64__
707	<	#define SIGSEGV_EXCEPTION_STATE_TYPE struct x86_exception_state64
707	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64
708	>	#define MACH_FIELD_NAME(X) __CONCAT(__,X)
709	>	#endif
710	>	#define SIGSEGV_EXCEPTION_STATE_TYPE x86_exception_state64_t
711		#define SIGSEGV_EXCEPTION_STATE_FLAVOR x86_EXCEPTION_STATE64
712		#define SIGSEGV_EXCEPTION_STATE_COUNT x86_EXCEPTION_STATE64_COUNT
713	<	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.faultvaddr
714	<	#define SIGSEGV_THREAD_STATE_TYPE struct x86_thread_state64
713	>	#define SIGSEGV_FAULT_ADDRESS SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
714	>	#define SIGSEGV_THREAD_STATE_TYPE x86_thread_state64_t
715		#define SIGSEGV_THREAD_STATE_FLAVOR x86_THREAD_STATE64
716		#define SIGSEGV_THREAD_STATE_COUNT x86_THREAD_STATE64_COUNT
717	<	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.rip
717	>	#define SIGSEGV_FAULT_INSTRUCTION SIP->thr_state.MACH_FIELD_NAME(rip)
718		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
719	<	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.rax) / RAX is the first GPR we consider */
719	>	#define SIGSEGV_REGISTER_FILE ((SIGSEGV_REGISTER_TYPE )&SIP->thr_state.MACH_FIELD_NAME(rax)) / RAX is the first GPR we consider */
720		#endif
721		#define SIGSEGV_FAULT_ADDRESS_FAST code[1]
722		#define SIGSEGV_FAULT_INSTRUCTION_FAST SIGSEGV_INVALID_ADDRESS
723		#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code
724		#define SIGSEGV_FAULT_HANDLER_ARGS thread, code
725
726	+	#ifndef MACH_FIELD_NAME
727	+	#define MACH_FIELD_NAME(X) X
728	+	#endif
729	+
730		// Since there can only be one exception thread running at any time
731		// this is not a problem.
732		#define MSG_SIZE 512
#	Line 1209 \| Line 1257 \| static bool ix86_skip_instruction(SIGSEG
1257		#endif
1258
1259		// Decode and skip IA-64 instruction
1260	<	#if defined(__ia64__)
1260	>	#if defined(__ia64) \|\| defined(__ia64__)
1261	>	typedef uint64_t ia64_bundle_t[2];
1262		#if defined(__linux__)
1263		// We can directly patch the slot number
1264	<	#define IA64_CAN_PATCH_IP_SLOT 1
1264	>	#define IA64_CAN_PATCH_IP_SLOT 1
1265		// Helper macros to access the machine context
1266		#define IA64_CONTEXT_TYPE struct sigcontext *
1267		#define IA64_CONTEXT scp
#	Line 1220 \| Line 1269 \| static bool ix86_skip_instruction(SIGSEG
1269		#define IA64_SET_IP(V) (IA64_CONTEXT->sc_ip = (V))
1270		#define IA64_GET_PR(P) ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1271		#define IA64_GET_NAT(I) ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1223	–	#define IA64_SET_NAT(I,V) (IA64_CONTEXT->sc_nat= (IA64_CONTEXT->sc_nat & ~(1ul << (I))) \| (((unsigned long)!!(V)) << (I)))
1272		#define IA64_GET_GR(R) (IA64_CONTEXT->sc_gr[(R)])
1273	<	#define IA64_SET_GR(R,V) (IA64_CONTEXT->sc_gr[(R)] = (V))
1273	>	#define _IA64_SET_GR(R,V) (IA64_CONTEXT->sc_gr[(R)] = (V))
1274	>	#define _IA64_SET_NAT(I,V) (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) \| (((uint64_t)!!(V)) << (I)))
1275	>	#define IA64_SET_GR(R,V,N) (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N))
1276	>
1277	>	// Load bundle (in little-endian)
1278	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1279	>	{
1280	>	uint64_t ip = (uint64_t )(raw_ip & ~3ull);
1281	>	bundle[0] = ip[0];
1282	>	bundle[1] = ip[1];
1283	>	}
1284	>	#endif
1285	>	#if defined(__hpux) \|\| defined(__hpux__)
1286	>	// We can directly patch the slot number
1287	>	#define IA64_CAN_PATCH_IP_SLOT 1
1288	>	// Helper macros to access the machine context
1289	>	#define IA64_CONTEXT_TYPE ucontext_t *
1290	>	#define IA64_CONTEXT ucp
1291	>	#define IA64_GET_IP() ia64_get_ip(IA64_CONTEXT)
1292	>	#define IA64_SET_IP(V) ia64_set_ip(IA64_CONTEXT, V)
1293	>	#define IA64_GET_PR(P) ia64_get_pr(IA64_CONTEXT, P)
1294	>	#define IA64_GET_NAT(I) ia64_get_nat(IA64_CONTEXT, I)
1295	>	#define IA64_GET_GR(R) ia64_get_gr(IA64_CONTEXT, R)
1296	>	#define IA64_SET_GR(R,V,N) ia64_set_gr(IA64_CONTEXT, R, V, N)
1297	>	#define UC_ACCESS(FUNC,ARGS) do { if (__uc_##FUNC ARGS != 0) abort(); } while (0)
1298	>
1299	>	static inline uint64_t ia64_get_ip(IA64_CONTEXT_TYPE IA64_CONTEXT)
1300	>	{ uint64_t v; UC_ACCESS(get_ip,(IA64_CONTEXT, &v)); return v; }
1301	>	static inline void ia64_set_ip(IA64_CONTEXT_TYPE IA64_CONTEXT, uint64_t v)
1302	>	{ UC_ACCESS(set_ip,(IA64_CONTEXT, v)); }
1303	>	static inline unsigned int ia64_get_pr(IA64_CONTEXT_TYPE IA64_CONTEXT, int pr)
1304	>	{ uint64_t v; UC_ACCESS(get_prs,(IA64_CONTEXT, &v)); return (v >> pr) & 1; }
1305	>	static inline unsigned int ia64_get_nat(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1306	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return (nat >> r) & 1; }
1307	>	static inline uint64_t ia64_get_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1308	>	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return v; }
1309	>
1310	>	static void ia64_set_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r, uint64_t v, unsigned int nat)
1311	>	{
1312	>	if (r == 0)
1313	>	return;
1314	>	if (r > 0 && r < 32)
1315	>	UC_ACCESS(set_grs,(IA64_CONTEXT, r, 1, &v, (!!nat) << r));
1316	>	else {
1317	>	uint64_t bsp, bspstore;
1318	>	UC_ACCESS(get_ar_bsp,(IA64_CONTEXT, &bsp));
1319	>	UC_ACCESS(get_ar_bspstore,(IA64_CONTEXT, &bspstore));
1320	>	abort(); /* XXX: use libunwind, this is not fun... */
1321	>	}
1322	>	}
1323	>
1324	>	// Byte-swapping
1325	>	#if defined(__GNUC__)
1326	>	#define BSWAP64(V) ({ uint64_t r; __asm__ __volatile__("mux1 %0=%1,@rev;;" : "=r" (r) : "r" (V)); r; })
1327	>	#elif defined (__HP_aCC)
1328	>	#define BSWAP64(V) _Asm_mux1(_MBTYPE_REV, V)
1329	>	#else
1330	>	#error "Define byte-swap instruction"
1331	>	#endif
1332	>
1333	>	// Load bundle (in little-endian)
1334	>	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1335	>	{
1336	>	uint64_t ip = (uint64_t )(raw_ip & ~3ull);
1337	>	bundle[0] = BSWAP64(ip[0]);
1338	>	bundle[1] = BSWAP64(ip[1]);
1339	>	}
1340		#endif
1341
1342		// Instruction operations
#	Line 1264 \| Line 1378 \| const int IA64_N_OPERANDS = 4;
1378
1379		// Decoded operand type
1380		struct ia64_operand_t {
1381	<	unsigned char commit; // commit result of operation to register file?
1382	<	unsigned char valid; // XXX: not really used, can be removed (debug)
1383	<	signed char index; // index of GPR, or -1 if immediate value
1384	<	unsigned char nat; // NaT state before operation
1385	<	unsigned long value; // register contents or immediate value
1381	>	uint8_t commit; // commit result of operation to register file?
1382	>	uint8_t valid; // XXX: not really used, can be removed (debug)
1383	>	int8_t index; // index of GPR, or -1 if immediate value
1384	>	uint8_t nat; // NaT state before operation
1385	>	uint64_t value; // register contents or immediate value
1386		};
1387
1388		// Decoded instruction type
1389		struct ia64_instruction_t {
1390	<	unsigned char mnemo; // operation to perform
1391	<	unsigned char pred; // predicate register to check
1392	<	unsigned char no_memory; // used to emulated main fault instruction
1393	<	unsigned long inst; // the raw instruction bits (41-bit wide)
1390	>	uint8_t mnemo; // operation to perform
1391	>	uint8_t pred; // predicate register to check
1392	>	uint8_t no_memory; // used to emulated main fault instruction
1393	>	uint64_t inst; // the raw instruction bits (41-bit wide)
1394		ia64_operand_t operands[IA64_N_OPERANDS];
1395		};
1396
1397		// Get immediate sign-bit
1398	<	static inline int ia64_inst_get_sbit(unsigned long inst)
1398	>	static inline int ia64_inst_get_sbit(uint64_t inst)
1399		{
1400		return (inst >> 36) & 1;
1401		}
1402
1403		// Get 8-bit immediate value (A3, A8, I27, M30)
1404	<	static inline unsigned long ia64_inst_get_imm8(unsigned long inst)
1404	>	static inline uint64_t ia64_inst_get_imm8(uint64_t inst)
1405		{
1406	<	unsigned long value = (inst >> 13) & 0x7ful;
1406	>	uint64_t value = (inst >> 13) & 0x7full;
1407		if (ia64_inst_get_sbit(inst))
1408	<	value \|= ~0x7ful;
1408	>	value \|= ~0x7full;
1409		return value;
1410		}
1411
1412		// Get 9-bit immediate value (M3)
1413	<	static inline unsigned long ia64_inst_get_imm9b(unsigned long inst)
1413	>	static inline uint64_t ia64_inst_get_imm9b(uint64_t inst)
1414		{
1415	<	unsigned long value = (((inst >> 27) & 1) << 7) \| ((inst >> 13) & 0x7f);
1415	>	uint64_t value = (((inst >> 27) & 1) << 7) \| ((inst >> 13) & 0x7f);
1416		if (ia64_inst_get_sbit(inst))
1417	<	value \|= ~0xfful;
1417	>	value \|= ~0xffull;
1418		return value;
1419		}
1420
1421		// Get 9-bit immediate value (M5)
1422	<	static inline unsigned long ia64_inst_get_imm9a(unsigned long inst)
1422	>	static inline uint64_t ia64_inst_get_imm9a(uint64_t inst)
1423		{
1424	<	unsigned long value = (((inst >> 27) & 1) << 7) \| ((inst >> 6) & 0x7f);
1424	>	uint64_t value = (((inst >> 27) & 1) << 7) \| ((inst >> 6) & 0x7f);
1425		if (ia64_inst_get_sbit(inst))
1426	<	value \|= ~0xfful;
1426	>	value \|= ~0xffull;
1427		return value;
1428		}
1429
1430		// Get 14-bit immediate value (A4)
1431	<	static inline unsigned long ia64_inst_get_imm14(unsigned long inst)
1431	>	static inline uint64_t ia64_inst_get_imm14(uint64_t inst)
1432		{
1433	<	unsigned long value = (((inst >> 27) & 0x3f) << 7) \| (inst & 0x7f);
1433	>	uint64_t value = (((inst >> 27) & 0x3f) << 7) \| (inst & 0x7f);
1434		if (ia64_inst_get_sbit(inst))
1435	<	value \|= ~0x1fful;
1435	>	value \|= ~0x1ffull;
1436		return value;
1437		}
1438
1439		// Get 22-bit immediate value (A5)
1440	<	static inline unsigned long ia64_inst_get_imm22(unsigned long inst)
1440	>	static inline uint64_t ia64_inst_get_imm22(uint64_t inst)
1441		{
1442	<	unsigned long value = ((((inst >> 22) & 0x1f) << 16) \|
1443	<	(((inst >> 27) & 0x1ff) << 7) \|
1444	<	(inst & 0x7f));
1442	>	uint64_t value = ((((inst >> 22) & 0x1f) << 16) \|
1443	>	(((inst >> 27) & 0x1ff) << 7) \|
1444	>	(inst & 0x7f));
1445		if (ia64_inst_get_sbit(inst))
1446	<	value \|= ~0x1ffffful;
1446	>	value \|= ~0x1fffffull;
1447		return value;
1448		}
1449
1450		// Get 21-bit immediate value (I19)
1451	<	static inline unsigned long ia64_inst_get_imm21(unsigned long inst)
1451	>	static inline uint64_t ia64_inst_get_imm21(uint64_t inst)
1452		{
1453		return (((inst >> 36) & 1) << 20) \| ((inst >> 6) & 0xfffff);
1454		}
1455
1456		// Get 2-bit count value (A2)
1457	<	static inline int ia64_inst_get_count2(unsigned long inst)
1457	>	static inline int ia64_inst_get_count2(uint64_t inst)
1458		{
1459		return (inst >> 27) & 0x3;
1460		}
1461
1462		// Get bundle template
1463	<	static inline unsigned int ia64_get_template(unsigned long raw_ip)
1463	>	static inline unsigned int ia64_get_template(uint64_t ip)
1464		{
1465	<	unsigned long ip = (unsigned long )(raw_ip & ~3ul);
1466	<	return ip[0] & 0x1f;
1465	>	ia64_bundle_t bundle;
1466	>	ia64_load_bundle(bundle, ip);
1467	>	return bundle[0] & 0x1f;
1468		}
1469
1470		// Get specified instruction in bundle
1471	<	static unsigned long ia64_get_instruction(unsigned long raw_ip, int slot)
1471	>	static uint64_t ia64_get_instruction(uint64_t ip, int slot)
1472		{
1473	<	unsigned long inst;
1474	<	unsigned long ip = (unsigned long )(raw_ip & ~3ul);
1473	>	uint64_t inst;
1474	>	ia64_bundle_t bundle;
1475	>	ia64_load_bundle(bundle, ip);
1476		#if DEBUG
1477	<	printf("Bundle: %016lx%016lx\n", ip[1], ip[0]);
1477	>	printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]);
1478		#endif
1479
1480		switch (slot) {
1481		case 0:
1482	<	inst = (ip[0] >> 5) & 0x1fffffffffful;
1482	>	inst = (bundle[0] >> 5) & 0x1ffffffffffull;
1483		break;
1484		case 1:
1485	<	inst = ((ip[1] & 0x7ffffful) << 18) \| ((ip[0] >> 46) & 0x3fffful);
1485	>	inst = ((bundle[1] & 0x7fffffull) << 18) \| ((bundle[0] >> 46) & 0x3ffffull);
1486		break;
1487		case 2:
1488	<	inst = (ip[1] >> 23) & 0x1fffffffffful;
1488	>	inst = (bundle[1] >> 23) & 0x1ffffffffffull;
1489		break;
1490		case 3:
1491		fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
#	Line 1378 \| Line 1494 \| static unsigned long ia64_get_instructio
1494		}
1495
1496		#if DEBUG
1497	<	printf(" Instruction %d: 0x%016lx\n", slot, inst);
1497	>	printf(" Instruction %d: 0x%016llx\n", slot, inst);
1498		#endif
1499		return inst;
1500		}
#	Line 1662 \| Line 1778 \| static bool ia64_emulate_instruction(ia6
1778		if (inst->pred && !IA64_GET_PR(inst->pred))
1779		return true;
1780
1781	<	unsigned char nat, nat2;
1782	<	unsigned long dst, dst2, src1, src2, src3;
1781	>	uint8_t nat, nat2;
1782	>	uint64_t dst, dst2, src1, src2, src3;
1783
1784		switch (inst->mnemo) {
1785		case IA64_INST_NOP:
#	Line 1700 \| Line 1816 \| static bool ia64_emulate_instruction(ia6
1816		case IA64_INST_ZXT4:
1817		src1 = inst->operands[1].value;
1818		switch (inst->mnemo) {
1819	<	case IA64_INST_SXT1: dst = (signed long)(signed char)src1; break;
1820	<	case IA64_INST_SXT2: dst = (signed long)(signed short)src1; break;
1821	<	case IA64_INST_SXT4: dst = (signed long)(signed int)src1; break;
1822	<	case IA64_INST_ZXT1: dst = (unsigned char)src1; break;
1823	<	case IA64_INST_ZXT2: dst = (unsigned short)src1; break;
1824	<	case IA64_INST_ZXT4: dst = (unsigned int)src1; break;
1819	>	case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1; break;
1820	>	case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1; break;
1821	>	case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1; break;
1822	>	case IA64_INST_ZXT1: dst = (uint8_t)src1; break;
1823	>	case IA64_INST_ZXT2: dst = (uint16_t)src1; break;
1824	>	case IA64_INST_ZXT4: dst = (uint32_t)src1; break;
1825		}
1826		inst->operands[0].commit = true;
1827		inst->operands[0].value = dst;
#	Line 1728 \| Line 1844 \| static bool ia64_emulate_instruction(ia6
1844		dst = 0;
1845		else {
1846		switch (inst->mnemo) {
1847	<	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = ((unsigned char )src1); break;
1848	<	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = ((unsigned short )src1); break;
1849	<	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = ((unsigned int )src1); break;
1850	<	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = ((unsigned long )src1); break;
1847	>	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = ((uint8_t )src1); break;
1848	>	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = ((uint16_t )src1); break;
1849	>	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = ((uint32_t )src1); break;
1850	>	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = ((uint64_t )src1); break;
1851		}
1852		}
1853		inst->operands[0].commit = true;
#	Line 1756 \| Line 1872 \| static bool ia64_emulate_instruction(ia6
1872		src1 = inst->operands[1].value;
1873		if (!inst->no_memory) {
1874		switch (inst->mnemo) {
1875	<	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: ((unsigned char )dst) = src1; break;
1876	<	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: ((unsigned short )dst) = src1; break;
1877	<	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: ((unsigned int )dst) = src1; break;
1878	<	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: ((unsigned long )dst) = src1; break;
1875	>	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: ((uint8_t )dst) = src1; break;
1876	>	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: ((uint16_t )dst) = src1; break;
1877	>	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: ((uint32_t )dst) = src1; break;
1878	>	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: ((uint64_t )dst) = src1; break;
1879		}
1880		}
1881		inst->operands[0].value = dst2;
#	Line 1775 \| Line 1891 \| static bool ia64_emulate_instruction(ia6
1891		continue;
1892		if (op.index == -1)
1893		return false; // XXX: internal error
1894	<	IA64_SET_GR(op.index, op.value);
1779	<	IA64_SET_NAT(op.index, op.nat);
1894	>	IA64_SET_GR(op.index, op.value, op.nat);
1895		}
1896		return true;
1897		}
1898
1899	<	static bool ia64_emulate_instruction(unsigned long raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1899	>	static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1900		{
1901		ia64_instruction_t inst;
1902		memset(&inst, 0, sizeof(inst));
#	Line 1793 \| Line 1908 \| static bool ia64_emulate_instruction(uns
1908
1909		static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1910		{
1911	<	unsigned long ip = IA64_GET_IP();
1911	>	uint64_t ip = IA64_GET_IP();
1912		#if DEBUG
1913	<	printf("IP: 0x%016lx\n", ip);
1913	>	printf("IP: 0x%016llx\n", ip);
1914		#if 0
1915		printf(" Template 0x%02x\n", ia64_get_template(ip));
1916		ia64_get_instruction(ip, 0);
#	Line 1913 \| Line 2028 \| static bool ia64_skip_instruction(IA64_C
2028
2029		#if IA64_CAN_PATCH_IP_SLOT
2030		if ((slot = ip & 3) < 2)
2031	<	IA64_SET_IP((ip & ~3ul) + (slot + 1));
2031	>	IA64_SET_IP((ip & ~3ull) + (slot + 1));
2032		else
2033		#endif
2034	<	IA64_SET_IP((ip & ~3ul) + 16);
2034	>	IA64_SET_IP((ip & ~3ull) + 16);
2035		#if DEBUG
2036	<	printf("IP: 0x%016lx\n", IA64_GET_IP());
2036	>	printf("IP: 0x%016llx\n", IA64_GET_IP());
2037		#endif
2038		return true;
2039		}

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.79 by gbeauche, 2008-01-12T23:01:40Z vs. Revision 1.83 by gbeauche, 2008-01-20T00:39:51Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.79 by gbeauche, 2008-01-12T23:01:40Z vs.
Revision 1.83 by gbeauche, 2008-01-20T00:39:51Z