ViewVC Help

View File | Revision Log | Show Annotations | Revision Graph | Root Listing

root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.62 by gbeauche, 2006-03-30T22:45:49Z vs.
Revision 1.85 by gbeauche, 2008-01-20T22:24:53Z

#	Line 10 | Line 10
10		*    tjw@omnigroup.com Sun, 4 Jun 2000
11		*    www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	*  Basilisk II (C) 1997-2005 Christian Bauer
13	>	*  Basilisk II (C) 1997-2008 Christian Bauer
14		*
15		*  This program is free software; you can redistribute it and/or modify
16		*  it under the terms of the GNU General Public License as published by
#	Line 49 | Line 49 | using std::list;
49		#define RETSIGTYPE void
50		#endif
51
52	+	// Size of an unsigned integer large enough to hold all bits of a pointer
53	+	// NOTE: this can be different than SIGSEGV_REGISTER_TYPE. In
54	+	// particular, on ILP32 systems with a 64-bit kernel (HP-UX/ia64?)
55	+	#ifdef HAVE_WIN32_VM
56	+	// Windows is either ILP32 or LLP64
57	+	typedef UINT_PTR sigsegv_uintptr_t;
58	+	#else
59	+	// Other systems are sane enough to follow ILP32 or LP64 models
60	+	typedef unsigned long sigsegv_uintptr_t;
61	+	#endif
62	+
63		// Type of the system signal handler
64		typedef RETSIGTYPE (*signal_handler)(int);
65
#	Line 66 | Line 77 | static bool sigsegv_do_install_handler(i
77		*  Instruction decoding aids
78		*/
79
80	+	// Transfer type
81	+	enum transfer_type_t {
82	+	SIGSEGV_TRANSFER_UNKNOWN        = 0,
83	+	SIGSEGV_TRANSFER_LOAD           = 1,
84	+	SIGSEGV_TRANSFER_STORE          = 2
85	+	};
86	+
87		// Transfer size
88		enum transfer_size_t {
89		SIZE_UNKNOWN,
90		SIZE_BYTE,
91		SIZE_WORD, // 2 bytes
92		SIZE_LONG, // 4 bytes
93	<	SIZE_QUAD, // 8 bytes
93	>	SIZE_QUAD  // 8 bytes
94		};
95
96	<	// Transfer type
79	<	typedef sigsegv_transfer_type_t transfer_type_t;
80	<
81	<	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__))
96	>	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__))
97		// Addressing mode
98		enum addressing_mode_t {
99		MODE_UNKNOWN,
#	Line 228 | Line 243 | static void powerpc_decode_instruction(i
243		// Generic extended signal handler
244		#if defined(__FreeBSD__)
245		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
246	+	#elif defined(__hpux)
247	+	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV) FAULT_HANDLER(SIGBUS)
248		#else
249		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
250		#endif
#	Line 240 | Line 257 | static void powerpc_decode_instruction(i
257		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
258		#define SIGSEGV_FAULT_INSTRUCTION               (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
259		#if (defined(mips) || defined(__mips))
260	<	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
260	>	#define SIGSEGV_REGISTER_FILE                   &SIGSEGV_CONTEXT_REGS[CTX_EPC], &SIGSEGV_CONTEXT_REGS[CTX_R0]
261		#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
262		#endif
263		#endif
#	Line 260 | Line 277 | static void powerpc_decode_instruction(i
277		#include <sys/regset.h>
278		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
279		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[EIP]
280	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
280	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
281		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
282		#endif
283		#endif
284		#if defined(__FreeBSD__) || defined(__OpenBSD__)
285		#if (defined(i386) || defined(__i386__))
286		#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_eip)
287	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
287	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
288		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
289		#endif
290		#endif
#	Line 276 | Line 293 | static void powerpc_decode_instruction(i
293		#include <sys/ucontext.h>
294		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.__gregs)
295		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[_REG_EIP]
296	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
296	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
297		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
298		#endif
299		#if (defined(powerpc) || defined(__powerpc__))
#	Line 292 | Line 309 | static void powerpc_decode_instruction(i
309		#include <sys/ucontext.h>
310		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
311		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
312	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
312	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
313		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
314		#endif
315		#if (defined(x86_64) || defined(__x86_64__))
316		#include <sys/ucontext.h>
317		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
318		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
319	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
319	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
320		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
321		#endif
322		#if (defined(ia64) || defined(__ia64__))
323	<	#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
323	>	#define SIGSEGV_CONTEXT_REGS                    ((struct sigcontext *)scp)
324	>	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
325	>	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
326	>	#define SIGSEGV_SKIP_INSTRUCTION                ia64_skip_instruction
327		#endif
328		#if (defined(powerpc) || defined(__powerpc__))
329		#include <sys/ucontext.h>
#	Line 323 | Line 343 | static void powerpc_decode_instruction(i
343		#define SIGSEGV_REGISTER_FILE                   (&SIGSEGV_CONTEXT_REGS.arm_r0)
344		#define SIGSEGV_SKIP_INSTRUCTION                arm_skip_instruction
345		#endif
346	+	#if (defined(mips) || defined(__mips__))
347	+	#include <sys/ucontext.h>
348	+	#define SIGSEGV_CONTEXT_REGS                    (((struct ucontext *)scp)->uc_mcontext)
349	+	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS.pc)
350	+	#define SIGSEGV_REGISTER_FILE                   &SIGSEGV_CONTEXT_REGS.pc, &SIGSEGV_CONTEXT_REGS.gregs[0]
351	+	#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
352	+	#endif
353	+	#endif
354	+	#if (defined(__hpux) || defined(__hpux__))
355	+	#if (defined(__hppa) || defined(__hppa__))
356	+	#define SIGSEGV_CONTEXT_REGS                    (&((ucontext_t *)scp)->uc_mcontext)
357	+	#define SIGSEGV_FAULT_INSTRUCTION_32    (SIGSEGV_CONTEXT_REGS->ss_narrow.ss_pcoq_head & ~3ul)
358	+	#define SIGSEGV_FAULT_INSTRUCTION_64    (SIGSEGV_CONTEXT_REGS->ss_wide.ss_64.ss_pcoq_head & ~3ull)
359	+	#if defined(__LP64__)
360	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_FAULT_INSTRUCTION_64
361	+	#else
362	+	#define SIGSEGV_FAULT_INSTRUCTION               ((SIGSEGV_CONTEXT_REGS->ss_flags & SS_WIDEREGS) ? \
363	+	(uint32_t)SIGSEGV_FAULT_INSTRUCTION_64 : \
364	+	SIGSEGV_FAULT_INSTRUCTION_32)
365	+	#endif
366	+	#endif
367	+	#if (defined(__ia64) || defined(__ia64__))
368	+	#include <sys/ucontext.h>
369	+	#define SIGSEGV_CONTEXT_REGS                    ((ucontext_t *)scp)
370	+	#define SIGSEGV_FAULT_INSTRUCTION               get_fault_instruction(SIGSEGV_CONTEXT_REGS)
371	+	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
372	+	#define SIGSEGV_SKIP_INSTRUCTION                ia64_skip_instruction
373	+
374	+	#include <sys/uc_access.h>
375	+	static inline sigsegv_address_t get_fault_instruction(const ucontext_t *ucp)
376	+	{
377	+	uint64_t ip;
378	+	if (__uc_get_ip(ucp, &ip) != 0)
379	+	return SIGSEGV_INVALID_ADDRESS;
380	+	return (sigsegv_address_t)(ip & ~3ULL);
381	+	}
382	+	#endif
383		#endif
384		#endif
385
#	Line 337 | Line 394 | static void powerpc_decode_instruction(i
394		#define SIGSEGV_FAULT_HANDLER_ARGS              &scs
395		#define SIGSEGV_FAULT_ADDRESS                   scp->cr2
396		#define SIGSEGV_FAULT_INSTRUCTION               scp->eip
397	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)scp
397	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)scp
398		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
399		#endif
400		#if (defined(sparc) || defined(__sparc__))
#	Line 458 | Line 515 | static sigsegv_address_t get_fault_addre
515		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp, addr
516		#define SIGSEGV_FAULT_ADDRESS                   addr
517		#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_eip
518	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&scp->sc_edi)
518	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&scp->sc_edi)
519		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
520		#endif
521		#if (defined(alpha) || defined(__alpha__))
#	Line 525 | Line 582 | static sigsegv_address_t get_fault_addre
582		#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
583		#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
584		#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
585	+	#if defined(_M_IX86)
586		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Eip
587	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
587	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi)
588		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
589		#endif
590	+	#if defined(_M_X64)
591	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Rip
592	+	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax)
593	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
594	+	#endif
595	+	#if defined(_M_IA64)
596	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->StIIP
597	+	#endif
598	+	#endif
599
600		#if HAVE_MACH_EXCEPTIONS
601
#	Line 550 | Line 617 | extern "C" {
617		#include <mach/mach.h>
618		#include <mach/mach_error.h>
619
620	<	extern boolean_t exc_server(mach_msg_header_t *, mach_msg_header_t *);
621	<	extern kern_return_t catch_exception_raise(mach_port_t, mach_port_t,
622	<	mach_port_t, exception_type_t, exception_data_t, mach_msg_type_number_t);
623	<	extern kern_return_t exception_raise(mach_port_t, mach_port_t, mach_port_t,
624	<	exception_type_t, exception_data_t, mach_msg_type_number_t);
625	<	extern kern_return_t exception_raise_state(mach_port_t, exception_type_t,
626	<	exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
620	>	#ifndef HAVE_MACH64_VM
621	>	#define MACH_EXCEPTION_CODES                                    0
622	>	#define mach_exception_data_t                                   exception_data_t
623	>	#define mach_exception_data_type_t                              exception_data_type_t
624	>	#define mach_exc_server                                                 exc_server
625	>	#define catch_mach_exception_raise                              catch_exception_raise
626	>	#define mach_exception_raise                                    exception_raise
627	>	#define mach_exception_raise_state                              exception_raise_state
628	>	#define mach_exception_raise_state_identity             exception_raise_state_identity
629	>	#endif
630	>
631	>	extern boolean_t mach_exc_server(mach_msg_header_t *, mach_msg_header_t *);
632	>	extern kern_return_t catch_mach_exception_raise(mach_port_t, mach_port_t,
633	>	mach_port_t, exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
634	>	extern kern_return_t catch_mach_exception_raise_state(mach_port_t exception_port,
635	>	exception_type_t exception, mach_exception_data_t code, mach_msg_type_number_t code_count,
636	>	int *flavor,
637	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
638	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
639	>	extern kern_return_t catch_mach_exception_raise_state_identity(mach_port_t exception_port,
640	>	mach_port_t thread_port, mach_port_t task_port, exception_type_t exception,
641	>	mach_exception_data_t code, mach_msg_type_number_t code_count,
642	>	int *flavor,
643	>	thread_state_t old_state, mach_msg_type_number_t old_state_count,
644	>	thread_state_t new_state, mach_msg_type_number_t *new_state_count);
645	>	extern kern_return_t mach_exception_raise(mach_port_t, mach_port_t, mach_port_t,
646	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t);
647	>	extern kern_return_t mach_exception_raise_state(mach_port_t, exception_type_t,
648	>	mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
649		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
650	<	extern kern_return_t exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
651	<	exception_type_t, exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
650	>	extern kern_return_t mach_exception_raise_state_identity(mach_port_t, mach_port_t, mach_port_t,
651	>	exception_type_t, mach_exception_data_t, mach_msg_type_number_t, thread_state_flavor_t *,
652		thread_state_t, mach_msg_type_number_t, thread_state_t, mach_msg_type_number_t *);
653		}
654
#	Line 591 | Line 680 | if (ret != KERN_SUCCESS) { \
680		}
681
682		#ifdef __ppc__
683	+	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE
684	+	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
685	+	#endif
686	+	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state_t
687	+	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE
688	+	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE_COUNT
689	+	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
690		#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state_t
691		#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE
692		#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE_COUNT
693	<	#define SIGSEGV_FAULT_INSTRUCTION               state->srr0
693	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
694		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
695	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&state->srr0, (unsigned long *)&state->r0
695	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
696	>	#endif
697	>	#ifdef __ppc64__
698	>	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64
699	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
700	>	#endif
701	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state64_t
702	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE64
703	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE64_COUNT
704	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
705	>	#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state64_t
706	>	#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE64
707	>	#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE64_COUNT
708	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
709	>	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
710	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
711		#endif
712		#ifdef __i386__
713	<	#ifdef i386_SAVED_STATE
714	<	#define SIGSEGV_THREAD_STATE_TYPE               struct i386_saved_state
715	<	#define SIGSEGV_THREAD_STATE_FLAVOR             i386_SAVED_STATE
716	<	#define SIGSEGV_THREAD_STATE_COUNT              i386_SAVED_STATE_COUNT
717	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&state->edi) /* EDI is the first GPR we consider */
718	<	#else
719	<	#define SIGSEGV_THREAD_STATE_TYPE               struct i386_thread_state
713	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32
714	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
715	>	#endif
716	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    i386_exception_state_t
717	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  i386_EXCEPTION_STATE
718	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   i386_EXCEPTION_STATE_COUNT
719	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
720	>	#define SIGSEGV_THREAD_STATE_TYPE               i386_thread_state_t
721		#define SIGSEGV_THREAD_STATE_FLAVOR             i386_THREAD_STATE
722		#define SIGSEGV_THREAD_STATE_COUNT              i386_THREAD_STATE_COUNT
723	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&state->eax) /* EAX is the first GPR we consider */
723	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(eip)
724	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
725	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(eax)) /* EAX is the first GPR we consider */
726		#endif
727	<	#define SIGSEGV_FAULT_INSTRUCTION               state->eip
727	>	#ifdef __x86_64__
728	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64
729	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
730	>	#endif
731	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    x86_exception_state64_t
732	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  x86_EXCEPTION_STATE64
733	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   x86_EXCEPTION_STATE64_COUNT
734	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
735	>	#define SIGSEGV_THREAD_STATE_TYPE               x86_thread_state64_t
736	>	#define SIGSEGV_THREAD_STATE_FLAVOR             x86_THREAD_STATE64
737	>	#define SIGSEGV_THREAD_STATE_COUNT              x86_THREAD_STATE64_COUNT
738	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(rip)
739		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
740	+	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(rax)) /* RAX is the first GPR we consider */
741	+	#endif
742	+	#define SIGSEGV_FAULT_ADDRESS_FAST              code[1]
743	+	#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_INVALID_ADDRESS
744	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, mach_exception_data_t code
745	+	#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code
746	+
747	+	#ifndef MACH_FIELD_NAME
748	+	#define MACH_FIELD_NAME(X) X
749		#endif
616	–	#define SIGSEGV_FAULT_ADDRESS                   code[1]
617	–	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP)  ((code[0] == KERN_PROTECTION_FAILURE) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE)
618	–	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code, SIGSEGV_THREAD_STATE_TYPE *state
619	–	#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code, &state
750
751		// Since there can only be one exception thread running at any time
752		// this is not a problem.
#	Line 647 | Line 777 | handleExceptions(void *priv)
777		_exceptionPort, 0, MACH_PORT_NULL);
778		MACH_CHECK_ERROR(mach_msg, krc);
779
780	<	if (!exc_server(msg, reply)) {
780	>	if (!mach_exc_server(msg, reply)) {
781		fprintf(stderr, "exc_server hated the message\n");
782		exit(1);
783		}
#	Line 669 | Line 799 | handleExceptions(void *priv)
799		*  Instruction skipping
800		*/
801
802	+	#ifndef SIGSEGV_REGISTER_TYPE
803	+	#define SIGSEGV_REGISTER_TYPE sigsegv_uintptr_t
804	+	#endif
805	+
806		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
807		// Decode and skip X86 instruction
808	<	#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
808	>	#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64))
809		#if defined(__linux__)
810		enum {
811		#if (defined(i386) || defined(__i386__))
#	Line 774 | Line 908 | enum {
908		#endif
909		#if defined(__APPLE__) && defined(__MACH__)
910		enum {
911	+	#if (defined(i386) || defined(__i386__))
912		#ifdef i386_SAVED_STATE
913		// same as FreeBSD (in Open Darwin 8.0.1)
914		X86_REG_EIP = 10,
#	Line 790 | Line 925 | enum {
925		X86_REG_EIP = 10,
926		X86_REG_EAX = 0,
927		X86_REG_ECX = 2,
928	<	X86_REG_EDX = 4,
928	>	X86_REG_EDX = 3,
929		X86_REG_EBX = 1,
930		X86_REG_ESP = 7,
931		X86_REG_EBP = 6,
932		X86_REG_ESI = 5,
933		X86_REG_EDI = 4
934		#endif
935	+	#endif
936	+	#if defined(__x86_64__)
937	+	X86_REG_R8  = 8,
938	+	X86_REG_R9  = 9,
939	+	X86_REG_R10 = 10,
940	+	X86_REG_R11 = 11,
941	+	X86_REG_R12 = 12,
942	+	X86_REG_R13 = 13,
943	+	X86_REG_R14 = 14,
944	+	X86_REG_R15 = 15,
945	+	X86_REG_EDI = 4,
946	+	X86_REG_ESI = 5,
947	+	X86_REG_EBP = 6,
948	+	X86_REG_EBX = 1,
949	+	X86_REG_EDX = 3,
950	+	X86_REG_EAX = 0,
951	+	X86_REG_ECX = 2,
952	+	X86_REG_ESP = 7,
953	+	X86_REG_EIP = 16
954	+	#endif
955		};
956		#endif
957		#if defined(_WIN32)
958		enum {
959	<	#if (defined(i386) || defined(__i386__))
959	>	#if defined(_M_IX86)
960		X86_REG_EIP = 7,
961		X86_REG_EAX = 5,
962		X86_REG_ECX = 4,
#	Line 812 | Line 967 | enum {
967		X86_REG_ESI = 1,
968		X86_REG_EDI = 0
969		#endif
970	+	#if defined(_M_X64)
971	+	X86_REG_EAX = 0,
972	+	X86_REG_ECX = 1,
973	+	X86_REG_EDX = 2,
974	+	X86_REG_EBX = 3,
975	+	X86_REG_ESP = 4,
976	+	X86_REG_EBP = 5,
977	+	X86_REG_ESI = 6,
978	+	X86_REG_EDI = 7,
979	+	X86_REG_R8  = 8,
980	+	X86_REG_R9  = 9,
981	+	X86_REG_R10 = 10,
982	+	X86_REG_R11 = 11,
983	+	X86_REG_R12 = 12,
984	+	X86_REG_R13 = 13,
985	+	X86_REG_R14 = 14,
986	+	X86_REG_R15 = 15,
987	+	X86_REG_EIP = 16
988	+	#endif
989		};
990		#endif
991		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 848 | Line 1022 | static inline int ix86_step_over_modrm(u
1022		return offset;
1023		}
1024
1025	<	static bool ix86_skip_instruction(unsigned long * regs)
1025	>	static bool ix86_skip_instruction(SIGSEGV_REGISTER_TYPE * regs)
1026		{
1027		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
1028
#	Line 859 | Line 1033 | static bool ix86_skip_instruction(unsign
1033		return false;
1034		#endif
1035
1036	+	enum instruction_type_t {
1037	+	i_MOV,
1038	+	i_ADD
1039	+	};
1040	+
1041		transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1042		transfer_size_t transfer_size = SIZE_LONG;
1043	+	instruction_type_t instruction_type = i_MOV;
1044
1045		int reg = -1;
1046		int len = 0;
#	Line 878 | Line 1058 | static bool ix86_skip_instruction(unsign
1058		}
1059
1060		// REX prefix
1061	<	#if defined(__x86_64__)
1061	>	#if defined(__x86_64__) || defined(_M_X64)
1062		struct rex_t {
1063		unsigned char W;
1064		unsigned char R;
#	Line 911 | Line 1091 | static bool ix86_skip_instruction(unsign
1091		#endif
1092
1093		// Decode instruction
1094	+	int op_len = 1;
1095		int target_size = SIZE_UNKNOWN;
1096		switch (eip[0]) {
1097		case 0x0f:
#	Line 925 | Line 1106 | static bool ix86_skip_instruction(unsign
1106		transfer_size = SIZE_WORD;
1107		goto do_mov_extend;
1108		do_mov_extend:
1109	<	switch (eip[2] & 0xc0) {
1110	<	case 0x80:
1111	<	reg = (eip[2] >> 3) & 7;
1112	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
1113	<	break;
933	<	case 0x40:
934	<	reg = (eip[2] >> 3) & 7;
935	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
936	<	break;
937	<	case 0x00:
938	<	reg = (eip[2] >> 3) & 7;
939	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
940	<	break;
941	<	}
942	<	len += 3 + ix86_step_over_modrm(eip + 2);
943	<	break;
944	<	}
945	<	break;
946	<	#if defined(__x86_64__)
1109	>	op_len = 2;
1110	>	goto do_transfer_load;
1111	>	}
1112	>	break;
1113	>	#if defined(__x86_64__) || defined(_M_X64)
1114		case 0x63: // MOVSXD r64, r/m32
1115		if (has_rex && rex.W) {
1116		transfer_size = SIZE_LONG;
#	Line 953 | Line 1120 | static bool ix86_skip_instruction(unsign
1120		transfer_size = SIZE_LONG;
1121		target_size = SIZE_QUAD;
1122		}
1123	<	switch (eip[1] & 0xc0) {
957	<	case 0x80:
958	<	reg = (eip[1] >> 3) & 7;
959	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
960	<	break;
961	<	case 0x40:
962	<	reg = (eip[1] >> 3) & 7;
963	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
964	<	break;
965	<	case 0x00:
966	<	reg = (eip[1] >> 3) & 7;
967	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
968	<	break;
969	<	}
970	<	len += 2 + ix86_step_over_modrm(eip + 1);
971	<	break;
1123	>	goto do_transfer_load;
1124		#endif
1125	+	case 0x02: // ADD r8, r/m8
1126	+	transfer_size = SIZE_BYTE;
1127	+	case 0x03: // ADD r32, r/m32
1128	+	instruction_type = i_ADD;
1129	+	goto do_transfer_load;
1130		case 0x8a: // MOV r8, r/m8
1131		transfer_size = SIZE_BYTE;
1132		case 0x8b: // MOV r32, r/m32 (or 16-bit operation)
1133	<	switch (eip[1] & 0xc0) {
1133	>	do_transfer_load:
1134	>	switch (eip[op_len] & 0xc0) {
1135		case 0x80:
1136	<	reg = (eip[1] >> 3) & 7;
1136	>	reg = (eip[op_len] >> 3) & 7;
1137		transfer_type = SIGSEGV_TRANSFER_LOAD;
1138		break;
1139		case 0x40:
1140	<	reg = (eip[1] >> 3) & 7;
1140	>	reg = (eip[op_len] >> 3) & 7;
1141		transfer_type = SIGSEGV_TRANSFER_LOAD;
1142		break;
1143		case 0x00:
1144	<	reg = (eip[1] >> 3) & 7;
1144	>	reg = (eip[op_len] >> 3) & 7;
1145		transfer_type = SIGSEGV_TRANSFER_LOAD;
1146		break;
1147		}
1148	<	len += 2 + ix86_step_over_modrm(eip + 1);
1148	>	len += 1 + op_len + ix86_step_over_modrm(eip + op_len);
1149		break;
1150	+	case 0x00: // ADD r/m8, r8
1151	+	transfer_size = SIZE_BYTE;
1152	+	case 0x01: // ADD r/m32, r32
1153	+	instruction_type = i_ADD;
1154	+	goto do_transfer_store;
1155		case 0x88: // MOV r/m8, r8
1156		transfer_size = SIZE_BYTE;
1157		case 0x89: // MOV r/m32, r32 (or 16-bit operation)
1158	<	switch (eip[1] & 0xc0) {
1158	>	do_transfer_store:
1159	>	switch (eip[op_len] & 0xc0) {
1160		case 0x80:
1161	<	reg = (eip[1] >> 3) & 7;
1161	>	reg = (eip[op_len] >> 3) & 7;
1162		transfer_type = SIGSEGV_TRANSFER_STORE;
1163		break;
1164		case 0x40:
1165	<	reg = (eip[1] >> 3) & 7;
1165	>	reg = (eip[op_len] >> 3) & 7;
1166		transfer_type = SIGSEGV_TRANSFER_STORE;
1167		break;
1168		case 0x00:
1169	<	reg = (eip[1] >> 3) & 7;
1169	>	reg = (eip[op_len] >> 3) & 7;
1170		transfer_type = SIGSEGV_TRANSFER_STORE;
1171		break;
1172		}
1173	<	len += 2 + ix86_step_over_modrm(eip + 1);
1173	>	len += 1 + op_len + ix86_step_over_modrm(eip + op_len);
1174		break;
1175		}
1176		if (target_size == SIZE_UNKNOWN)
#	Line 1017 | Line 1181 | static bool ix86_skip_instruction(unsign
1181		return false;
1182		}
1183
1184	<	#if defined(__x86_64__)
1184	>	#if defined(__x86_64__) || defined(_M_X64)
1185		if (rex.R)
1186		reg += 8;
1187		#endif
1188
1189	<	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
1189	>	if (instruction_type == i_MOV && transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
1190		static const int x86_reg_map[] = {
1191		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
1192		X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
1193	<	#if defined(__x86_64__)
1193	>	#if defined(__x86_64__) || defined(_M_X64)
1194		X86_REG_R8,  X86_REG_R9,  X86_REG_R10, X86_REG_R11,
1195		X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
1196		#endif
#	Line 1058 | Line 1222 | static bool ix86_skip_instruction(unsign
1222		}
1223
1224		#if DEBUG
1225	<	printf("%08x: %s %s access", regs[X86_REG_EIP],
1225	>	printf("%p: %s %s access", (void *)regs[X86_REG_EIP],
1226		transfer_size == SIZE_BYTE ? "byte" :
1227		transfer_size == SIZE_WORD ? "word" :
1228		transfer_size == SIZE_LONG ? "long" :
#	Line 1113 | Line 1277 | static bool ix86_skip_instruction(unsign
1277		}
1278		#endif
1279
1280	+	// Decode and skip IA-64 instruction
1281	+	#if defined(__ia64) || defined(__ia64__)
1282	+	typedef uint64_t ia64_bundle_t[2];
1283	+	#if defined(__linux__)
1284	+	// We can directly patch the slot number
1285	+	#define IA64_CAN_PATCH_IP_SLOT  1
1286	+	// Helper macros to access the machine context
1287	+	#define IA64_CONTEXT_TYPE               struct sigcontext *
1288	+	#define IA64_CONTEXT                    scp
1289	+	#define IA64_GET_IP()                   (IA64_CONTEXT->sc_ip)
1290	+	#define IA64_SET_IP(V)                  (IA64_CONTEXT->sc_ip = (V))
1291	+	#define IA64_GET_PR(P)                  ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1292	+	#define IA64_GET_NAT(I)                 ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1293	+	#define IA64_GET_GR(R)                  (IA64_CONTEXT->sc_gr[(R)])
1294	+	#define _IA64_SET_GR(R,V)               (IA64_CONTEXT->sc_gr[(R)] = (V))
1295	+	#define _IA64_SET_NAT(I,V)              (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) | (((uint64_t)!!(V)) << (I)))
1296	+	#define IA64_SET_GR(R,V,N)              (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N))
1297	+
1298	+	// Load bundle (in little-endian)
1299	+	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1300	+	{
1301	+	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1302	+	bundle[0] = ip[0];
1303	+	bundle[1] = ip[1];
1304	+	}
1305	+	#endif
1306	+	#if defined(__hpux) || defined(__hpux__)
1307	+	// We can directly patch the slot number
1308	+	#define IA64_CAN_PATCH_IP_SLOT  1
1309	+	// Helper macros to access the machine context
1310	+	#define IA64_CONTEXT_TYPE               ucontext_t *
1311	+	#define IA64_CONTEXT                    ucp
1312	+	#define IA64_GET_IP()                   ia64_get_ip(IA64_CONTEXT)
1313	+	#define IA64_SET_IP(V)                  ia64_set_ip(IA64_CONTEXT, V)
1314	+	#define IA64_GET_PR(P)                  ia64_get_pr(IA64_CONTEXT, P)
1315	+	#define IA64_GET_NAT(I)                 ia64_get_nat(IA64_CONTEXT, I)
1316	+	#define IA64_GET_GR(R)                  ia64_get_gr(IA64_CONTEXT, R)
1317	+	#define IA64_SET_GR(R,V,N)              ia64_set_gr(IA64_CONTEXT, R, V, N)
1318	+	#define UC_ACCESS(FUNC,ARGS)    do { if (__uc_##FUNC ARGS != 0) abort(); } while (0)
1319	+
1320	+	static inline uint64_t ia64_get_ip(IA64_CONTEXT_TYPE IA64_CONTEXT)
1321	+	{ uint64_t v; UC_ACCESS(get_ip,(IA64_CONTEXT, &v)); return v; }
1322	+	static inline void ia64_set_ip(IA64_CONTEXT_TYPE IA64_CONTEXT, uint64_t v)
1323	+	{ UC_ACCESS(set_ip,(IA64_CONTEXT, v)); }
1324	+	static inline unsigned int ia64_get_pr(IA64_CONTEXT_TYPE IA64_CONTEXT, int pr)
1325	+	{ uint64_t v; UC_ACCESS(get_prs,(IA64_CONTEXT, &v)); return (v >> pr) & 1; }
1326	+	static inline unsigned int ia64_get_nat(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1327	+	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return (nat >> r) & 1; }
1328	+	static inline uint64_t ia64_get_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r)
1329	+	{ uint64_t v; unsigned int nat; UC_ACCESS(get_grs,(IA64_CONTEXT, r, 1, &v, &nat)); return v; }
1330	+
1331	+	static void ia64_set_gr(IA64_CONTEXT_TYPE IA64_CONTEXT, int r, uint64_t v, unsigned int nat)
1332	+	{
1333	+	if (r == 0)
1334	+	return;
1335	+	if (r > 0 && r < 32)
1336	+	UC_ACCESS(set_grs,(IA64_CONTEXT, r, 1, &v, (!!nat) << r));
1337	+	else {
1338	+	uint64_t bsp, bspstore;
1339	+	UC_ACCESS(get_ar_bsp,(IA64_CONTEXT, &bsp));
1340	+	UC_ACCESS(get_ar_bspstore,(IA64_CONTEXT, &bspstore));
1341	+	abort(); /* XXX: use libunwind, this is not fun... */
1342	+	}
1343	+	}
1344	+
1345	+	// Byte-swapping
1346	+	#if defined(__GNUC__)
1347	+	#define BSWAP64(V) ({ uint64_t r; __asm__ __volatile__("mux1 %0=%1,@rev;;" : "=r" (r) : "r" (V)); r; })
1348	+	#elif defined (__HP_aCC)
1349	+	#define BSWAP64(V) _Asm_mux1(_MBTYPE_REV, V)
1350	+	#else
1351	+	#error "Define byte-swap instruction"
1352	+	#endif
1353	+
1354	+	// Load bundle (in little-endian)
1355	+	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1356	+	{
1357	+	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1358	+	bundle[0] = BSWAP64(ip[0]);
1359	+	bundle[1] = BSWAP64(ip[1]);
1360	+	}
1361	+	#endif
1362	+
1363	+	// Instruction operations
1364	+	enum {
1365	+	IA64_INST_UNKNOWN = 0,
1366	+	IA64_INST_LD1,                          // ld1 op0=[op1]
1367	+	IA64_INST_LD1_UPDATE,           // ld1 op0=[op1],op2
1368	+	IA64_INST_LD2,                          // ld2 op0=[op1]
1369	+	IA64_INST_LD2_UPDATE,           // ld2 op0=[op1],op2
1370	+	IA64_INST_LD4,                          // ld4 op0=[op1]
1371	+	IA64_INST_LD4_UPDATE,           // ld4 op0=[op1],op2
1372	+	IA64_INST_LD8,                          // ld8 op0=[op1]
1373	+	IA64_INST_LD8_UPDATE,           // ld8 op0=[op1],op2
1374	+	IA64_INST_ST1,                          // st1 [op0]=op1
1375	+	IA64_INST_ST1_UPDATE,           // st1 [op0]=op1,op2
1376	+	IA64_INST_ST2,                          // st2 [op0]=op1
1377	+	IA64_INST_ST2_UPDATE,           // st2 [op0]=op1,op2
1378	+	IA64_INST_ST4,                          // st4 [op0]=op1
1379	+	IA64_INST_ST4_UPDATE,           // st4 [op0]=op1,op2
1380	+	IA64_INST_ST8,                          // st8 [op0]=op1
1381	+	IA64_INST_ST8_UPDATE,           // st8 [op0]=op1,op2
1382	+	IA64_INST_ADD,                          // add op0=op1,op2,op3
1383	+	IA64_INST_SUB,                          // sub op0=op1,op2,op3
1384	+	IA64_INST_SHLADD,                       // shladd op0=op1,op3,op2
1385	+	IA64_INST_AND,                          // and op0=op1,op2
1386	+	IA64_INST_ANDCM,                        // andcm op0=op1,op2
1387	+	IA64_INST_OR,                           // or op0=op1,op2
1388	+	IA64_INST_XOR,                          // xor op0=op1,op2
1389	+	IA64_INST_SXT1,                         // sxt1 op0=op1
1390	+	IA64_INST_SXT2,                         // sxt2 op0=op1
1391	+	IA64_INST_SXT4,                         // sxt4 op0=op1
1392	+	IA64_INST_ZXT1,                         // zxt1 op0=op1
1393	+	IA64_INST_ZXT2,                         // zxt2 op0=op1
1394	+	IA64_INST_ZXT4,                         // zxt4 op0=op1
1395	+	IA64_INST_NOP                           // nop op0
1396	+	};
1397	+
1398	+	const int IA64_N_OPERANDS = 4;
1399	+
1400	+	// Decoded operand type
1401	+	struct ia64_operand_t {
1402	+	uint8_t commit;                         // commit result of operation to register file?
1403	+	uint8_t valid;                          // XXX: not really used, can be removed (debug)
1404	+	int8_t index;                           // index of GPR, or -1 if immediate value
1405	+	uint8_t nat;                            // NaT state before operation
1406	+	uint64_t value;                         // register contents or immediate value
1407	+	};
1408	+
1409	+	// Decoded instruction type
1410	+	struct ia64_instruction_t {
1411	+	uint8_t mnemo;                          // operation to perform
1412	+	uint8_t pred;                           // predicate register to check
1413	+	uint8_t no_memory;                      // used to emulated main fault instruction
1414	+	uint64_t inst;                          // the raw instruction bits (41-bit wide)
1415	+	ia64_operand_t operands[IA64_N_OPERANDS];
1416	+	};
1417	+
1418	+	// Get immediate sign-bit
1419	+	static inline int ia64_inst_get_sbit(uint64_t inst)
1420	+	{
1421	+	return (inst >> 36) & 1;
1422	+	}
1423	+
1424	+	// Get 8-bit immediate value (A3, A8, I27, M30)
1425	+	static inline uint64_t ia64_inst_get_imm8(uint64_t inst)
1426	+	{
1427	+	uint64_t value = (inst >> 13) & 0x7full;
1428	+	if (ia64_inst_get_sbit(inst))
1429	+	value |= ~0x7full;
1430	+	return value;
1431	+	}
1432	+
1433	+	// Get 9-bit immediate value (M3)
1434	+	static inline uint64_t ia64_inst_get_imm9b(uint64_t inst)
1435	+	{
1436	+	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f);
1437	+	if (ia64_inst_get_sbit(inst))
1438	+	value |= ~0xffull;
1439	+	return value;
1440	+	}
1441	+
1442	+	// Get 9-bit immediate value (M5)
1443	+	static inline uint64_t ia64_inst_get_imm9a(uint64_t inst)
1444	+	{
1445	+	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f);
1446	+	if (ia64_inst_get_sbit(inst))
1447	+	value |= ~0xffull;
1448	+	return value;
1449	+	}
1450	+
1451	+	// Get 14-bit immediate value (A4)
1452	+	static inline uint64_t ia64_inst_get_imm14(uint64_t inst)
1453	+	{
1454	+	uint64_t value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f);
1455	+	if (ia64_inst_get_sbit(inst))
1456	+	value |= ~0x1ffull;
1457	+	return value;
1458	+	}
1459	+
1460	+	// Get 22-bit immediate value (A5)
1461	+	static inline uint64_t ia64_inst_get_imm22(uint64_t inst)
1462	+	{
1463	+	uint64_t value = ((((inst >> 22) & 0x1f) << 16) |
1464	+	(((inst >> 27) & 0x1ff) << 7) |
1465	+	(inst & 0x7f));
1466	+	if (ia64_inst_get_sbit(inst))
1467	+	value |= ~0x1fffffull;
1468	+	return value;
1469	+	}
1470	+
1471	+	// Get 21-bit immediate value (I19)
1472	+	static inline uint64_t ia64_inst_get_imm21(uint64_t inst)
1473	+	{
1474	+	return (((inst >> 36) & 1) << 20) | ((inst >> 6) & 0xfffff);
1475	+	}
1476	+
1477	+	// Get 2-bit count value (A2)
1478	+	static inline int ia64_inst_get_count2(uint64_t inst)
1479	+	{
1480	+	return (inst >> 27) & 0x3;
1481	+	}
1482	+
1483	+	// Get bundle template
1484	+	static inline unsigned int ia64_get_template(uint64_t ip)
1485	+	{
1486	+	ia64_bundle_t bundle;
1487	+	ia64_load_bundle(bundle, ip);
1488	+	return bundle[0] & 0x1f;
1489	+	}
1490	+
1491	+	// Get specified instruction in bundle
1492	+	static uint64_t ia64_get_instruction(uint64_t ip, int slot)
1493	+	{
1494	+	uint64_t inst;
1495	+	ia64_bundle_t bundle;
1496	+	ia64_load_bundle(bundle, ip);
1497	+	#if DEBUG
1498	+	printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]);
1499	+	#endif
1500	+
1501	+	switch (slot) {
1502	+	case 0:
1503	+	inst = (bundle[0] >> 5) & 0x1ffffffffffull;
1504	+	break;
1505	+	case 1:
1506	+	inst = ((bundle[1] & 0x7fffffull) << 18) | ((bundle[0] >> 46) & 0x3ffffull);
1507	+	break;
1508	+	case 2:
1509	+	inst = (bundle[1] >> 23) & 0x1ffffffffffull;
1510	+	break;
1511	+	case 3:
1512	+	fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
1513	+	abort();
1514	+	break;
1515	+	}
1516	+
1517	+	#if DEBUG
1518	+	printf(" Instruction %d: 0x%016llx\n", slot, inst);
1519	+	#endif
1520	+	return inst;
1521	+	}
1522	+
1523	+	// Decode group 0 instructions
1524	+	static bool ia64_decode_instruction_0(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1525	+	{
1526	+	const int r1 = (inst->inst >>  6) & 0x7f;
1527	+	const int r3 = (inst->inst >> 20) & 0x7f;
1528	+
1529	+	const int x3 = (inst->inst >> 33) & 0x07;
1530	+	const int x6 = (inst->inst >> 27) & 0x3f;
1531	+	const int x2 = (inst->inst >> 31) & 0x03;
1532	+	const int x4 = (inst->inst >> 27) & 0x0f;
1533	+
1534	+	if (x3 == 0) {
1535	+	switch (x6) {
1536	+	case 0x01:                                              // nop.i (I19)
1537	+	inst->mnemo = IA64_INST_NOP;
1538	+	inst->operands[0].valid = true;
1539	+	inst->operands[0].index = -1;
1540	+	inst->operands[0].value = ia64_inst_get_imm21(inst->inst);
1541	+	return true;
1542	+	case 0x14:                                              // sxt1 (I29)
1543	+	case 0x15:                                              // sxt2 (I29)
1544	+	case 0x16:                                              // sxt4 (I29)
1545	+	case 0x10:                                              // zxt1 (I29)
1546	+	case 0x11:                                              // zxt2 (I29)
1547	+	case 0x12:                                              // zxt4 (I29)
1548	+	switch (x6) {
1549	+	case 0x14: inst->mnemo = IA64_INST_SXT1; break;
1550	+	case 0x15: inst->mnemo = IA64_INST_SXT2; break;
1551	+	case 0x16: inst->mnemo = IA64_INST_SXT4; break;
1552	+	case 0x10: inst->mnemo = IA64_INST_ZXT1; break;
1553	+	case 0x11: inst->mnemo = IA64_INST_ZXT2; break;
1554	+	case 0x12: inst->mnemo = IA64_INST_ZXT4; break;
1555	+	default: abort();
1556	+	}
1557	+	inst->operands[0].valid = true;
1558	+	inst->operands[0].index = r1;
1559	+	inst->operands[1].valid = true;
1560	+	inst->operands[1].index = r3;
1561	+	inst->operands[1].value = IA64_GET_GR(r3);
1562	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1563	+	return true;
1564	+	}
1565	+	}
1566	+	return false;
1567	+	}
1568	+
1569	+	// Decode group 4 instructions (load/store instructions)
1570	+	static bool ia64_decode_instruction_4(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1571	+	{
1572	+	const int r1 = (inst->inst >> 6) & 0x7f;
1573	+	const int r2 = (inst->inst >> 13) & 0x7f;
1574	+	const int r3 = (inst->inst >> 20) & 0x7f;
1575	+
1576	+	const int m  = (inst->inst >> 36) & 1;
1577	+	const int x  = (inst->inst >> 27) & 1;
1578	+	const int x6 = (inst->inst >> 30) & 0x3f;
1579	+
1580	+	switch (x6) {
1581	+	case 0x00:
1582	+	case 0x01:
1583	+	case 0x02:
1584	+	case 0x03:
1585	+	if (x == 0) {
1586	+	inst->operands[0].valid = true;
1587	+	inst->operands[0].index = r1;
1588	+	inst->operands[1].valid = true;
1589	+	inst->operands[1].index = r3;
1590	+	inst->operands[1].value = IA64_GET_GR(r3);
1591	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1592	+	if (m == 0) {
1593	+	switch (x6) {
1594	+	case 0x00: inst->mnemo = IA64_INST_LD1; break;
1595	+	case 0x01: inst->mnemo = IA64_INST_LD2; break;
1596	+	case 0x02: inst->mnemo = IA64_INST_LD4; break;
1597	+	case 0x03: inst->mnemo = IA64_INST_LD8; break;
1598	+	}
1599	+	}
1600	+	else {
1601	+	inst->operands[2].valid = true;
1602	+	inst->operands[2].index = r2;
1603	+	inst->operands[2].value = IA64_GET_GR(r2);
1604	+	inst->operands[2].nat   = IA64_GET_NAT(r2);
1605	+	switch (x6) {
1606	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1607	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1608	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1609	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1610	+	}
1611	+	}
1612	+	return true;
1613	+	}
1614	+	break;
1615	+	case 0x30:
1616	+	case 0x31:
1617	+	case 0x32:
1618	+	case 0x33:
1619	+	if (m == 0 && x == 0) {
1620	+	inst->operands[0].valid = true;
1621	+	inst->operands[0].index = r3;
1622	+	inst->operands[0].value = IA64_GET_GR(r3);
1623	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1624	+	inst->operands[1].valid = true;
1625	+	inst->operands[1].index = r2;
1626	+	inst->operands[1].value = IA64_GET_GR(r2);
1627	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1628	+	switch (x6) {
1629	+	case 0x30: inst->mnemo = IA64_INST_ST1; break;
1630	+	case 0x31: inst->mnemo = IA64_INST_ST2; break;
1631	+	case 0x32: inst->mnemo = IA64_INST_ST4; break;
1632	+	case 0x33: inst->mnemo = IA64_INST_ST8; break;
1633	+	}
1634	+	return true;
1635	+	}
1636	+	break;
1637	+	}
1638	+	return false;
1639	+	}
1640	+
1641	+	// Decode group 5 instructions (load/store instructions)
1642	+	static bool ia64_decode_instruction_5(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1643	+	{
1644	+	const int r1 = (inst->inst >> 6) & 0x7f;
1645	+	const int r2 = (inst->inst >> 13) & 0x7f;
1646	+	const int r3 = (inst->inst >> 20) & 0x7f;
1647	+
1648	+	const int x6 = (inst->inst >> 30) & 0x3f;
1649	+
1650	+	switch (x6) {
1651	+	case 0x00:
1652	+	case 0x01:
1653	+	case 0x02:
1654	+	case 0x03:
1655	+	inst->operands[0].valid = true;
1656	+	inst->operands[0].index = r1;
1657	+	inst->operands[1].valid = true;
1658	+	inst->operands[1].index = r3;
1659	+	inst->operands[1].value = IA64_GET_GR(r3);
1660	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1661	+	inst->operands[2].valid = true;
1662	+	inst->operands[2].index = -1;
1663	+	inst->operands[2].value = ia64_inst_get_imm9b(inst->inst);
1664	+	inst->operands[2].nat   = 0;
1665	+	switch (x6) {
1666	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1667	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1668	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1669	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1670	+	}
1671	+	return true;
1672	+	case 0x30:
1673	+	case 0x31:
1674	+	case 0x32:
1675	+	case 0x33:
1676	+	inst->operands[0].valid = true;
1677	+	inst->operands[0].index = r3;
1678	+	inst->operands[0].value = IA64_GET_GR(r3);
1679	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1680	+	inst->operands[1].valid = true;
1681	+	inst->operands[1].index = r2;
1682	+	inst->operands[1].value = IA64_GET_GR(r2);
1683	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1684	+	inst->operands[2].valid = true;
1685	+	inst->operands[2].index = -1;
1686	+	inst->operands[2].value = ia64_inst_get_imm9a(inst->inst);
1687	+	inst->operands[2].nat   = 0;
1688	+	switch (x6) {
1689	+	case 0x30: inst->mnemo = IA64_INST_ST1_UPDATE; break;
1690	+	case 0x31: inst->mnemo = IA64_INST_ST2_UPDATE; break;
1691	+	case 0x32: inst->mnemo = IA64_INST_ST4_UPDATE; break;
1692	+	case 0x33: inst->mnemo = IA64_INST_ST8_UPDATE; break;
1693	+	}
1694	+	return true;
1695	+	}
1696	+	return false;
1697	+	}
1698	+
1699	+	// Decode group 8 instructions (ALU integer)
1700	+	static bool ia64_decode_instruction_8(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1701	+	{
1702	+	const int r1  = (inst->inst >> 6) & 0x7f;
1703	+	const int r2  = (inst->inst >> 13) & 0x7f;
1704	+	const int r3  = (inst->inst >> 20) & 0x7f;
1705	+
1706	+	const int x2a = (inst->inst >> 34) & 0x3;
1707	+	const int x2b = (inst->inst >> 27) & 0x3;
1708	+	const int x4  = (inst->inst >> 29) & 0xf;
1709	+	const int ve  = (inst->inst >> 33) & 0x1;
1710	+
1711	+	// destination register (r1) is always valid in this group
1712	+	inst->operands[0].valid = true;
1713	+	inst->operands[0].index = r1;
1714	+
1715	+	// source register (r3) is always valid in this group
1716	+	inst->operands[2].valid = true;
1717	+	inst->operands[2].index = r3;
1718	+	inst->operands[2].value = IA64_GET_GR(r3);
1719	+	inst->operands[2].nat   = IA64_GET_NAT(r3);
1720	+
1721	+	if (x2a == 0 && ve == 0) {
1722	+	inst->operands[1].valid = true;
1723	+	inst->operands[1].index = r2;
1724	+	inst->operands[1].value = IA64_GET_GR(r2);
1725	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1726	+	switch (x4) {
1727	+	case 0x0:                               // add (A1)
1728	+	inst->mnemo = IA64_INST_ADD;
1729	+	inst->operands[3].valid = true;
1730	+	inst->operands[3].index = -1;
1731	+	inst->operands[3].value = x2b == 1;
1732	+	return true;
1733	+	case 0x1:                               // add (A1)
1734	+	inst->mnemo = IA64_INST_SUB;
1735	+	inst->operands[3].valid = true;
1736	+	inst->operands[3].index = -1;
1737	+	inst->operands[3].value = x2b == 0;
1738	+	return true;
1739	+	case 0x4:                               // shladd (A2)
1740	+	inst->mnemo = IA64_INST_SHLADD;
1741	+	inst->operands[3].valid = true;
1742	+	inst->operands[3].index = -1;
1743	+	inst->operands[3].value = ia64_inst_get_count2(inst->inst);
1744	+	return true;
1745	+	case 0x9:
1746	+	if (x2b == 1) {
1747	+	inst->mnemo = IA64_INST_SUB;
1748	+	inst->operands[1].index = -1;
1749	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1750	+	inst->operands[1].nat   = 0;
1751	+	return true;
1752	+	}
1753	+	break;
1754	+	case 0xb:
1755	+	inst->operands[1].index = -1;
1756	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1757	+	inst->operands[1].nat   = 0;
1758	+	// fall-through
1759	+	case 0x3:
1760	+	switch (x2b) {
1761	+	case 0: inst->mnemo = IA64_INST_AND;   break;
1762	+	case 1: inst->mnemo = IA64_INST_ANDCM; break;
1763	+	case 2: inst->mnemo = IA64_INST_OR;    break;
1764	+	case 3: inst->mnemo = IA64_INST_XOR;   break;
1765	+	}
1766	+	return true;
1767	+	}
1768	+	}
1769	+	return false;
1770	+	}
1771	+
1772	+	// Decode instruction
1773	+	static bool ia64_decode_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1774	+	{
1775	+	const int major = (inst->inst >> 37) & 0xf;
1776	+
1777	+	inst->mnemo = IA64_INST_UNKNOWN;
1778	+	inst->pred  = inst->inst & 0x3f;
1779	+	memset(&inst->operands[0], 0, sizeof(inst->operands));
1780	+
1781	+	switch (major) {
1782	+	case 0x0: return ia64_decode_instruction_0(inst, IA64_CONTEXT);
1783	+	case 0x4: return ia64_decode_instruction_4(inst, IA64_CONTEXT);
1784	+	case 0x5: return ia64_decode_instruction_5(inst, IA64_CONTEXT);
1785	+	case 0x8: return ia64_decode_instruction_8(inst, IA64_CONTEXT);
1786	+	}
1787	+	return false;
1788	+	}
1789	+
1790	+	static bool ia64_emulate_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1791	+	{
1792	+	// XXX: handle Register NaT Consumption fault?
1793	+	// XXX: this simple emulator assumes instructions in a bundle
1794	+	// don't depend on effects of other instructions in the same
1795	+	// bundle. It probably would be simpler to JIT-generate code to be
1796	+	// executed natively but probably more costly (inject/extract CPU state)
1797	+	if (inst->mnemo == IA64_INST_UNKNOWN)
1798	+	return false;
1799	+	if (inst->pred && !IA64_GET_PR(inst->pred))
1800	+	return true;
1801	+
1802	+	uint8_t nat, nat2;
1803	+	uint64_t dst, dst2, src1, src2, src3;
1804	+
1805	+	switch (inst->mnemo) {
1806	+	case IA64_INST_NOP:
1807	+	break;
1808	+	case IA64_INST_ADD:
1809	+	case IA64_INST_SUB:
1810	+	case IA64_INST_SHLADD:
1811	+	src3 = inst->operands[3].value;
1812	+	// fall-through
1813	+	case IA64_INST_AND:
1814	+	case IA64_INST_ANDCM:
1815	+	case IA64_INST_OR:
1816	+	case IA64_INST_XOR:
1817	+	src1 = inst->operands[1].value;
1818	+	src2 = inst->operands[2].value;
1819	+	switch (inst->mnemo) {
1820	+	case IA64_INST_ADD:   dst = src1 + src2 + src3; break;
1821	+	case IA64_INST_SUB:   dst = src1 - src2 - src3; break;
1822	+	case IA64_INST_SHLADD: dst = (src1 << src3) + src2; break;
1823	+	case IA64_INST_AND:   dst = src1 & src2;                break;
1824	+	case IA64_INST_ANDCM: dst = src1 &~ src2;               break;
1825	+	case IA64_INST_OR:    dst = src1 | src2;                break;
1826	+	case IA64_INST_XOR:   dst = src1 ^ src2;                break;
1827	+	}
1828	+	inst->operands[0].commit = true;
1829	+	inst->operands[0].value  = dst;
1830	+	inst->operands[0].nat    = inst->operands[1].nat | inst->operands[2].nat;
1831	+	break;
1832	+	case IA64_INST_SXT1:
1833	+	case IA64_INST_SXT2:
1834	+	case IA64_INST_SXT4:
1835	+	case IA64_INST_ZXT1:
1836	+	case IA64_INST_ZXT2:
1837	+	case IA64_INST_ZXT4:
1838	+	src1 = inst->operands[1].value;
1839	+	switch (inst->mnemo) {
1840	+	case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1;               break;
1841	+	case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1;              break;
1842	+	case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1;              break;
1843	+	case IA64_INST_ZXT1: dst = (uint8_t)src1;                               break;
1844	+	case IA64_INST_ZXT2: dst = (uint16_t)src1;                              break;
1845	+	case IA64_INST_ZXT4: dst = (uint32_t)src1;                              break;
1846	+	}
1847	+	inst->operands[0].commit = true;
1848	+	inst->operands[0].value  = dst;
1849	+	inst->operands[0].nat    = inst->operands[1].nat;
1850	+	break;
1851	+	case IA64_INST_LD1_UPDATE:
1852	+	case IA64_INST_LD2_UPDATE:
1853	+	case IA64_INST_LD4_UPDATE:
1854	+	case IA64_INST_LD8_UPDATE:
1855	+	inst->operands[1].commit = true;
1856	+	dst2 = inst->operands[1].value + inst->operands[2].value;
1857	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1858	+	// fall-through
1859	+	case IA64_INST_LD1:
1860	+	case IA64_INST_LD2:
1861	+	case IA64_INST_LD4:
1862	+	case IA64_INST_LD8:
1863	+	src1 = inst->operands[1].value;
1864	+	if (inst->no_memory)
1865	+	dst = 0;
1866	+	else {
1867	+	switch (inst->mnemo) {
1868	+	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((uint8_t *)src1);        break;
1869	+	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((uint16_t *)src1);       break;
1870	+	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((uint32_t *)src1);       break;
1871	+	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((uint64_t *)src1);       break;
1872	+	}
1873	+	}
1874	+	inst->operands[0].commit = true;
1875	+	inst->operands[0].value  = dst;
1876	+	inst->operands[0].nat    = 0;
1877	+	inst->operands[1].value  = dst2;
1878	+	inst->operands[1].nat    = nat2;
1879	+	break;
1880	+	case IA64_INST_ST1_UPDATE:
1881	+	case IA64_INST_ST2_UPDATE:
1882	+	case IA64_INST_ST4_UPDATE:
1883	+	case IA64_INST_ST8_UPDATE:
1884	+	inst->operands[0].commit = 0;
1885	+	dst2 = inst->operands[0].value + inst->operands[2].value;
1886	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1887	+	// fall-through
1888	+	case IA64_INST_ST1:
1889	+	case IA64_INST_ST2:
1890	+	case IA64_INST_ST4:
1891	+	case IA64_INST_ST8:
1892	+	dst  = inst->operands[0].value;
1893	+	src1 = inst->operands[1].value;
1894	+	if (!inst->no_memory) {
1895	+	switch (inst->mnemo) {
1896	+	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((uint8_t *)dst) = src1;        break;
1897	+	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((uint16_t *)dst) = src1;       break;
1898	+	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((uint32_t *)dst) = src1;       break;
1899	+	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((uint64_t *)dst) = src1;       break;
1900	+	}
1901	+	}
1902	+	inst->operands[0].value  = dst2;
1903	+	inst->operands[0].nat    = nat2;
1904	+	break;
1905	+	default:
1906	+	return false;
1907	+	}
1908	+
1909	+	for (int i = 0; i < IA64_N_OPERANDS; i++) {
1910	+	ia64_operand_t const & op = inst->operands[i];
1911	+	if (!op.commit)
1912	+	continue;
1913	+	if (op.index == -1)
1914	+	return false; // XXX: internal error
1915	+	IA64_SET_GR(op.index, op.value, op.nat);
1916	+	}
1917	+	return true;
1918	+	}
1919	+
1920	+	static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1921	+	{
1922	+	ia64_instruction_t inst;
1923	+	memset(&inst, 0, sizeof(inst));
1924	+	inst.inst = raw_inst;
1925	+	if (!ia64_decode_instruction(&inst, IA64_CONTEXT))
1926	+	return false;
1927	+	return ia64_emulate_instruction(&inst, IA64_CONTEXT);
1928	+	}
1929	+
1930	+	static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1931	+	{
1932	+	uint64_t ip = IA64_GET_IP();
1933	+	#if DEBUG
1934	+	printf("IP: 0x%016llx\n", ip);
1935	+	#if 0
1936	+	printf(" Template 0x%02x\n", ia64_get_template(ip));
1937	+	ia64_get_instruction(ip, 0);
1938	+	ia64_get_instruction(ip, 1);
1939	+	ia64_get_instruction(ip, 2);
1940	+	#endif
1941	+	#endif
1942	+
1943	+	// Select which decode switch to use
1944	+	ia64_instruction_t inst;
1945	+	inst.inst = ia64_get_instruction(ip, ip & 3);
1946	+	if (!ia64_decode_instruction(&inst, IA64_CONTEXT)) {
1947	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not decode instruction\n");
1948	+	return false;
1949	+	}
1950	+
1951	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1952	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1953	+
1954	+	switch (inst.mnemo) {
1955	+	case IA64_INST_LD1:
1956	+	case IA64_INST_LD2:
1957	+	case IA64_INST_LD4:
1958	+	case IA64_INST_LD8:
1959	+	case IA64_INST_LD1_UPDATE:
1960	+	case IA64_INST_LD2_UPDATE:
1961	+	case IA64_INST_LD4_UPDATE:
1962	+	case IA64_INST_LD8_UPDATE:
1963	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1964	+	break;
1965	+	case IA64_INST_ST1:
1966	+	case IA64_INST_ST2:
1967	+	case IA64_INST_ST4:
1968	+	case IA64_INST_ST8:
1969	+	case IA64_INST_ST1_UPDATE:
1970	+	case IA64_INST_ST2_UPDATE:
1971	+	case IA64_INST_ST4_UPDATE:
1972	+	case IA64_INST_ST8_UPDATE:
1973	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1974	+	break;
1975	+	}
1976	+
1977	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1978	+	// Unknown machine code, let it crash. Then patch the decoder
1979	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): not a load/store instruction\n");
1980	+	return false;
1981	+	}
1982	+
1983	+	switch (inst.mnemo) {
1984	+	case IA64_INST_LD1:
1985	+	case IA64_INST_LD1_UPDATE:
1986	+	case IA64_INST_ST1:
1987	+	case IA64_INST_ST1_UPDATE:
1988	+	transfer_size = SIZE_BYTE;
1989	+	break;
1990	+	case IA64_INST_LD2:
1991	+	case IA64_INST_LD2_UPDATE:
1992	+	case IA64_INST_ST2:
1993	+	case IA64_INST_ST2_UPDATE:
1994	+	transfer_size = SIZE_WORD;
1995	+	break;
1996	+	case IA64_INST_LD4:
1997	+	case IA64_INST_LD4_UPDATE:
1998	+	case IA64_INST_ST4:
1999	+	case IA64_INST_ST4_UPDATE:
2000	+	transfer_size = SIZE_LONG;
2001	+	break;
2002	+	case IA64_INST_LD8:
2003	+	case IA64_INST_LD8_UPDATE:
2004	+	case IA64_INST_ST8:
2005	+	case IA64_INST_ST8_UPDATE:
2006	+	transfer_size = SIZE_QUAD;
2007	+	break;
2008	+	}
2009	+
2010	+	if (transfer_size == SIZE_UNKNOWN) {
2011	+	// Unknown machine code, let it crash. Then patch the decoder
2012	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): unknown transfer size\n");
2013	+	return false;
2014	+	}
2015	+
2016	+	inst.no_memory = true;
2017	+	if (!ia64_emulate_instruction(&inst, IA64_CONTEXT)) {
2018	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate fault instruction\n");
2019	+	return false;
2020	+	}
2021	+
2022	+	int slot = ip & 3;
2023	+	bool emulate_next = false;
2024	+	switch (slot) {
2025	+	case 0:
2026	+	switch (ia64_get_template(ip)) {
2027	+	case 0x2: // MI;I
2028	+	case 0x3: // MI;I;
2029	+	emulate_next = true;
2030	+	slot = 2;
2031	+	break;
2032	+	case 0xa: // M;MI
2033	+	case 0xb: // M;MI;
2034	+	emulate_next = true;
2035	+	slot = 1;
2036	+	break;
2037	+	}
2038	+	break;
2039	+	}
2040	+	if (emulate_next && !IA64_CAN_PATCH_IP_SLOT) {
2041	+	while (slot < 3) {
2042	+	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), IA64_CONTEXT)) {
2043	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate instruction\n");
2044	+	return false;
2045	+	}
2046	+	++slot;
2047	+	}
2048	+	}
2049	+
2050	+	#if IA64_CAN_PATCH_IP_SLOT
2051	+	if ((slot = ip & 3) < 2)
2052	+	IA64_SET_IP((ip & ~3ull) + (slot + 1));
2053	+	else
2054	+	#endif
2055	+	IA64_SET_IP((ip & ~3ull) + 16);
2056	+	#if DEBUG
2057	+	printf("IP: 0x%016llx\n", IA64_GET_IP());
2058	+	#endif
2059	+	return true;
2060	+	}
2061	+	#endif
2062	+
2063		// Decode and skip PPC instruction
2064	<	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__))
2064	>	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__))
2065		static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
2066		{
2067		instruction_t instr;
#	Line 1150 | Line 2097 | static bool powerpc_skip_instruction(uns
2097
2098		// Decode and skip MIPS instruction
2099		#if (defined(mips) || defined(__mips))
2100	<	enum {
1154	<	#if (defined(sgi) || defined(__sgi))
1155	<	MIPS_REG_EPC = 35,
1156	<	#endif
1157	<	};
1158	<	static bool mips_skip_instruction(greg_t * regs)
2100	>	static bool mips_skip_instruction(greg_t * pc_p, greg_t * regs)
2101		{
2102	<	unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC];
2102	>	unsigned int * epc = (unsigned int *)(unsigned long)*pc_p;
2103
2104		if (epc == 0)
2105		return false;
#	Line 1306 | Line 2248 | static bool mips_skip_instruction(greg_t
2248		mips_gpr_names[reg]);
2249		#endif
2250
2251	<	regs[MIPS_REG_EPC] += 4;
2251	>	*pc_p += 4;
2252		return true;
2253		}
2254		#endif
#	Line 1594 | Line 2536 | static bool arm_skip_instruction(unsigne
2536
2537
2538		// Fallbacks
2539	+	#ifndef SIGSEGV_FAULT_ADDRESS_FAST
2540	+	#define SIGSEGV_FAULT_ADDRESS_FAST              SIGSEGV_FAULT_ADDRESS
2541	+	#endif
2542	+	#ifndef SIGSEGV_FAULT_INSTRUCTION_FAST
2543	+	#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_FAULT_INSTRUCTION
2544	+	#endif
2545		#ifndef SIGSEGV_FAULT_INSTRUCTION
2546	<	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_INVALID_PC
2546	>	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_INVALID_ADDRESS
2547		#endif
2548		#ifndef SIGSEGV_FAULT_HANDLER_ARGLIST_1
2549		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 SIGSEGV_FAULT_HANDLER_ARGLIST
2550		#endif
2551		#ifndef SIGSEGV_FAULT_HANDLER_INVOKE
2552	<	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP)  sigsegv_fault_handler(ADDR, IP)
2552	>	#define SIGSEGV_FAULT_HANDLER_INVOKE(P) sigsegv_fault_handler(P)
2553		#endif
2554
2555		// SIGSEGV recovery supported ?
#	Line 1614 | Line 2562 | static bool arm_skip_instruction(unsigne
2562		*  SIGSEGV global handler
2563		*/
2564
2565	+	struct sigsegv_info_t {
2566	+	sigsegv_address_t addr;
2567	+	sigsegv_address_t pc;
2568	+	#ifdef HAVE_MACH_EXCEPTIONS
2569	+	mach_port_t thread;
2570	+	bool has_exc_state;
2571	+	SIGSEGV_EXCEPTION_STATE_TYPE exc_state;
2572	+	mach_msg_type_number_t exc_state_count;
2573	+	bool has_thr_state;
2574	+	SIGSEGV_THREAD_STATE_TYPE thr_state;
2575	+	mach_msg_type_number_t thr_state_count;
2576	+	#endif
2577	+	};
2578	+
2579	+	#ifdef HAVE_MACH_EXCEPTIONS
2580	+	static void mach_get_exception_state(sigsegv_info_t *SIP)
2581	+	{
2582	+	SIP->exc_state_count = SIGSEGV_EXCEPTION_STATE_COUNT;
2583	+	kern_return_t krc = thread_get_state(SIP->thread,
2584	+	SIGSEGV_EXCEPTION_STATE_FLAVOR,
2585	+	(natural_t *)&SIP->exc_state,
2586	+	&SIP->exc_state_count);
2587	+	MACH_CHECK_ERROR(thread_get_state, krc);
2588	+	SIP->has_exc_state = true;
2589	+	}
2590	+
2591	+	static void mach_get_thread_state(sigsegv_info_t *SIP)
2592	+	{
2593	+	SIP->thr_state_count = SIGSEGV_THREAD_STATE_COUNT;
2594	+	kern_return_t krc = thread_get_state(SIP->thread,
2595	+	SIGSEGV_THREAD_STATE_FLAVOR,
2596	+	(natural_t *)&SIP->thr_state,
2597	+	&SIP->thr_state_count);
2598	+	MACH_CHECK_ERROR(thread_get_state, krc);
2599	+	SIP->has_thr_state = true;
2600	+	}
2601	+
2602	+	static void mach_set_thread_state(sigsegv_info_t *SIP)
2603	+	{
2604	+	kern_return_t krc = thread_set_state(SIP->thread,
2605	+	SIGSEGV_THREAD_STATE_FLAVOR,
2606	+	(natural_t *)&SIP->thr_state,
2607	+	SIP->thr_state_count);
2608	+	MACH_CHECK_ERROR(thread_set_state, krc);
2609	+	}
2610	+	#endif
2611	+
2612	+	// Return the address of the invalid memory reference
2613	+	sigsegv_address_t sigsegv_get_fault_address(sigsegv_info_t *SIP)
2614	+	{
2615	+	#ifdef HAVE_MACH_EXCEPTIONS
2616	+	static int use_fast_path = -1;
2617	+	if (use_fast_path != 1 && !SIP->has_exc_state) {
2618	+	mach_get_exception_state(SIP);
2619	+
2620	+	sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
2621	+	if (use_fast_path < 0) {
2622	+	const char *machfault = getenv("SIGSEGV_MACH_FAULT");
2623	+	if (machfault) {
2624	+	if (strcmp(machfault, "fast") == 0)
2625	+	use_fast_path = 1;
2626	+	else if (strcmp(machfault, "slow") == 0)
2627	+	use_fast_path = 0;
2628	+	}
2629	+	if (use_fast_path < 0)
2630	+	use_fast_path = addr == SIP->addr;
2631	+	}
2632	+	SIP->addr = addr;
2633	+	}
2634	+	#endif
2635	+	return SIP->addr;
2636	+	}
2637	+
2638	+	// Return the address of the instruction that caused the fault, or
2639	+	// SIGSEGV_INVALID_ADDRESS if we could not retrieve this information
2640	+	sigsegv_address_t sigsegv_get_fault_instruction_address(sigsegv_info_t *SIP)
2641	+	{
2642	+	#ifdef HAVE_MACH_EXCEPTIONS
2643	+	if (!SIP->has_thr_state) {
2644	+	mach_get_thread_state(SIP);
2645	+
2646	+	SIP->pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
2647	+	}
2648	+	#endif
2649	+	return SIP->pc;
2650	+	}
2651	+
2652		// This function handles the badaccess to memory.
2653		// It is called from the signal handler or the exception handler.
2654		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
2655		{
2656	+	sigsegv_info_t SI;
2657	+	SI.addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS_FAST;
2658	+	SI.pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION_FAST;
2659		#ifdef HAVE_MACH_EXCEPTIONS
2660	<	// We must match the initial count when writing back the CPU state registers
2661	<	kern_return_t krc;
2662	<	mach_msg_type_number_t count;
1625	<
1626	<	count = SIGSEGV_THREAD_STATE_COUNT;
1627	<	krc = thread_get_state(thread, SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state, &count);
1628	<	MACH_CHECK_ERROR (thread_get_state, krc);
2660	>	SI.thread = thread;
2661	>	SI.has_exc_state = false;
2662	>	SI.has_thr_state = false;
2663		#endif
2664	+	sigsegv_info_t * const SIP = &SI;
2665
1631	–	sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
1632	–	sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
1633	–
2666		// Call user's handler and reinstall the global handler, if required
2667	<	switch (SIGSEGV_FAULT_HANDLER_INVOKE(fault_address, fault_instruction)) {
2667	>	switch (SIGSEGV_FAULT_HANDLER_INVOKE(SIP)) {
2668		case SIGSEGV_RETURN_SUCCESS:
2669		return true;
2670
#	Line 1640 | Line 2672 | static bool handle_badaccess(SIGSEGV_FAU
2672		case SIGSEGV_RETURN_SKIP_INSTRUCTION:
2673		// Call the instruction skipper with the register file
2674		// available
2675	+	#ifdef HAVE_MACH_EXCEPTIONS
2676	+	if (!SIP->has_thr_state)
2677	+	mach_get_thread_state(SIP);
2678	+	#endif
2679		if (SIGSEGV_SKIP_INSTRUCTION(SIGSEGV_REGISTER_FILE)) {
2680		#ifdef HAVE_MACH_EXCEPTIONS
2681		// Unlike UNIX signals where the thread state
2682		// is modified off of the stack, in Mach we
2683		// need to actually call thread_set_state to
2684		// have the register values updated.
2685	<	krc = thread_set_state(thread,
1650	<	SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state,
1651	<	count);
1652	<	MACH_CHECK_ERROR (thread_set_state, krc);
2685	>	mach_set_thread_state(SIP);
2686		#endif
2687		return true;
2688		}
#	Line 1658 | Line 2691 | static bool handle_badaccess(SIGSEGV_FAU
2691		case SIGSEGV_RETURN_FAILURE:
2692		// We can't do anything with the fault_address, dump state?
2693		if (sigsegv_state_dumper != 0)
2694	<	sigsegv_state_dumper(fault_address, fault_instruction);
2694	>	sigsegv_state_dumper(SIP);
2695		break;
2696		}
2697
#	Line 1691 | Line 2724 | static inline kern_return_t
2724		forward_exception(mach_port_t thread_port,
2725		mach_port_t task_port,
2726		exception_type_t exception_type,
2727	<	exception_data_t exception_data,
2727	>	mach_exception_data_t exception_data,
2728		mach_msg_type_number_t data_count,
2729		ExceptionPorts *oldExceptionPorts)
2730		{
#	Line 1719 | Line 2752 | forward_exception(mach_port_t thread_por
2752		behavior = oldExceptionPorts->behaviors[portIndex];
2753		flavor = oldExceptionPorts->flavors[portIndex];
2754
2755	+	if (!VALID_THREAD_STATE_FLAVOR(flavor)) {
2756	+	fprintf(stderr, "Invalid thread_state flavor = %d. Not forwarding\n", flavor);
2757	+	return KERN_FAILURE;
2758	+	}
2759	+
2760		/*
2761		fprintf(stderr, "forwarding exception, port = 0x%x, behaviour = %d, flavor = %d\n", port, behavior, flavor);
2762		*/
#	Line 1733 | Line 2771 | forward_exception(mach_port_t thread_por
2771		switch (behavior) {
2772		case EXCEPTION_DEFAULT:
2773		// fprintf(stderr, "forwarding to exception_raise\n");
2774	<	kret = exception_raise(port, thread_port, task_port, exception_type,
2775	<	exception_data, data_count);
2776	<	MACH_CHECK_ERROR (exception_raise, kret);
2774	>	kret = mach_exception_raise(port, thread_port, task_port, exception_type,
2775	>	exception_data, data_count);
2776	>	MACH_CHECK_ERROR (mach_exception_raise, kret);
2777		break;
2778		case EXCEPTION_STATE:
2779		// fprintf(stderr, "forwarding to exception_raise_state\n");
2780	<	kret = exception_raise_state(port, exception_type, exception_data,
2781	<	data_count, &flavor,
2782	<	(natural_t *)&thread_state, thread_state_count,
2783	<	(natural_t *)&thread_state, &thread_state_count);
2784	<	MACH_CHECK_ERROR (exception_raise_state, kret);
2780	>	kret = mach_exception_raise_state(port, exception_type, exception_data,
2781	>	data_count, &flavor,
2782	>	(natural_t *)&thread_state, thread_state_count,
2783	>	(natural_t *)&thread_state, &thread_state_count);
2784	>	MACH_CHECK_ERROR (mach_exception_raise_state, kret);
2785		break;
2786		case EXCEPTION_STATE_IDENTITY:
2787		// fprintf(stderr, "forwarding to exception_raise_state_identity\n");
2788	<	kret = exception_raise_state_identity(port, thread_port, task_port,
2789	<	exception_type, exception_data,
2790	<	data_count, &flavor,
2791	<	(natural_t *)&thread_state, thread_state_count,
2792	<	(natural_t *)&thread_state, &thread_state_count);
2793	<	MACH_CHECK_ERROR (exception_raise_state_identity, kret);
2788	>	kret = mach_exception_raise_state_identity(port, thread_port, task_port,
2789	>	exception_type, exception_data,
2790	>	data_count, &flavor,
2791	>	(natural_t *)&thread_state, thread_state_count,
2792	>	(natural_t *)&thread_state, &thread_state_count);
2793	>	MACH_CHECK_ERROR (mach_exception_raise_state_identity, kret);
2794		break;
2795		default:
2796		fprintf(stderr, "forward_exception got unknown behavior\n");
2797	+	kret = KERN_FAILURE;
2798		break;
2799		}
2800
#	Line 1765 | Line 2804 | forward_exception(mach_port_t thread_por
2804		MACH_CHECK_ERROR (thread_set_state, kret);
2805		}
2806
2807	<	return KERN_SUCCESS;
2807	>	return kret;
2808		}
2809
2810		/*
#	Line 1788 | Line 2827 | forward_exception(mach_port_t thread_por
2827		* linkage because that is what exc_server expects.
2828		*/
2829		kern_return_t
2830	<	catch_exception_raise(mach_port_t exception_port,
2831	<	mach_port_t thread,
2832	<	mach_port_t task,
2833	<	exception_type_t exception,
2834	<	exception_data_t code,
2835	<	mach_msg_type_number_t codeCount)
2830	>	catch_mach_exception_raise(mach_port_t exception_port,
2831	>	mach_port_t thread,
2832	>	mach_port_t task,
2833	>	exception_type_t exception,
2834	>	mach_exception_data_t code,
2835	>	mach_msg_type_number_t code_count)
2836		{
1798	–	SIGSEGV_THREAD_STATE_TYPE state;
2837		kern_return_t krc;
2838
2839	<	if ((exception == EXC_BAD_ACCESS)  && (codeCount >= 2)) {
2840	<	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
2841	<	return KERN_SUCCESS;
2839	>	if (exception == EXC_BAD_ACCESS) {
2840	>	switch (code[0]) {
2841	>	case KERN_PROTECTION_FAILURE:
2842	>	case KERN_INVALID_ADDRESS:
2843	>	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
2844	>	return KERN_SUCCESS;
2845	>	break;
2846	>	}
2847		}
2848
2849		// In Mach we do not need to remove the exception handler.
2850		// If we forward the exception, eventually some exception handler
2851		// will take care of this exception.
2852	<	krc = forward_exception(thread, task, exception, code, codeCount, &ports);
2852	>	krc = forward_exception(thread, task, exception, code, code_count, &ports);
2853
2854		return krc;
2855		}
2856	+
2857	+	/* XXX: borrowed from launchd and gdb */
2858	+	kern_return_t
2859	+	catch_mach_exception_raise_state(mach_port_t exception_port,
2860	+	exception_type_t exception,
2861	+	mach_exception_data_t code,
2862	+	mach_msg_type_number_t code_count,
2863	+	int *flavor,
2864	+	thread_state_t old_state,
2865	+	mach_msg_type_number_t old_state_count,
2866	+	thread_state_t new_state,
2867	+	mach_msg_type_number_t *new_state_count)
2868	+	{
2869	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2870	+	*new_state_count = old_state_count;
2871	+	return KERN_SUCCESS;
2872	+	}
2873	+
2874	+	/* XXX: borrowed from launchd and gdb */
2875	+	kern_return_t
2876	+	catch_mach_exception_raise_state_identity(mach_port_t exception_port,
2877	+	mach_port_t thread_port,
2878	+	mach_port_t task_port,
2879	+	exception_type_t exception,
2880	+	mach_exception_data_t code,
2881	+	mach_msg_type_number_t code_count,
2882	+	int *flavor,
2883	+	thread_state_t old_state,
2884	+	mach_msg_type_number_t old_state_count,
2885	+	thread_state_t new_state,
2886	+	mach_msg_type_number_t *new_state_count)
2887	+	{
2888	+	kern_return_t kret;
2889	+
2890	+	memcpy(new_state, old_state, old_state_count * sizeof(old_state[0]));
2891	+	*new_state_count = old_state_count;
2892	+
2893	+	kret = mach_port_deallocate(mach_task_self(), task_port);
2894	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2895	+	kret = mach_port_deallocate(mach_task_self(), thread_port);
2896	+	MACH_CHECK_ERROR(mach_port_deallocate, kret);
2897	+
2898	+	return KERN_SUCCESS;
2899	+	}
2900		#endif
2901
2902		#ifdef HAVE_SIGSEGV_RECOVERY
#	Line 1934 | Line 3021 | static bool sigsegv_do_install_handler(s
3021		// addressing modes) used in PPC instructions, you will need the
3022		// GPR state anyway.
3023		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
3024	<	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
3024	>	EXCEPTION_DEFAULT | MACH_EXCEPTION_CODES, SIGSEGV_THREAD_STATE_FLAVOR);
3025		if (krc != KERN_SUCCESS) {
3026		mach_error("thread_set_exception_ports", krc);
3027		return false;
#	Line 1962 | Line 3049 | static LONG WINAPI main_exception_filter
3049		{
3050		if (sigsegv_fault_handler != NULL
3051		&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
3052	<	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
3052	>	&& ExceptionInfo->ExceptionRecord->NumberParameters >= 2
3053		&& handle_badaccess(ExceptionInfo))
3054		return EXCEPTION_CONTINUE_EXECUTION;
3055
#	Line 2114 | Line 3201 | void sigsegv_set_dump_state(sigsegv_stat
3201		const int REF_INDEX = 123;
3202		const int REF_VALUE = 45;
3203
3204	<	static int page_size;
3204	>	static sigsegv_uintptr_t page_size;
3205		static volatile char * page = 0;
3206		static volatile int handler_called = 0;
3207
#	Line 2130 | Line 3217 | static volatile int handler_called = 0;
3217		static void *b_region, *e_region;
3218		#endif
3219
3220	<	static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
3220	>	static sigsegv_return_t sigsegv_test_handler(sigsegv_info_t *sip)
3221		{
3222	+	const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip);
3223	+	const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip);
3224		#if DEBUG
3225		printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
3226		printf("expected fault at %p\n", page + REF_INDEX);
#	Line 2145 | Line 3234 | static sigsegv_return_t sigsegv_test_han
3234		#ifdef __GNUC__
3235		// Make sure reported fault instruction address falls into
3236		// expected code range
3237	<	if (instruction_address != SIGSEGV_INVALID_PC
3237	>	if (instruction_address != SIGSEGV_INVALID_ADDRESS
3238		&& ((instruction_address <  (sigsegv_address_t)b_region) ||
3239		(instruction_address >= (sigsegv_address_t)e_region)))
3240		exit(11);
3241		#endif
3242	<	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
3242	>	if (vm_protect((char *)((sigsegv_uintptr_t)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
3243		exit(12);
3244		return SIGSEGV_RETURN_SUCCESS;
3245		}
3246
3247		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
3248	<	static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
3248	>	static sigsegv_return_t sigsegv_insn_handler(sigsegv_info_t *sip)
3249		{
3250	+	const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip);
3251	+	const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip);
3252		#if DEBUG
3253		printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
3254		#endif
3255	<	if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
3255	>	if (((sigsegv_uintptr_t)fault_address - (sigsegv_uintptr_t)page) < page_size) {
3256		#ifdef __GNUC__
3257		// Make sure reported fault instruction address falls into
3258		// expected code range
3259	<	if (instruction_address != SIGSEGV_INVALID_PC
3259	>	if (instruction_address != SIGSEGV_INVALID_ADDRESS
3260		&& ((instruction_address <  (sigsegv_address_t)b_region) ||
3261		(instruction_address >= (sigsegv_address_t)e_region)))
3262		return SIGSEGV_RETURN_FAILURE;
#	Line 2179 | Line 3270 | static sigsegv_return_t sigsegv_insn_han
3270		// More sophisticated tests for instruction skipper
3271		static bool arch_insn_skipper_tests()
3272		{
3273	<	#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
3273	>	#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64))
3274		static const unsigned char code[] = {
3275		0x8a, 0x00,                    // mov    (%eax),%al
3276		0x8a, 0x2c, 0x18,              // mov    (%eax,%ebx,1),%ch
#	Line 2193 | Line 3284 | static bool arch_insn_skipper_tests()
3284		0x8b, 0x0c, 0x18,              // mov    (%eax,%ebx,1),%ecx
3285		0x89, 0x00,                    // mov    %eax,(%eax)
3286		0x89, 0x0c, 0x18,              // mov    %ecx,(%eax,%ebx,1)
3287	<	#if defined(__x86_64__)
3287	>	#if defined(__x86_64__) || defined(_M_X64)
3288		0x44, 0x8a, 0x00,              // mov    (%rax),%r8b
3289		0x44, 0x8a, 0x20,              // mov    (%rax),%r12b
3290		0x42, 0x8a, 0x3c, 0x10,        // mov    (%rax,%r10,1),%dil
#	Line 2222 | Line 3313 | static bool arch_insn_skipper_tests()
3313		0                              // end
3314		};
3315		const int N_REGS = 20;
3316	<	unsigned long regs[N_REGS];
3316	>	SIGSEGV_REGISTER_TYPE regs[N_REGS];
3317		for (int i = 0; i < N_REGS; i++)
3318		regs[i] = i;
3319	<	const unsigned long start_code = (unsigned long)&code;
3319	>	const sigsegv_uintptr_t start_code = (sigsegv_uintptr_t)&code;
3320		regs[X86_REG_EIP] = start_code;
3321		while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
3322		&& ix86_skip_instruction(regs))
#	Line 2251 | Line 3342 | int main(void)
3342
3343		if (!sigsegv_install_handler(sigsegv_test_handler))
3344		return 4;
3345	<
3345	>
3346		#ifdef __GNUC__
3347		b_region = &&L_b_region1;
3348		e_region = &&L_e_region1;
3349		#endif
3350	<	L_b_region1:
3351	<	page[REF_INDEX] = REF_VALUE;
3352	<	if (page[REF_INDEX] != REF_VALUE)
3353	<	exit(20);
3354	<	page[REF_INDEX] = REF_VALUE;
3355	<	BARRIER();
3356	<	L_e_region1:
3350	>	/* This is a really awful hack but otherwise gcc is smart enough
3351	>	* (or bug'ous enough?) to optimize the labels and place them
3352	>	* e.g. at the "main" entry point, which is wrong.
3353	>	*/
3354	>	volatile int label_hack = 1;
3355	>	switch (label_hack) {
3356	>	case 1:
3357	>	L_b_region1:
3358	>	page[REF_INDEX] = REF_VALUE;
3359	>	if (page[REF_INDEX] != REF_VALUE)
3360	>	exit(20);
3361	>	page[REF_INDEX] = REF_VALUE;
3362	>	BARRIER();
3363	>	// fall-through
3364	>	case 2:
3365	>	L_e_region1:
3366	>	BARRIER();
3367	>	break;
3368	>	}
3369
3370		if (handler_called != 1)
3371		return 5;
#	Line 2293 | Line 3396 | int main(void)
3396		b_region = &&L_b_region2;
3397		e_region = &&L_e_region2;
3398		#endif
3399	<	L_b_region2:
3400	<	TEST_SKIP_INSTRUCTION(unsigned char);
3401	<	TEST_SKIP_INSTRUCTION(unsigned short);
3402	<	TEST_SKIP_INSTRUCTION(unsigned int);
3403	<	TEST_SKIP_INSTRUCTION(unsigned long);
3404	<	TEST_SKIP_INSTRUCTION(signed char);
3405	<	TEST_SKIP_INSTRUCTION(signed short);
3406	<	TEST_SKIP_INSTRUCTION(signed int);
3407	<	TEST_SKIP_INSTRUCTION(signed long);
3408	<	BARRIER();
3409	<	L_e_region2:
3410	<
3399	>	switch (label_hack) {
3400	>	case 1:
3401	>	L_b_region2:
3402	>	TEST_SKIP_INSTRUCTION(unsigned char);
3403	>	TEST_SKIP_INSTRUCTION(unsigned short);
3404	>	TEST_SKIP_INSTRUCTION(unsigned int);
3405	>	TEST_SKIP_INSTRUCTION(unsigned long);
3406	>	TEST_SKIP_INSTRUCTION(signed char);
3407	>	TEST_SKIP_INSTRUCTION(signed short);
3408	>	TEST_SKIP_INSTRUCTION(signed int);
3409	>	TEST_SKIP_INSTRUCTION(signed long);
3410	>	BARRIER();
3411	>	// fall-through
3412	>	case 2:
3413	>	L_e_region2:
3414	>	BARRIER();
3415	>	break;
3416	>	}
3417		if (!arch_insn_skipper_tests())
3418		return 20;
3419		#endif

Diff Legend

–	Removed lines
+	Added lines
<	Changed lines
>	Changed lines