[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.39 by gbeauche, 2003-12-20T21:50:08Z vs.
Revision 1.62 by gbeauche, 2006-03-30T22:45:49Z

#	Line 10 \| Line 10
10		* tjw@omnigroup.com Sun, 4 Jun 2000
11		* www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	* Basilisk II (C) 1997-2002 Christian Bauer
13	>	* Basilisk II (C) 1997-2005 Christian Bauer
14		*
15		* This program is free software; you can redistribute it and/or modify
16		* it under the terms of the GNU General Public License as published by
#	Line 97 \| Line 97 \| struct instruction_t {
97		char ra, rd;
98		};
99
100	<	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned int gpr)
100	>	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned long gpr)
101		{
102		// Get opcode and divide into fields
103	<	unsigned int opcode = ((unsigned int )nip);
103	>	unsigned int opcode = ((unsigned int )(unsigned long)nip);
104		unsigned int primop = opcode >> 26;
105		unsigned int exop = (opcode >> 1) & 0x3ff;
106		unsigned int ra = (opcode >> 16) & 0x1f;
#	Line 174 \| Line 174 \| static void powerpc_decode_instruction(i
174		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break;
175		case 45: // sthu
176		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break;
177	+	case 58: // ld, ldu, lwa
178	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
179	+	transfer_size = SIZE_QUAD;
180	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
181	+	imm &= ~3;
182	+	break;
183	+	case 62: // std, stdu, stq
184	+	transfer_type = SIGSEGV_TRANSFER_STORE;
185	+	transfer_size = SIZE_QUAD;
186	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
187	+	imm &= ~3;
188	+	break;
189		}
190
191		// Calculate effective address
#	Line 214 \| Line 226 \| static void powerpc_decode_instruction(i
226
227		#if HAVE_SIGINFO_T
228		// Generic extended signal handler
229	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
229	>	#if defined(__FreeBSD__)
230		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
231		#else
232		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
#	Line 234 \| Line 246 \| static void powerpc_decode_instruction(i
246		#endif
247		#if defined(__sun__)
248		#if (defined(sparc) \|\| defined(__sparc__))
249	+	#include <sys/stack.h>
250	+	#include <sys/regset.h>
251		#include <sys/ucontext.h>
252		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
253		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[REG_PC]
254	+	#define SIGSEGV_SPARC_GWINDOWS (((ucontext_t *)scp)->uc_mcontext.gwins)
255	+	#define SIGSEGV_SPARC_RWINDOW (struct rwindow )((char )SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
256	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
257	+	#define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction
258	+	#endif
259	+	#if defined(__i386__)
260	+	#include <sys/regset.h>
261	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
262	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[EIP]
263	+	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
264	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
265		#endif
266		#endif
267	<	#if defined(__FreeBSD__)
267	>	#if defined(__FreeBSD__) \|\| defined(__OpenBSD__)
268		#if (defined(i386) \|\| defined(__i386__))
269		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
270		#define SIGSEGV_REGISTER_FILE ((unsigned long )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
271		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
272		#endif
273		#endif
274	+	#if defined(__NetBSD__)
275	+	#if (defined(i386) \|\| defined(__i386__))
276	+	#include <sys/ucontext.h>
277	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
278	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP]
279	+	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
280	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
281	+	#endif
282	+	#if (defined(powerpc) \|\| defined(__powerpc__))
283	+	#include <sys/ucontext.h>
284	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
285	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_PC]
286	+	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIGSEGV_CONTEXT_REGS[_REG_PC], (unsigned long )&SIGSEGV_CONTEXT_REGS[_REG_R0]
287	+	#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
288	+	#endif
289	+	#endif
290		#if defined(__linux__)
291		#if (defined(i386) \|\| defined(__i386__))
292		#include <sys/ucontext.h>
#	Line 268 \| Line 309 \| static void powerpc_decode_instruction(i
309		#include <sys/ucontext.h>
310		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.regs)
311		#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->nip)
312	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&SIGSEGV_CONTEXT_REGS->nip, (unsigned int )(SIGSEGV_CONTEXT_REGS->gpr)
312	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIGSEGV_CONTEXT_REGS->nip, (unsigned long )(SIGSEGV_CONTEXT_REGS->gpr)
313		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
314		#endif
315		#if (defined(hppa) \|\| defined(__hppa__))
316		#undef SIGSEGV_FAULT_ADDRESS
317		#define SIGSEGV_FAULT_ADDRESS sip->si_ptr
318		#endif
319	+	#if (defined(arm) \|\| defined(__arm__))
320	+	#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
321	+	#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext)
322	+	#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.arm_pc)
323	+	#define SIGSEGV_REGISTER_FILE (&SIGSEGV_CONTEXT_REGS.arm_r0)
324	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
325	+	#endif
326		#endif
327		#endif
328
#	Line 304 \| Line 352 \| static void powerpc_decode_instruction(i
352		#define SIGSEGV_FAULT_HANDLER_ARGS sig, scp
353		#define SIGSEGV_FAULT_ADDRESS scp->regs->dar
354		#define SIGSEGV_FAULT_INSTRUCTION scp->regs->nip
355	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&scp->regs->nip, (unsigned int )(scp->regs->gpr)
355	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&scp->regs->nip, (unsigned long )(scp->regs->gpr)
356		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
357		#endif
358		#if (defined(alpha) \|\| defined(__alpha__))
#	Line 314 \| Line 362 \| static void powerpc_decode_instruction(i
362		#define SIGSEGV_FAULT_ADDRESS get_fault_address(scp)
363		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
364		#endif
365	+	#if (defined(arm) \|\| defined(__arm__))
366	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int r1, int r2, int r3, struct sigcontext sc
367	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp
368	+	#define SIGSEGV_FAULT_HANDLER_ARGS &sc
369	+	#define SIGSEGV_FAULT_ADDRESS scp->fault_address
370	+	#define SIGSEGV_FAULT_INSTRUCTION scp->arm_pc
371	+	#define SIGSEGV_REGISTER_FILE &scp->arm_r0
372	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
373	+	#endif
374		#endif
375
376		// Irix 5 or 6 on MIPS
#	Line 459 \| Line 516 \| static sigsegv_address_t get_fault_addre
516		#endif
517		#endif
518
519	+	#if HAVE_WIN32_EXCEPTIONS
520	+	#define WIN32_LEAN_AND_MEAN /* avoid including junk */
521	+	#include <windows.h>
522	+	#include <winerror.h>
523	+
524	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo
525	+	#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo
526	+	#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
527	+	#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord
528	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip
529	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
530	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
531	+	#endif
532	+
533		#if HAVE_MACH_EXCEPTIONS
534
535		// This can easily be extended to other Mach systems, but really who
#	Line 519 \| Line 590 \| if (ret != KERN_SUCCESS) { \
590		exit (1); \
591		}
592
593	+	#ifdef __ppc__
594	+	#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t
595	+	#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE
596	+	#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT
597	+	#define SIGSEGV_FAULT_INSTRUCTION state->srr0
598	+	#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
599	+	#define SIGSEGV_REGISTER_FILE (unsigned long )&state->srr0, (unsigned long )&state->r0
600	+	#endif
601	+	#ifdef __i386__
602	+	#ifdef i386_SAVED_STATE
603	+	#define SIGSEGV_THREAD_STATE_TYPE struct i386_saved_state
604	+	#define SIGSEGV_THREAD_STATE_FLAVOR i386_SAVED_STATE
605	+	#define SIGSEGV_THREAD_STATE_COUNT i386_SAVED_STATE_COUNT
606	+	#define SIGSEGV_REGISTER_FILE ((unsigned long )&state->edi) / EDI is the first GPR we consider */
607	+	#else
608	+	#define SIGSEGV_THREAD_STATE_TYPE struct i386_thread_state
609	+	#define SIGSEGV_THREAD_STATE_FLAVOR i386_THREAD_STATE
610	+	#define SIGSEGV_THREAD_STATE_COUNT i386_THREAD_STATE_COUNT
611	+	#define SIGSEGV_REGISTER_FILE ((unsigned long )&state->eax) / EAX is the first GPR we consider */
612	+	#endif
613	+	#define SIGSEGV_FAULT_INSTRUCTION state->eip
614	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
615	+	#endif
616		#define SIGSEGV_FAULT_ADDRESS code[1]
523	–	#define SIGSEGV_FAULT_INSTRUCTION get_fault_instruction(thread, state)
617		#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) ((code[0] == KERN_PROTECTION_FAILURE) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE)
618	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code, ppc_thread_state_t *state
618	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code, SIGSEGV_THREAD_STATE_TYPE *state
619		#define SIGSEGV_FAULT_HANDLER_ARGS thread, code, &state
527	–	#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
528	–	#define SIGSEGV_REGISTER_FILE &state->srr0, &state->r0
529	–
530	–	// Given a suspended thread, stuff the current instruction and
531	–	// registers into state.
532	–	//
533	–	// It would have been nice to have this be ppc/x86 independant which
534	–	// could have been done easily with a thread_state_t instead of
535	–	// ppc_thread_state_t, but because of the way this is called it is
536	–	// easier to do it this way.
537	–	#if (defined(ppc) \|\| defined(__ppc__))
538	–	static inline sigsegv_address_t get_fault_instruction(mach_port_t thread, ppc_thread_state_t *state)
539	–	{
540	–	kern_return_t krc;
541	–	mach_msg_type_number_t count;
542	–
543	–	count = MACHINE_THREAD_STATE_COUNT;
544	–	krc = thread_get_state(thread, MACHINE_THREAD_STATE, (thread_state_t)state, &count);
545	–	MACH_CHECK_ERROR (thread_get_state, krc);
546	–
547	–	return (sigsegv_address_t)state->srr0;
548	–	}
549	–	#endif
620
621		// Since there can only be one exception thread running at any time
622		// this is not a problem.
#	Line 636 \| Line 706 \| enum {
706		#endif
707		};
708		#endif
709	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
709	>	#if defined(__NetBSD__)
710	>	enum {
711	>	#if (defined(i386) \|\| defined(__i386__))
712	>	X86_REG_EIP = _REG_EIP,
713	>	X86_REG_EAX = _REG_EAX,
714	>	X86_REG_ECX = _REG_ECX,
715	>	X86_REG_EDX = _REG_EDX,
716	>	X86_REG_EBX = _REG_EBX,
717	>	X86_REG_ESP = _REG_ESP,
718	>	X86_REG_EBP = _REG_EBP,
719	>	X86_REG_ESI = _REG_ESI,
720	>	X86_REG_EDI = _REG_EDI
721	>	#endif
722	>	};
723	>	#endif
724	>	#if defined(__FreeBSD__)
725		enum {
726		#if (defined(i386) \|\| defined(__i386__))
727		X86_REG_EIP = 10,
#	Line 651 \| Line 736 \| enum {
736		#endif
737		};
738		#endif
739	+	#if defined(__OpenBSD__)
740	+	enum {
741	+	#if defined(__i386__)
742	+	// EDI is the first register we consider
743	+	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
744	+	#define DREG(REG) ((OREG(REG) - OREG(edi)) / 4)
745	+	X86_REG_EIP = DREG(eip), // 7
746	+	X86_REG_EAX = DREG(eax), // 6
747	+	X86_REG_ECX = DREG(ecx), // 5
748	+	X86_REG_EDX = DREG(edx), // 4
749	+	X86_REG_EBX = DREG(ebx), // 3
750	+	X86_REG_ESP = DREG(esp), // 10
751	+	X86_REG_EBP = DREG(ebp), // 2
752	+	X86_REG_ESI = DREG(esi), // 1
753	+	X86_REG_EDI = DREG(edi) // 0
754	+	#undef DREG
755	+	#undef OREG
756	+	#endif
757	+	};
758	+	#endif
759	+	#if defined(__sun__)
760	+	// Same as for Linux, need to check for x86-64
761	+	enum {
762	+	#if defined(__i386__)
763	+	X86_REG_EIP = EIP,
764	+	X86_REG_EAX = EAX,
765	+	X86_REG_ECX = ECX,
766	+	X86_REG_EDX = EDX,
767	+	X86_REG_EBX = EBX,
768	+	X86_REG_ESP = ESP,
769	+	X86_REG_EBP = EBP,
770	+	X86_REG_ESI = ESI,
771	+	X86_REG_EDI = EDI
772	+	#endif
773	+	};
774	+	#endif
775	+	#if defined(__APPLE__) && defined(__MACH__)
776	+	enum {
777	+	#ifdef i386_SAVED_STATE
778	+	// same as FreeBSD (in Open Darwin 8.0.1)
779	+	X86_REG_EIP = 10,
780	+	X86_REG_EAX = 7,
781	+	X86_REG_ECX = 6,
782	+	X86_REG_EDX = 5,
783	+	X86_REG_EBX = 4,
784	+	X86_REG_ESP = 13,
785	+	X86_REG_EBP = 2,
786	+	X86_REG_ESI = 1,
787	+	X86_REG_EDI = 0
788	+	#else
789	+	// new layout (MacOS X 10.4.4 for x86)
790	+	X86_REG_EIP = 10,
791	+	X86_REG_EAX = 0,
792	+	X86_REG_ECX = 2,
793	+	X86_REG_EDX = 4,
794	+	X86_REG_EBX = 1,
795	+	X86_REG_ESP = 7,
796	+	X86_REG_EBP = 6,
797	+	X86_REG_ESI = 5,
798	+	X86_REG_EDI = 4
799	+	#endif
800	+	};
801	+	#endif
802	+	#if defined(_WIN32)
803	+	enum {
804	+	#if (defined(i386) \|\| defined(__i386__))
805	+	X86_REG_EIP = 7,
806	+	X86_REG_EAX = 5,
807	+	X86_REG_ECX = 4,
808	+	X86_REG_EDX = 3,
809	+	X86_REG_EBX = 2,
810	+	X86_REG_ESP = 10,
811	+	X86_REG_EBP = 6,
812	+	X86_REG_ESI = 1,
813	+	X86_REG_EDI = 0
814	+	#endif
815	+	};
816	+	#endif
817		// FIXME: this is partly redundant with the instruction decoding phase
818		// to discover transfer type and register number
819		static inline int ix86_step_over_modrm(unsigned char * p)
#	Line 691 \| Line 854 \| static bool ix86_skip_instruction(unsign
854
855		if (eip == 0)
856		return false;
857	+	#ifdef _WIN32
858	+	if (IsBadCodePtr((FARPROC)eip))
859	+	return false;
860	+	#endif
861
862		transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
863		transfer_size_t transfer_size = SIZE_LONG;
#	Line 744 \| Line 911 \| static bool ix86_skip_instruction(unsign
911		#endif
912
913		// Decode instruction
914	+	int target_size = SIZE_UNKNOWN;
915		switch (eip[0]) {
916		case 0x0f:
917	+	target_size = transfer_size;
918		switch (eip[1]) {
919	+	case 0xbe: // MOVSX r32, r/m8
920		case 0xb6: // MOVZX r32, r/m8
921	+	transfer_size = SIZE_BYTE;
922	+	goto do_mov_extend;
923	+	case 0xbf: // MOVSX r32, r/m16
924		case 0xb7: // MOVZX r32, r/m16
925	<	switch (eip[2] & 0xc0) {
925	>	transfer_size = SIZE_WORD;
926	>	goto do_mov_extend;
927	>	do_mov_extend:
928	>	switch (eip[2] & 0xc0) {
929	>	case 0x80:
930	>	reg = (eip[2] >> 3) & 7;
931	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
932	>	break;
933	>	case 0x40:
934	>	reg = (eip[2] >> 3) & 7;
935	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
936	>	break;
937	>	case 0x00:
938	>	reg = (eip[2] >> 3) & 7;
939	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
940	>	break;
941	>	}
942	>	len += 3 + ix86_step_over_modrm(eip + 2);
943	>	break;
944	>	}
945	>	break;
946	>	#if defined(__x86_64__)
947	>	case 0x63: // MOVSXD r64, r/m32
948	>	if (has_rex && rex.W) {
949	>	transfer_size = SIZE_LONG;
950	>	target_size = SIZE_QUAD;
951	>	}
952	>	else if (transfer_size != SIZE_WORD) {
953	>	transfer_size = SIZE_LONG;
954	>	target_size = SIZE_QUAD;
955	>	}
956	>	switch (eip[1] & 0xc0) {
957		case 0x80:
958	<	reg = (eip[2] >> 3) & 7;
959	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
960	<	break;
958	>	reg = (eip[1] >> 3) & 7;
959	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
960	>	break;
961		case 0x40:
962	<	reg = (eip[2] >> 3) & 7;
963	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
964	<	break;
962	>	reg = (eip[1] >> 3) & 7;
963	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
964	>	break;
965		case 0x00:
966	<	reg = (eip[2] >> 3) & 7;
967	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
968	<	break;
966	>	reg = (eip[1] >> 3) & 7;
967	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
968	>	break;
969		}
970	<	len += 3 + ix86_step_over_modrm(eip + 2);
970	>	len += 2 + ix86_step_over_modrm(eip + 1);
971		break;
972	<	}
769	<	break;
972	>	#endif
973		case 0x8a: // MOV r8, r/m8
974		transfer_size = SIZE_BYTE;
975		case 0x8b: // MOV r32, r/m32 (or 16-bit operation)
#	Line 806 \| Line 1009 \| static bool ix86_skip_instruction(unsign
1009		len += 2 + ix86_step_over_modrm(eip + 1);
1010		break;
1011		}
1012	+	if (target_size == SIZE_UNKNOWN)
1013	+	target_size = transfer_size;
1014
1015		if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1016		// Unknown machine code, let it crash. Then patch the decoder
#	Line 833 \| Line 1038 \| static bool ix86_skip_instruction(unsign
1038		// Set 0 to the relevant register part
1039		// NOTE: this is only valid for MOV alike instructions
1040		int rloc = x86_reg_map[reg];
1041	<	switch (transfer_size) {
1041	>	switch (target_size) {
1042		case SIZE_BYTE:
1043		if (has_rex \|\| reg < 4)
1044		regs[rloc] = (regs[rloc] & ~0x00ffL);
#	Line 887 \| Line 1092 \| static bool ix86_skip_instruction(unsign
1092		"r12", "r13", "r14", "r15",
1093		};
1094		const char * reg_str = NULL;
1095	<	switch (transfer_size) {
1095	>	switch (target_size) {
1096		case SIZE_BYTE:
1097		reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
1098		break;
#	Line 910 \| Line 1115 \| static bool ix86_skip_instruction(unsign
1115
1116		// Decode and skip PPC instruction
1117		#if (defined(powerpc) \|\| defined(__powerpc__) \|\| defined(__ppc__))
1118	<	static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs)
1118	>	static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
1119		{
1120		instruction_t instr;
1121		powerpc_decode_instruction(&instr, *nip_p, regs);
#	Line 922 \| Line 1127 \| static bool powerpc_skip_instruction(uns
1127
1128		#if DEBUG
1129		printf("%08x: %s %s access", *nip_p,
1130	<	instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long",
1130	>	instr.transfer_size == SIZE_BYTE ? "byte" :
1131	>	instr.transfer_size == SIZE_WORD ? "word" :
1132	>	instr.transfer_size == SIZE_LONG ? "long" : "quad",
1133		instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1134
1135		if (instr.addr_mode == MODE_U \|\| instr.addr_mode == MODE_UX)
#	Line 1103 \| Line 1310 \| static bool mips_skip_instruction(greg_t
1310		return true;
1311		}
1312		#endif
1313	+
1314	+	// Decode and skip SPARC instruction
1315	+	#if (defined(sparc) \|\| defined(__sparc__))
1316	+	enum {
1317	+	#if (defined(__sun__))
1318	+	SPARC_REG_G1 = REG_G1,
1319	+	SPARC_REG_O0 = REG_O0,
1320	+	SPARC_REG_PC = REG_PC,
1321	+	SPARC_REG_nPC = REG_nPC
1322	+	#endif
1323	+	};
1324	+	static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
1325	+	{
1326	+	unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
1327	+
1328	+	if (pc == 0)
1329	+	return false;
1330	+
1331	+	#if DEBUG
1332	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1333	+	#endif
1334	+
1335	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1336	+	transfer_size_t transfer_size = SIZE_LONG;
1337	+	bool register_pair = false;
1338	+
1339	+	const unsigned int opcode = pc[0];
1340	+	if ((opcode >> 30) != 3)
1341	+	return false;
1342	+	switch ((opcode >> 19) & 0x3f) {
1343	+	case 9: // Load Signed Byte
1344	+	case 1: // Load Unsigned Byte
1345	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1346	+	transfer_size = SIZE_BYTE;
1347	+	break;
1348	+	case 10:// Load Signed Halfword
1349	+	case 2: // Load Unsigned Word
1350	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1351	+	transfer_size = SIZE_WORD;
1352	+	break;
1353	+	case 8: // Load Word
1354	+	case 0: // Load Unsigned Word
1355	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1356	+	transfer_size = SIZE_LONG;
1357	+	break;
1358	+	case 11:// Load Extended Word
1359	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1360	+	transfer_size = SIZE_QUAD;
1361	+	break;
1362	+	case 3: // Load Doubleword
1363	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1364	+	transfer_size = SIZE_LONG;
1365	+	register_pair = true;
1366	+	break;
1367	+	case 5: // Store Byte
1368	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1369	+	transfer_size = SIZE_BYTE;
1370	+	break;
1371	+	case 6: // Store Halfword
1372	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1373	+	transfer_size = SIZE_WORD;
1374	+	break;
1375	+	case 4: // Store Word
1376	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1377	+	transfer_size = SIZE_LONG;
1378	+	break;
1379	+	case 14:// Store Extended Word
1380	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1381	+	transfer_size = SIZE_QUAD;
1382	+	break;
1383	+	case 7: // Store Doubleword
1384	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1385	+	transfer_size = SIZE_LONG;
1386	+	register_pair = true;
1387	+	break;
1388	+	}
1389	+
1390	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1391	+	// Unknown machine code, let it crash. Then patch the decoder
1392	+	return false;
1393	+	}
1394	+
1395	+	const int reg = (opcode >> 25) & 0x1f;
1396	+
1397	+	#if DEBUG
1398	+	static const char * reg_names[] = {
1399	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1400	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1401	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1402	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1403	+	};
1404	+	printf("%s %s register %s\n",
1405	+	transfer_size == SIZE_BYTE ? "byte" :
1406	+	transfer_size == SIZE_WORD ? "word" :
1407	+	transfer_size == SIZE_LONG ? "long" :
1408	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1409	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1410	+	reg_names[reg]);
1411	+	#endif
1412	+
1413	+	// Zero target register in case of a load operation
1414	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1415	+	// FIXME: code to handle local & input registers is not tested
1416	+	if (reg >= 1 && reg < 8) {
1417	+	// global registers
1418	+	regs[reg - 1 + SPARC_REG_G1] = 0;
1419	+	}
1420	+	else if (reg >= 8 && reg < 16) {
1421	+	// output registers
1422	+	regs[reg - 8 + SPARC_REG_O0] = 0;
1423	+	}
1424	+	else if (reg >= 16 && reg < 24) {
1425	+	// local registers (in register windows)
1426	+	if (gwins)
1427	+	gwins->wbuf->rw_local[reg - 16] = 0;
1428	+	else
1429	+	rwin->rw_local[reg - 16] = 0;
1430	+	}
1431	+	else {
1432	+	// input registers (in register windows)
1433	+	if (gwins)
1434	+	gwins->wbuf->rw_in[reg - 24] = 0;
1435	+	else
1436	+	rwin->rw_in[reg - 24] = 0;
1437	+	}
1438	+	}
1439	+
1440	+	regs[SPARC_REG_PC] += 4;
1441	+	regs[SPARC_REG_nPC] += 4;
1442	+	return true;
1443	+	}
1444	+	#endif
1445		#endif
1446
1447	+	// Decode and skip ARM instruction
1448	+	#if (defined(arm) \|\| defined(__arm__))
1449	+	enum {
1450	+	#if (defined(__linux__))
1451	+	ARM_REG_PC = 15,
1452	+	ARM_REG_CPSR = 16
1453	+	#endif
1454	+	};
1455	+	static bool arm_skip_instruction(unsigned long * regs)
1456	+	{
1457	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
1458	+
1459	+	if (pc == 0)
1460	+	return false;
1461	+
1462	+	#if DEBUG
1463	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1464	+	#endif
1465	+
1466	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1467	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1468	+	enum { op_sdt = 1, op_sdth = 2 };
1469	+	int op = 0;
1470	+
1471	+	// Handle load/store instructions only
1472	+	const unsigned int opcode = pc[0];
1473	+	switch ((opcode >> 25) & 7) {
1474	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
1475	+	op = op_sdth;
1476	+	// Determine transfer size (S/H bits)
1477	+	switch ((opcode >> 5) & 3) {
1478	+	case 0: // SWP instruction
1479	+	break;
1480	+	case 1: // Unsigned halfwords
1481	+	case 3: // Signed halfwords
1482	+	transfer_size = SIZE_WORD;
1483	+	break;
1484	+	case 2: // Signed byte
1485	+	transfer_size = SIZE_BYTE;
1486	+	break;
1487	+	}
1488	+	break;
1489	+	case 2:
1490	+	case 3: // Single Data Transfer (LDR, STR)
1491	+	op = op_sdt;
1492	+	// Determine transfer size (B bit)
1493	+	if (((opcode >> 22) & 1) == 1)
1494	+	transfer_size = SIZE_BYTE;
1495	+	else
1496	+	transfer_size = SIZE_LONG;
1497	+	break;
1498	+	default:
1499	+	// FIXME: support load/store mutliple?
1500	+	return false;
1501	+	}
1502	+
1503	+	// Check for invalid transfer size (SWP instruction?)
1504	+	if (transfer_size == SIZE_UNKNOWN)
1505	+	return false;
1506	+
1507	+	// Determine transfer type (L bit)
1508	+	if (((opcode >> 20) & 1) == 1)
1509	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1510	+	else
1511	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1512	+
1513	+	// Compute offset
1514	+	int offset;
1515	+	if (((opcode >> 25) & 1) == 0) {
1516	+	if (op == op_sdt)
1517	+	offset = opcode & 0xfff;
1518	+	else if (op == op_sdth) {
1519	+	int rm = opcode & 0xf;
1520	+	if (((opcode >> 22) & 1) == 0) {
1521	+	// register offset
1522	+	offset = regs[rm];
1523	+	}
1524	+	else {
1525	+	// immediate offset
1526	+	offset = ((opcode >> 4) & 0xf0) \| (opcode & 0x0f);
1527	+	}
1528	+	}
1529	+	}
1530	+	else {
1531	+	const int rm = opcode & 0xf;
1532	+	const int sh = (opcode >> 7) & 0x1f;
1533	+	if (((opcode >> 4) & 1) == 1) {
1534	+	// we expect only legal load/store instructions
1535	+	printf("FATAL: invalid shift operand\n");
1536	+	return false;
1537	+	}
1538	+	const unsigned int v = regs[rm];
1539	+	switch ((opcode >> 5) & 3) {
1540	+	case 0: // logical shift left
1541	+	offset = sh ? v << sh : v;
1542	+	break;
1543	+	case 1: // logical shift right
1544	+	offset = sh ? v >> sh : 0;
1545	+	break;
1546	+	case 2: // arithmetic shift right
1547	+	if (sh)
1548	+	offset = ((signed int)v) >> sh;
1549	+	else
1550	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
1551	+	break;
1552	+	case 3: // rotate right
1553	+	if (sh)
1554	+	offset = (v >> sh) \| (v << (32 - sh));
1555	+	else
1556	+	offset = (v >> 1) \| ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
1557	+	break;
1558	+	}
1559	+	}
1560	+	if (((opcode >> 23) & 1) == 0)
1561	+	offset = -offset;
1562	+
1563	+	int rd = (opcode >> 12) & 0xf;
1564	+	int rn = (opcode >> 16) & 0xf;
1565	+	#if DEBUG
1566	+	static const char * reg_names[] = {
1567	+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1568	+	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
1569	+	};
1570	+	printf("%s %s register %s\n",
1571	+	transfer_size == SIZE_BYTE ? "byte" :
1572	+	transfer_size == SIZE_WORD ? "word" :
1573	+	transfer_size == SIZE_LONG ? "long" : "unknown",
1574	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1575	+	reg_names[rd]);
1576	+	#endif
1577	+
1578	+	unsigned int base = regs[rn];
1579	+	if (((opcode >> 24) & 1) == 1)
1580	+	base += offset;
1581	+
1582	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
1583	+	regs[rd] = 0;
1584	+
1585	+	if (((opcode >> 24) & 1) == 0) // post-index addressing
1586	+	regs[rn] += offset;
1587	+	else if (((opcode >> 21) & 1) == 1) // write-back address into base
1588	+	regs[rn] = base;
1589	+
1590	+	regs[ARM_REG_PC] += 4;
1591	+	return true;
1592	+	}
1593	+	#endif
1594	+
1595	+
1596		// Fallbacks
1597		#ifndef SIGSEGV_FAULT_INSTRUCTION
1598		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_INVALID_PC
#	Line 1126 \| Line 1614 \| static bool mips_skip_instruction(greg_t
1614		* SIGSEGV global handler
1615		*/
1616
1129	–	#if defined(HAVE_SIGSEGV_RECOVERY) \|\| defined(HAVE_MACH_EXCEPTIONS)
1617		// This function handles the badaccess to memory.
1618		// It is called from the signal handler or the exception handler.
1619		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
1620		{
1621	+	#ifdef HAVE_MACH_EXCEPTIONS
1622	+	// We must match the initial count when writing back the CPU state registers
1623	+	kern_return_t krc;
1624	+	mach_msg_type_number_t count;
1625	+
1626	+	count = SIGSEGV_THREAD_STATE_COUNT;
1627	+	krc = thread_get_state(thread, SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state, &count);
1628	+	MACH_CHECK_ERROR (thread_get_state, krc);
1629	+	#endif
1630	+
1631		sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
1632		sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
1633
#	Line 1149 \| Line 1646 \| static bool handle_badaccess(SIGSEGV_FAU
1646		// is modified off of the stack, in Mach we
1647		// need to actually call thread_set_state to
1648		// have the register values updated.
1152	–	kern_return_t krc;
1153	–
1649		krc = thread_set_state(thread,
1650	<	MACHINE_THREAD_STATE, (thread_state_t)state,
1651	<	MACHINE_THREAD_STATE_COUNT);
1652	<	MACH_CHECK_ERROR (thread_get_state, krc);
1650	>	SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state,
1651	>	count);
1652	>	MACH_CHECK_ERROR (thread_set_state, krc);
1653		#endif
1654		return true;
1655		}
1656		break;
1657		#endif
1658	+	case SIGSEGV_RETURN_FAILURE:
1659	+	// We can't do anything with the fault_address, dump state?
1660	+	if (sigsegv_state_dumper != 0)
1661	+	sigsegv_state_dumper(fault_address, fault_instruction);
1662	+	break;
1663		}
1164	–
1165	–	// We can't do anything with the fault_address, dump state?
1166	–	if (sigsegv_state_dumper != 0)
1167	–	sigsegv_state_dumper(fault_address, fault_instruction);
1664
1665		return false;
1666		}
1171	–	#endif
1667
1668
1669		/*
#	Line 1205 \| Line 1700 \| forward_exception(mach_port_t thread_por
1700		mach_port_t port;
1701		exception_behavior_t behavior;
1702		thread_state_flavor_t flavor;
1703	<	thread_state_t thread_state;
1703	>	thread_state_data_t thread_state;
1704		mach_msg_type_number_t thread_state_count;
1705
1706		for (portIndex = 0; portIndex < oldExceptionPorts->maskCount; portIndex++) {
#	Line 1230 \| Line 1725 \| forward_exception(mach_port_t thread_por
1725
1726		if (behavior != EXCEPTION_DEFAULT) {
1727		thread_state_count = THREAD_STATE_MAX;
1728	<	kret = thread_get_state (thread_port, flavor, thread_state,
1728	>	kret = thread_get_state (thread_port, flavor, (natural_t *)&thread_state,
1729		&thread_state_count);
1730		MACH_CHECK_ERROR (thread_get_state, kret);
1731		}
#	Line 1246 \| Line 1741 \| forward_exception(mach_port_t thread_por
1741		// fprintf(stderr, "forwarding to exception_raise_state\n");
1742		kret = exception_raise_state(port, exception_type, exception_data,
1743		data_count, &flavor,
1744	<	thread_state, thread_state_count,
1745	<	thread_state, &thread_state_count);
1744	>	(natural_t *)&thread_state, thread_state_count,
1745	>	(natural_t *)&thread_state, &thread_state_count);
1746		MACH_CHECK_ERROR (exception_raise_state, kret);
1747		break;
1748		case EXCEPTION_STATE_IDENTITY:
#	Line 1255 \| Line 1750 \| forward_exception(mach_port_t thread_por
1750		kret = exception_raise_state_identity(port, thread_port, task_port,
1751		exception_type, exception_data,
1752		data_count, &flavor,
1753	<	thread_state, thread_state_count,
1754	<	thread_state, &thread_state_count);
1753	>	(natural_t *)&thread_state, thread_state_count,
1754	>	(natural_t *)&thread_state, &thread_state_count);
1755		MACH_CHECK_ERROR (exception_raise_state_identity, kret);
1756		break;
1757		default:
#	Line 1265 \| Line 1760 \| forward_exception(mach_port_t thread_por
1760		}
1761
1762		if (behavior != EXCEPTION_DEFAULT) {
1763	<	kret = thread_set_state (thread_port, flavor, thread_state,
1763	>	kret = thread_set_state (thread_port, flavor, (natural_t *)&thread_state,
1764		thread_state_count);
1765		MACH_CHECK_ERROR (thread_set_state, kret);
1766		}
#	Line 1300 \| Line 1795 \| catch_exception_raise(mach_port_t except
1795		exception_data_t code,
1796		mach_msg_type_number_t codeCount)
1797		{
1798	<	ppc_thread_state_t state;
1798	>	SIGSEGV_THREAD_STATE_TYPE state;
1799		kern_return_t krc;
1800
1801		if ((exception == EXC_BAD_ACCESS) && (codeCount >= 2)) {
#	Line 1439 \| Line 1934 \| static bool sigsegv_do_install_handler(s
1934		// addressing modes) used in PPC instructions, you will need the
1935		// GPR state anyway.
1936		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
1937	<	EXCEPTION_DEFAULT, MACHINE_THREAD_STATE);
1937	>	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
1938		if (krc != KERN_SUCCESS) {
1939		mach_error("thread_set_exception_ports", krc);
1940		return false;
#	Line 1462 \| Line 1957 \| static bool sigsegv_do_install_handler(s
1957		}
1958		#endif
1959
1960	+	#ifdef HAVE_WIN32_EXCEPTIONS
1961	+	static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo)
1962	+	{
1963	+	if (sigsegv_fault_handler != NULL
1964	+	&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
1965	+	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
1966	+	&& handle_badaccess(ExceptionInfo))
1967	+	return EXCEPTION_CONTINUE_EXECUTION;
1968	+
1969	+	return EXCEPTION_CONTINUE_SEARCH;
1970	+	}
1971	+
1972	+	#if defined __CYGWIN__ && defined __i386__
1973	+	/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin
1974	+	installs a global exception handler. We have to dig deep in order to install
1975	+	our main_exception_filter. */
1976	+
1977	+	/* Data structures for the current thread's exception handler chain.
1978	+	On the x86 Windows uses register fs, offset 0 to point to the current
1979	+	exception handler; Cygwin mucks with it, so we must do the same... :-/ */
1980	+
1981	+	/* Magic taken from winsup/cygwin/include/exceptions.h. */
1982	+
1983	+	struct exception_list {
1984	+	struct exception_list *prev;
1985	+	int (handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
1986	+	};
1987	+	typedef struct exception_list exception_list;
1988	+
1989	+	/* Magic taken from winsup/cygwin/exceptions.cc. */
1990	+
1991	+	__asm__ (".equ __except_list,0");
1992	+
1993	+	extern exception_list *_except_list __asm__ ("%fs:__except_list");
1994	+
1995	+	/* For debugging. _except_list is not otherwise accessible from gdb. */
1996	+	static exception_list *
1997	+	debug_get_except_list ()
1998	+	{
1999	+	return _except_list;
2000	+	}
2001	+
2002	+	/* Cygwin's original exception handler. */
2003	+	static int (cygwin_exception_handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
2004	+
2005	+	/* Our exception handler. */
2006	+	static int
2007	+	libsigsegv_exception_handler (EXCEPTION_RECORD exception, void frame, CONTEXT context, void dispatch)
2008	+	{
2009	+	EXCEPTION_POINTERS ExceptionInfo;
2010	+	ExceptionInfo.ExceptionRecord = exception;
2011	+	ExceptionInfo.ContextRecord = context;
2012	+	if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH)
2013	+	return cygwin_exception_handler (exception, frame, context, dispatch);
2014	+	else
2015	+	return 0;
2016	+	}
2017	+
2018	+	static void
2019	+	do_install_main_exception_filter ()
2020	+	{
2021	+	/* We cannot insert any handler into the chain, because such handlers
2022	+	must lie on the stack (?). Instead, we have to replace(!) Cygwin's
2023	+	global exception handler. */
2024	+	cygwin_exception_handler = _except_list->handler;
2025	+	_except_list->handler = libsigsegv_exception_handler;
2026	+	}
2027	+
2028	+	#else
2029	+
2030	+	static void
2031	+	do_install_main_exception_filter ()
2032	+	{
2033	+	SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter);
2034	+	}
2035	+	#endif
2036	+
2037	+	static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler)
2038	+	{
2039	+	static bool main_exception_filter_installed = false;
2040	+	if (!main_exception_filter_installed) {
2041	+	do_install_main_exception_filter();
2042	+	main_exception_filter_installed = true;
2043	+	}
2044	+	sigsegv_fault_handler = handler;
2045	+	return true;
2046	+	}
2047	+	#endif
2048	+
2049		bool sigsegv_install_handler(sigsegv_fault_handler_t handler)
2050		{
2051		#if defined(HAVE_SIGSEGV_RECOVERY)
#	Line 1472 \| Line 2056 \| bool sigsegv_install_handler(sigsegv_fau
2056		if (success)
2057		sigsegv_fault_handler = handler;
2058		return success;
2059	<	#elif defined(HAVE_MACH_EXCEPTIONS)
2059	>	#elif defined(HAVE_MACH_EXCEPTIONS) \|\| defined(HAVE_WIN32_EXCEPTIONS)
2060		return sigsegv_do_install_handler(handler);
2061		#else
2062		// FAIL: no siginfo_t nor sigcontext subterfuge is available
#	Line 1498 \| Line 2082 \| void sigsegv_deinstall_handler(void)
2082		SIGSEGV_ALL_SIGNALS
2083		#undef FAULT_HANDLER
2084		#endif
2085	+	#ifdef HAVE_WIN32_EXCEPTIONS
2086	+	sigsegv_fault_handler = NULL;
2087	+	#endif
2088		}
2089
2090
#	Line 1519 \| Line 2106 \| void sigsegv_set_dump_state(sigsegv_stat
2106		#include <stdio.h>
2107		#include <stdlib.h>
2108		#include <fcntl.h>
2109	+	#ifdef HAVE_SYS_MMAN_H
2110		#include <sys/mman.h>
2111	+	#endif
2112		#include "vm_alloc.h"
2113
2114		const int REF_INDEX = 123;
#	Line 1529 \| Line 2118 \| static int page_size;
2118		static volatile char * page = 0;
2119		static volatile int handler_called = 0;
2120
2121	+	/* Barriers */
2122	+	#ifdef __GNUC__
2123	+	#define BARRIER() asm volatile ("" : : : "memory")
2124	+	#else
2125	+	#define BARRIER() /* nothing */
2126	+	#endif
2127	+
2128		#ifdef __GNUC__
2129		// Code range where we expect the fault to come from
2130		static void b_region, e_region;
#	Line 1562 \| Line 2158 \| static sigsegv_return_t sigsegv_test_han
2158		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
2159		static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2160		{
2161	+	#if DEBUG
2162	+	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
2163	+	#endif
2164		if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
2165		#ifdef __GNUC__
2166		// Make sure reported fault instruction address falls into
#	Line 1617 \| Line 2216 \| static bool arch_insn_skipper_tests()
2216		0x4c, 0x89, 0x18, // mov %r11,(%rax)
2217		0x4a, 0x89, 0x0c, 0x10, // mov %rcx,(%rax,%r10,1)
2218		0x4e, 0x89, 0x1c, 0x10, // mov %r11,(%rax,%r10,1)
2219	+	0x63, 0x47, 0x04, // movslq 4(%rdi),%eax
2220	+	0x48, 0x63, 0x47, 0x04, // movslq 4(%rdi),%rax
2221		#endif
2222		0 // end
2223		};
#	Line 1640 \| Line 2241 \| int main(void)
2241		if (vm_init() < 0)
2242		return 1;
2243
2244	<	page_size = getpagesize();
2244	>	page_size = vm_get_page_size();
2245		if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED)
2246		return 2;
2247
#	Line 1660 \| Line 2261 \| int main(void)
2261		if (page[REF_INDEX] != REF_VALUE)
2262		exit(20);
2263		page[REF_INDEX] = REF_VALUE;
2264	+	BARRIER();
2265		L_e_region1:
2266
2267		if (handler_called != 1)
#	Line 1696 \| Line 2298 \| int main(void)
2298		TEST_SKIP_INSTRUCTION(unsigned short);
2299		TEST_SKIP_INSTRUCTION(unsigned int);
2300		TEST_SKIP_INSTRUCTION(unsigned long);
2301	+	TEST_SKIP_INSTRUCTION(signed char);
2302	+	TEST_SKIP_INSTRUCTION(signed short);
2303	+	TEST_SKIP_INSTRUCTION(signed int);
2304	+	TEST_SKIP_INSTRUCTION(signed long);
2305	+	BARRIER();
2306		L_e_region2:
2307
2308		if (!arch_insn_skipper_tests())

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.39 by gbeauche, 2003-12-20T21:50:08Z vs. Revision 1.62 by gbeauche, 2006-03-30T22:45:49Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.39 by gbeauche, 2003-12-20T21:50:08Z vs.
Revision 1.62 by gbeauche, 2006-03-30T22:45:49Z