[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.34 by gbeauche, 2003-11-10T23:47:39Z vs.
Revision 1.52 by gbeauche, 2005-01-30T21:42:14Z

#	Line 10 \| Line 10
10		* tjw@omnigroup.com Sun, 4 Jun 2000
11		* www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	* Basilisk II (C) 1997-2002 Christian Bauer
13	>	* Basilisk II (C) 1997-2005 Christian Bauer
14		*
15		* This program is free software; you can redistribute it and/or modify
16		* it under the terms of the GNU General Public License as published by
#	Line 36 \| Line 36
36		#endif
37
38		#include <list>
39	+	#include <stdio.h>
40		#include <signal.h>
41		#include "sigsegv.h"
42
#	Line 96 \| Line 97 \| struct instruction_t {
97		char ra, rd;
98		};
99
100	<	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned int gpr)
100	>	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned long gpr)
101		{
102		// Get opcode and divide into fields
103	<	unsigned int opcode = ((unsigned int )nip);
103	>	unsigned int opcode = ((unsigned int )(unsigned long)nip);
104		unsigned int primop = opcode >> 26;
105		unsigned int exop = (opcode >> 1) & 0x3ff;
106		unsigned int ra = (opcode >> 16) & 0x1f;
#	Line 173 \| Line 174 \| static void powerpc_decode_instruction(i
174		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break;
175		case 45: // sthu
176		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break;
177	+	case 58: // ld, ldu, lwa
178	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
179	+	transfer_size = SIZE_QUAD;
180	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
181	+	imm &= ~3;
182	+	break;
183	+	case 62: // std, stdu, stq
184	+	transfer_type = SIGSEGV_TRANSFER_STORE;
185	+	transfer_size = SIZE_QUAD;
186	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
187	+	imm &= ~3;
188	+	break;
189		}
190
191		// Calculate effective address
#	Line 213 \| Line 226 \| static void powerpc_decode_instruction(i
226
227		#if HAVE_SIGINFO_T
228		// Generic extended signal handler
229	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
229	>	#if defined(__FreeBSD__)
230		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
231		#else
232		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
#	Line 222 \| Line 235 \| static void powerpc_decode_instruction(i
235		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t sip, void scp
236		#define SIGSEGV_FAULT_HANDLER_ARGS sip, scp
237		#define SIGSEGV_FAULT_ADDRESS sip->si_addr
238	+	#if (defined(sgi) \|\| defined(__sgi))
239	+	#include <ucontext.h>
240	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
241	+	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
242	+	#if (defined(mips) \|\| defined(__mips))
243	+	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
244	+	#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
245	+	#endif
246	+	#endif
247		#if defined(__sun__)
248		#if (defined(sparc) \|\| defined(__sparc__))
249	+	#include <sys/stack.h>
250	+	#include <sys/regset.h>
251		#include <sys/ucontext.h>
252		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
253		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[REG_PC]
254	+	#define SIGSEGV_SPARC_GWINDOWS (((ucontext_t *)scp)->uc_mcontext.gwins)
255	+	#define SIGSEGV_SPARC_RWINDOW (struct rwindow )((char )SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
256	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
257	+	#define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction
258		#endif
259		#endif
260		#if defined(__FreeBSD__)
#	Line 236 \| Line 264 \| static void powerpc_decode_instruction(i
264		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
265		#endif
266		#endif
267	+	#if defined(__NetBSD__)
268	+	#if (defined(i386) \|\| defined(__i386__))
269	+	#include <sys/ucontext.h>
270	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
271	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP]
272	+	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
273	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
274	+	#endif
275	+	#endif
276		#if defined(__linux__)
277		#if (defined(i386) \|\| defined(__i386__))
278		#include <sys/ucontext.h>
#	Line 258 \| Line 295 \| static void powerpc_decode_instruction(i
295		#include <sys/ucontext.h>
296		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.regs)
297		#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->nip)
298	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&SIGSEGV_CONTEXT_REGS->nip, (unsigned int )(SIGSEGV_CONTEXT_REGS->gpr)
298	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIGSEGV_CONTEXT_REGS->nip, (unsigned long )(SIGSEGV_CONTEXT_REGS->gpr)
299		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
300		#endif
301	+	#if (defined(hppa) \|\| defined(__hppa__))
302	+	#undef SIGSEGV_FAULT_ADDRESS
303	+	#define SIGSEGV_FAULT_ADDRESS sip->si_ptr
304	+	#endif
305	+	#if (defined(arm) \|\| defined(__arm__))
306	+	#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
307	+	#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext)
308	+	#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.arm_pc)
309	+	#define SIGSEGV_REGISTER_FILE (&SIGSEGV_CONTEXT_REGS.arm_r0)
310	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
311	+	#endif
312		#endif
313		#endif
314
#	Line 290 \| Line 338 \| static void powerpc_decode_instruction(i
338		#define SIGSEGV_FAULT_HANDLER_ARGS sig, scp
339		#define SIGSEGV_FAULT_ADDRESS scp->regs->dar
340		#define SIGSEGV_FAULT_INSTRUCTION scp->regs->nip
341	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&scp->regs->nip, (unsigned int )(scp->regs->gpr)
341	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&scp->regs->nip, (unsigned long )(scp->regs->gpr)
342		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
343		#endif
344		#if (defined(alpha) \|\| defined(__alpha__))
#	Line 300 \| Line 348 \| static void powerpc_decode_instruction(i
348		#define SIGSEGV_FAULT_ADDRESS get_fault_address(scp)
349		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
350		#endif
351	+	#if (defined(arm) \|\| defined(__arm__))
352	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int r1, int r2, int r3, struct sigcontext sc
353	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp
354	+	#define SIGSEGV_FAULT_HANDLER_ARGS &sc
355	+	#define SIGSEGV_FAULT_ADDRESS scp->fault_address
356	+	#define SIGSEGV_FAULT_INSTRUCTION scp->arm_pc
357	+	#define SIGSEGV_REGISTER_FILE &scp->arm_r0
358	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
359	+	#endif
360		#endif
361
362		// Irix 5 or 6 on MIPS
363	<	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(__SYSTYPE_SVR4))
363	>	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(_SYSTYPE_SVR4))
364		#include <ucontext.h>
365		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp
366		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp
367	<	#define SIGSEGV_FAULT_ADDRESS scp->sc_badvaddr
367	>	#define SIGSEGV_FAULT_ADDRESS (unsigned long)scp->sc_badvaddr
368	>	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)scp->sc_pc
369		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
370		#endif
371
#	Line 380 \| Line 438 \| static sigsegv_address_t get_fault_addre
438		#endif
439		#endif
440		#if defined(__FreeBSD__)
383	–	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
441		#if (defined(i386) \|\| defined(__i386__))
442	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
443		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext scp, char addr
444		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr
445		#define SIGSEGV_FAULT_ADDRESS addr
#	Line 389 \| Line 447 \| static sigsegv_address_t get_fault_addre
447		#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi)
448		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
449		#endif
450	+	#if (defined(alpha) \|\| defined(__alpha__))
451	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
452	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, char addr, struct sigcontext scp
453	+	#define SIGSEGV_FAULT_HANDLER_ARGS sig, addr, scp
454	+	#define SIGSEGV_FAULT_ADDRESS addr
455	+	#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
456	+	#endif
457		#endif
458
459		// Extract fault address out of a sigcontext
#	Line 437 \| Line 502 \| static sigsegv_address_t get_fault_addre
502		#endif
503		#endif
504
505	+	#if HAVE_WIN32_EXCEPTIONS
506	+	#define WIN32_LEAN_AND_MEAN /* avoid including junk */
507	+	#include <windows.h>
508	+	#include <winerror.h>
509	+
510	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo
511	+	#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo
512	+	#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
513	+	#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord
514	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip
515	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
516	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
517	+	#endif
518	+
519		#if HAVE_MACH_EXCEPTIONS
520
521		// This can easily be extended to other Mach systems, but really who
#	Line 614 \| Line 693 \| enum {
693		#endif
694		};
695		#endif
696	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
696	>	#if defined(__NetBSD__)
697	>	enum {
698	>	#if (defined(i386) \|\| defined(__i386__))
699	>	X86_REG_EIP = _REG_EIP,
700	>	X86_REG_EAX = _REG_EAX,
701	>	X86_REG_ECX = _REG_ECX,
702	>	X86_REG_EDX = _REG_EDX,
703	>	X86_REG_EBX = _REG_EBX,
704	>	X86_REG_ESP = _REG_ESP,
705	>	X86_REG_EBP = _REG_EBP,
706	>	X86_REG_ESI = _REG_ESI,
707	>	X86_REG_EDI = _REG_EDI
708	>	#endif
709	>	};
710	>	#endif
711	>	#if defined(__FreeBSD__)
712		enum {
713		#if (defined(i386) \|\| defined(__i386__))
714		X86_REG_EIP = 10,
#	Line 629 \| Line 723 \| enum {
723		#endif
724		};
725		#endif
726	+	#if defined(_WIN32)
727	+	enum {
728	+	#if (defined(i386) \|\| defined(__i386__))
729	+	X86_REG_EIP = 7,
730	+	X86_REG_EAX = 5,
731	+	X86_REG_ECX = 4,
732	+	X86_REG_EDX = 3,
733	+	X86_REG_EBX = 2,
734	+	X86_REG_ESP = 10,
735	+	X86_REG_EBP = 6,
736	+	X86_REG_ESI = 1,
737	+	X86_REG_EDI = 0
738	+	#endif
739	+	};
740	+	#endif
741		// FIXME: this is partly redundant with the instruction decoding phase
742		// to discover transfer type and register number
743		static inline int ix86_step_over_modrm(unsigned char * p)
#	Line 669 \| Line 778 \| static bool ix86_skip_instruction(unsign
778
779		if (eip == 0)
780		return false;
781	+	#ifdef _WIN32
782	+	if (IsBadCodePtr((FARPROC)eip))
783	+	return false;
784	+	#endif
785
786		transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
787		transfer_size_t transfer_size = SIZE_LONG;
#	Line 722 \| Line 835 \| static bool ix86_skip_instruction(unsign
835		#endif
836
837		// Decode instruction
838	+	int target_size = SIZE_UNKNOWN;
839		switch (eip[0]) {
840		case 0x0f:
841	+	target_size = transfer_size;
842		switch (eip[1]) {
843	+	case 0xbe: // MOVSX r32, r/m8
844		case 0xb6: // MOVZX r32, r/m8
845	+	transfer_size = SIZE_BYTE;
846	+	goto do_mov_extend;
847	+	case 0xbf: // MOVSX r32, r/m16
848		case 0xb7: // MOVZX r32, r/m16
849	<	switch (eip[2] & 0xc0) {
850	<	case 0x80:
851	<	reg = (eip[2] >> 3) & 7;
852	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
853	<	break;
854	<	case 0x40:
855	<	reg = (eip[2] >> 3) & 7;
856	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
857	<	break;
858	<	case 0x00:
859	<	reg = (eip[2] >> 3) & 7;
860	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
861	<	break;
862	<	}
863	<	len += 3 + ix86_step_over_modrm(eip + 2);
864	<	break;
849	>	transfer_size = SIZE_WORD;
850	>	goto do_mov_extend;
851	>	do_mov_extend:
852	>	switch (eip[2] & 0xc0) {
853	>	case 0x80:
854	>	reg = (eip[2] >> 3) & 7;
855	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
856	>	break;
857	>	case 0x40:
858	>	reg = (eip[2] >> 3) & 7;
859	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
860	>	break;
861	>	case 0x00:
862	>	reg = (eip[2] >> 3) & 7;
863	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
864	>	break;
865	>	}
866	>	len += 3 + ix86_step_over_modrm(eip + 2);
867	>	break;
868		}
869		break;
870		case 0x8a: // MOV r8, r/m8
#	Line 784 \| Line 906 \| static bool ix86_skip_instruction(unsign
906		len += 2 + ix86_step_over_modrm(eip + 1);
907		break;
908		}
909	+	if (target_size == SIZE_UNKNOWN)
910	+	target_size = transfer_size;
911
912		if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
913		// Unknown machine code, let it crash. Then patch the decoder
#	Line 811 \| Line 935 \| static bool ix86_skip_instruction(unsign
935		// Set 0 to the relevant register part
936		// NOTE: this is only valid for MOV alike instructions
937		int rloc = x86_reg_map[reg];
938	<	switch (transfer_size) {
938	>	switch (target_size) {
939		case SIZE_BYTE:
940	<	if (!has_rex && reg >= 4)
941	<	regs[rloc - 4] = (regs[rloc - 4] & ~0xff00L);
942	<	else
943	<	regs[rloc] = (regs[rloc] & ~0xffL);
940	>	if (has_rex \|\| reg < 4)
941	>	regs[rloc] = (regs[rloc] & ~0x00ffL);
942	>	else {
943	>	rloc = x86_reg_map[reg - 4];
944	>	regs[rloc] = (regs[rloc] & ~0xff00L);
945	>	}
946		break;
947		case SIZE_WORD:
948		regs[rloc] = (regs[rloc] & ~0xffffL);
#	Line 863 \| Line 989 \| static bool ix86_skip_instruction(unsign
989		"r12", "r13", "r14", "r15",
990		};
991		const char * reg_str = NULL;
992	<	switch (transfer_size) {
992	>	switch (target_size) {
993		case SIZE_BYTE:
994		reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
995		break;
#	Line 886 \| Line 1012 \| static bool ix86_skip_instruction(unsign
1012
1013		// Decode and skip PPC instruction
1014		#if (defined(powerpc) \|\| defined(__powerpc__) \|\| defined(__ppc__))
1015	<	static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs)
1015	>	static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
1016		{
1017		instruction_t instr;
1018		powerpc_decode_instruction(&instr, *nip_p, regs);
#	Line 898 \| Line 1024 \| static bool powerpc_skip_instruction(uns
1024
1025		#if DEBUG
1026		printf("%08x: %s %s access", *nip_p,
1027	<	instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long",
1027	>	instr.transfer_size == SIZE_BYTE ? "byte" :
1028	>	instr.transfer_size == SIZE_WORD ? "word" :
1029	>	instr.transfer_size == SIZE_LONG ? "long" : "quad",
1030		instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1031
1032		if (instr.addr_mode == MODE_U \|\| instr.addr_mode == MODE_UX)
#	Line 916 \| Line 1044 \| static bool powerpc_skip_instruction(uns
1044		return true;
1045		}
1046		#endif
1047	+
1048	+	// Decode and skip MIPS instruction
1049	+	#if (defined(mips) \|\| defined(__mips))
1050	+	enum {
1051	+	#if (defined(sgi) \|\| defined(__sgi))
1052	+	MIPS_REG_EPC = 35,
1053		#endif
1054	+	};
1055	+	static bool mips_skip_instruction(greg_t * regs)
1056	+	{
1057	+	unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC];
1058	+
1059	+	if (epc == 0)
1060	+	return false;
1061	+
1062	+	#if DEBUG
1063	+	printf("IP: %p [%08x]\n", epc, epc[0]);
1064	+	#endif
1065	+
1066	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1067	+	transfer_size_t transfer_size = SIZE_LONG;
1068	+	int direction = 0;
1069	+
1070	+	const unsigned int opcode = epc[0];
1071	+	switch (opcode >> 26) {
1072	+	case 32: // Load Byte
1073	+	case 36: // Load Byte Unsigned
1074	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1075	+	transfer_size = SIZE_BYTE;
1076	+	break;
1077	+	case 33: // Load Halfword
1078	+	case 37: // Load Halfword Unsigned
1079	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1080	+	transfer_size = SIZE_WORD;
1081	+	break;
1082	+	case 35: // Load Word
1083	+	case 39: // Load Word Unsigned
1084	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1085	+	transfer_size = SIZE_LONG;
1086	+	break;
1087	+	case 34: // Load Word Left
1088	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1089	+	transfer_size = SIZE_LONG;
1090	+	direction = -1;
1091	+	break;
1092	+	case 38: // Load Word Right
1093	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1094	+	transfer_size = SIZE_LONG;
1095	+	direction = 1;
1096	+	break;
1097	+	case 55: // Load Doubleword
1098	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1099	+	transfer_size = SIZE_QUAD;
1100	+	break;
1101	+	case 26: // Load Doubleword Left
1102	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1103	+	transfer_size = SIZE_QUAD;
1104	+	direction = -1;
1105	+	break;
1106	+	case 27: // Load Doubleword Right
1107	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1108	+	transfer_size = SIZE_QUAD;
1109	+	direction = 1;
1110	+	break;
1111	+	case 40: // Store Byte
1112	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1113	+	transfer_size = SIZE_BYTE;
1114	+	break;
1115	+	case 41: // Store Halfword
1116	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1117	+	transfer_size = SIZE_WORD;
1118	+	break;
1119	+	case 43: // Store Word
1120	+	case 42: // Store Word Left
1121	+	case 46: // Store Word Right
1122	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1123	+	transfer_size = SIZE_LONG;
1124	+	break;
1125	+	case 63: // Store Doubleword
1126	+	case 44: // Store Doubleword Left
1127	+	case 45: // Store Doubleword Right
1128	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1129	+	transfer_size = SIZE_QUAD;
1130	+	break;
1131	+	/* Misc instructions unlikely to be used within CPU emulators */
1132	+	case 48: // Load Linked Word
1133	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1134	+	transfer_size = SIZE_LONG;
1135	+	break;
1136	+	case 52: // Load Linked Doubleword
1137	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1138	+	transfer_size = SIZE_QUAD;
1139	+	break;
1140	+	case 56: // Store Conditional Word
1141	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1142	+	transfer_size = SIZE_LONG;
1143	+	break;
1144	+	case 60: // Store Conditional Doubleword
1145	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1146	+	transfer_size = SIZE_QUAD;
1147	+	break;
1148	+	}
1149	+
1150	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1151	+	// Unknown machine code, let it crash. Then patch the decoder
1152	+	return false;
1153	+	}
1154	+
1155	+	// Zero target register in case of a load operation
1156	+	const int reg = (opcode >> 16) & 0x1f;
1157	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD) {
1158	+	if (direction == 0)
1159	+	regs[reg] = 0;
1160	+	else {
1161	+	// FIXME: untested code
1162	+	unsigned long ea = regs[(opcode >> 21) & 0x1f];
1163	+	ea += (signed long)(signed int)(signed short)(opcode & 0xffff);
1164	+	const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7);
1165	+	unsigned long value;
1166	+	if (direction > 0) {
1167	+	const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1);
1168	+	value = regs[reg] & rmask;
1169	+	}
1170	+	else {
1171	+	const unsigned long lmask = (1L << (offset * 8)) - 1;
1172	+	value = regs[reg] & lmask;
1173	+	}
1174	+	// restore most significant bits
1175	+	if (transfer_size == SIZE_LONG)
1176	+	value = (signed long)(signed int)value;
1177	+	regs[reg] = value;
1178	+	}
1179	+	}
1180	+
1181	+	#if DEBUG
1182	+	#if (defined(_ABIN32) \|\| defined(_ABI64))
1183	+	static const char * mips_gpr_names[32] = {
1184	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1185	+	"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1186	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1187	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1188	+	};
1189	+	#else
1190	+	static const char * mips_gpr_names[32] = {
1191	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1192	+	"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
1193	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1194	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1195	+	};
1196	+	#endif
1197	+	printf("%s %s register %s\n",
1198	+	transfer_size == SIZE_BYTE ? "byte" :
1199	+	transfer_size == SIZE_WORD ? "word" :
1200	+	transfer_size == SIZE_LONG ? "long" :
1201	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1202	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1203	+	mips_gpr_names[reg]);
1204	+	#endif
1205	+
1206	+	regs[MIPS_REG_EPC] += 4;
1207	+	return true;
1208	+	}
1209	+	#endif
1210	+
1211	+	// Decode and skip SPARC instruction
1212	+	#if (defined(sparc) \|\| defined(__sparc__))
1213	+	enum {
1214	+	#if (defined(__sun__))
1215	+	SPARC_REG_G1 = REG_G1,
1216	+	SPARC_REG_O0 = REG_O0,
1217	+	SPARC_REG_PC = REG_PC,
1218	+	#endif
1219	+	};
1220	+	static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
1221	+	{
1222	+	unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
1223	+
1224	+	if (pc == 0)
1225	+	return false;
1226	+
1227	+	#if DEBUG
1228	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1229	+	#endif
1230	+
1231	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1232	+	transfer_size_t transfer_size = SIZE_LONG;
1233	+	bool register_pair = false;
1234	+
1235	+	const unsigned int opcode = pc[0];
1236	+	if ((opcode >> 30) != 3)
1237	+	return false;
1238	+	switch ((opcode >> 19) & 0x3f) {
1239	+	case 9: // Load Signed Byte
1240	+	case 1: // Load Unsigned Byte
1241	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1242	+	transfer_size = SIZE_BYTE;
1243	+	break;
1244	+	case 10:// Load Signed Halfword
1245	+	case 2: // Load Unsigned Word
1246	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1247	+	transfer_size = SIZE_WORD;
1248	+	break;
1249	+	case 8: // Load Word
1250	+	case 0: // Load Unsigned Word
1251	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1252	+	transfer_size = SIZE_LONG;
1253	+	break;
1254	+	case 11:// Load Extended Word
1255	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1256	+	transfer_size = SIZE_QUAD;
1257	+	break;
1258	+	case 3: // Load Doubleword
1259	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1260	+	transfer_size = SIZE_LONG;
1261	+	register_pair = true;
1262	+	break;
1263	+	case 5: // Store Byte
1264	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1265	+	transfer_size = SIZE_BYTE;
1266	+	break;
1267	+	case 6: // Store Halfword
1268	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1269	+	transfer_size = SIZE_WORD;
1270	+	break;
1271	+	case 4: // Store Word
1272	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1273	+	transfer_size = SIZE_LONG;
1274	+	break;
1275	+	case 14:// Store Extended Word
1276	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1277	+	transfer_size = SIZE_QUAD;
1278	+	break;
1279	+	case 7: // Store Doubleword
1280	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1281	+	transfer_size = SIZE_WORD;
1282	+	register_pair = true;
1283	+	break;
1284	+	}
1285	+
1286	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1287	+	// Unknown machine code, let it crash. Then patch the decoder
1288	+	return false;
1289	+	}
1290	+
1291	+	// Zero target register in case of a load operation
1292	+	const int reg = (opcode >> 25) & 0x1f;
1293	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1294	+	// FIXME: code to handle local & input registers is not tested
1295	+	if (reg >= 1 && reg <= 7) {
1296	+	// global registers
1297	+	regs[reg - 1 + SPARC_REG_G1] = 0;
1298	+	}
1299	+	else if (reg >= 8 && reg <= 15) {
1300	+	// output registers
1301	+	regs[reg - 8 + SPARC_REG_O0] = 0;
1302	+	}
1303	+	else if (reg >= 16 && reg <= 23) {
1304	+	// local registers (in register windows)
1305	+	if (gwins)
1306	+	gwins->wbuf->rw_local[reg - 16] = 0;
1307	+	else
1308	+	rwin->rw_local[reg - 16] = 0;
1309	+	}
1310	+	else {
1311	+	// input registers (in register windows)
1312	+	if (gwins)
1313	+	gwins->wbuf->rw_in[reg - 24] = 0;
1314	+	else
1315	+	rwin->rw_in[reg - 24] = 0;
1316	+	}
1317	+	}
1318	+
1319	+	#if DEBUG
1320	+	static const char * reg_names[] = {
1321	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1322	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1323	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1324	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1325	+	};
1326	+	printf("%s %s register %s\n",
1327	+	transfer_size == SIZE_BYTE ? "byte" :
1328	+	transfer_size == SIZE_WORD ? "word" :
1329	+	transfer_size == SIZE_LONG ? "long" :
1330	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1331	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1332	+	reg_names[reg]);
1333	+	#endif
1334	+
1335	+	regs[SPARC_REG_PC] += 4;
1336	+	return true;
1337	+	}
1338	+	#endif
1339	+	#endif
1340	+
1341	+	// Decode and skip ARM instruction
1342	+	#if (defined(arm) \|\| defined(__arm__))
1343	+	enum {
1344	+	#if (defined(__linux__))
1345	+	ARM_REG_PC = 15,
1346	+	ARM_REG_CPSR = 16
1347	+	#endif
1348	+	};
1349	+	static bool arm_skip_instruction(unsigned long * regs)
1350	+	{
1351	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
1352	+
1353	+	if (pc == 0)
1354	+	return false;
1355	+
1356	+	#if DEBUG
1357	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1358	+	#endif
1359	+
1360	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1361	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1362	+	enum { op_sdt = 1, op_sdth = 2 };
1363	+	int op = 0;
1364	+
1365	+	// Handle load/store instructions only
1366	+	const unsigned int opcode = pc[0];
1367	+	switch ((opcode >> 25) & 7) {
1368	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
1369	+	op = op_sdth;
1370	+	// Determine transfer size (S/H bits)
1371	+	switch ((opcode >> 5) & 3) {
1372	+	case 0: // SWP instruction
1373	+	break;
1374	+	case 1: // Unsigned halfwords
1375	+	case 3: // Signed halfwords
1376	+	transfer_size = SIZE_WORD;
1377	+	break;
1378	+	case 2: // Signed byte
1379	+	transfer_size = SIZE_BYTE;
1380	+	break;
1381	+	}
1382	+	break;
1383	+	case 2:
1384	+	case 3: // Single Data Transfer (LDR, STR)
1385	+	op = op_sdt;
1386	+	// Determine transfer size (B bit)
1387	+	if (((opcode >> 22) & 1) == 1)
1388	+	transfer_size = SIZE_BYTE;
1389	+	else
1390	+	transfer_size = SIZE_LONG;
1391	+	break;
1392	+	default:
1393	+	// FIXME: support load/store mutliple?
1394	+	return false;
1395	+	}
1396	+
1397	+	// Check for invalid transfer size (SWP instruction?)
1398	+	if (transfer_size == SIZE_UNKNOWN)
1399	+	return false;
1400	+
1401	+	// Determine transfer type (L bit)
1402	+	if (((opcode >> 20) & 1) == 1)
1403	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1404	+	else
1405	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1406	+
1407	+	// Compute offset
1408	+	int offset;
1409	+	if (((opcode >> 25) & 1) == 0) {
1410	+	if (op == op_sdt)
1411	+	offset = opcode & 0xfff;
1412	+	else if (op == op_sdth) {
1413	+	int rm = opcode & 0xf;
1414	+	if (((opcode >> 22) & 1) == 0) {
1415	+	// register offset
1416	+	offset = regs[rm];
1417	+	}
1418	+	else {
1419	+	// immediate offset
1420	+	offset = ((opcode >> 4) & 0xf0) \| (opcode & 0x0f);
1421	+	}
1422	+	}
1423	+	}
1424	+	else {
1425	+	const int rm = opcode & 0xf;
1426	+	const int sh = (opcode >> 7) & 0x1f;
1427	+	if (((opcode >> 4) & 1) == 1) {
1428	+	// we expect only legal load/store instructions
1429	+	printf("FATAL: invalid shift operand\n");
1430	+	return false;
1431	+	}
1432	+	const unsigned int v = regs[rm];
1433	+	switch ((opcode >> 5) & 3) {
1434	+	case 0: // logical shift left
1435	+	offset = sh ? v << sh : v;
1436	+	break;
1437	+	case 1: // logical shift right
1438	+	offset = sh ? v >> sh : 0;
1439	+	break;
1440	+	case 2: // arithmetic shift right
1441	+	if (sh)
1442	+	offset = ((signed int)v) >> sh;
1443	+	else
1444	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
1445	+	break;
1446	+	case 3: // rotate right
1447	+	if (sh)
1448	+	offset = (v >> sh) \| (v << (32 - sh));
1449	+	else
1450	+	offset = (v >> 1) \| ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
1451	+	break;
1452	+	}
1453	+	}
1454	+	if (((opcode >> 23) & 1) == 0)
1455	+	offset = -offset;
1456	+
1457	+	int rd = (opcode >> 12) & 0xf;
1458	+	int rn = (opcode >> 16) & 0xf;
1459	+	#if DEBUG
1460	+	static const char * reg_names[] = {
1461	+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1462	+	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
1463	+	};
1464	+	printf("%s %s register %s\n",
1465	+	transfer_size == SIZE_BYTE ? "byte" :
1466	+	transfer_size == SIZE_WORD ? "word" :
1467	+	transfer_size == SIZE_LONG ? "long" : "unknown",
1468	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1469	+	reg_names[rd]);
1470	+	#endif
1471	+
1472	+	unsigned int base = regs[rn];
1473	+	if (((opcode >> 24) & 1) == 1)
1474	+	base += offset;
1475	+
1476	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
1477	+	regs[rd] = 0;
1478	+
1479	+	if (((opcode >> 24) & 1) == 0) // post-index addressing
1480	+	regs[rn] += offset;
1481	+	else if (((opcode >> 21) & 1) == 1) // write-back address into base
1482	+	regs[rn] = base;
1483	+
1484	+	regs[ARM_REG_PC] += 4;
1485	+	return true;
1486	+	}
1487	+	#endif
1488	+
1489
1490		// Fallbacks
1491		#ifndef SIGSEGV_FAULT_INSTRUCTION
#	Line 939 \| Line 1508 \| static bool powerpc_skip_instruction(uns
1508		* SIGSEGV global handler
1509		*/
1510
942	–	#if defined(HAVE_SIGSEGV_RECOVERY) \|\| defined(HAVE_MACH_EXCEPTIONS)
1511		// This function handles the badaccess to memory.
1512		// It is called from the signal handler or the exception handler.
1513		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
#	Line 973 \| Line 1541 \| static bool handle_badaccess(SIGSEGV_FAU
1541		}
1542		break;
1543		#endif
1544	+	case SIGSEGV_RETURN_FAILURE:
1545	+	// We can't do anything with the fault_address, dump state?
1546	+	if (sigsegv_state_dumper != 0)
1547	+	sigsegv_state_dumper(fault_address, fault_instruction);
1548	+	break;
1549		}
977	–
978	–	// We can't do anything with the fault_address, dump state?
979	–	if (sigsegv_state_dumper != 0)
980	–	sigsegv_state_dumper(fault_address, fault_instruction);
1550
1551		return false;
1552		}
984	–	#endif
1553
1554
1555		/*
#	Line 1275 \| Line 1843 \| static bool sigsegv_do_install_handler(s
1843		}
1844		#endif
1845
1846	+	#ifdef HAVE_WIN32_EXCEPTIONS
1847	+	static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo)
1848	+	{
1849	+	if (sigsegv_fault_handler != NULL
1850	+	&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
1851	+	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
1852	+	&& handle_badaccess(ExceptionInfo))
1853	+	return EXCEPTION_CONTINUE_EXECUTION;
1854	+
1855	+	return EXCEPTION_CONTINUE_SEARCH;
1856	+	}
1857	+
1858	+	#if defined __CYGWIN__ && defined __i386__
1859	+	/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin
1860	+	installs a global exception handler. We have to dig deep in order to install
1861	+	our main_exception_filter. */
1862	+
1863	+	/* Data structures for the current thread's exception handler chain.
1864	+	On the x86 Windows uses register fs, offset 0 to point to the current
1865	+	exception handler; Cygwin mucks with it, so we must do the same... :-/ */
1866	+
1867	+	/* Magic taken from winsup/cygwin/include/exceptions.h. */
1868	+
1869	+	struct exception_list {
1870	+	struct exception_list *prev;
1871	+	int (handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
1872	+	};
1873	+	typedef struct exception_list exception_list;
1874	+
1875	+	/* Magic taken from winsup/cygwin/exceptions.cc. */
1876	+
1877	+	__asm__ (".equ __except_list,0");
1878	+
1879	+	extern exception_list *_except_list __asm__ ("%fs:__except_list");
1880	+
1881	+	/* For debugging. _except_list is not otherwise accessible from gdb. */
1882	+	static exception_list *
1883	+	debug_get_except_list ()
1884	+	{
1885	+	return _except_list;
1886	+	}
1887	+
1888	+	/* Cygwin's original exception handler. */
1889	+	static int (cygwin_exception_handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
1890	+
1891	+	/* Our exception handler. */
1892	+	static int
1893	+	libsigsegv_exception_handler (EXCEPTION_RECORD exception, void frame, CONTEXT context, void dispatch)
1894	+	{
1895	+	EXCEPTION_POINTERS ExceptionInfo;
1896	+	ExceptionInfo.ExceptionRecord = exception;
1897	+	ExceptionInfo.ContextRecord = context;
1898	+	if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH)
1899	+	return cygwin_exception_handler (exception, frame, context, dispatch);
1900	+	else
1901	+	return 0;
1902	+	}
1903	+
1904	+	static void
1905	+	do_install_main_exception_filter ()
1906	+	{
1907	+	/* We cannot insert any handler into the chain, because such handlers
1908	+	must lie on the stack (?). Instead, we have to replace(!) Cygwin's
1909	+	global exception handler. */
1910	+	cygwin_exception_handler = _except_list->handler;
1911	+	_except_list->handler = libsigsegv_exception_handler;
1912	+	}
1913	+
1914	+	#else
1915	+
1916	+	static void
1917	+	do_install_main_exception_filter ()
1918	+	{
1919	+	SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter);
1920	+	}
1921	+	#endif
1922	+
1923	+	static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler)
1924	+	{
1925	+	static bool main_exception_filter_installed = false;
1926	+	if (!main_exception_filter_installed) {
1927	+	do_install_main_exception_filter();
1928	+	main_exception_filter_installed = true;
1929	+	}
1930	+	sigsegv_fault_handler = handler;
1931	+	return true;
1932	+	}
1933	+	#endif
1934	+
1935		bool sigsegv_install_handler(sigsegv_fault_handler_t handler)
1936		{
1937		#if defined(HAVE_SIGSEGV_RECOVERY)
#	Line 1285 \| Line 1942 \| bool sigsegv_install_handler(sigsegv_fau
1942		if (success)
1943		sigsegv_fault_handler = handler;
1944		return success;
1945	<	#elif defined(HAVE_MACH_EXCEPTIONS)
1945	>	#elif defined(HAVE_MACH_EXCEPTIONS) \|\| defined(HAVE_WIN32_EXCEPTIONS)
1946		return sigsegv_do_install_handler(handler);
1947		#else
1948		// FAIL: no siginfo_t nor sigcontext subterfuge is available
#	Line 1311 \| Line 1968 \| void sigsegv_deinstall_handler(void)
1968		SIGSEGV_ALL_SIGNALS
1969		#undef FAULT_HANDLER
1970		#endif
1971	+	#ifdef HAVE_WIN32_EXCEPTIONS
1972	+	sigsegv_fault_handler = NULL;
1973	+	#endif
1974		}
1975
1976
#	Line 1332 \| Line 1992 \| void sigsegv_set_dump_state(sigsegv_stat
1992		#include <stdio.h>
1993		#include <stdlib.h>
1994		#include <fcntl.h>
1995	+	#ifdef HAVE_SYS_MMAN_H
1996		#include <sys/mman.h>
1997	+	#endif
1998		#include "vm_alloc.h"
1999
2000		const int REF_INDEX = 123;
#	Line 1349 \| Line 2011 \| *static void b_region, e_region;*
2011
2012		static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2013		{
2014	+	#if DEBUG
2015	+	printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
2016	+	printf("expected fault at %p\n", page + REF_INDEX);
2017	+	#ifdef __GNUC__
2018	+	printf("expected instruction address range: %p-%p\n", b_region, e_region);
2019	+	#endif
2020	+	#endif
2021		handler_called++;
2022		if ((fault_address - REF_INDEX) != page)
2023		exit(10);
#	Line 1368 \| Line 2037 \| static sigsegv_return_t sigsegv_test_han
2037		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
2038		static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2039		{
2040	+	#if DEBUG
2041	+	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
2042	+	#endif
2043		if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
2044		#ifdef __GNUC__
2045		// Make sure reported fault instruction address falls into
#	Line 1446 \| Line 2118 \| int main(void)
2118		if (vm_init() < 0)
2119		return 1;
2120
2121	+	#ifdef _WIN32
2122	+	page_size = 4096;
2123	+	#else
2124		page_size = getpagesize();
2125	+	#endif
2126		if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED)
2127		return 2;
2128
#	Line 1502 \| Line 2178 \| int main(void)
2178		TEST_SKIP_INSTRUCTION(unsigned short);
2179		TEST_SKIP_INSTRUCTION(unsigned int);
2180		TEST_SKIP_INSTRUCTION(unsigned long);
2181	+	TEST_SKIP_INSTRUCTION(signed char);
2182	+	TEST_SKIP_INSTRUCTION(signed short);
2183	+	TEST_SKIP_INSTRUCTION(signed int);
2184	+	TEST_SKIP_INSTRUCTION(signed long);
2185		L_e_region2:
1506	–	#endif
2186
2187		if (!arch_insn_skipper_tests())
2188		return 20;
2189	+	#endif
2190
2191		vm_exit();
2192		return 0;

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.34 by gbeauche, 2003-11-10T23:47:39Z vs. Revision 1.52 by gbeauche, 2005-01-30T21:42:14Z

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.34 by gbeauche, 2003-11-10T23:47:39Z vs.
Revision 1.52 by gbeauche, 2005-01-30T21:42:14Z