[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.33 by gbeauche, 2003-10-21T23:10:19Z vs.
Revision 1.67 by gbeauche, 2007-12-30T08:45:18Z

#	Line 10 \| Line 10
10		* tjw@omnigroup.com Sun, 4 Jun 2000
11		* www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	* Basilisk II (C) 1997-2002 Christian Bauer
13	>	* Basilisk II (C) 1997-2005 Christian Bauer
14		*
15		* This program is free software; you can redistribute it and/or modify
16		* it under the terms of the GNU General Public License as published by
#	Line 36 \| Line 36
36		#endif
37
38		#include <list>
39	+	#include <stdio.h>
40		#include <signal.h>
41		#include "sigsegv.h"
42
#	Line 65 \| Line 66 \| static bool sigsegv_do_install_handler(i
66		* Instruction decoding aids
67		*/
68
69	+	// Transfer type
70	+	enum transfer_type_t {
71	+	SIGSEGV_TRANSFER_UNKNOWN = 0,
72	+	SIGSEGV_TRANSFER_LOAD = 1,
73	+	SIGSEGV_TRANSFER_STORE = 2,
74	+	};
75	+
76		// Transfer size
77		enum transfer_size_t {
78		SIZE_UNKNOWN,
79		SIZE_BYTE,
80	<	SIZE_WORD,
81	<	SIZE_LONG
80	>	SIZE_WORD, // 2 bytes
81	>	SIZE_LONG, // 4 bytes
82	>	SIZE_QUAD, // 8 bytes
83		};
84
76	–	// Transfer type
77	–	typedef sigsegv_transfer_type_t transfer_type_t;
78	–
85		#if (defined(powerpc) \|\| defined(__powerpc__) \|\| defined(__ppc__))
86		// Addressing mode
87		enum addressing_mode_t {
#	Line 95 \| Line 101 \| struct instruction_t {
101		char ra, rd;
102		};
103
104	<	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned int gpr)
104	>	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned long gpr)
105		{
106		// Get opcode and divide into fields
107	<	unsigned int opcode = ((unsigned int )nip);
107	>	unsigned int opcode = ((unsigned int )(unsigned long)nip);
108		unsigned int primop = opcode >> 26;
109		unsigned int exop = (opcode >> 1) & 0x3ff;
110		unsigned int ra = (opcode >> 16) & 0x1f;
#	Line 172 \| Line 178 \| static void powerpc_decode_instruction(i
178		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break;
179		case 45: // sthu
180		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break;
181	+	case 58: // ld, ldu, lwa
182	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
183	+	transfer_size = SIZE_QUAD;
184	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
185	+	imm &= ~3;
186	+	break;
187	+	case 62: // std, stdu, stq
188	+	transfer_type = SIGSEGV_TRANSFER_STORE;
189	+	transfer_size = SIZE_QUAD;
190	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
191	+	imm &= ~3;
192	+	break;
193		}
194
195		// Calculate effective address
#	Line 212 \| Line 230 \| static void powerpc_decode_instruction(i
230
231		#if HAVE_SIGINFO_T
232		// Generic extended signal handler
233	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
233	>	#if defined(__FreeBSD__)
234		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
235		#else
236		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
#	Line 221 \| Line 239 \| static void powerpc_decode_instruction(i
239		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t sip, void scp
240		#define SIGSEGV_FAULT_HANDLER_ARGS sip, scp
241		#define SIGSEGV_FAULT_ADDRESS sip->si_addr
242	+	#if (defined(sgi) \|\| defined(__sgi))
243	+	#include <ucontext.h>
244	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
245	+	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
246	+	#if (defined(mips) \|\| defined(__mips))
247	+	#define SIGSEGV_REGISTER_FILE &SIGSEGV_CONTEXT_REGS[CTX_EPC], &SIGSEGV_CONTEXT_REGS[CTX_R0]
248	+	#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
249	+	#endif
250	+	#endif
251		#if defined(__sun__)
252		#if (defined(sparc) \|\| defined(__sparc__))
253	+	#include <sys/stack.h>
254	+	#include <sys/regset.h>
255		#include <sys/ucontext.h>
256		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
257		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[REG_PC]
258	+	#define SIGSEGV_SPARC_GWINDOWS (((ucontext_t *)scp)->uc_mcontext.gwins)
259	+	#define SIGSEGV_SPARC_RWINDOW (struct rwindow )((char )SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
260	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
261	+	#define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction
262	+	#endif
263	+	#if defined(__i386__)
264	+	#include <sys/regset.h>
265	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
266	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[EIP]
267	+	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
268	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
269		#endif
270		#endif
271	<	#if defined(__FreeBSD__)
271	>	#if defined(__FreeBSD__) \|\| defined(__OpenBSD__)
272		#if (defined(i386) \|\| defined(__i386__))
273		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
274	<	#define SIGSEGV_REGISTER_FILE ((unsigned int )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
274	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
275		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
276		#endif
277		#endif
278	+	#if defined(__NetBSD__)
279	+	#if (defined(i386) \|\| defined(__i386__))
280	+	#include <sys/ucontext.h>
281	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
282	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP]
283	+	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
284	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
285	+	#endif
286	+	#if (defined(powerpc) \|\| defined(__powerpc__))
287	+	#include <sys/ucontext.h>
288	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
289	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_PC]
290	+	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIGSEGV_CONTEXT_REGS[_REG_PC], (unsigned long )&SIGSEGV_CONTEXT_REGS[_REG_R0]
291	+	#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
292	+	#endif
293	+	#endif
294		#if defined(__linux__)
295		#if (defined(i386) \|\| defined(__i386__))
296		#include <sys/ucontext.h>
297		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
298		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
299	<	#define SIGSEGV_REGISTER_FILE (unsigned int *)SIGSEGV_CONTEXT_REGS
299	>	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
300		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
301		#endif
302		#if (defined(x86_64) \|\| defined(__x86_64__))
#	Line 248 \| Line 304 \| static void powerpc_decode_instruction(i
304		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
305		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
306		#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
307	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
308		#endif
309		#if (defined(ia64) \|\| defined(__ia64__))
310		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext )scp)->sc_ip & ~0x3ULL) / slot number is in bits 0 and 1 */
#	Line 256 \| Line 313 \| static void powerpc_decode_instruction(i
313		#include <sys/ucontext.h>
314		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.regs)
315		#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->nip)
316	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&SIGSEGV_CONTEXT_REGS->nip, (unsigned int )(SIGSEGV_CONTEXT_REGS->gpr)
316	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIGSEGV_CONTEXT_REGS->nip, (unsigned long )(SIGSEGV_CONTEXT_REGS->gpr)
317		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
318		#endif
319	+	#if (defined(hppa) \|\| defined(__hppa__))
320	+	#undef SIGSEGV_FAULT_ADDRESS
321	+	#define SIGSEGV_FAULT_ADDRESS sip->si_ptr
322	+	#endif
323	+	#if (defined(arm) \|\| defined(__arm__))
324	+	#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
325	+	#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext)
326	+	#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.arm_pc)
327	+	#define SIGSEGV_REGISTER_FILE (&SIGSEGV_CONTEXT_REGS.arm_r0)
328	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
329	+	#endif
330	+	#if (defined(mips) \|\| defined(__mips__))
331	+	#include <sys/ucontext.h>
332	+	#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext)
333	+	#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.pc)
334	+	#define SIGSEGV_REGISTER_FILE &SIGSEGV_CONTEXT_REGS.pc, &SIGSEGV_CONTEXT_REGS.gregs[0]
335	+	#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
336	+	#endif
337		#endif
338		#endif
339
#	Line 273 \| Line 348 \| static void powerpc_decode_instruction(i
348		#define SIGSEGV_FAULT_HANDLER_ARGS &scs
349		#define SIGSEGV_FAULT_ADDRESS scp->cr2
350		#define SIGSEGV_FAULT_INSTRUCTION scp->eip
351	<	#define SIGSEGV_REGISTER_FILE (unsigned int *)scp
351	>	#define SIGSEGV_REGISTER_FILE (unsigned long *)scp
352		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
353		#endif
354		#if (defined(sparc) \|\| defined(__sparc__))
#	Line 288 \| Line 363 \| static void powerpc_decode_instruction(i
363		#define SIGSEGV_FAULT_HANDLER_ARGS sig, scp
364		#define SIGSEGV_FAULT_ADDRESS scp->regs->dar
365		#define SIGSEGV_FAULT_INSTRUCTION scp->regs->nip
366	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&scp->regs->nip, (unsigned int )(scp->regs->gpr)
366	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&scp->regs->nip, (unsigned long )(scp->regs->gpr)
367		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
368		#endif
369		#if (defined(alpha) \|\| defined(__alpha__))
#	Line 298 \| Line 373 \| static void powerpc_decode_instruction(i
373		#define SIGSEGV_FAULT_ADDRESS get_fault_address(scp)
374		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
375		#endif
376	+	#if (defined(arm) \|\| defined(__arm__))
377	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int r1, int r2, int r3, struct sigcontext sc
378	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp
379	+	#define SIGSEGV_FAULT_HANDLER_ARGS &sc
380	+	#define SIGSEGV_FAULT_ADDRESS scp->fault_address
381	+	#define SIGSEGV_FAULT_INSTRUCTION scp->arm_pc
382	+	#define SIGSEGV_REGISTER_FILE &scp->arm_r0
383	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
384	+	#endif
385		#endif
386
387		// Irix 5 or 6 on MIPS
388	<	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(__SYSTYPE_SVR4))
388	>	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(_SYSTYPE_SVR4))
389		#include <ucontext.h>
390		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp
391		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp
392	<	#define SIGSEGV_FAULT_ADDRESS scp->sc_badvaddr
392	>	#define SIGSEGV_FAULT_ADDRESS (unsigned long)scp->sc_badvaddr
393	>	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)scp->sc_pc
394		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
395		#endif
396
#	Line 378 \| Line 463 \| static sigsegv_address_t get_fault_addre
463		#endif
464		#endif
465		#if defined(__FreeBSD__)
381	–	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
466		#if (defined(i386) \|\| defined(__i386__))
467	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
468		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext scp, char addr
469		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr
470		#define SIGSEGV_FAULT_ADDRESS addr
471		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_eip
472	<	#define SIGSEGV_REGISTER_FILE ((unsigned int *)&scp->sc_edi)
472	>	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi)
473		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
474		#endif
475	+	#if (defined(alpha) \|\| defined(__alpha__))
476	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
477	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, char addr, struct sigcontext scp
478	+	#define SIGSEGV_FAULT_HANDLER_ARGS sig, addr, scp
479	+	#define SIGSEGV_FAULT_ADDRESS addr
480	+	#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
481	+	#endif
482		#endif
483
484		// Extract fault address out of a sigcontext
#	Line 435 \| Line 527 \| static sigsegv_address_t get_fault_addre
527		#endif
528		#endif
529
530	+	#if HAVE_WIN32_EXCEPTIONS
531	+	#define WIN32_LEAN_AND_MEAN /* avoid including junk */
532	+	#include <windows.h>
533	+	#include <winerror.h>
534	+
535	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo
536	+	#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo
537	+	#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
538	+	#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord
539	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip
540	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
541	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
542	+	#endif
543	+
544		#if HAVE_MACH_EXCEPTIONS
545
546		// This can easily be extended to other Mach systems, but really who
#	Line 495 \| Line 601 \| if (ret != KERN_SUCCESS) { \
601		exit (1); \
602		}
603
604	<	#define SIGSEGV_FAULT_ADDRESS code[1]
605	<	#define SIGSEGV_FAULT_INSTRUCTION get_fault_instruction(thread, state)
606	<	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) ((code[0] == KERN_PROTECTION_FAILURE) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE)
607	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code, ppc_thread_state_t *state
608	<	#define SIGSEGV_FAULT_HANDLER_ARGS thread, code, &state
604	>	#ifdef __ppc__
605	>	#define SIGSEGV_EXCEPTION_STATE_TYPE ppc_exception_state_t
606	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR PPC_EXCEPTION_STATE
607	>	#define SIGSEGV_EXCEPTION_STATE_COUNT PPC_EXCEPTION_STATE_COUNT
608	>	#define SIGSEGV_FAULT_ADDRESS exc_state->dar
609	>	#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t
610	>	#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE
611	>	#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT
612	>	#define SIGSEGV_FAULT_INSTRUCTION state.srr0
613		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
614	<	#define SIGSEGV_REGISTER_FILE &state->srr0, &state->r0
615	<
616	<	// Given a suspended thread, stuff the current instruction and
617	<	// registers into state.
618	<	//
619	<	// It would have been nice to have this be ppc/x86 independant which
620	<	// could have been done easily with a thread_state_t instead of
621	<	// ppc_thread_state_t, but because of the way this is called it is
622	<	// easier to do it this way.
623	<	#if (defined(ppc) \|\| defined(__ppc__))
624	<	static inline sigsegv_address_t get_fault_instruction(mach_port_t thread, ppc_thread_state_t *state)
625	<	{
626	<	kern_return_t krc;
627	<	mach_msg_type_number_t count;
628	<
629	<	count = MACHINE_THREAD_STATE_COUNT;
630	<	krc = thread_get_state(thread, MACHINE_THREAD_STATE, (thread_state_t)state, &count);
631	<	MACH_CHECK_ERROR (thread_get_state, krc);
632	<
633	<	return (sigsegv_address_t)state->srr0;
634	<	}
614	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&state.srr0, (unsigned long )&state.r0
615	>	#endif
616	>	#ifdef __i386__
617	>	#ifdef i386_SAVED_STATE
618	>	#define SIGSEGV_THREAD_STATE_TYPE struct i386_saved_state
619	>	#define SIGSEGV_THREAD_STATE_FLAVOR i386_SAVED_STATE
620	>	#define SIGSEGV_THREAD_STATE_COUNT i386_SAVED_STATE_COUNT
621	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&state.edi) / EDI is the first GPR we consider */
622	>	#else
623	>	#define SIGSEGV_EXCEPTION_STATE_TYPE struct i386_exception_state
624	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR i386_EXCEPTION_STATE
625	>	#define SIGSEGV_EXCEPTION_STATE_COUNT i386_EXCEPTION_STATE_COUNT
626	>	#define SIGSEGV_FAULT_ADDRESS exc_state->faultvaddr
627	>	#define SIGSEGV_THREAD_STATE_TYPE struct i386_thread_state
628	>	#define SIGSEGV_THREAD_STATE_FLAVOR i386_THREAD_STATE
629	>	#define SIGSEGV_THREAD_STATE_COUNT i386_THREAD_STATE_COUNT
630	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&state.eax) / EAX is the first GPR we consider */
631	>	#endif
632	>	#define SIGSEGV_FAULT_INSTRUCTION state.eip
633	>	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
634	>	#endif
635	>	#ifdef __x86_64__
636	>	#define SIGSEGV_EXCEPTION_STATE_TYPE struct x86_exception_state64
637	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR x86_EXCEPTION_STATE64
638	>	#define SIGSEGV_EXCEPTION_STATE_COUNT x86_EXCEPTION_STATE64_COUNT
639	>	#define SIGSEGV_FAULT_ADDRESS exc_state->faultvaddr
640	>	#define SIGSEGV_THREAD_STATE_TYPE struct x86_thread_state64
641	>	#define SIGSEGV_THREAD_STATE_FLAVOR x86_THREAD_STATE64
642	>	#define SIGSEGV_THREAD_STATE_COUNT x86_THREAD_STATE64_COUNT
643	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&state.rax) / RAX is the first GPR we consider */
644	>	#define SIGSEGV_FAULT_INSTRUCTION state.rip
645	>	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
646	>	#endif
647	>	#ifdef SIGSEGV_EXCEPTION_STATE_TYPE
648	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, SIGSEGV_EXCEPTION_STATE_TYPE *exc_state
649	>	#define SIGSEGV_FAULT_HANDLER_ARGS thread, &exc_state
650	>	#else
651	>	#define SIGSEGV_FAULT_ADDRESS code[1]
652	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code
653	>	#define SIGSEGV_FAULT_HANDLER_ARGS thread, code
654		#endif
655
656		// Since there can only be one exception thread running at any time
#	Line 577 \| Line 706 \| *handleExceptions(void priv)**
706
707		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
708		// Decode and skip X86 instruction
709	<	#if (defined(i386) \|\| defined(__i386__))
709	>	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
710		#if defined(__linux__)
711		enum {
712	+	#if (defined(i386) \|\| defined(__i386__))
713		X86_REG_EIP = 14,
714		X86_REG_EAX = 11,
715		X86_REG_ECX = 10,
#	Line 589 \| Line 719 \| enum {
719		X86_REG_EBP = 6,
720		X86_REG_ESI = 5,
721		X86_REG_EDI = 4
722	+	#endif
723	+	#if defined(__x86_64__)
724	+	X86_REG_R8 = 0,
725	+	X86_REG_R9 = 1,
726	+	X86_REG_R10 = 2,
727	+	X86_REG_R11 = 3,
728	+	X86_REG_R12 = 4,
729	+	X86_REG_R13 = 5,
730	+	X86_REG_R14 = 6,
731	+	X86_REG_R15 = 7,
732	+	X86_REG_EDI = 8,
733	+	X86_REG_ESI = 9,
734	+	X86_REG_EBP = 10,
735	+	X86_REG_EBX = 11,
736	+	X86_REG_EDX = 12,
737	+	X86_REG_EAX = 13,
738	+	X86_REG_ECX = 14,
739	+	X86_REG_ESP = 15,
740	+	X86_REG_EIP = 16
741	+	#endif
742	+	};
743	+	#endif
744	+	#if defined(__NetBSD__)
745	+	enum {
746	+	#if (defined(i386) \|\| defined(__i386__))
747	+	X86_REG_EIP = _REG_EIP,
748	+	X86_REG_EAX = _REG_EAX,
749	+	X86_REG_ECX = _REG_ECX,
750	+	X86_REG_EDX = _REG_EDX,
751	+	X86_REG_EBX = _REG_EBX,
752	+	X86_REG_ESP = _REG_ESP,
753	+	X86_REG_EBP = _REG_EBP,
754	+	X86_REG_ESI = _REG_ESI,
755	+	X86_REG_EDI = _REG_EDI
756	+	#endif
757	+	};
758	+	#endif
759	+	#if defined(__FreeBSD__)
760	+	enum {
761	+	#if (defined(i386) \|\| defined(__i386__))
762	+	X86_REG_EIP = 10,
763	+	X86_REG_EAX = 7,
764	+	X86_REG_ECX = 6,
765	+	X86_REG_EDX = 5,
766	+	X86_REG_EBX = 4,
767	+	X86_REG_ESP = 13,
768	+	X86_REG_EBP = 2,
769	+	X86_REG_ESI = 1,
770	+	X86_REG_EDI = 0
771	+	#endif
772		};
773		#endif
774	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
774	>	#if defined(__OpenBSD__)
775		enum {
776	+	#if defined(__i386__)
777	+	// EDI is the first register we consider
778	+	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
779	+	#define DREG(REG) ((OREG(REG) - OREG(edi)) / 4)
780	+	X86_REG_EIP = DREG(eip), // 7
781	+	X86_REG_EAX = DREG(eax), // 6
782	+	X86_REG_ECX = DREG(ecx), // 5
783	+	X86_REG_EDX = DREG(edx), // 4
784	+	X86_REG_EBX = DREG(ebx), // 3
785	+	X86_REG_ESP = DREG(esp), // 10
786	+	X86_REG_EBP = DREG(ebp), // 2
787	+	X86_REG_ESI = DREG(esi), // 1
788	+	X86_REG_EDI = DREG(edi) // 0
789	+	#undef DREG
790	+	#undef OREG
791	+	#endif
792	+	};
793	+	#endif
794	+	#if defined(__sun__)
795	+	// Same as for Linux, need to check for x86-64
796	+	enum {
797	+	#if defined(__i386__)
798	+	X86_REG_EIP = EIP,
799	+	X86_REG_EAX = EAX,
800	+	X86_REG_ECX = ECX,
801	+	X86_REG_EDX = EDX,
802	+	X86_REG_EBX = EBX,
803	+	X86_REG_ESP = ESP,
804	+	X86_REG_EBP = EBP,
805	+	X86_REG_ESI = ESI,
806	+	X86_REG_EDI = EDI
807	+	#endif
808	+	};
809	+	#endif
810	+	#if defined(__APPLE__) && defined(__MACH__)
811	+	enum {
812	+	#if (defined(i386) \|\| defined(__i386__))
813	+	#ifdef i386_SAVED_STATE
814	+	// same as FreeBSD (in Open Darwin 8.0.1)
815		X86_REG_EIP = 10,
816		X86_REG_EAX = 7,
817		X86_REG_ECX = 6,
#	Line 602 \| Line 821 \| enum {
821		X86_REG_EBP = 2,
822		X86_REG_ESI = 1,
823		X86_REG_EDI = 0
824	+	#else
825	+	// new layout (MacOS X 10.4.4 for x86)
826	+	X86_REG_EIP = 10,
827	+	X86_REG_EAX = 0,
828	+	X86_REG_ECX = 2,
829	+	X86_REG_EDX = 3,
830	+	X86_REG_EBX = 1,
831	+	X86_REG_ESP = 7,
832	+	X86_REG_EBP = 6,
833	+	X86_REG_ESI = 5,
834	+	X86_REG_EDI = 4
835	+	#endif
836	+	#endif
837	+	#if defined(__x86_64__)
838	+	X86_REG_R8 = 8,
839	+	X86_REG_R9 = 9,
840	+	X86_REG_R10 = 10,
841	+	X86_REG_R11 = 11,
842	+	X86_REG_R12 = 12,
843	+	X86_REG_R13 = 13,
844	+	X86_REG_R14 = 14,
845	+	X86_REG_R15 = 15,
846	+	X86_REG_EDI = 4,
847	+	X86_REG_ESI = 5,
848	+	X86_REG_EBP = 6,
849	+	X86_REG_EBX = 1,
850	+	X86_REG_EDX = 3,
851	+	X86_REG_EAX = 0,
852	+	X86_REG_ECX = 2,
853	+	X86_REG_ESP = 7,
854	+	X86_REG_EIP = 16
855	+	#endif
856	+	};
857	+	#endif
858	+	#if defined(_WIN32)
859	+	enum {
860	+	#if (defined(i386) \|\| defined(__i386__))
861	+	X86_REG_EIP = 7,
862	+	X86_REG_EAX = 5,
863	+	X86_REG_ECX = 4,
864	+	X86_REG_EDX = 3,
865	+	X86_REG_EBX = 2,
866	+	X86_REG_ESP = 10,
867	+	X86_REG_EBP = 6,
868	+	X86_REG_ESI = 1,
869	+	X86_REG_EDI = 0
870	+	#endif
871		};
872		#endif
873		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 638 \| Line 904 \| static inline int ix86_step_over_modrm(u
904		return offset;
905		}
906
907	<	static bool ix86_skip_instruction(unsigned int * regs)
907	>	static bool ix86_skip_instruction(unsigned long * regs)
908		{
909		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
910
911		if (eip == 0)
912		return false;
913	+	#ifdef _WIN32
914	+	if (IsBadCodePtr((FARPROC)eip))
915	+	return false;
916	+	#endif
917
918	+	enum instruction_type_t {
919	+	i_MOV,
920	+	i_ADD
921	+	};
922	+
923		transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
924		transfer_size_t transfer_size = SIZE_LONG;
925	+	instruction_type_t instruction_type = i_MOV;
926
927		int reg = -1;
928		int len = 0;
929	<
929	>
930	>	#if DEBUG
931	>	printf("IP: %p [%02x %02x %02x %02x...]\n",
932	>	eip, eip[0], eip[1], eip[2], eip[3]);
933	>	#endif
934	>
935		// Operand size prefix
936		if (*eip == 0x66) {
937		eip++;
#	Line 658 \| Line 939 \| static bool ix86_skip_instruction(unsign
939		transfer_size = SIZE_WORD;
940		}
941
942	+	// REX prefix
943	+	#if defined(__x86_64__)
944	+	struct rex_t {
945	+	unsigned char W;
946	+	unsigned char R;
947	+	unsigned char X;
948	+	unsigned char B;
949	+	};
950	+	rex_t rex = { 0, 0, 0, 0 };
951	+	bool has_rex = false;
952	+	if ((*eip & 0xf0) == 0x40) {
953	+	has_rex = true;
954	+	const unsigned char b = *eip;
955	+	rex.W = b & (1 << 3);
956	+	rex.R = b & (1 << 2);
957	+	rex.X = b & (1 << 1);
958	+	rex.B = b & (1 << 0);
959	+	#if DEBUG
960	+	printf("REX: %c,%c,%c,%c\n",
961	+	rex.W ? 'W' : '_',
962	+	rex.R ? 'R' : '_',
963	+	rex.X ? 'X' : '_',
964	+	rex.B ? 'B' : '_');
965	+	#endif
966	+	eip++;
967	+	len++;
968	+	if (rex.W)
969	+	transfer_size = SIZE_QUAD;
970	+	}
971	+	#else
972	+	const bool has_rex = false;
973	+	#endif
974	+
975		// Decode instruction
976	+	int op_len = 1;
977	+	int target_size = SIZE_UNKNOWN;
978		switch (eip[0]) {
979		case 0x0f:
980	+	target_size = transfer_size;
981		switch (eip[1]) {
982	+	case 0xbe: // MOVSX r32, r/m8
983		case 0xb6: // MOVZX r32, r/m8
984	+	transfer_size = SIZE_BYTE;
985	+	goto do_mov_extend;
986	+	case 0xbf: // MOVSX r32, r/m16
987		case 0xb7: // MOVZX r32, r/m16
988	<	switch (eip[2] & 0xc0) {
989	<	case 0x80:
990	<	reg = (eip[2] >> 3) & 7;
991	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
992	<	break;
672	<	case 0x40:
673	<	reg = (eip[2] >> 3) & 7;
674	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
675	<	break;
676	<	case 0x00:
677	<	reg = (eip[2] >> 3) & 7;
678	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
679	<	break;
988	>	transfer_size = SIZE_WORD;
989	>	goto do_mov_extend;
990	>	do_mov_extend:
991	>	op_len = 2;
992	>	goto do_transfer_load;
993		}
681	–	len += 3 + ix86_step_over_modrm(eip + 2);
994		break;
995	<	}
996	<	break;
995	>	#if defined(__x86_64__)
996	>	case 0x63: // MOVSXD r64, r/m32
997	>	if (has_rex && rex.W) {
998	>	transfer_size = SIZE_LONG;
999	>	target_size = SIZE_QUAD;
1000	>	}
1001	>	else if (transfer_size != SIZE_WORD) {
1002	>	transfer_size = SIZE_LONG;
1003	>	target_size = SIZE_QUAD;
1004	>	}
1005	>	goto do_transfer_load;
1006	>	#endif
1007	>	case 0x02: // ADD r8, r/m8
1008	>	transfer_size = SIZE_BYTE;
1009	>	case 0x03: // ADD r32, r/m32
1010	>	instruction_type = i_ADD;
1011	>	goto do_transfer_load;
1012		case 0x8a: // MOV r8, r/m8
1013		transfer_size = SIZE_BYTE;
1014		case 0x8b: // MOV r32, r/m32 (or 16-bit operation)
1015	<	switch (eip[1] & 0xc0) {
1015	>	do_transfer_load:
1016	>	switch (eip[op_len] & 0xc0) {
1017		case 0x80:
1018	<	reg = (eip[1] >> 3) & 7;
1018	>	reg = (eip[op_len] >> 3) & 7;
1019		transfer_type = SIGSEGV_TRANSFER_LOAD;
1020		break;
1021		case 0x40:
1022	<	reg = (eip[1] >> 3) & 7;
1022	>	reg = (eip[op_len] >> 3) & 7;
1023		transfer_type = SIGSEGV_TRANSFER_LOAD;
1024		break;
1025		case 0x00:
1026	<	reg = (eip[1] >> 3) & 7;
1026	>	reg = (eip[op_len] >> 3) & 7;
1027		transfer_type = SIGSEGV_TRANSFER_LOAD;
1028		break;
1029		}
1030	<	len += 2 + ix86_step_over_modrm(eip + 1);
1030	>	len += 1 + op_len + ix86_step_over_modrm(eip + op_len);
1031		break;
1032	+	case 0x00: // ADD r/m8, r8
1033	+	transfer_size = SIZE_BYTE;
1034	+	case 0x01: // ADD r/m32, r32
1035	+	instruction_type = i_ADD;
1036	+	goto do_transfer_store;
1037		case 0x88: // MOV r/m8, r8
1038		transfer_size = SIZE_BYTE;
1039		case 0x89: // MOV r/m32, r32 (or 16-bit operation)
1040	<	switch (eip[1] & 0xc0) {
1040	>	do_transfer_store:
1041	>	switch (eip[op_len] & 0xc0) {
1042		case 0x80:
1043	<	reg = (eip[1] >> 3) & 7;
1043	>	reg = (eip[op_len] >> 3) & 7;
1044		transfer_type = SIGSEGV_TRANSFER_STORE;
1045		break;
1046		case 0x40:
1047	<	reg = (eip[1] >> 3) & 7;
1047	>	reg = (eip[op_len] >> 3) & 7;
1048		transfer_type = SIGSEGV_TRANSFER_STORE;
1049		break;
1050		case 0x00:
1051	<	reg = (eip[1] >> 3) & 7;
1051	>	reg = (eip[op_len] >> 3) & 7;
1052		transfer_type = SIGSEGV_TRANSFER_STORE;
1053		break;
1054		}
1055	<	len += 2 + ix86_step_over_modrm(eip + 1);
1055	>	len += 1 + op_len + ix86_step_over_modrm(eip + op_len);
1056		break;
1057		}
1058	+	if (target_size == SIZE_UNKNOWN)
1059	+	target_size = transfer_size;
1060
1061		if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1062		// Unknown machine code, let it crash. Then patch the decoder
1063		return false;
1064		}
1065
1066	<	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
1067	<	static const int x86_reg_map[8] = {
1066	>	#if defined(__x86_64__)
1067	>	if (rex.R)
1068	>	reg += 8;
1069	>	#endif
1070	>
1071	>	if (instruction_type == i_MOV && transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
1072	>	static const int x86_reg_map[] = {
1073		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
1074	<	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI
1074	>	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
1075	>	#if defined(__x86_64__)
1076	>	X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
1077	>	X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
1078	>	#endif
1079		};
1080
1081	<	if (reg < 0 \|\| reg >= 8)
1081	>	if (reg < 0 \|\| reg >= (sizeof(x86_reg_map)/sizeof(x86_reg_map[0]) - 1))
1082		return false;
1083
1084	+	// Set 0 to the relevant register part
1085	+	// NOTE: this is only valid for MOV alike instructions
1086		int rloc = x86_reg_map[reg];
1087	<	switch (transfer_size) {
1087	>	switch (target_size) {
1088		case SIZE_BYTE:
1089	<	regs[rloc] = (regs[rloc] & ~0xff);
1089	>	if (has_rex \|\| reg < 4)
1090	>	regs[rloc] = (regs[rloc] & ~0x00ffL);
1091	>	else {
1092	>	rloc = x86_reg_map[reg - 4];
1093	>	regs[rloc] = (regs[rloc] & ~0xff00L);
1094	>	}
1095		break;
1096		case SIZE_WORD:
1097	<	regs[rloc] = (regs[rloc] & ~0xffff);
1097	>	regs[rloc] = (regs[rloc] & ~0xffffL);
1098		break;
1099		case SIZE_LONG:
1100	+	case SIZE_QUAD: // zero-extension
1101		regs[rloc] = 0;
1102		break;
1103		}
1104		}
1105
1106		#if DEBUG
1107	<	printf("%08x: %s %s access", regs[X86_REG_EIP],
1108	<	transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : "long",
1107	>	printf("%p: %s %s access", (void *)regs[X86_REG_EIP],
1108	>	transfer_size == SIZE_BYTE ? "byte" :
1109	>	transfer_size == SIZE_WORD ? "word" :
1110	>	transfer_size == SIZE_LONG ? "long" :
1111	>	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1112		transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1113
1114		if (reg != -1) {
1115	<	static const char * x86_reg_str_map[8] = {
1116	<	"eax", "ecx", "edx", "ebx",
1117	<	"esp", "ebp", "esi", "edi"
1115	>	static const char * x86_byte_reg_str_map[] = {
1116	>	"al", "cl", "dl", "bl",
1117	>	"spl", "bpl", "sil", "dil",
1118	>	"r8b", "r9b", "r10b", "r11b",
1119	>	"r12b", "r13b", "r14b", "r15b",
1120	>	"ah", "ch", "dh", "bh",
1121	>	};
1122	>	static const char * x86_word_reg_str_map[] = {
1123	>	"ax", "cx", "dx", "bx",
1124	>	"sp", "bp", "si", "di",
1125	>	"r8w", "r9w", "r10w", "r11w",
1126	>	"r12w", "r13w", "r14w", "r15w",
1127	>	};
1128	>	static const char *x86_long_reg_str_map[] = {
1129	>	"eax", "ecx", "edx", "ebx",
1130	>	"esp", "ebp", "esi", "edi",
1131	>	"r8d", "r9d", "r10d", "r11d",
1132	>	"r12d", "r13d", "r14d", "r15d",
1133	>	};
1134	>	static const char *x86_quad_reg_str_map[] = {
1135	>	"rax", "rcx", "rdx", "rbx",
1136	>	"rsp", "rbp", "rsi", "rdi",
1137	>	"r8", "r9", "r10", "r11",
1138	>	"r12", "r13", "r14", "r15",
1139		};
1140	<	printf(" %s register %%%s", transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from", x86_reg_str_map[reg]);
1140	>	const char * reg_str = NULL;
1141	>	switch (target_size) {
1142	>	case SIZE_BYTE:
1143	>	reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
1144	>	break;
1145	>	case SIZE_WORD: reg_str = x86_word_reg_str_map[reg]; break;
1146	>	case SIZE_LONG: reg_str = x86_long_reg_str_map[reg]; break;
1147	>	case SIZE_QUAD: reg_str = x86_quad_reg_str_map[reg]; break;
1148	>	}
1149	>	if (reg_str)
1150	>	printf(" %s register %%%s",
1151	>	transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from",
1152	>	reg_str);
1153		}
1154		printf(", %d bytes instruction\n", len);
1155		#endif
#	Line 772 \| Line 1161 \| static bool ix86_skip_instruction(unsign
1161
1162		// Decode and skip PPC instruction
1163		#if (defined(powerpc) \|\| defined(__powerpc__) \|\| defined(__ppc__))
1164	<	static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs)
1164	>	static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
1165		{
1166		instruction_t instr;
1167		powerpc_decode_instruction(&instr, *nip_p, regs);
#	Line 784 \| Line 1173 \| static bool powerpc_skip_instruction(uns
1173
1174		#if DEBUG
1175		printf("%08x: %s %s access", *nip_p,
1176	<	instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long",
1176	>	instr.transfer_size == SIZE_BYTE ? "byte" :
1177	>	instr.transfer_size == SIZE_WORD ? "word" :
1178	>	instr.transfer_size == SIZE_LONG ? "long" : "quad",
1179		instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1180
1181		if (instr.addr_mode == MODE_U \|\| instr.addr_mode == MODE_UX)
#	Line 802 \| Line 1193 \| static bool powerpc_skip_instruction(uns
1193		return true;
1194		}
1195		#endif
1196	+
1197	+	// Decode and skip MIPS instruction
1198	+	#if (defined(mips) \|\| defined(__mips))
1199	+	static bool mips_skip_instruction(greg_t * pc_p, greg_t * regs)
1200	+	{
1201	+	unsigned int * epc = (unsigned int )(unsigned long)pc_p;
1202	+
1203	+	if (epc == 0)
1204	+	return false;
1205	+
1206	+	#if DEBUG
1207	+	printf("IP: %p [%08x]\n", epc, epc[0]);
1208	+	#endif
1209	+
1210	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1211	+	transfer_size_t transfer_size = SIZE_LONG;
1212	+	int direction = 0;
1213	+
1214	+	const unsigned int opcode = epc[0];
1215	+	switch (opcode >> 26) {
1216	+	case 32: // Load Byte
1217	+	case 36: // Load Byte Unsigned
1218	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1219	+	transfer_size = SIZE_BYTE;
1220	+	break;
1221	+	case 33: // Load Halfword
1222	+	case 37: // Load Halfword Unsigned
1223	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1224	+	transfer_size = SIZE_WORD;
1225	+	break;
1226	+	case 35: // Load Word
1227	+	case 39: // Load Word Unsigned
1228	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1229	+	transfer_size = SIZE_LONG;
1230	+	break;
1231	+	case 34: // Load Word Left
1232	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1233	+	transfer_size = SIZE_LONG;
1234	+	direction = -1;
1235	+	break;
1236	+	case 38: // Load Word Right
1237	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1238	+	transfer_size = SIZE_LONG;
1239	+	direction = 1;
1240	+	break;
1241	+	case 55: // Load Doubleword
1242	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1243	+	transfer_size = SIZE_QUAD;
1244	+	break;
1245	+	case 26: // Load Doubleword Left
1246	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1247	+	transfer_size = SIZE_QUAD;
1248	+	direction = -1;
1249	+	break;
1250	+	case 27: // Load Doubleword Right
1251	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1252	+	transfer_size = SIZE_QUAD;
1253	+	direction = 1;
1254	+	break;
1255	+	case 40: // Store Byte
1256	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1257	+	transfer_size = SIZE_BYTE;
1258	+	break;
1259	+	case 41: // Store Halfword
1260	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1261	+	transfer_size = SIZE_WORD;
1262	+	break;
1263	+	case 43: // Store Word
1264	+	case 42: // Store Word Left
1265	+	case 46: // Store Word Right
1266	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1267	+	transfer_size = SIZE_LONG;
1268	+	break;
1269	+	case 63: // Store Doubleword
1270	+	case 44: // Store Doubleword Left
1271	+	case 45: // Store Doubleword Right
1272	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1273	+	transfer_size = SIZE_QUAD;
1274	+	break;
1275	+	/* Misc instructions unlikely to be used within CPU emulators */
1276	+	case 48: // Load Linked Word
1277	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1278	+	transfer_size = SIZE_LONG;
1279	+	break;
1280	+	case 52: // Load Linked Doubleword
1281	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1282	+	transfer_size = SIZE_QUAD;
1283	+	break;
1284	+	case 56: // Store Conditional Word
1285	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1286	+	transfer_size = SIZE_LONG;
1287	+	break;
1288	+	case 60: // Store Conditional Doubleword
1289	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1290	+	transfer_size = SIZE_QUAD;
1291	+	break;
1292	+	}
1293	+
1294	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1295	+	// Unknown machine code, let it crash. Then patch the decoder
1296	+	return false;
1297	+	}
1298	+
1299	+	// Zero target register in case of a load operation
1300	+	const int reg = (opcode >> 16) & 0x1f;
1301	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD) {
1302	+	if (direction == 0)
1303	+	regs[reg] = 0;
1304	+	else {
1305	+	// FIXME: untested code
1306	+	unsigned long ea = regs[(opcode >> 21) & 0x1f];
1307	+	ea += (signed long)(signed int)(signed short)(opcode & 0xffff);
1308	+	const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7);
1309	+	unsigned long value;
1310	+	if (direction > 0) {
1311	+	const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1);
1312	+	value = regs[reg] & rmask;
1313	+	}
1314	+	else {
1315	+	const unsigned long lmask = (1L << (offset * 8)) - 1;
1316	+	value = regs[reg] & lmask;
1317	+	}
1318	+	// restore most significant bits
1319	+	if (transfer_size == SIZE_LONG)
1320	+	value = (signed long)(signed int)value;
1321	+	regs[reg] = value;
1322	+	}
1323	+	}
1324	+
1325	+	#if DEBUG
1326	+	#if (defined(_ABIN32) \|\| defined(_ABI64))
1327	+	static const char * mips_gpr_names[32] = {
1328	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1329	+	"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1330	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1331	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1332	+	};
1333	+	#else
1334	+	static const char * mips_gpr_names[32] = {
1335	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1336	+	"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
1337	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1338	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1339	+	};
1340	+	#endif
1341	+	printf("%s %s register %s\n",
1342	+	transfer_size == SIZE_BYTE ? "byte" :
1343	+	transfer_size == SIZE_WORD ? "word" :
1344	+	transfer_size == SIZE_LONG ? "long" :
1345	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1346	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1347	+	mips_gpr_names[reg]);
1348	+	#endif
1349	+
1350	+	*pc_p += 4;
1351	+	return true;
1352	+	}
1353	+	#endif
1354	+
1355	+	// Decode and skip SPARC instruction
1356	+	#if (defined(sparc) \|\| defined(__sparc__))
1357	+	enum {
1358	+	#if (defined(__sun__))
1359	+	SPARC_REG_G1 = REG_G1,
1360	+	SPARC_REG_O0 = REG_O0,
1361	+	SPARC_REG_PC = REG_PC,
1362	+	SPARC_REG_nPC = REG_nPC
1363	+	#endif
1364	+	};
1365	+	static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
1366	+	{
1367	+	unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
1368	+
1369	+	if (pc == 0)
1370	+	return false;
1371	+
1372	+	#if DEBUG
1373	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1374	+	#endif
1375	+
1376	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1377	+	transfer_size_t transfer_size = SIZE_LONG;
1378	+	bool register_pair = false;
1379	+
1380	+	const unsigned int opcode = pc[0];
1381	+	if ((opcode >> 30) != 3)
1382	+	return false;
1383	+	switch ((opcode >> 19) & 0x3f) {
1384	+	case 9: // Load Signed Byte
1385	+	case 1: // Load Unsigned Byte
1386	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1387	+	transfer_size = SIZE_BYTE;
1388	+	break;
1389	+	case 10:// Load Signed Halfword
1390	+	case 2: // Load Unsigned Word
1391	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1392	+	transfer_size = SIZE_WORD;
1393	+	break;
1394	+	case 8: // Load Word
1395	+	case 0: // Load Unsigned Word
1396	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1397	+	transfer_size = SIZE_LONG;
1398	+	break;
1399	+	case 11:// Load Extended Word
1400	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1401	+	transfer_size = SIZE_QUAD;
1402	+	break;
1403	+	case 3: // Load Doubleword
1404	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1405	+	transfer_size = SIZE_LONG;
1406	+	register_pair = true;
1407	+	break;
1408	+	case 5: // Store Byte
1409	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1410	+	transfer_size = SIZE_BYTE;
1411	+	break;
1412	+	case 6: // Store Halfword
1413	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1414	+	transfer_size = SIZE_WORD;
1415	+	break;
1416	+	case 4: // Store Word
1417	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1418	+	transfer_size = SIZE_LONG;
1419	+	break;
1420	+	case 14:// Store Extended Word
1421	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1422	+	transfer_size = SIZE_QUAD;
1423	+	break;
1424	+	case 7: // Store Doubleword
1425	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1426	+	transfer_size = SIZE_LONG;
1427	+	register_pair = true;
1428	+	break;
1429	+	}
1430	+
1431	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1432	+	// Unknown machine code, let it crash. Then patch the decoder
1433	+	return false;
1434	+	}
1435	+
1436	+	const int reg = (opcode >> 25) & 0x1f;
1437	+
1438	+	#if DEBUG
1439	+	static const char * reg_names[] = {
1440	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1441	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1442	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1443	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1444	+	};
1445	+	printf("%s %s register %s\n",
1446	+	transfer_size == SIZE_BYTE ? "byte" :
1447	+	transfer_size == SIZE_WORD ? "word" :
1448	+	transfer_size == SIZE_LONG ? "long" :
1449	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1450	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1451	+	reg_names[reg]);
1452	+	#endif
1453	+
1454	+	// Zero target register in case of a load operation
1455	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1456	+	// FIXME: code to handle local & input registers is not tested
1457	+	if (reg >= 1 && reg < 8) {
1458	+	// global registers
1459	+	regs[reg - 1 + SPARC_REG_G1] = 0;
1460	+	}
1461	+	else if (reg >= 8 && reg < 16) {
1462	+	// output registers
1463	+	regs[reg - 8 + SPARC_REG_O0] = 0;
1464	+	}
1465	+	else if (reg >= 16 && reg < 24) {
1466	+	// local registers (in register windows)
1467	+	if (gwins)
1468	+	gwins->wbuf->rw_local[reg - 16] = 0;
1469	+	else
1470	+	rwin->rw_local[reg - 16] = 0;
1471	+	}
1472	+	else {
1473	+	// input registers (in register windows)
1474	+	if (gwins)
1475	+	gwins->wbuf->rw_in[reg - 24] = 0;
1476	+	else
1477	+	rwin->rw_in[reg - 24] = 0;
1478	+	}
1479	+	}
1480	+
1481	+	regs[SPARC_REG_PC] += 4;
1482	+	regs[SPARC_REG_nPC] += 4;
1483	+	return true;
1484	+	}
1485	+	#endif
1486	+	#endif
1487	+
1488	+	// Decode and skip ARM instruction
1489	+	#if (defined(arm) \|\| defined(__arm__))
1490	+	enum {
1491	+	#if (defined(__linux__))
1492	+	ARM_REG_PC = 15,
1493	+	ARM_REG_CPSR = 16
1494	+	#endif
1495	+	};
1496	+	static bool arm_skip_instruction(unsigned long * regs)
1497	+	{
1498	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
1499	+
1500	+	if (pc == 0)
1501	+	return false;
1502	+
1503	+	#if DEBUG
1504	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1505	+	#endif
1506	+
1507	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1508	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1509	+	enum { op_sdt = 1, op_sdth = 2 };
1510	+	int op = 0;
1511	+
1512	+	// Handle load/store instructions only
1513	+	const unsigned int opcode = pc[0];
1514	+	switch ((opcode >> 25) & 7) {
1515	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
1516	+	op = op_sdth;
1517	+	// Determine transfer size (S/H bits)
1518	+	switch ((opcode >> 5) & 3) {
1519	+	case 0: // SWP instruction
1520	+	break;
1521	+	case 1: // Unsigned halfwords
1522	+	case 3: // Signed halfwords
1523	+	transfer_size = SIZE_WORD;
1524	+	break;
1525	+	case 2: // Signed byte
1526	+	transfer_size = SIZE_BYTE;
1527	+	break;
1528	+	}
1529	+	break;
1530	+	case 2:
1531	+	case 3: // Single Data Transfer (LDR, STR)
1532	+	op = op_sdt;
1533	+	// Determine transfer size (B bit)
1534	+	if (((opcode >> 22) & 1) == 1)
1535	+	transfer_size = SIZE_BYTE;
1536	+	else
1537	+	transfer_size = SIZE_LONG;
1538	+	break;
1539	+	default:
1540	+	// FIXME: support load/store mutliple?
1541	+	return false;
1542	+	}
1543	+
1544	+	// Check for invalid transfer size (SWP instruction?)
1545	+	if (transfer_size == SIZE_UNKNOWN)
1546	+	return false;
1547	+
1548	+	// Determine transfer type (L bit)
1549	+	if (((opcode >> 20) & 1) == 1)
1550	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1551	+	else
1552	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1553	+
1554	+	// Compute offset
1555	+	int offset;
1556	+	if (((opcode >> 25) & 1) == 0) {
1557	+	if (op == op_sdt)
1558	+	offset = opcode & 0xfff;
1559	+	else if (op == op_sdth) {
1560	+	int rm = opcode & 0xf;
1561	+	if (((opcode >> 22) & 1) == 0) {
1562	+	// register offset
1563	+	offset = regs[rm];
1564	+	}
1565	+	else {
1566	+	// immediate offset
1567	+	offset = ((opcode >> 4) & 0xf0) \| (opcode & 0x0f);
1568	+	}
1569	+	}
1570	+	}
1571	+	else {
1572	+	const int rm = opcode & 0xf;
1573	+	const int sh = (opcode >> 7) & 0x1f;
1574	+	if (((opcode >> 4) & 1) == 1) {
1575	+	// we expect only legal load/store instructions
1576	+	printf("FATAL: invalid shift operand\n");
1577	+	return false;
1578	+	}
1579	+	const unsigned int v = regs[rm];
1580	+	switch ((opcode >> 5) & 3) {
1581	+	case 0: // logical shift left
1582	+	offset = sh ? v << sh : v;
1583	+	break;
1584	+	case 1: // logical shift right
1585	+	offset = sh ? v >> sh : 0;
1586	+	break;
1587	+	case 2: // arithmetic shift right
1588	+	if (sh)
1589	+	offset = ((signed int)v) >> sh;
1590	+	else
1591	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
1592	+	break;
1593	+	case 3: // rotate right
1594	+	if (sh)
1595	+	offset = (v >> sh) \| (v << (32 - sh));
1596	+	else
1597	+	offset = (v >> 1) \| ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
1598	+	break;
1599	+	}
1600	+	}
1601	+	if (((opcode >> 23) & 1) == 0)
1602	+	offset = -offset;
1603	+
1604	+	int rd = (opcode >> 12) & 0xf;
1605	+	int rn = (opcode >> 16) & 0xf;
1606	+	#if DEBUG
1607	+	static const char * reg_names[] = {
1608	+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1609	+	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
1610	+	};
1611	+	printf("%s %s register %s\n",
1612	+	transfer_size == SIZE_BYTE ? "byte" :
1613	+	transfer_size == SIZE_WORD ? "word" :
1614	+	transfer_size == SIZE_LONG ? "long" : "unknown",
1615	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1616	+	reg_names[rd]);
1617	+	#endif
1618	+
1619	+	unsigned int base = regs[rn];
1620	+	if (((opcode >> 24) & 1) == 1)
1621	+	base += offset;
1622	+
1623	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
1624	+	regs[rd] = 0;
1625	+
1626	+	if (((opcode >> 24) & 1) == 0) // post-index addressing
1627	+	regs[rn] += offset;
1628	+	else if (((opcode >> 21) & 1) == 1) // write-back address into base
1629	+	regs[rn] = base;
1630	+
1631	+	regs[ARM_REG_PC] += 4;
1632	+	return true;
1633	+	}
1634		#endif
1635
1636	+
1637		// Fallbacks
1638		#ifndef SIGSEGV_FAULT_INSTRUCTION
1639	<	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_INVALID_PC
1639	>	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_INVALID_ADDRESS
1640		#endif
1641		#ifndef SIGSEGV_FAULT_HANDLER_ARGLIST_1
1642		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 SIGSEGV_FAULT_HANDLER_ARGLIST
1643		#endif
1644		#ifndef SIGSEGV_FAULT_HANDLER_INVOKE
1645	<	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) sigsegv_fault_handler(ADDR, IP)
1645	>	#define SIGSEGV_FAULT_HANDLER_INVOKE(P) sigsegv_fault_handler(P)
1646		#endif
1647
1648		// SIGSEGV recovery supported ?
#	Line 825 \| Line 1655 \| static bool powerpc_skip_instruction(uns
1655		* SIGSEGV global handler
1656		*/
1657
1658	<	#if defined(HAVE_SIGSEGV_RECOVERY) \|\| defined(HAVE_MACH_EXCEPTIONS)
1658	>	struct sigsegv_info_t {
1659	>	sigsegv_address_t addr;
1660	>	sigsegv_address_t pc;
1661	>	};
1662	>
1663	>	// Return the address of the invalid memory reference
1664	>	sigsegv_address_t sigsegv_get_fault_address(sigsegv_info_t *sip)
1665	>	{
1666	>	return sip->addr;
1667	>	}
1668	>
1669	>	// Return the address of the instruction that caused the fault, or
1670	>	// SIGSEGV_INVALID_ADDRESS if we could not retrieve this information
1671	>	sigsegv_address_t sigsegv_get_fault_instruction_address(sigsegv_info_t *sip)
1672	>	{
1673	>	return sip->pc;
1674	>	}
1675	>
1676		// This function handles the badaccess to memory.
1677		// It is called from the signal handler or the exception handler.
1678		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
1679		{
1680	<	sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
1681	<	sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
1680	>	#ifdef HAVE_MACH_EXCEPTIONS
1681	>	// We must match the initial count when writing back the CPU state registers
1682	>	kern_return_t krc;
1683	>	mach_msg_type_number_t count;
1684	>	SIGSEGV_THREAD_STATE_TYPE state;
1685	>
1686	>	count = SIGSEGV_THREAD_STATE_COUNT;
1687	>	krc = thread_get_state(thread, SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)&state, &count);
1688	>	MACH_CHECK_ERROR (thread_get_state, krc);
1689	>	#endif
1690	>
1691	>	sigsegv_info_t si;
1692	>	si.addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
1693	>	si.pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
1694
1695		// Call user's handler and reinstall the global handler, if required
1696	<	switch (SIGSEGV_FAULT_HANDLER_INVOKE(fault_address, fault_instruction)) {
1696	>	switch (SIGSEGV_FAULT_HANDLER_INVOKE(&si)) {
1697		case SIGSEGV_RETURN_SUCCESS:
1698		return true;
1699
#	Line 848 \| Line 1707 \| static bool handle_badaccess(SIGSEGV_FAU
1707		// is modified off of the stack, in Mach we
1708		// need to actually call thread_set_state to
1709		// have the register values updated.
851	–	kern_return_t krc;
852	–
1710		krc = thread_set_state(thread,
1711	<	MACHINE_THREAD_STATE, (thread_state_t)state,
1712	<	MACHINE_THREAD_STATE_COUNT);
1713	<	MACH_CHECK_ERROR (thread_get_state, krc);
1711	>	SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)&state,
1712	>	count);
1713	>	MACH_CHECK_ERROR (thread_set_state, krc);
1714		#endif
1715		return true;
1716		}
1717		break;
1718		#endif
1719	+	case SIGSEGV_RETURN_FAILURE:
1720	+	// We can't do anything with the fault_address, dump state?
1721	+	if (sigsegv_state_dumper != 0)
1722	+	sigsegv_state_dumper(&si);
1723	+	break;
1724		}
863	–
864	–	// We can't do anything with the fault_address, dump state?
865	–	if (sigsegv_state_dumper != 0)
866	–	sigsegv_state_dumper(fault_address, fault_instruction);
1725
1726		return false;
1727		}
870	–	#endif
1728
1729
1730		/*
#	Line 904 \| Line 1761 \| forward_exception(mach_port_t thread_por
1761		mach_port_t port;
1762		exception_behavior_t behavior;
1763		thread_state_flavor_t flavor;
1764	<	thread_state_t thread_state;
1764	>	thread_state_data_t thread_state;
1765		mach_msg_type_number_t thread_state_count;
1766
1767		for (portIndex = 0; portIndex < oldExceptionPorts->maskCount; portIndex++) {
#	Line 923 \| Line 1780 \| forward_exception(mach_port_t thread_por
1780		behavior = oldExceptionPorts->behaviors[portIndex];
1781		flavor = oldExceptionPorts->flavors[portIndex];
1782
1783	+	if (!VALID_THREAD_STATE_FLAVOR(flavor)) {
1784	+	fprintf(stderr, "Invalid thread_state flavor = %d. Not forwarding\n", flavor);
1785	+	return KERN_FAILURE;
1786	+	}
1787	+
1788		/*
1789		fprintf(stderr, "forwarding exception, port = 0x%x, behaviour = %d, flavor = %d\n", port, behavior, flavor);
1790		*/
1791
1792		if (behavior != EXCEPTION_DEFAULT) {
1793		thread_state_count = THREAD_STATE_MAX;
1794	<	kret = thread_get_state (thread_port, flavor, thread_state,
1794	>	kret = thread_get_state (thread_port, flavor, (natural_t *)&thread_state,
1795		&thread_state_count);
1796		MACH_CHECK_ERROR (thread_get_state, kret);
1797		}
#	Line 945 \| Line 1807 \| forward_exception(mach_port_t thread_por
1807		// fprintf(stderr, "forwarding to exception_raise_state\n");
1808		kret = exception_raise_state(port, exception_type, exception_data,
1809		data_count, &flavor,
1810	<	thread_state, thread_state_count,
1811	<	thread_state, &thread_state_count);
1810	>	(natural_t *)&thread_state, thread_state_count,
1811	>	(natural_t *)&thread_state, &thread_state_count);
1812		MACH_CHECK_ERROR (exception_raise_state, kret);
1813		break;
1814		case EXCEPTION_STATE_IDENTITY:
#	Line 954 \| Line 1816 \| forward_exception(mach_port_t thread_por
1816		kret = exception_raise_state_identity(port, thread_port, task_port,
1817		exception_type, exception_data,
1818		data_count, &flavor,
1819	<	thread_state, thread_state_count,
1820	<	thread_state, &thread_state_count);
1819	>	(natural_t *)&thread_state, thread_state_count,
1820	>	(natural_t *)&thread_state, &thread_state_count);
1821		MACH_CHECK_ERROR (exception_raise_state_identity, kret);
1822		break;
1823		default:
1824		fprintf(stderr, "forward_exception got unknown behavior\n");
1825	+	kret = KERN_FAILURE;
1826		break;
1827		}
1828
1829		if (behavior != EXCEPTION_DEFAULT) {
1830	<	kret = thread_set_state (thread_port, flavor, thread_state,
1830	>	kret = thread_set_state (thread_port, flavor, (natural_t *)&thread_state,
1831		thread_state_count);
1832		MACH_CHECK_ERROR (thread_set_state, kret);
1833		}
1834
1835	<	return KERN_SUCCESS;
1835	>	return kret;
1836		}
1837
1838		/*
#	Line 997 \| Line 1860 \| catch_exception_raise(mach_port_t except
1860		mach_port_t task,
1861		exception_type_t exception,
1862		exception_data_t code,
1863	<	mach_msg_type_number_t codeCount)
1863	>	mach_msg_type_number_t code_count)
1864		{
1002	–	ppc_thread_state_t state;
1865		kern_return_t krc;
1866
1867	<	if ((exception == EXC_BAD_ACCESS) && (codeCount >= 2)) {
1868	<	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
1869	<	return KERN_SUCCESS;
1867	>	if (exception == EXC_BAD_ACCESS) {
1868	>	switch (code[0]) {
1869	>	case KERN_PROTECTION_FAILURE:
1870	>	case KERN_INVALID_ADDRESS:
1871	>	{
1872	>	#ifdef SIGSEGV_EXCEPTION_STATE_TYPE
1873	>	SIGSEGV_EXCEPTION_STATE_TYPE exc_state;
1874	>	mach_msg_type_number_t exc_state_count;
1875	>	exc_state_count = SIGSEGV_EXCEPTION_STATE_COUNT;
1876	>	krc = thread_get_state(thread, SIGSEGV_EXCEPTION_STATE_FLAVOR, (natural_t *)&exc_state, &exc_state_count);
1877	>	MACH_CHECK_ERROR (thread_get_state, krc);
1878	>	#endif
1879	>
1880	>	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
1881	>	return KERN_SUCCESS;
1882	>	break;
1883	>	}
1884	>	}
1885		}
1886
1887		// In Mach we do not need to remove the exception handler.
1888		// If we forward the exception, eventually some exception handler
1889		// will take care of this exception.
1890	<	krc = forward_exception(thread, task, exception, code, codeCount, &ports);
1890	>	krc = forward_exception(thread, task, exception, code, code_count, &ports);
1891
1892		return krc;
1893		}
#	Line 1138 \| Line 2015 \| static bool sigsegv_do_install_handler(s
2015		// addressing modes) used in PPC instructions, you will need the
2016		// GPR state anyway.
2017		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
2018	<	EXCEPTION_DEFAULT, MACHINE_THREAD_STATE);
2018	>	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
2019		if (krc != KERN_SUCCESS) {
2020		mach_error("thread_set_exception_ports", krc);
2021		return false;
#	Line 1161 \| Line 2038 \| static bool sigsegv_do_install_handler(s
2038		}
2039		#endif
2040
2041	+	#ifdef HAVE_WIN32_EXCEPTIONS
2042	+	static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo)
2043	+	{
2044	+	if (sigsegv_fault_handler != NULL
2045	+	&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
2046	+	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
2047	+	&& handle_badaccess(ExceptionInfo))
2048	+	return EXCEPTION_CONTINUE_EXECUTION;
2049	+
2050	+	return EXCEPTION_CONTINUE_SEARCH;
2051	+	}
2052	+
2053	+	#if defined __CYGWIN__ && defined __i386__
2054	+	/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin
2055	+	installs a global exception handler. We have to dig deep in order to install
2056	+	our main_exception_filter. */
2057	+
2058	+	/* Data structures for the current thread's exception handler chain.
2059	+	On the x86 Windows uses register fs, offset 0 to point to the current
2060	+	exception handler; Cygwin mucks with it, so we must do the same... :-/ */
2061	+
2062	+	/* Magic taken from winsup/cygwin/include/exceptions.h. */
2063	+
2064	+	struct exception_list {
2065	+	struct exception_list *prev;
2066	+	int (handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
2067	+	};
2068	+	typedef struct exception_list exception_list;
2069	+
2070	+	/* Magic taken from winsup/cygwin/exceptions.cc. */
2071	+
2072	+	__asm__ (".equ __except_list,0");
2073	+
2074	+	extern exception_list *_except_list __asm__ ("%fs:__except_list");
2075	+
2076	+	/* For debugging. _except_list is not otherwise accessible from gdb. */
2077	+	static exception_list *
2078	+	debug_get_except_list ()
2079	+	{
2080	+	return _except_list;
2081	+	}
2082	+
2083	+	/* Cygwin's original exception handler. */
2084	+	static int (cygwin_exception_handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
2085	+
2086	+	/* Our exception handler. */
2087	+	static int
2088	+	libsigsegv_exception_handler (EXCEPTION_RECORD exception, void frame, CONTEXT context, void dispatch)
2089	+	{
2090	+	EXCEPTION_POINTERS ExceptionInfo;
2091	+	ExceptionInfo.ExceptionRecord = exception;
2092	+	ExceptionInfo.ContextRecord = context;
2093	+	if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH)
2094	+	return cygwin_exception_handler (exception, frame, context, dispatch);
2095	+	else
2096	+	return 0;
2097	+	}
2098	+
2099	+	static void
2100	+	do_install_main_exception_filter ()
2101	+	{
2102	+	/* We cannot insert any handler into the chain, because such handlers
2103	+	must lie on the stack (?). Instead, we have to replace(!) Cygwin's
2104	+	global exception handler. */
2105	+	cygwin_exception_handler = _except_list->handler;
2106	+	_except_list->handler = libsigsegv_exception_handler;
2107	+	}
2108	+
2109	+	#else
2110	+
2111	+	static void
2112	+	do_install_main_exception_filter ()
2113	+	{
2114	+	SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter);
2115	+	}
2116	+	#endif
2117	+
2118	+	static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler)
2119	+	{
2120	+	static bool main_exception_filter_installed = false;
2121	+	if (!main_exception_filter_installed) {
2122	+	do_install_main_exception_filter();
2123	+	main_exception_filter_installed = true;
2124	+	}
2125	+	sigsegv_fault_handler = handler;
2126	+	return true;
2127	+	}
2128	+	#endif
2129	+
2130		bool sigsegv_install_handler(sigsegv_fault_handler_t handler)
2131		{
2132		#if defined(HAVE_SIGSEGV_RECOVERY)
#	Line 1171 \| Line 2137 \| bool sigsegv_install_handler(sigsegv_fau
2137		if (success)
2138		sigsegv_fault_handler = handler;
2139		return success;
2140	<	#elif defined(HAVE_MACH_EXCEPTIONS)
2140	>	#elif defined(HAVE_MACH_EXCEPTIONS) \|\| defined(HAVE_WIN32_EXCEPTIONS)
2141		return sigsegv_do_install_handler(handler);
2142		#else
2143		// FAIL: no siginfo_t nor sigcontext subterfuge is available
#	Line 1197 \| Line 2163 \| void sigsegv_deinstall_handler(void)
2163		SIGSEGV_ALL_SIGNALS
2164		#undef FAULT_HANDLER
2165		#endif
2166	+	#ifdef HAVE_WIN32_EXCEPTIONS
2167	+	sigsegv_fault_handler = NULL;
2168	+	#endif
2169		}
2170
2171
#	Line 1218 \| Line 2187 \| void sigsegv_set_dump_state(sigsegv_stat
2187		#include <stdio.h>
2188		#include <stdlib.h>
2189		#include <fcntl.h>
2190	+	#ifdef HAVE_SYS_MMAN_H
2191		#include <sys/mman.h>
2192	+	#endif
2193		#include "vm_alloc.h"
2194
2195		const int REF_INDEX = 123;
#	Line 1228 \| Line 2199 \| static int page_size;
2199		static volatile char * page = 0;
2200		static volatile int handler_called = 0;
2201
2202	+	/* Barriers */
2203	+	#ifdef __GNUC__
2204	+	#define BARRIER() asm volatile ("" : : : "memory")
2205	+	#else
2206	+	#define BARRIER() /* nothing */
2207	+	#endif
2208	+
2209		#ifdef __GNUC__
2210		// Code range where we expect the fault to come from
2211		static void b_region, e_region;
2212		#endif
2213
2214	<	static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2214	>	static sigsegv_return_t sigsegv_test_handler(sigsegv_info_t *sip)
2215		{
2216	+	const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip);
2217	+	const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip);
2218	+	#if DEBUG
2219	+	printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
2220	+	printf("expected fault at %p\n", page + REF_INDEX);
2221	+	#ifdef __GNUC__
2222	+	printf("expected instruction address range: %p-%p\n", b_region, e_region);
2223	+	#endif
2224	+	#endif
2225		handler_called++;
2226		if ((fault_address - REF_INDEX) != page)
2227		exit(10);
2228		#ifdef __GNUC__
2229		// Make sure reported fault instruction address falls into
2230		// expected code range
2231	<	if (instruction_address != SIGSEGV_INVALID_PC
2231	>	if (instruction_address != SIGSEGV_INVALID_ADDRESS
2232		&& ((instruction_address < (sigsegv_address_t)b_region) \|\|
2233		(instruction_address >= (sigsegv_address_t)e_region)))
2234		exit(11);
#	Line 1252 \| Line 2239 \| static sigsegv_return_t sigsegv_test_han
2239		}
2240
2241		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
2242	<	static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2242	>	static sigsegv_return_t sigsegv_insn_handler(sigsegv_info_t *sip)
2243		{
2244	+	const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip);
2245	+	const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip);
2246	+	#if DEBUG
2247	+	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
2248	+	#endif
2249		if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
2250		#ifdef __GNUC__
2251		// Make sure reported fault instruction address falls into
2252		// expected code range
2253	<	if (instruction_address != SIGSEGV_INVALID_PC
2253	>	if (instruction_address != SIGSEGV_INVALID_ADDRESS
2254		&& ((instruction_address < (sigsegv_address_t)b_region) \|\|
2255		(instruction_address >= (sigsegv_address_t)e_region)))
2256		return SIGSEGV_RETURN_FAILURE;
#	Line 1268 \| Line 2260 \| static sigsegv_return_t sigsegv_insn_han
2260
2261		return SIGSEGV_RETURN_FAILURE;
2262		}
2263	+
2264	+	// More sophisticated tests for instruction skipper
2265	+	static bool arch_insn_skipper_tests()
2266	+	{
2267	+	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
2268	+	static const unsigned char code[] = {
2269	+	0x8a, 0x00, // mov (%eax),%al
2270	+	0x8a, 0x2c, 0x18, // mov (%eax,%ebx,1),%ch
2271	+	0x88, 0x20, // mov %ah,(%eax)
2272	+	0x88, 0x08, // mov %cl,(%eax)
2273	+	0x66, 0x8b, 0x00, // mov (%eax),%ax
2274	+	0x66, 0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%cx
2275	+	0x66, 0x89, 0x00, // mov %ax,(%eax)
2276	+	0x66, 0x89, 0x0c, 0x18, // mov %cx,(%eax,%ebx,1)
2277	+	0x8b, 0x00, // mov (%eax),%eax
2278	+	0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%ecx
2279	+	0x89, 0x00, // mov %eax,(%eax)
2280	+	0x89, 0x0c, 0x18, // mov %ecx,(%eax,%ebx,1)
2281	+	#if defined(__x86_64__)
2282	+	0x44, 0x8a, 0x00, // mov (%rax),%r8b
2283	+	0x44, 0x8a, 0x20, // mov (%rax),%r12b
2284	+	0x42, 0x8a, 0x3c, 0x10, // mov (%rax,%r10,1),%dil
2285	+	0x44, 0x88, 0x00, // mov %r8b,(%rax)
2286	+	0x44, 0x88, 0x20, // mov %r12b,(%rax)
2287	+	0x42, 0x88, 0x3c, 0x10, // mov %dil,(%rax,%r10,1)
2288	+	0x66, 0x44, 0x8b, 0x00, // mov (%rax),%r8w
2289	+	0x66, 0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%cx
2290	+	0x66, 0x44, 0x89, 0x00, // mov %r8w,(%rax)
2291	+	0x66, 0x42, 0x89, 0x0c, 0x10, // mov %cx,(%rax,%r10,1)
2292	+	0x44, 0x8b, 0x00, // mov (%rax),%r8d
2293	+	0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%ecx
2294	+	0x44, 0x89, 0x00, // mov %r8d,(%rax)
2295	+	0x42, 0x89, 0x0c, 0x10, // mov %ecx,(%rax,%r10,1)
2296	+	0x48, 0x8b, 0x08, // mov (%rax),%rcx
2297	+	0x4c, 0x8b, 0x18, // mov (%rax),%r11
2298	+	0x4a, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%rcx
2299	+	0x4e, 0x8b, 0x1c, 0x10, // mov (%rax,%r10,1),%r11
2300	+	0x48, 0x89, 0x08, // mov %rcx,(%rax)
2301	+	0x4c, 0x89, 0x18, // mov %r11,(%rax)
2302	+	0x4a, 0x89, 0x0c, 0x10, // mov %rcx,(%rax,%r10,1)
2303	+	0x4e, 0x89, 0x1c, 0x10, // mov %r11,(%rax,%r10,1)
2304	+	0x63, 0x47, 0x04, // movslq 4(%rdi),%eax
2305	+	0x48, 0x63, 0x47, 0x04, // movslq 4(%rdi),%rax
2306	+	#endif
2307	+	0 // end
2308	+	};
2309	+	const int N_REGS = 20;
2310	+	unsigned long regs[N_REGS];
2311	+	for (int i = 0; i < N_REGS; i++)
2312	+	regs[i] = i;
2313	+	const unsigned long start_code = (unsigned long)&code;
2314	+	regs[X86_REG_EIP] = start_code;
2315	+	while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
2316	+	&& ix86_skip_instruction(regs))
2317	+	; /* simply iterate */
2318	+	return (regs[X86_REG_EIP] - start_code) == (sizeof(code) - 1);
2319	+	#endif
2320	+	return true;
2321	+	}
2322		#endif
2323
2324		int main(void)
#	Line 1275 \| Line 2326 \| int main(void)
2326		if (vm_init() < 0)
2327		return 1;
2328
2329	<	page_size = getpagesize();
2329	>	page_size = vm_get_page_size();
2330		if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED)
2331		return 2;
2332
#	Line 1295 \| Line 2346 \| int main(void)
2346		if (page[REF_INDEX] != REF_VALUE)
2347		exit(20);
2348		page[REF_INDEX] = REF_VALUE;
2349	+	BARRIER();
2350		L_e_region1:
2351
2352		if (handler_called != 1)
#	Line 1314 \| Line 2366 \| int main(void)
2366		return 8;
2367
2368		#define TEST_SKIP_INSTRUCTION(TYPE) do { \
2369	<	const unsigned int TAG = 0x12345678; \
2369	>	const unsigned long TAG = 0x12345678 \| \
2370	>	(sizeof(long) == 8 ? 0x9abcdef0UL << 31 : 0); \
2371		TYPE data = ((TYPE )(page + sizeof(TYPE))); \
2372	<	volatile unsigned int effect = data + TAG; \
2372	>	volatile unsigned long effect = data + TAG; \
2373		if (effect != TAG) \
2374		return 9; \
2375		} while (0)
#	Line 1329 \| Line 2382 \| int main(void)
2382		TEST_SKIP_INSTRUCTION(unsigned char);
2383		TEST_SKIP_INSTRUCTION(unsigned short);
2384		TEST_SKIP_INSTRUCTION(unsigned int);
2385	+	TEST_SKIP_INSTRUCTION(unsigned long);
2386	+	TEST_SKIP_INSTRUCTION(signed char);
2387	+	TEST_SKIP_INSTRUCTION(signed short);
2388	+	TEST_SKIP_INSTRUCTION(signed int);
2389	+	TEST_SKIP_INSTRUCTION(signed long);
2390	+	BARRIER();
2391		L_e_region2:
2392	+
2393	+	if (!arch_insn_skipper_tests())
2394	+	return 20;
2395		#endif
2396
2397		vm_exit();
2398		return 0;
2399		}
2400		#endif
1339	–
1340	–
1341	–
1342	–
1343	–
1344	–
1345	–
1346	–
1347	–
1348	–
1349	–
1350	–
1351	–
1352	–
1353	–

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+Removed lines
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+Changed lines
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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.33 by gbeauche, 2003-10-21T23:10:19Z vs. Revision 1.67 by gbeauche, 2007-12-30T08:45:18Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.33 by gbeauche, 2003-10-21T23:10:19Z vs.
Revision 1.67 by gbeauche, 2007-12-30T08:45:18Z