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root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.30 by gbeauche, 2003-10-13T19:56:17Z vs.
Revision 1.81 by gbeauche, 2008-01-19T22:25:27Z

#	Line 10 | Line 10
10		*    tjw@omnigroup.com Sun, 4 Jun 2000
11		*    www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	*  Basilisk II (C) 1997-2002 Christian Bauer
13	>	*  Basilisk II (C) 1997-2008 Christian Bauer
14		*
15		*  This program is free software; you can redistribute it and/or modify
16		*  it under the terms of the GNU General Public License as published by
#	Line 36 | Line 36
36		#endif
37
38		#include <list>
39	+	#include <stdio.h>
40		#include <signal.h>
41		#include "sigsegv.h"
42
#	Line 48 | Line 49 | using std::list;
49		#define RETSIGTYPE void
50		#endif
51
52	+	// Size of an unsigned integer large enough to hold all bits of a pointer
53	+	// NOTE: this can be different than SIGSEGV_REGISTER_TYPE. In
54	+	// particular, on ILP32 systems with a 64-bit kernel (HP-UX/ia64?)
55	+	#ifdef HAVE_WIN32_VM
56	+	// Windows is either ILP32 or LLP64
57	+	typedef UINT_PTR sigsegv_uintptr_t;
58	+	#else
59	+	// Other systems are sane enough to follow ILP32 or LP64 models
60	+	typedef unsigned long sigsegv_uintptr_t;
61	+	#endif
62	+
63		// Type of the system signal handler
64		typedef RETSIGTYPE (*signal_handler)(int);
65
#	Line 65 | Line 77 | static bool sigsegv_do_install_handler(i
77		*  Instruction decoding aids
78		*/
79
80	+	// Transfer type
81	+	enum transfer_type_t {
82	+	SIGSEGV_TRANSFER_UNKNOWN        = 0,
83	+	SIGSEGV_TRANSFER_LOAD           = 1,
84	+	SIGSEGV_TRANSFER_STORE          = 2
85	+	};
86	+
87		// Transfer size
88		enum transfer_size_t {
89		SIZE_UNKNOWN,
90		SIZE_BYTE,
91	<	SIZE_WORD,
92	<	SIZE_LONG
91	>	SIZE_WORD, // 2 bytes
92	>	SIZE_LONG, // 4 bytes
93	>	SIZE_QUAD  // 8 bytes
94		};
95
96	<	// Transfer type
77	<	typedef sigsegv_transfer_type_t transfer_type_t;
78	<
79	<	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__))
96	>	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__))
97		// Addressing mode
98		enum addressing_mode_t {
99		MODE_UNKNOWN,
#	Line 95 | Line 112 | struct instruction_t {
112		char                            ra, rd;
113		};
114
115	<	static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned int * gpr)
115	>	static void powerpc_decode_instruction(instruction_t *instruction, unsigned int nip, unsigned long * gpr)
116		{
117		// Get opcode and divide into fields
118	<	unsigned int opcode = *((unsigned int *)nip);
118	>	unsigned int opcode = *((unsigned int *)(unsigned long)nip);
119		unsigned int primop = opcode >> 26;
120		unsigned int exop = (opcode >> 1) & 0x3ff;
121		unsigned int ra = (opcode >> 16) & 0x1f;
#	Line 172 | Line 189 | static void powerpc_decode_instruction(i
189		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break;
190		case 45:        // sthu
191		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break;
192	+	case 58:        // ld, ldu, lwa
193	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
194	+	transfer_size = SIZE_QUAD;
195	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
196	+	imm &= ~3;
197	+	break;
198	+	case 62:        // std, stdu, stq
199	+	transfer_type = SIGSEGV_TRANSFER_STORE;
200	+	transfer_size = SIZE_QUAD;
201	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
202	+	imm &= ~3;
203	+	break;
204		}
205
206		// Calculate effective address
#	Line 212 | Line 241 | static void powerpc_decode_instruction(i
241
242		#if HAVE_SIGINFO_T
243		// Generic extended signal handler
244	<	#define SIGSEGV_FAULT_HANDLER                   sigsegv_fault_handler
216	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
244	>	#if defined(__FreeBSD__)
245		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
246		#else
247		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
#	Line 222 | Line 250 | static void powerpc_decode_instruction(i
250		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t *sip, void *scp
251		#define SIGSEGV_FAULT_HANDLER_ARGS              sip, scp
252		#define SIGSEGV_FAULT_ADDRESS                   sip->si_addr
253	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
253	>	#if (defined(sgi) || defined(__sgi))
254	>	#include <ucontext.h>
255	>	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
256	>	#define SIGSEGV_FAULT_INSTRUCTION               (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
257	>	#if (defined(mips) || defined(__mips))
258	>	#define SIGSEGV_REGISTER_FILE                   &SIGSEGV_CONTEXT_REGS[CTX_EPC], &SIGSEGV_CONTEXT_REGS[CTX_R0]
259	>	#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
260	>	#endif
261	>	#endif
262	>	#if defined(__sun__)
263	>	#if (defined(sparc) || defined(__sparc__))
264	>	#include <sys/stack.h>
265	>	#include <sys/regset.h>
266	>	#include <sys/ucontext.h>
267	>	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
268	>	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[REG_PC]
269	>	#define SIGSEGV_SPARC_GWINDOWS                  (((ucontext_t *)scp)->uc_mcontext.gwins)
270	>	#define SIGSEGV_SPARC_RWINDOW                   (struct rwindow *)((char *)SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
271	>	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
272	>	#define SIGSEGV_SKIP_INSTRUCTION                sparc_skip_instruction
273	>	#endif
274	>	#if defined(__i386__)
275	>	#include <sys/regset.h>
276	>	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
277	>	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[EIP]
278	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
279	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
280	>	#endif
281	>	#endif
282	>	#if defined(__FreeBSD__) || defined(__OpenBSD__)
283		#if (defined(i386) || defined(__i386__))
284		#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_eip)
285	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned int *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
285	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
286	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
287	>	#endif
288	>	#endif
289	>	#if defined(__NetBSD__)
290	>	#if (defined(i386) || defined(__i386__))
291	>	#include <sys/ucontext.h>
292	>	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.__gregs)
293	>	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[_REG_EIP]
294	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
295		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
296		#endif
297	+	#if (defined(powerpc) || defined(__powerpc__))
298	+	#include <sys/ucontext.h>
299	+	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.__gregs)
300	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[_REG_PC]
301	+	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_PC], (unsigned long *)&SIGSEGV_CONTEXT_REGS[_REG_R0]
302	+	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
303	+	#endif
304		#endif
305		#if defined(__linux__)
306		#if (defined(i386) || defined(__i386__))
307		#include <sys/ucontext.h>
308		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
309		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
310	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)SIGSEGV_CONTEXT_REGS
310	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
311		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
312		#endif
313		#if (defined(x86_64) || defined(__x86_64__))
314		#include <sys/ucontext.h>
315		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
316		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
317	<	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
317	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)SIGSEGV_CONTEXT_REGS
318	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
319		#endif
320		#if (defined(ia64) || defined(__ia64__))
321	<	#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
321	>	#define SIGSEGV_CONTEXT_REGS                    ((struct sigcontext *)scp)
322	>	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
323	>	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
324	>	#define SIGSEGV_SKIP_INSTRUCTION                ia64_skip_instruction
325		#endif
326		#if (defined(powerpc) || defined(__powerpc__))
327		#include <sys/ucontext.h>
328		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.regs)
329		#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS->nip)
330	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned int *)(SIGSEGV_CONTEXT_REGS->gpr)
330	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned long *)(SIGSEGV_CONTEXT_REGS->gpr)
331		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
332		#endif
333	+	#if (defined(hppa) || defined(__hppa__))
334	+	#undef  SIGSEGV_FAULT_ADDRESS
335	+	#define SIGSEGV_FAULT_ADDRESS                   sip->si_ptr
336	+	#endif
337	+	#if (defined(arm) || defined(__arm__))
338	+	#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
339	+	#define SIGSEGV_CONTEXT_REGS                    (((struct ucontext *)scp)->uc_mcontext)
340	+	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS.arm_pc)
341	+	#define SIGSEGV_REGISTER_FILE                   (&SIGSEGV_CONTEXT_REGS.arm_r0)
342	+	#define SIGSEGV_SKIP_INSTRUCTION                arm_skip_instruction
343	+	#endif
344	+	#if (defined(mips) || defined(__mips__))
345	+	#include <sys/ucontext.h>
346	+	#define SIGSEGV_CONTEXT_REGS                    (((struct ucontext *)scp)->uc_mcontext)
347	+	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS.pc)
348	+	#define SIGSEGV_REGISTER_FILE                   &SIGSEGV_CONTEXT_REGS.pc, &SIGSEGV_CONTEXT_REGS.gregs[0]
349	+	#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
350	+	#endif
351		#endif
352		#endif
353
354		#if HAVE_SIGCONTEXT_SUBTERFUGE
260	–	#define SIGSEGV_FAULT_HANDLER                   sigsegv_fault_handler
355		// Linux kernels prior to 2.4 ?
356		#if defined(__linux__)
357		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
#	Line 268 | Line 362 | static void powerpc_decode_instruction(i
362		#define SIGSEGV_FAULT_HANDLER_ARGS              &scs
363		#define SIGSEGV_FAULT_ADDRESS                   scp->cr2
364		#define SIGSEGV_FAULT_INSTRUCTION               scp->eip
365	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)scp
365	>	#define SIGSEGV_REGISTER_FILE                   (SIGSEGV_REGISTER_TYPE *)scp
366		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
367		#endif
368		#if (defined(sparc) || defined(__sparc__))
#	Line 283 | Line 377 | static void powerpc_decode_instruction(i
377		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, scp
378		#define SIGSEGV_FAULT_ADDRESS                   scp->regs->dar
379		#define SIGSEGV_FAULT_INSTRUCTION               scp->regs->nip
380	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&scp->regs->nip, (unsigned int *)(scp->regs->gpr)
380	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&scp->regs->nip, (unsigned long *)(scp->regs->gpr)
381		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
382		#endif
383		#if (defined(alpha) || defined(__alpha__))
#	Line 292 | Line 386 | static void powerpc_decode_instruction(i
386		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
387		#define SIGSEGV_FAULT_ADDRESS                   get_fault_address(scp)
388		#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_pc
389	<
390	<	// From Boehm's GC 6.0alpha8
391	<	static sigsegv_address_t get_fault_address(struct sigcontext *scp)
392	<	{
393	<	unsigned int instruction = *((unsigned int *)(scp->sc_pc));
394	<	unsigned long fault_address = scp->sc_regs[(instruction >> 16) & 0x1f];
395	<	fault_address += (signed long)(signed short)(instruction & 0xffff);
396	<	return (sigsegv_address_t)fault_address;
397	<	}
389	>	#endif
390	>	#if (defined(arm) || defined(__arm__))
391	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int r1, int r2, int r3, struct sigcontext sc
392	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp
393	>	#define SIGSEGV_FAULT_HANDLER_ARGS              &sc
394	>	#define SIGSEGV_FAULT_ADDRESS                   scp->fault_address
395	>	#define SIGSEGV_FAULT_INSTRUCTION               scp->arm_pc
396	>	#define SIGSEGV_REGISTER_FILE                   &scp->arm_r0
397	>	#define SIGSEGV_SKIP_INSTRUCTION                arm_skip_instruction
398		#endif
399		#endif
400
401		// Irix 5 or 6 on MIPS
402	<	#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(__SYSTYPE_SVR4))
402	>	#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(_SYSTYPE_SVR4))
403		#include <ucontext.h>
404		#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
405		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
406	<	#define SIGSEGV_FAULT_ADDRESS                   scp->sc_badvaddr
406	>	#define SIGSEGV_FAULT_ADDRESS                   (unsigned long)scp->sc_badvaddr
407	>	#define SIGSEGV_FAULT_INSTRUCTION               (unsigned long)scp->sc_pc
408		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
409		#endif
410
#	Line 338 | Line 433 | static sigsegv_address_t get_fault_addre
433		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
434		#endif
435
436	<	// NetBSD or FreeBSD
437	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
436	>	// NetBSD
437	>	#if defined(__NetBSD__)
438		#if (defined(m68k) || defined(__m68k__))
439		#include <m68k/frame.h>
440		#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
#	Line 367 | Line 462 | static sigsegv_address_t get_fault_addre
462		}
463		return (sigsegv_address_t)fault_addr;
464		}
465	<	#else
466	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, void *scp, char *addr
465	>	#endif
466	>	#if (defined(alpha) || defined(__alpha__))
467	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
468	>	#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
469	>	#define SIGSEGV_FAULT_ADDRESS                   get_fault_address(scp)
470	>	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
471	>	#endif
472	>	#if (defined(i386) || defined(__i386__))
473	>	#error "FIXME: need to decode instruction and compute EA"
474	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
475	>	#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
476	>	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
477	>	#endif
478	>	#endif
479	>	#if defined(__FreeBSD__)
480	>	#if (defined(i386) || defined(__i386__))
481	>	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
482	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp, char *addr
483		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp, addr
484		#define SIGSEGV_FAULT_ADDRESS                   addr
485	<	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
485	>	#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_eip
486	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&scp->sc_edi)
487	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
488	>	#endif
489	>	#if (defined(alpha) || defined(__alpha__))
490	>	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
491	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, char *addr, struct sigcontext *scp
492	>	#define SIGSEGV_FAULT_HANDLER_ARGS              sig, addr, scp
493	>	#define SIGSEGV_FAULT_ADDRESS                   addr
494	>	#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_pc
495		#endif
496		#endif
497
498	+	// Extract fault address out of a sigcontext
499	+	#if (defined(alpha) || defined(__alpha__))
500	+	// From Boehm's GC 6.0alpha8
501	+	static sigsegv_address_t get_fault_address(struct sigcontext *scp)
502	+	{
503	+	unsigned int instruction = *((unsigned int *)(scp->sc_pc));
504	+	unsigned long fault_address = scp->sc_regs[(instruction >> 16) & 0x1f];
505	+	fault_address += (signed long)(signed short)(instruction & 0xffff);
506	+	return (sigsegv_address_t)fault_address;
507	+	}
508	+	#endif
509	+
510	+
511		// MacOS X, not sure which version this works in. Under 10.1
512		// vm_protect does not appear to work from a signal handler. Under
513		// 10.2 signal handlers get siginfo type arguments but the si_addr
#	Line 408 | Line 541 | static sigsegv_address_t get_fault_addre
541		#endif
542		#endif
543
544	+	#if HAVE_WIN32_EXCEPTIONS
545	+	#define WIN32_LEAN_AND_MEAN /* avoid including junk */
546	+	#include <windows.h>
547	+	#include <winerror.h>
548	+
549	+	#if defined(_M_IX86)
550	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
551	+	#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
552	+	#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
553	+	#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
554	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Eip
555	+	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Edi)
556	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
557	+	#endif
558	+	#if defined(_M_X64)
559	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST   EXCEPTION_POINTERS *ExceptionInfo
560	+	#define SIGSEGV_FAULT_HANDLER_ARGS              ExceptionInfo
561	+	#define SIGSEGV_FAULT_ADDRESS                   ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
562	+	#define SIGSEGV_CONTEXT_REGS                    ExceptionInfo->ContextRecord
563	+	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS->Rip
564	+	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIGSEGV_CONTEXT_REGS->Rax)
565	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
566	+	#endif
567	+	#endif
568	+
569		#if HAVE_MACH_EXCEPTIONS
570
571		// This can easily be extended to other Mach systems, but really who
#	Line 468 | Line 626 | if (ret != KERN_SUCCESS) { \
626		exit (1); \
627		}
628
629	<	#define SIGSEGV_FAULT_ADDRESS                   code[1]
630	<	#define SIGSEGV_FAULT_INSTRUCTION               get_fault_instruction(thread, state)
631	<	#define SIGSEGV_FAULT_HANDLER                   (code[0] == KERN_PROTECTION_FAILURE) && sigsegv_fault_handler
632	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code, ppc_thread_state_t *state
633	<	#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code, &state
629	>	#ifdef __ppc__
630	>	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE
631	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
632	>	#endif
633	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state_t
634	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE
635	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE_COUNT
636	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
637	>	#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state_t
638	>	#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE
639	>	#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE_COUNT
640	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
641		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
642	<	#define SIGSEGV_REGISTER_FILE                   &state->srr0, &state->r0
643	<
644	<	// Given a suspended thread, stuff the current instruction and
645	<	// registers into state.
646	<	//
647	<	// It would have been nice to have this be ppc/x86 independant which
648	<	// could have been done easily with a thread_state_t instead of
649	<	// ppc_thread_state_t, but because of the way this is called it is
650	<	// easier to do it this way.
651	<	#if (defined(ppc) || defined(__ppc__))
652	<	static inline sigsegv_address_t get_fault_instruction(mach_port_t thread, ppc_thread_state_t *state)
653	<	{
654	<	kern_return_t krc;
655	<	mach_msg_type_number_t count;
656	<
657	<	count = MACHINE_THREAD_STATE_COUNT;
658	<	krc = thread_get_state(thread, MACHINE_THREAD_STATE, (thread_state_t)state, &count);
659	<	MACH_CHECK_ERROR (thread_get_state, krc);
642	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
643	>	#endif
644	>	#ifdef __ppc64__
645	>	#if __DARWIN_UNIX03 && defined _STRUCT_PPC_THREAD_STATE64
646	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
647	>	#endif
648	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    ppc_exception_state64_t
649	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  PPC_EXCEPTION_STATE64
650	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   PPC_EXCEPTION_STATE64_COUNT
651	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(dar)
652	>	#define SIGSEGV_THREAD_STATE_TYPE               ppc_thread_state64_t
653	>	#define SIGSEGV_THREAD_STATE_FLAVOR             PPC_THREAD_STATE64
654	>	#define SIGSEGV_THREAD_STATE_COUNT              PPC_THREAD_STATE64_COUNT
655	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(srr0)
656	>	#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
657	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(srr0), (unsigned long *)&SIP->thr_state.MACH_FIELD_NAME(r0)
658	>	#endif
659	>	#ifdef __i386__
660	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE32
661	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
662	>	#endif
663	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    i386_exception_state_t
664	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  i386_EXCEPTION_STATE
665	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   i386_EXCEPTION_STATE_COUNT
666	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
667	>	#define SIGSEGV_THREAD_STATE_TYPE               i386_thread_state_t
668	>	#define SIGSEGV_THREAD_STATE_FLAVOR             i386_THREAD_STATE
669	>	#define SIGSEGV_THREAD_STATE_COUNT              i386_THREAD_STATE_COUNT
670	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(eip)
671	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
672	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(eax)) /* EAX is the first GPR we consider */
673	>	#endif
674	>	#ifdef __x86_64__
675	>	#if __DARWIN_UNIX03 && defined _STRUCT_X86_THREAD_STATE64
676	>	#define MACH_FIELD_NAME(X)                              __CONCAT(__,X)
677	>	#endif
678	>	#define SIGSEGV_EXCEPTION_STATE_TYPE    x86_exception_state64_t
679	>	#define SIGSEGV_EXCEPTION_STATE_FLAVOR  x86_EXCEPTION_STATE64
680	>	#define SIGSEGV_EXCEPTION_STATE_COUNT   x86_EXCEPTION_STATE64_COUNT
681	>	#define SIGSEGV_FAULT_ADDRESS                   SIP->exc_state.MACH_FIELD_NAME(faultvaddr)
682	>	#define SIGSEGV_THREAD_STATE_TYPE               x86_thread_state64_t
683	>	#define SIGSEGV_THREAD_STATE_FLAVOR             x86_THREAD_STATE64
684	>	#define SIGSEGV_THREAD_STATE_COUNT              x86_THREAD_STATE64_COUNT
685	>	#define SIGSEGV_FAULT_INSTRUCTION               SIP->thr_state.MACH_FIELD_NAME(rip)
686	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
687	>	#define SIGSEGV_REGISTER_FILE                   ((SIGSEGV_REGISTER_TYPE *)&SIP->thr_state.MACH_FIELD_NAME(rax)) /* RAX is the first GPR we consider */
688	>	#endif
689	>	#define SIGSEGV_FAULT_ADDRESS_FAST              code[1]
690	>	#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_INVALID_ADDRESS
691	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code
692	>	#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code
693
694	<	return (sigsegv_address_t)state->srr0;
695	<	}
694	>	#ifndef MACH_FIELD_NAME
695	>	#define MACH_FIELD_NAME(X) X
696		#endif
697
698		// Since there can only be one exception thread running at any time
#	Line 548 | Line 746 | handleExceptions(void *priv)
746		*  Instruction skipping
747		*/
748
749	+	#ifndef SIGSEGV_REGISTER_TYPE
750	+	#define SIGSEGV_REGISTER_TYPE sigsegv_uintptr_t
751	+	#endif
752	+
753		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
754		// Decode and skip X86 instruction
755	<	#if (defined(i386) || defined(__i386__))
755	>	#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64))
756		#if defined(__linux__)
757		enum {
758	+	#if (defined(i386) || defined(__i386__))
759		X86_REG_EIP = 14,
760		X86_REG_EAX = 11,
761		X86_REG_ECX = 10,
#	Line 562 | Line 765 | enum {
765		X86_REG_EBP = 6,
766		X86_REG_ESI = 5,
767		X86_REG_EDI = 4
768	+	#endif
769	+	#if defined(__x86_64__)
770	+	X86_REG_R8  = 0,
771	+	X86_REG_R9  = 1,
772	+	X86_REG_R10 = 2,
773	+	X86_REG_R11 = 3,
774	+	X86_REG_R12 = 4,
775	+	X86_REG_R13 = 5,
776	+	X86_REG_R14 = 6,
777	+	X86_REG_R15 = 7,
778	+	X86_REG_EDI = 8,
779	+	X86_REG_ESI = 9,
780	+	X86_REG_EBP = 10,
781	+	X86_REG_EBX = 11,
782	+	X86_REG_EDX = 12,
783	+	X86_REG_EAX = 13,
784	+	X86_REG_ECX = 14,
785	+	X86_REG_ESP = 15,
786	+	X86_REG_EIP = 16
787	+	#endif
788		};
789		#endif
790	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
790	>	#if defined(__NetBSD__)
791		enum {
792	+	#if (defined(i386) || defined(__i386__))
793	+	X86_REG_EIP = _REG_EIP,
794	+	X86_REG_EAX = _REG_EAX,
795	+	X86_REG_ECX = _REG_ECX,
796	+	X86_REG_EDX = _REG_EDX,
797	+	X86_REG_EBX = _REG_EBX,
798	+	X86_REG_ESP = _REG_ESP,
799	+	X86_REG_EBP = _REG_EBP,
800	+	X86_REG_ESI = _REG_ESI,
801	+	X86_REG_EDI = _REG_EDI
802	+	#endif
803	+	};
804	+	#endif
805	+	#if defined(__FreeBSD__)
806	+	enum {
807	+	#if (defined(i386) || defined(__i386__))
808		X86_REG_EIP = 10,
809		X86_REG_EAX = 7,
810		X86_REG_ECX = 6,
#	Line 575 | Line 814 | enum {
814		X86_REG_EBP = 2,
815		X86_REG_ESI = 1,
816		X86_REG_EDI = 0
817	+	#endif
818	+	};
819	+	#endif
820	+	#if defined(__OpenBSD__)
821	+	enum {
822	+	#if defined(__i386__)
823	+	// EDI is the first register we consider
824	+	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
825	+	#define DREG(REG) ((OREG(REG) - OREG(edi)) / 4)
826	+	X86_REG_EIP = DREG(eip), // 7
827	+	X86_REG_EAX = DREG(eax), // 6
828	+	X86_REG_ECX = DREG(ecx), // 5
829	+	X86_REG_EDX = DREG(edx), // 4
830	+	X86_REG_EBX = DREG(ebx), // 3
831	+	X86_REG_ESP = DREG(esp), // 10
832	+	X86_REG_EBP = DREG(ebp), // 2
833	+	X86_REG_ESI = DREG(esi), // 1
834	+	X86_REG_EDI = DREG(edi)  // 0
835	+	#undef DREG
836	+	#undef OREG
837	+	#endif
838	+	};
839	+	#endif
840	+	#if defined(__sun__)
841	+	// Same as for Linux, need to check for x86-64
842	+	enum {
843	+	#if defined(__i386__)
844	+	X86_REG_EIP = EIP,
845	+	X86_REG_EAX = EAX,
846	+	X86_REG_ECX = ECX,
847	+	X86_REG_EDX = EDX,
848	+	X86_REG_EBX = EBX,
849	+	X86_REG_ESP = ESP,
850	+	X86_REG_EBP = EBP,
851	+	X86_REG_ESI = ESI,
852	+	X86_REG_EDI = EDI
853	+	#endif
854	+	};
855	+	#endif
856	+	#if defined(__APPLE__) && defined(__MACH__)
857	+	enum {
858	+	#if (defined(i386) || defined(__i386__))
859	+	#ifdef i386_SAVED_STATE
860	+	// same as FreeBSD (in Open Darwin 8.0.1)
861	+	X86_REG_EIP = 10,
862	+	X86_REG_EAX = 7,
863	+	X86_REG_ECX = 6,
864	+	X86_REG_EDX = 5,
865	+	X86_REG_EBX = 4,
866	+	X86_REG_ESP = 13,
867	+	X86_REG_EBP = 2,
868	+	X86_REG_ESI = 1,
869	+	X86_REG_EDI = 0
870	+	#else
871	+	// new layout (MacOS X 10.4.4 for x86)
872	+	X86_REG_EIP = 10,
873	+	X86_REG_EAX = 0,
874	+	X86_REG_ECX = 2,
875	+	X86_REG_EDX = 3,
876	+	X86_REG_EBX = 1,
877	+	X86_REG_ESP = 7,
878	+	X86_REG_EBP = 6,
879	+	X86_REG_ESI = 5,
880	+	X86_REG_EDI = 4
881	+	#endif
882	+	#endif
883	+	#if defined(__x86_64__)
884	+	X86_REG_R8  = 8,
885	+	X86_REG_R9  = 9,
886	+	X86_REG_R10 = 10,
887	+	X86_REG_R11 = 11,
888	+	X86_REG_R12 = 12,
889	+	X86_REG_R13 = 13,
890	+	X86_REG_R14 = 14,
891	+	X86_REG_R15 = 15,
892	+	X86_REG_EDI = 4,
893	+	X86_REG_ESI = 5,
894	+	X86_REG_EBP = 6,
895	+	X86_REG_EBX = 1,
896	+	X86_REG_EDX = 3,
897	+	X86_REG_EAX = 0,
898	+	X86_REG_ECX = 2,
899	+	X86_REG_ESP = 7,
900	+	X86_REG_EIP = 16
901	+	#endif
902	+	};
903	+	#endif
904	+	#if defined(_WIN32)
905	+	enum {
906	+	#if defined(_M_IX86)
907	+	X86_REG_EIP = 7,
908	+	X86_REG_EAX = 5,
909	+	X86_REG_ECX = 4,
910	+	X86_REG_EDX = 3,
911	+	X86_REG_EBX = 2,
912	+	X86_REG_ESP = 10,
913	+	X86_REG_EBP = 6,
914	+	X86_REG_ESI = 1,
915	+	X86_REG_EDI = 0
916	+	#endif
917	+	#if defined(_M_X64)
918	+	X86_REG_EAX = 0,
919	+	X86_REG_ECX = 1,
920	+	X86_REG_EDX = 2,
921	+	X86_REG_EBX = 3,
922	+	X86_REG_ESP = 4,
923	+	X86_REG_EBP = 5,
924	+	X86_REG_ESI = 6,
925	+	X86_REG_EDI = 7,
926	+	X86_REG_R8  = 8,
927	+	X86_REG_R9  = 9,
928	+	X86_REG_R10 = 10,
929	+	X86_REG_R11 = 11,
930	+	X86_REG_R12 = 12,
931	+	X86_REG_R13 = 13,
932	+	X86_REG_R14 = 14,
933	+	X86_REG_R15 = 15,
934	+	X86_REG_EIP = 16
935	+	#endif
936		};
937		#endif
938		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 611 | Line 969 | static inline int ix86_step_over_modrm(u
969		return offset;
970		}
971
972	<	static bool ix86_skip_instruction(unsigned int * regs)
972	>	static bool ix86_skip_instruction(SIGSEGV_REGISTER_TYPE * regs)
973		{
974		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
975
976		if (eip == 0)
977		return false;
978	+	#ifdef _WIN32
979	+	if (IsBadCodePtr((FARPROC)eip))
980	+	return false;
981	+	#endif
982
983	+	enum instruction_type_t {
984	+	i_MOV,
985	+	i_ADD
986	+	};
987	+
988		transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
989		transfer_size_t transfer_size = SIZE_LONG;
990	+	instruction_type_t instruction_type = i_MOV;
991
992		int reg = -1;
993		int len = 0;
994	<
994	>
995	>	#if DEBUG
996	>	printf("IP: %p [%02x %02x %02x %02x...]\n",
997	>	eip, eip[0], eip[1], eip[2], eip[3]);
998	>	#endif
999	>
1000		// Operand size prefix
1001		if (*eip == 0x66) {
1002		eip++;
#	Line 631 | Line 1004 | static bool ix86_skip_instruction(unsign
1004		transfer_size = SIZE_WORD;
1005		}
1006
1007	+	// REX prefix
1008	+	#if defined(__x86_64__) || defined(_M_X64)
1009	+	struct rex_t {
1010	+	unsigned char W;
1011	+	unsigned char R;
1012	+	unsigned char X;
1013	+	unsigned char B;
1014	+	};
1015	+	rex_t rex = { 0, 0, 0, 0 };
1016	+	bool has_rex = false;
1017	+	if ((*eip & 0xf0) == 0x40) {
1018	+	has_rex = true;
1019	+	const unsigned char b = *eip;
1020	+	rex.W = b & (1 << 3);
1021	+	rex.R = b & (1 << 2);
1022	+	rex.X = b & (1 << 1);
1023	+	rex.B = b & (1 << 0);
1024	+	#if DEBUG
1025	+	printf("REX: %c,%c,%c,%c\n",
1026	+	rex.W ? 'W' : '_',
1027	+	rex.R ? 'R' : '_',
1028	+	rex.X ? 'X' : '_',
1029	+	rex.B ? 'B' : '_');
1030	+	#endif
1031	+	eip++;
1032	+	len++;
1033	+	if (rex.W)
1034	+	transfer_size = SIZE_QUAD;
1035	+	}
1036	+	#else
1037	+	const bool has_rex = false;
1038	+	#endif
1039	+
1040		// Decode instruction
1041	+	int op_len = 1;
1042	+	int target_size = SIZE_UNKNOWN;
1043		switch (eip[0]) {
1044		case 0x0f:
1045	+	target_size = transfer_size;
1046		switch (eip[1]) {
1047	+	case 0xbe: // MOVSX r32, r/m8
1048		case 0xb6: // MOVZX r32, r/m8
1049	+	transfer_size = SIZE_BYTE;
1050	+	goto do_mov_extend;
1051	+	case 0xbf: // MOVSX r32, r/m16
1052		case 0xb7: // MOVZX r32, r/m16
1053	<	switch (eip[2] & 0xc0) {
1054	<	case 0x80:
1055	<	reg = (eip[2] >> 3) & 7;
1056	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
1057	<	break;
645	<	case 0x40:
646	<	reg = (eip[2] >> 3) & 7;
647	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
648	<	break;
649	<	case 0x00:
650	<	reg = (eip[2] >> 3) & 7;
651	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
652	<	break;
1053	>	transfer_size = SIZE_WORD;
1054	>	goto do_mov_extend;
1055	>	do_mov_extend:
1056	>	op_len = 2;
1057	>	goto do_transfer_load;
1058		}
654	–	len += 3 + ix86_step_over_modrm(eip + 2);
1059		break;
1060	<	}
1061	<	break;
1060	>	#if defined(__x86_64__) || defined(_M_X64)
1061	>	case 0x63: // MOVSXD r64, r/m32
1062	>	if (has_rex && rex.W) {
1063	>	transfer_size = SIZE_LONG;
1064	>	target_size = SIZE_QUAD;
1065	>	}
1066	>	else if (transfer_size != SIZE_WORD) {
1067	>	transfer_size = SIZE_LONG;
1068	>	target_size = SIZE_QUAD;
1069	>	}
1070	>	goto do_transfer_load;
1071	>	#endif
1072	>	case 0x02: // ADD r8, r/m8
1073	>	transfer_size = SIZE_BYTE;
1074	>	case 0x03: // ADD r32, r/m32
1075	>	instruction_type = i_ADD;
1076	>	goto do_transfer_load;
1077		case 0x8a: // MOV r8, r/m8
1078		transfer_size = SIZE_BYTE;
1079		case 0x8b: // MOV r32, r/m32 (or 16-bit operation)
1080	<	switch (eip[1] & 0xc0) {
1080	>	do_transfer_load:
1081	>	switch (eip[op_len] & 0xc0) {
1082		case 0x80:
1083	<	reg = (eip[1] >> 3) & 7;
1083	>	reg = (eip[op_len] >> 3) & 7;
1084		transfer_type = SIGSEGV_TRANSFER_LOAD;
1085		break;
1086		case 0x40:
1087	<	reg = (eip[1] >> 3) & 7;
1087	>	reg = (eip[op_len] >> 3) & 7;
1088		transfer_type = SIGSEGV_TRANSFER_LOAD;
1089		break;
1090		case 0x00:
1091	<	reg = (eip[1] >> 3) & 7;
1091	>	reg = (eip[op_len] >> 3) & 7;
1092		transfer_type = SIGSEGV_TRANSFER_LOAD;
1093		break;
1094		}
1095	<	len += 2 + ix86_step_over_modrm(eip + 1);
1095	>	len += 1 + op_len + ix86_step_over_modrm(eip + op_len);
1096		break;
1097	+	case 0x00: // ADD r/m8, r8
1098	+	transfer_size = SIZE_BYTE;
1099	+	case 0x01: // ADD r/m32, r32
1100	+	instruction_type = i_ADD;
1101	+	goto do_transfer_store;
1102		case 0x88: // MOV r/m8, r8
1103		transfer_size = SIZE_BYTE;
1104		case 0x89: // MOV r/m32, r32 (or 16-bit operation)
1105	<	switch (eip[1] & 0xc0) {
1105	>	do_transfer_store:
1106	>	switch (eip[op_len] & 0xc0) {
1107		case 0x80:
1108	<	reg = (eip[1] >> 3) & 7;
1108	>	reg = (eip[op_len] >> 3) & 7;
1109		transfer_type = SIGSEGV_TRANSFER_STORE;
1110		break;
1111		case 0x40:
1112	<	reg = (eip[1] >> 3) & 7;
1112	>	reg = (eip[op_len] >> 3) & 7;
1113		transfer_type = SIGSEGV_TRANSFER_STORE;
1114		break;
1115		case 0x00:
1116	<	reg = (eip[1] >> 3) & 7;
1116	>	reg = (eip[op_len] >> 3) & 7;
1117		transfer_type = SIGSEGV_TRANSFER_STORE;
1118		break;
1119		}
1120	<	len += 2 + ix86_step_over_modrm(eip + 1);
1120	>	len += 1 + op_len + ix86_step_over_modrm(eip + op_len);
1121		break;
1122		}
1123	+	if (target_size == SIZE_UNKNOWN)
1124	+	target_size = transfer_size;
1125
1126		if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1127		// Unknown machine code, let it crash. Then patch the decoder
1128		return false;
1129		}
1130
1131	<	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
1132	<	static const int x86_reg_map[8] = {
1131	>	#if defined(__x86_64__) || defined(_M_X64)
1132	>	if (rex.R)
1133	>	reg += 8;
1134	>	#endif
1135	>
1136	>	if (instruction_type == i_MOV && transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
1137	>	static const int x86_reg_map[] = {
1138		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
1139	<	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI
1139	>	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
1140	>	#if defined(__x86_64__) || defined(_M_X64)
1141	>	X86_REG_R8,  X86_REG_R9,  X86_REG_R10, X86_REG_R11,
1142	>	X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
1143	>	#endif
1144		};
1145
1146	<	if (reg < 0 || reg >= 8)
1146	>	if (reg < 0 || reg >= (sizeof(x86_reg_map)/sizeof(x86_reg_map[0]) - 1))
1147		return false;
1148
1149	+	// Set 0 to the relevant register part
1150	+	// NOTE: this is only valid for MOV alike instructions
1151		int rloc = x86_reg_map[reg];
1152	<	switch (transfer_size) {
1152	>	switch (target_size) {
1153		case SIZE_BYTE:
1154	<	regs[rloc] = (regs[rloc] & ~0xff);
1154	>	if (has_rex || reg < 4)
1155	>	regs[rloc] = (regs[rloc] & ~0x00ffL);
1156	>	else {
1157	>	rloc = x86_reg_map[reg - 4];
1158	>	regs[rloc] = (regs[rloc] & ~0xff00L);
1159	>	}
1160		break;
1161		case SIZE_WORD:
1162	<	regs[rloc] = (regs[rloc] & ~0xffff);
1162	>	regs[rloc] = (regs[rloc] & ~0xffffL);
1163		break;
1164		case SIZE_LONG:
1165	+	case SIZE_QUAD: // zero-extension
1166		regs[rloc] = 0;
1167		break;
1168		}
1169		}
1170
1171		#if DEBUG
1172	<	printf("%08x: %s %s access", regs[X86_REG_EIP],
1173	<	transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : "long",
1172	>	printf("%p: %s %s access", (void *)regs[X86_REG_EIP],
1173	>	transfer_size == SIZE_BYTE ? "byte" :
1174	>	transfer_size == SIZE_WORD ? "word" :
1175	>	transfer_size == SIZE_LONG ? "long" :
1176	>	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1177		transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1178
1179		if (reg != -1) {
1180	<	static const char * x86_reg_str_map[8] = {
1181	<	"eax", "ecx", "edx", "ebx",
1182	<	"esp", "ebp", "esi", "edi"
1180	>	static const char * x86_byte_reg_str_map[] = {
1181	>	"al",   "cl",   "dl",   "bl",
1182	>	"spl",  "bpl",  "sil",  "dil",
1183	>	"r8b",  "r9b",  "r10b", "r11b",
1184	>	"r12b", "r13b", "r14b", "r15b",
1185	>	"ah",   "ch",   "dh",   "bh",
1186		};
1187	<	printf(" %s register %%%s", transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from", x86_reg_str_map[reg]);
1187	>	static const char * x86_word_reg_str_map[] = {
1188	>	"ax",   "cx",   "dx",   "bx",
1189	>	"sp",   "bp",   "si",   "di",
1190	>	"r8w",  "r9w",  "r10w", "r11w",
1191	>	"r12w", "r13w", "r14w", "r15w",
1192	>	};
1193	>	static const char *x86_long_reg_str_map[] = {
1194	>	"eax",  "ecx",  "edx",  "ebx",
1195	>	"esp",  "ebp",  "esi",  "edi",
1196	>	"r8d",  "r9d",  "r10d", "r11d",
1197	>	"r12d", "r13d", "r14d", "r15d",
1198	>	};
1199	>	static const char *x86_quad_reg_str_map[] = {
1200	>	"rax", "rcx", "rdx", "rbx",
1201	>	"rsp", "rbp", "rsi", "rdi",
1202	>	"r8",  "r9",  "r10", "r11",
1203	>	"r12", "r13", "r14", "r15",
1204	>	};
1205	>	const char * reg_str = NULL;
1206	>	switch (target_size) {
1207	>	case SIZE_BYTE:
1208	>	reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
1209	>	break;
1210	>	case SIZE_WORD: reg_str = x86_word_reg_str_map[reg]; break;
1211	>	case SIZE_LONG: reg_str = x86_long_reg_str_map[reg]; break;
1212	>	case SIZE_QUAD: reg_str = x86_quad_reg_str_map[reg]; break;
1213	>	}
1214	>	if (reg_str)
1215	>	printf(" %s register %%%s",
1216	>	transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from",
1217	>	reg_str);
1218		}
1219		printf(", %d bytes instruction\n", len);
1220		#endif
#	Line 743 | Line 1224 | static bool ix86_skip_instruction(unsign
1224		}
1225		#endif
1226
1227	+	// Decode and skip IA-64 instruction
1228	+	#if defined(__ia64__)
1229	+	typedef uint64_t ia64_bundle_t[2];
1230	+	#if defined(__linux__)
1231	+	// We can directly patch the slot number
1232	+	#define IA64_CAN_PATCH_IP_SLOT  1
1233	+	// Helper macros to access the machine context
1234	+	#define IA64_CONTEXT_TYPE               struct sigcontext *
1235	+	#define IA64_CONTEXT                    scp
1236	+	#define IA64_GET_IP()                   (IA64_CONTEXT->sc_ip)
1237	+	#define IA64_SET_IP(V)                  (IA64_CONTEXT->sc_ip = (V))
1238	+	#define IA64_GET_PR(P)                  ((IA64_CONTEXT->sc_pr >> (P)) & 1)
1239	+	#define IA64_GET_NAT(I)                 ((IA64_CONTEXT->sc_nat >> (I)) & 1)
1240	+	#define IA64_GET_GR(R)                  (IA64_CONTEXT->sc_gr[(R)])
1241	+	#define _IA64_SET_GR(R,V)               (IA64_CONTEXT->sc_gr[(R)] = (V))
1242	+	#define _IA64_SET_NAT(I,V)              (IA64_CONTEXT->sc_nat = (IA64_CONTEXT->sc_nat & ~(1ull << (I))) | (((uint64_t)!!(V)) << (I)))
1243	+	#define IA64_SET_GR(R,V,N)              (_IA64_SET_GR(R,V), _IA64_SET_NAT(R,N))
1244	+
1245	+	// Load bundle (in little-endian)
1246	+	static inline void ia64_load_bundle(ia64_bundle_t bundle, uint64_t raw_ip)
1247	+	{
1248	+	uint64_t *ip = (uint64_t *)(raw_ip & ~3ull);
1249	+	bundle[0] = ip[0];
1250	+	bundle[1] = ip[1];
1251	+	}
1252	+	#endif
1253	+
1254	+	// Instruction operations
1255	+	enum {
1256	+	IA64_INST_UNKNOWN = 0,
1257	+	IA64_INST_LD1,                          // ld1 op0=[op1]
1258	+	IA64_INST_LD1_UPDATE,           // ld1 op0=[op1],op2
1259	+	IA64_INST_LD2,                          // ld2 op0=[op1]
1260	+	IA64_INST_LD2_UPDATE,           // ld2 op0=[op1],op2
1261	+	IA64_INST_LD4,                          // ld4 op0=[op1]
1262	+	IA64_INST_LD4_UPDATE,           // ld4 op0=[op1],op2
1263	+	IA64_INST_LD8,                          // ld8 op0=[op1]
1264	+	IA64_INST_LD8_UPDATE,           // ld8 op0=[op1],op2
1265	+	IA64_INST_ST1,                          // st1 [op0]=op1
1266	+	IA64_INST_ST1_UPDATE,           // st1 [op0]=op1,op2
1267	+	IA64_INST_ST2,                          // st2 [op0]=op1
1268	+	IA64_INST_ST2_UPDATE,           // st2 [op0]=op1,op2
1269	+	IA64_INST_ST4,                          // st4 [op0]=op1
1270	+	IA64_INST_ST4_UPDATE,           // st4 [op0]=op1,op2
1271	+	IA64_INST_ST8,                          // st8 [op0]=op1
1272	+	IA64_INST_ST8_UPDATE,           // st8 [op0]=op1,op2
1273	+	IA64_INST_ADD,                          // add op0=op1,op2,op3
1274	+	IA64_INST_SUB,                          // sub op0=op1,op2,op3
1275	+	IA64_INST_SHLADD,                       // shladd op0=op1,op3,op2
1276	+	IA64_INST_AND,                          // and op0=op1,op2
1277	+	IA64_INST_ANDCM,                        // andcm op0=op1,op2
1278	+	IA64_INST_OR,                           // or op0=op1,op2
1279	+	IA64_INST_XOR,                          // xor op0=op1,op2
1280	+	IA64_INST_SXT1,                         // sxt1 op0=op1
1281	+	IA64_INST_SXT2,                         // sxt2 op0=op1
1282	+	IA64_INST_SXT4,                         // sxt4 op0=op1
1283	+	IA64_INST_ZXT1,                         // zxt1 op0=op1
1284	+	IA64_INST_ZXT2,                         // zxt2 op0=op1
1285	+	IA64_INST_ZXT4,                         // zxt4 op0=op1
1286	+	IA64_INST_NOP                           // nop op0
1287	+	};
1288	+
1289	+	const int IA64_N_OPERANDS = 4;
1290	+
1291	+	// Decoded operand type
1292	+	struct ia64_operand_t {
1293	+	uint8_t commit;                         // commit result of operation to register file?
1294	+	uint8_t valid;                          // XXX: not really used, can be removed (debug)
1295	+	int8_t index;                           // index of GPR, or -1 if immediate value
1296	+	uint8_t nat;                            // NaT state before operation
1297	+	uint64_t value;                         // register contents or immediate value
1298	+	};
1299	+
1300	+	// Decoded instruction type
1301	+	struct ia64_instruction_t {
1302	+	uint8_t mnemo;                          // operation to perform
1303	+	uint8_t pred;                           // predicate register to check
1304	+	uint8_t no_memory;                      // used to emulated main fault instruction
1305	+	uint64_t inst;                          // the raw instruction bits (41-bit wide)
1306	+	ia64_operand_t operands[IA64_N_OPERANDS];
1307	+	};
1308	+
1309	+	// Get immediate sign-bit
1310	+	static inline int ia64_inst_get_sbit(uint64_t inst)
1311	+	{
1312	+	return (inst >> 36) & 1;
1313	+	}
1314	+
1315	+	// Get 8-bit immediate value (A3, A8, I27, M30)
1316	+	static inline uint64_t ia64_inst_get_imm8(uint64_t inst)
1317	+	{
1318	+	uint64_t value = (inst >> 13) & 0x7full;
1319	+	if (ia64_inst_get_sbit(inst))
1320	+	value |= ~0x7full;
1321	+	return value;
1322	+	}
1323	+
1324	+	// Get 9-bit immediate value (M3)
1325	+	static inline uint64_t ia64_inst_get_imm9b(uint64_t inst)
1326	+	{
1327	+	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 13) & 0x7f);
1328	+	if (ia64_inst_get_sbit(inst))
1329	+	value |= ~0xffull;
1330	+	return value;
1331	+	}
1332	+
1333	+	// Get 9-bit immediate value (M5)
1334	+	static inline uint64_t ia64_inst_get_imm9a(uint64_t inst)
1335	+	{
1336	+	uint64_t value = (((inst >> 27) & 1) << 7) | ((inst >> 6) & 0x7f);
1337	+	if (ia64_inst_get_sbit(inst))
1338	+	value |= ~0xffull;
1339	+	return value;
1340	+	}
1341	+
1342	+	// Get 14-bit immediate value (A4)
1343	+	static inline uint64_t ia64_inst_get_imm14(uint64_t inst)
1344	+	{
1345	+	uint64_t value = (((inst >> 27) & 0x3f) << 7) | (inst & 0x7f);
1346	+	if (ia64_inst_get_sbit(inst))
1347	+	value |= ~0x1ffull;
1348	+	return value;
1349	+	}
1350	+
1351	+	// Get 22-bit immediate value (A5)
1352	+	static inline uint64_t ia64_inst_get_imm22(uint64_t inst)
1353	+	{
1354	+	uint64_t value = ((((inst >> 22) & 0x1f) << 16) |
1355	+	(((inst >> 27) & 0x1ff) << 7) |
1356	+	(inst & 0x7f));
1357	+	if (ia64_inst_get_sbit(inst))
1358	+	value |= ~0x1fffffull;
1359	+	return value;
1360	+	}
1361	+
1362	+	// Get 21-bit immediate value (I19)
1363	+	static inline uint64_t ia64_inst_get_imm21(uint64_t inst)
1364	+	{
1365	+	return (((inst >> 36) & 1) << 20) | ((inst >> 6) & 0xfffff);
1366	+	}
1367	+
1368	+	// Get 2-bit count value (A2)
1369	+	static inline int ia64_inst_get_count2(uint64_t inst)
1370	+	{
1371	+	return (inst >> 27) & 0x3;
1372	+	}
1373	+
1374	+	// Get bundle template
1375	+	static inline unsigned int ia64_get_template(uint64_t ip)
1376	+	{
1377	+	ia64_bundle_t bundle;
1378	+	ia64_load_bundle(bundle, ip);
1379	+	return bundle[0] & 0x1f;
1380	+	}
1381	+
1382	+	// Get specified instruction in bundle
1383	+	static uint64_t ia64_get_instruction(uint64_t ip, int slot)
1384	+	{
1385	+	uint64_t inst;
1386	+	ia64_bundle_t bundle;
1387	+	ia64_load_bundle(bundle, ip);
1388	+	#if DEBUG
1389	+	printf("Bundle: %016llx%016llx\n", bundle[1], bundle[0]);
1390	+	#endif
1391	+
1392	+	switch (slot) {
1393	+	case 0:
1394	+	inst = (bundle[0] >> 5) & 0x1ffffffffffull;
1395	+	break;
1396	+	case 1:
1397	+	inst = ((bundle[1] & 0x7fffffull) << 18) | ((bundle[0] >> 46) & 0x3ffffull);
1398	+	break;
1399	+	case 2:
1400	+	inst = (bundle[1] >> 23) & 0x1ffffffffffull;
1401	+	break;
1402	+	case 3:
1403	+	fprintf(stderr, "ERROR: ia64_get_instruction(), invalid slot number %d\n", slot);
1404	+	abort();
1405	+	break;
1406	+	}
1407	+
1408	+	#if DEBUG
1409	+	printf(" Instruction %d: 0x%016llx\n", slot, inst);
1410	+	#endif
1411	+	return inst;
1412	+	}
1413	+
1414	+	// Decode group 0 instructions
1415	+	static bool ia64_decode_instruction_0(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1416	+	{
1417	+	const int r1 = (inst->inst >>  6) & 0x7f;
1418	+	const int r3 = (inst->inst >> 20) & 0x7f;
1419	+
1420	+	const int x3 = (inst->inst >> 33) & 0x07;
1421	+	const int x6 = (inst->inst >> 27) & 0x3f;
1422	+	const int x2 = (inst->inst >> 31) & 0x03;
1423	+	const int x4 = (inst->inst >> 27) & 0x0f;
1424	+
1425	+	if (x3 == 0) {
1426	+	switch (x6) {
1427	+	case 0x01:                                              // nop.i (I19)
1428	+	inst->mnemo = IA64_INST_NOP;
1429	+	inst->operands[0].valid = true;
1430	+	inst->operands[0].index = -1;
1431	+	inst->operands[0].value = ia64_inst_get_imm21(inst->inst);
1432	+	return true;
1433	+	case 0x14:                                              // sxt1 (I29)
1434	+	case 0x15:                                              // sxt2 (I29)
1435	+	case 0x16:                                              // sxt4 (I29)
1436	+	case 0x10:                                              // zxt1 (I29)
1437	+	case 0x11:                                              // zxt2 (I29)
1438	+	case 0x12:                                              // zxt4 (I29)
1439	+	switch (x6) {
1440	+	case 0x14: inst->mnemo = IA64_INST_SXT1; break;
1441	+	case 0x15: inst->mnemo = IA64_INST_SXT2; break;
1442	+	case 0x16: inst->mnemo = IA64_INST_SXT4; break;
1443	+	case 0x10: inst->mnemo = IA64_INST_ZXT1; break;
1444	+	case 0x11: inst->mnemo = IA64_INST_ZXT2; break;
1445	+	case 0x12: inst->mnemo = IA64_INST_ZXT4; break;
1446	+	default: abort();
1447	+	}
1448	+	inst->operands[0].valid = true;
1449	+	inst->operands[0].index = r1;
1450	+	inst->operands[1].valid = true;
1451	+	inst->operands[1].index = r3;
1452	+	inst->operands[1].value = IA64_GET_GR(r3);
1453	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1454	+	return true;
1455	+	}
1456	+	}
1457	+	return false;
1458	+	}
1459	+
1460	+	// Decode group 4 instructions (load/store instructions)
1461	+	static bool ia64_decode_instruction_4(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1462	+	{
1463	+	const int r1 = (inst->inst >> 6) & 0x7f;
1464	+	const int r2 = (inst->inst >> 13) & 0x7f;
1465	+	const int r3 = (inst->inst >> 20) & 0x7f;
1466	+
1467	+	const int m  = (inst->inst >> 36) & 1;
1468	+	const int x  = (inst->inst >> 27) & 1;
1469	+	const int x6 = (inst->inst >> 30) & 0x3f;
1470	+
1471	+	switch (x6) {
1472	+	case 0x00:
1473	+	case 0x01:
1474	+	case 0x02:
1475	+	case 0x03:
1476	+	if (x == 0) {
1477	+	inst->operands[0].valid = true;
1478	+	inst->operands[0].index = r1;
1479	+	inst->operands[1].valid = true;
1480	+	inst->operands[1].index = r3;
1481	+	inst->operands[1].value = IA64_GET_GR(r3);
1482	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1483	+	if (m == 0) {
1484	+	switch (x6) {
1485	+	case 0x00: inst->mnemo = IA64_INST_LD1; break;
1486	+	case 0x01: inst->mnemo = IA64_INST_LD2; break;
1487	+	case 0x02: inst->mnemo = IA64_INST_LD4; break;
1488	+	case 0x03: inst->mnemo = IA64_INST_LD8; break;
1489	+	}
1490	+	}
1491	+	else {
1492	+	inst->operands[2].valid = true;
1493	+	inst->operands[2].index = r2;
1494	+	inst->operands[2].value = IA64_GET_GR(r2);
1495	+	inst->operands[2].nat   = IA64_GET_NAT(r2);
1496	+	switch (x6) {
1497	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1498	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1499	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1500	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1501	+	}
1502	+	}
1503	+	return true;
1504	+	}
1505	+	break;
1506	+	case 0x30:
1507	+	case 0x31:
1508	+	case 0x32:
1509	+	case 0x33:
1510	+	if (m == 0 && x == 0) {
1511	+	inst->operands[0].valid = true;
1512	+	inst->operands[0].index = r3;
1513	+	inst->operands[0].value = IA64_GET_GR(r3);
1514	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1515	+	inst->operands[1].valid = true;
1516	+	inst->operands[1].index = r2;
1517	+	inst->operands[1].value = IA64_GET_GR(r2);
1518	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1519	+	switch (x6) {
1520	+	case 0x30: inst->mnemo = IA64_INST_ST1; break;
1521	+	case 0x31: inst->mnemo = IA64_INST_ST2; break;
1522	+	case 0x32: inst->mnemo = IA64_INST_ST4; break;
1523	+	case 0x33: inst->mnemo = IA64_INST_ST8; break;
1524	+	}
1525	+	return true;
1526	+	}
1527	+	break;
1528	+	}
1529	+	return false;
1530	+	}
1531	+
1532	+	// Decode group 5 instructions (load/store instructions)
1533	+	static bool ia64_decode_instruction_5(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1534	+	{
1535	+	const int r1 = (inst->inst >> 6) & 0x7f;
1536	+	const int r2 = (inst->inst >> 13) & 0x7f;
1537	+	const int r3 = (inst->inst >> 20) & 0x7f;
1538	+
1539	+	const int x6 = (inst->inst >> 30) & 0x3f;
1540	+
1541	+	switch (x6) {
1542	+	case 0x00:
1543	+	case 0x01:
1544	+	case 0x02:
1545	+	case 0x03:
1546	+	inst->operands[0].valid = true;
1547	+	inst->operands[0].index = r1;
1548	+	inst->operands[1].valid = true;
1549	+	inst->operands[1].index = r3;
1550	+	inst->operands[1].value = IA64_GET_GR(r3);
1551	+	inst->operands[1].nat   = IA64_GET_NAT(r3);
1552	+	inst->operands[2].valid = true;
1553	+	inst->operands[2].index = -1;
1554	+	inst->operands[2].value = ia64_inst_get_imm9b(inst->inst);
1555	+	inst->operands[2].nat   = 0;
1556	+	switch (x6) {
1557	+	case 0x00: inst->mnemo = IA64_INST_LD1_UPDATE; break;
1558	+	case 0x01: inst->mnemo = IA64_INST_LD2_UPDATE; break;
1559	+	case 0x02: inst->mnemo = IA64_INST_LD4_UPDATE; break;
1560	+	case 0x03: inst->mnemo = IA64_INST_LD8_UPDATE; break;
1561	+	}
1562	+	return true;
1563	+	case 0x30:
1564	+	case 0x31:
1565	+	case 0x32:
1566	+	case 0x33:
1567	+	inst->operands[0].valid = true;
1568	+	inst->operands[0].index = r3;
1569	+	inst->operands[0].value = IA64_GET_GR(r3);
1570	+	inst->operands[0].nat   = IA64_GET_NAT(r3);
1571	+	inst->operands[1].valid = true;
1572	+	inst->operands[1].index = r2;
1573	+	inst->operands[1].value = IA64_GET_GR(r2);
1574	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1575	+	inst->operands[2].valid = true;
1576	+	inst->operands[2].index = -1;
1577	+	inst->operands[2].value = ia64_inst_get_imm9a(inst->inst);
1578	+	inst->operands[2].nat   = 0;
1579	+	switch (x6) {
1580	+	case 0x30: inst->mnemo = IA64_INST_ST1_UPDATE; break;
1581	+	case 0x31: inst->mnemo = IA64_INST_ST2_UPDATE; break;
1582	+	case 0x32: inst->mnemo = IA64_INST_ST4_UPDATE; break;
1583	+	case 0x33: inst->mnemo = IA64_INST_ST8_UPDATE; break;
1584	+	}
1585	+	return true;
1586	+	}
1587	+	return false;
1588	+	}
1589	+
1590	+	// Decode group 8 instructions (ALU integer)
1591	+	static bool ia64_decode_instruction_8(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1592	+	{
1593	+	const int r1  = (inst->inst >> 6) & 0x7f;
1594	+	const int r2  = (inst->inst >> 13) & 0x7f;
1595	+	const int r3  = (inst->inst >> 20) & 0x7f;
1596	+
1597	+	const int x2a = (inst->inst >> 34) & 0x3;
1598	+	const int x2b = (inst->inst >> 27) & 0x3;
1599	+	const int x4  = (inst->inst >> 29) & 0xf;
1600	+	const int ve  = (inst->inst >> 33) & 0x1;
1601	+
1602	+	// destination register (r1) is always valid in this group
1603	+	inst->operands[0].valid = true;
1604	+	inst->operands[0].index = r1;
1605	+
1606	+	// source register (r3) is always valid in this group
1607	+	inst->operands[2].valid = true;
1608	+	inst->operands[2].index = r3;
1609	+	inst->operands[2].value = IA64_GET_GR(r3);
1610	+	inst->operands[2].nat   = IA64_GET_NAT(r3);
1611	+
1612	+	if (x2a == 0 && ve == 0) {
1613	+	inst->operands[1].valid = true;
1614	+	inst->operands[1].index = r2;
1615	+	inst->operands[1].value = IA64_GET_GR(r2);
1616	+	inst->operands[1].nat   = IA64_GET_NAT(r2);
1617	+	switch (x4) {
1618	+	case 0x0:                               // add (A1)
1619	+	inst->mnemo = IA64_INST_ADD;
1620	+	inst->operands[3].valid = true;
1621	+	inst->operands[3].index = -1;
1622	+	inst->operands[3].value = x2b == 1;
1623	+	return true;
1624	+	case 0x1:                               // add (A1)
1625	+	inst->mnemo = IA64_INST_SUB;
1626	+	inst->operands[3].valid = true;
1627	+	inst->operands[3].index = -1;
1628	+	inst->operands[3].value = x2b == 0;
1629	+	return true;
1630	+	case 0x4:                               // shladd (A2)
1631	+	inst->mnemo = IA64_INST_SHLADD;
1632	+	inst->operands[3].valid = true;
1633	+	inst->operands[3].index = -1;
1634	+	inst->operands[3].value = ia64_inst_get_count2(inst->inst);
1635	+	return true;
1636	+	case 0x9:
1637	+	if (x2b == 1) {
1638	+	inst->mnemo = IA64_INST_SUB;
1639	+	inst->operands[1].index = -1;
1640	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1641	+	inst->operands[1].nat   = 0;
1642	+	return true;
1643	+	}
1644	+	break;
1645	+	case 0xb:
1646	+	inst->operands[1].index = -1;
1647	+	inst->operands[1].value = ia64_inst_get_imm8(inst->inst);
1648	+	inst->operands[1].nat   = 0;
1649	+	// fall-through
1650	+	case 0x3:
1651	+	switch (x2b) {
1652	+	case 0: inst->mnemo = IA64_INST_AND;   break;
1653	+	case 1: inst->mnemo = IA64_INST_ANDCM; break;
1654	+	case 2: inst->mnemo = IA64_INST_OR;    break;
1655	+	case 3: inst->mnemo = IA64_INST_XOR;   break;
1656	+	}
1657	+	return true;
1658	+	}
1659	+	}
1660	+	return false;
1661	+	}
1662	+
1663	+	// Decode instruction
1664	+	static bool ia64_decode_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1665	+	{
1666	+	const int major = (inst->inst >> 37) & 0xf;
1667	+
1668	+	inst->mnemo = IA64_INST_UNKNOWN;
1669	+	inst->pred  = inst->inst & 0x3f;
1670	+	memset(&inst->operands[0], 0, sizeof(inst->operands));
1671	+
1672	+	switch (major) {
1673	+	case 0x0: return ia64_decode_instruction_0(inst, IA64_CONTEXT);
1674	+	case 0x4: return ia64_decode_instruction_4(inst, IA64_CONTEXT);
1675	+	case 0x5: return ia64_decode_instruction_5(inst, IA64_CONTEXT);
1676	+	case 0x8: return ia64_decode_instruction_8(inst, IA64_CONTEXT);
1677	+	}
1678	+	return false;
1679	+	}
1680	+
1681	+	static bool ia64_emulate_instruction(ia64_instruction_t *inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1682	+	{
1683	+	// XXX: handle Register NaT Consumption fault?
1684	+	// XXX: this simple emulator assumes instructions in a bundle
1685	+	// don't depend on effects of other instructions in the same
1686	+	// bundle. It probably would be simpler to JIT-generate code to be
1687	+	// executed natively but probably more costly (inject/extract CPU state)
1688	+	if (inst->mnemo == IA64_INST_UNKNOWN)
1689	+	return false;
1690	+	if (inst->pred && !IA64_GET_PR(inst->pred))
1691	+	return true;
1692	+
1693	+	uint8_t nat, nat2;
1694	+	uint64_t dst, dst2, src1, src2, src3;
1695	+
1696	+	switch (inst->mnemo) {
1697	+	case IA64_INST_NOP:
1698	+	break;
1699	+	case IA64_INST_ADD:
1700	+	case IA64_INST_SUB:
1701	+	case IA64_INST_SHLADD:
1702	+	src3 = inst->operands[3].value;
1703	+	// fall-through
1704	+	case IA64_INST_AND:
1705	+	case IA64_INST_ANDCM:
1706	+	case IA64_INST_OR:
1707	+	case IA64_INST_XOR:
1708	+	src1 = inst->operands[1].value;
1709	+	src2 = inst->operands[2].value;
1710	+	switch (inst->mnemo) {
1711	+	case IA64_INST_ADD:   dst = src1 + src2 + src3; break;
1712	+	case IA64_INST_SUB:   dst = src1 - src2 - src3; break;
1713	+	case IA64_INST_SHLADD: dst = (src1 << src3) + src2; break;
1714	+	case IA64_INST_AND:   dst = src1 & src2;                break;
1715	+	case IA64_INST_ANDCM: dst = src1 &~ src2;               break;
1716	+	case IA64_INST_OR:    dst = src1 | src2;                break;
1717	+	case IA64_INST_XOR:   dst = src1 ^ src2;                break;
1718	+	}
1719	+	inst->operands[0].commit = true;
1720	+	inst->operands[0].value  = dst;
1721	+	inst->operands[0].nat    = inst->operands[1].nat | inst->operands[2].nat;
1722	+	break;
1723	+	case IA64_INST_SXT1:
1724	+	case IA64_INST_SXT2:
1725	+	case IA64_INST_SXT4:
1726	+	case IA64_INST_ZXT1:
1727	+	case IA64_INST_ZXT2:
1728	+	case IA64_INST_ZXT4:
1729	+	src1 = inst->operands[1].value;
1730	+	switch (inst->mnemo) {
1731	+	case IA64_INST_SXT1: dst = (int64_t)(int8_t)src1;               break;
1732	+	case IA64_INST_SXT2: dst = (int64_t)(int16_t)src1;              break;
1733	+	case IA64_INST_SXT4: dst = (int64_t)(int32_t)src1;              break;
1734	+	case IA64_INST_ZXT1: dst = (uint8_t)src1;                               break;
1735	+	case IA64_INST_ZXT2: dst = (uint16_t)src1;                              break;
1736	+	case IA64_INST_ZXT4: dst = (uint32_t)src1;                              break;
1737	+	}
1738	+	inst->operands[0].commit = true;
1739	+	inst->operands[0].value  = dst;
1740	+	inst->operands[0].nat    = inst->operands[1].nat;
1741	+	break;
1742	+	case IA64_INST_LD1_UPDATE:
1743	+	case IA64_INST_LD2_UPDATE:
1744	+	case IA64_INST_LD4_UPDATE:
1745	+	case IA64_INST_LD8_UPDATE:
1746	+	inst->operands[1].commit = true;
1747	+	dst2 = inst->operands[1].value + inst->operands[2].value;
1748	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1749	+	// fall-through
1750	+	case IA64_INST_LD1:
1751	+	case IA64_INST_LD2:
1752	+	case IA64_INST_LD4:
1753	+	case IA64_INST_LD8:
1754	+	src1 = inst->operands[1].value;
1755	+	if (inst->no_memory)
1756	+	dst = 0;
1757	+	else {
1758	+	switch (inst->mnemo) {
1759	+	case IA64_INST_LD1: case IA64_INST_LD1_UPDATE: dst = *((uint8_t *)src1);        break;
1760	+	case IA64_INST_LD2: case IA64_INST_LD2_UPDATE: dst = *((uint16_t *)src1);       break;
1761	+	case IA64_INST_LD4: case IA64_INST_LD4_UPDATE: dst = *((uint32_t *)src1);       break;
1762	+	case IA64_INST_LD8: case IA64_INST_LD8_UPDATE: dst = *((uint64_t *)src1);       break;
1763	+	}
1764	+	}
1765	+	inst->operands[0].commit = true;
1766	+	inst->operands[0].value  = dst;
1767	+	inst->operands[0].nat    = 0;
1768	+	inst->operands[1].value  = dst2;
1769	+	inst->operands[1].nat    = nat2;
1770	+	break;
1771	+	case IA64_INST_ST1_UPDATE:
1772	+	case IA64_INST_ST2_UPDATE:
1773	+	case IA64_INST_ST4_UPDATE:
1774	+	case IA64_INST_ST8_UPDATE:
1775	+	inst->operands[0].commit = 0;
1776	+	dst2 = inst->operands[0].value + inst->operands[2].value;
1777	+	nat2 = inst->operands[2].nat ? inst->operands[2].nat : 0;
1778	+	// fall-through
1779	+	case IA64_INST_ST1:
1780	+	case IA64_INST_ST2:
1781	+	case IA64_INST_ST4:
1782	+	case IA64_INST_ST8:
1783	+	dst  = inst->operands[0].value;
1784	+	src1 = inst->operands[1].value;
1785	+	if (!inst->no_memory) {
1786	+	switch (inst->mnemo) {
1787	+	case IA64_INST_ST1: case IA64_INST_ST1_UPDATE: *((uint8_t *)dst) = src1;        break;
1788	+	case IA64_INST_ST2: case IA64_INST_ST2_UPDATE: *((uint16_t *)dst) = src1;       break;
1789	+	case IA64_INST_ST4: case IA64_INST_ST4_UPDATE: *((uint32_t *)dst) = src1;       break;
1790	+	case IA64_INST_ST8: case IA64_INST_ST8_UPDATE: *((uint64_t *)dst) = src1;       break;
1791	+	}
1792	+	}
1793	+	inst->operands[0].value  = dst2;
1794	+	inst->operands[0].nat    = nat2;
1795	+	break;
1796	+	default:
1797	+	return false;
1798	+	}
1799	+
1800	+	for (int i = 0; i < IA64_N_OPERANDS; i++) {
1801	+	ia64_operand_t const & op = inst->operands[i];
1802	+	if (!op.commit)
1803	+	continue;
1804	+	if (op.index == -1)
1805	+	return false; // XXX: internal error
1806	+	IA64_SET_GR(op.index, op.value, op.nat);
1807	+	}
1808	+	return true;
1809	+	}
1810	+
1811	+	static bool ia64_emulate_instruction(uint64_t raw_inst, IA64_CONTEXT_TYPE IA64_CONTEXT)
1812	+	{
1813	+	ia64_instruction_t inst;
1814	+	memset(&inst, 0, sizeof(inst));
1815	+	inst.inst = raw_inst;
1816	+	if (!ia64_decode_instruction(&inst, IA64_CONTEXT))
1817	+	return false;
1818	+	return ia64_emulate_instruction(&inst, IA64_CONTEXT);
1819	+	}
1820	+
1821	+	static bool ia64_skip_instruction(IA64_CONTEXT_TYPE IA64_CONTEXT)
1822	+	{
1823	+	uint64_t ip = IA64_GET_IP();
1824	+	#if DEBUG
1825	+	printf("IP: 0x%016llx\n", ip);
1826	+	#if 0
1827	+	printf(" Template 0x%02x\n", ia64_get_template(ip));
1828	+	ia64_get_instruction(ip, 0);
1829	+	ia64_get_instruction(ip, 1);
1830	+	ia64_get_instruction(ip, 2);
1831	+	#endif
1832	+	#endif
1833	+
1834	+	// Select which decode switch to use
1835	+	ia64_instruction_t inst;
1836	+	inst.inst = ia64_get_instruction(ip, ip & 3);
1837	+	if (!ia64_decode_instruction(&inst, IA64_CONTEXT)) {
1838	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not decode instruction\n");
1839	+	return false;
1840	+	}
1841	+
1842	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1843	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1844	+
1845	+	switch (inst.mnemo) {
1846	+	case IA64_INST_LD1:
1847	+	case IA64_INST_LD2:
1848	+	case IA64_INST_LD4:
1849	+	case IA64_INST_LD8:
1850	+	case IA64_INST_LD1_UPDATE:
1851	+	case IA64_INST_LD2_UPDATE:
1852	+	case IA64_INST_LD4_UPDATE:
1853	+	case IA64_INST_LD8_UPDATE:
1854	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1855	+	break;
1856	+	case IA64_INST_ST1:
1857	+	case IA64_INST_ST2:
1858	+	case IA64_INST_ST4:
1859	+	case IA64_INST_ST8:
1860	+	case IA64_INST_ST1_UPDATE:
1861	+	case IA64_INST_ST2_UPDATE:
1862	+	case IA64_INST_ST4_UPDATE:
1863	+	case IA64_INST_ST8_UPDATE:
1864	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1865	+	break;
1866	+	}
1867	+
1868	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1869	+	// Unknown machine code, let it crash. Then patch the decoder
1870	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): not a load/store instruction\n");
1871	+	return false;
1872	+	}
1873	+
1874	+	switch (inst.mnemo) {
1875	+	case IA64_INST_LD1:
1876	+	case IA64_INST_LD1_UPDATE:
1877	+	case IA64_INST_ST1:
1878	+	case IA64_INST_ST1_UPDATE:
1879	+	transfer_size = SIZE_BYTE;
1880	+	break;
1881	+	case IA64_INST_LD2:
1882	+	case IA64_INST_LD2_UPDATE:
1883	+	case IA64_INST_ST2:
1884	+	case IA64_INST_ST2_UPDATE:
1885	+	transfer_size = SIZE_WORD;
1886	+	break;
1887	+	case IA64_INST_LD4:
1888	+	case IA64_INST_LD4_UPDATE:
1889	+	case IA64_INST_ST4:
1890	+	case IA64_INST_ST4_UPDATE:
1891	+	transfer_size = SIZE_LONG;
1892	+	break;
1893	+	case IA64_INST_LD8:
1894	+	case IA64_INST_LD8_UPDATE:
1895	+	case IA64_INST_ST8:
1896	+	case IA64_INST_ST8_UPDATE:
1897	+	transfer_size = SIZE_QUAD;
1898	+	break;
1899	+	}
1900	+
1901	+	if (transfer_size == SIZE_UNKNOWN) {
1902	+	// Unknown machine code, let it crash. Then patch the decoder
1903	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): unknown transfer size\n");
1904	+	return false;
1905	+	}
1906	+
1907	+	inst.no_memory = true;
1908	+	if (!ia64_emulate_instruction(&inst, IA64_CONTEXT)) {
1909	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate fault instruction\n");
1910	+	return false;
1911	+	}
1912	+
1913	+	int slot = ip & 3;
1914	+	bool emulate_next = false;
1915	+	switch (slot) {
1916	+	case 0:
1917	+	switch (ia64_get_template(ip)) {
1918	+	case 0x2: // MI;I
1919	+	case 0x3: // MI;I;
1920	+	emulate_next = true;
1921	+	slot = 2;
1922	+	break;
1923	+	case 0xa: // M;MI
1924	+	case 0xb: // M;MI;
1925	+	emulate_next = true;
1926	+	slot = 1;
1927	+	break;
1928	+	}
1929	+	break;
1930	+	}
1931	+	if (emulate_next && !IA64_CAN_PATCH_IP_SLOT) {
1932	+	while (slot < 3) {
1933	+	if (!ia64_emulate_instruction(ia64_get_instruction(ip, slot), IA64_CONTEXT)) {
1934	+	fprintf(stderr, "ERROR: ia64_skip_instruction(): could not emulate instruction\n");
1935	+	return false;
1936	+	}
1937	+	++slot;
1938	+	}
1939	+	}
1940	+
1941	+	#if IA64_CAN_PATCH_IP_SLOT
1942	+	if ((slot = ip & 3) < 2)
1943	+	IA64_SET_IP((ip & ~3ull) + (slot + 1));
1944	+	else
1945	+	#endif
1946	+	IA64_SET_IP((ip & ~3ull) + 16);
1947	+	#if DEBUG
1948	+	printf("IP: 0x%016llx\n", IA64_GET_IP());
1949	+	#endif
1950	+	return true;
1951	+	}
1952	+	#endif
1953	+
1954		// Decode and skip PPC instruction
1955	<	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__))
1956	<	static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs)
1955	>	#if (defined(powerpc) || defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__))
1956	>	static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
1957		{
1958		instruction_t instr;
1959		powerpc_decode_instruction(&instr, *nip_p, regs);
#	Line 757 | Line 1965 | static bool powerpc_skip_instruction(uns
1965
1966		#if DEBUG
1967		printf("%08x: %s %s access", *nip_p,
1968	<	instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long",
1968	>	instr.transfer_size == SIZE_BYTE ? "byte" :
1969	>	instr.transfer_size == SIZE_WORD ? "word" :
1970	>	instr.transfer_size == SIZE_LONG ? "long" : "quad",
1971		instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1972
1973		if (instr.addr_mode == MODE_U || instr.addr_mode == MODE_UX)
#	Line 775 | Line 1985 | static bool powerpc_skip_instruction(uns
1985		return true;
1986		}
1987		#endif
1988	+
1989	+	// Decode and skip MIPS instruction
1990	+	#if (defined(mips) || defined(__mips))
1991	+	static bool mips_skip_instruction(greg_t * pc_p, greg_t * regs)
1992	+	{
1993	+	unsigned int * epc = (unsigned int *)(unsigned long)*pc_p;
1994	+
1995	+	if (epc == 0)
1996	+	return false;
1997	+
1998	+	#if DEBUG
1999	+	printf("IP: %p [%08x]\n", epc, epc[0]);
2000	+	#endif
2001	+
2002	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
2003	+	transfer_size_t transfer_size = SIZE_LONG;
2004	+	int direction = 0;
2005	+
2006	+	const unsigned int opcode = epc[0];
2007	+	switch (opcode >> 26) {
2008	+	case 32: // Load Byte
2009	+	case 36: // Load Byte Unsigned
2010	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2011	+	transfer_size = SIZE_BYTE;
2012	+	break;
2013	+	case 33: // Load Halfword
2014	+	case 37: // Load Halfword Unsigned
2015	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2016	+	transfer_size = SIZE_WORD;
2017	+	break;
2018	+	case 35: // Load Word
2019	+	case 39: // Load Word Unsigned
2020	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2021	+	transfer_size = SIZE_LONG;
2022	+	break;
2023	+	case 34: // Load Word Left
2024	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2025	+	transfer_size = SIZE_LONG;
2026	+	direction = -1;
2027	+	break;
2028	+	case 38: // Load Word Right
2029	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2030	+	transfer_size = SIZE_LONG;
2031	+	direction = 1;
2032	+	break;
2033	+	case 55: // Load Doubleword
2034	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2035	+	transfer_size = SIZE_QUAD;
2036	+	break;
2037	+	case 26: // Load Doubleword Left
2038	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2039	+	transfer_size = SIZE_QUAD;
2040	+	direction = -1;
2041	+	break;
2042	+	case 27: // Load Doubleword Right
2043	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2044	+	transfer_size = SIZE_QUAD;
2045	+	direction = 1;
2046	+	break;
2047	+	case 40: // Store Byte
2048	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2049	+	transfer_size = SIZE_BYTE;
2050	+	break;
2051	+	case 41: // Store Halfword
2052	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2053	+	transfer_size = SIZE_WORD;
2054	+	break;
2055	+	case 43: // Store Word
2056	+	case 42: // Store Word Left
2057	+	case 46: // Store Word Right
2058	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2059	+	transfer_size = SIZE_LONG;
2060	+	break;
2061	+	case 63: // Store Doubleword
2062	+	case 44: // Store Doubleword Left
2063	+	case 45: // Store Doubleword Right
2064	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2065	+	transfer_size = SIZE_QUAD;
2066	+	break;
2067	+	/* Misc instructions unlikely to be used within CPU emulators */
2068	+	case 48: // Load Linked Word
2069	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2070	+	transfer_size = SIZE_LONG;
2071	+	break;
2072	+	case 52: // Load Linked Doubleword
2073	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2074	+	transfer_size = SIZE_QUAD;
2075	+	break;
2076	+	case 56: // Store Conditional Word
2077	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2078	+	transfer_size = SIZE_LONG;
2079	+	break;
2080	+	case 60: // Store Conditional Doubleword
2081	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2082	+	transfer_size = SIZE_QUAD;
2083	+	break;
2084	+	}
2085	+
2086	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
2087	+	// Unknown machine code, let it crash. Then patch the decoder
2088	+	return false;
2089	+	}
2090	+
2091	+	// Zero target register in case of a load operation
2092	+	const int reg = (opcode >> 16) & 0x1f;
2093	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD) {
2094	+	if (direction == 0)
2095	+	regs[reg] = 0;
2096	+	else {
2097	+	// FIXME: untested code
2098	+	unsigned long ea = regs[(opcode >> 21) & 0x1f];
2099	+	ea += (signed long)(signed int)(signed short)(opcode & 0xffff);
2100	+	const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7);
2101	+	unsigned long value;
2102	+	if (direction > 0) {
2103	+	const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1);
2104	+	value = regs[reg] & rmask;
2105	+	}
2106	+	else {
2107	+	const unsigned long lmask = (1L << (offset * 8)) - 1;
2108	+	value = regs[reg] & lmask;
2109	+	}
2110	+	// restore most significant bits
2111	+	if (transfer_size == SIZE_LONG)
2112	+	value = (signed long)(signed int)value;
2113	+	regs[reg] = value;
2114	+	}
2115	+	}
2116	+
2117	+	#if DEBUG
2118	+	#if (defined(_ABIN32) || defined(_ABI64))
2119	+	static const char * mips_gpr_names[32] = {
2120	+	"zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
2121	+	"t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
2122	+	"s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
2123	+	"t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
2124	+	};
2125	+	#else
2126	+	static const char * mips_gpr_names[32] = {
2127	+	"zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
2128	+	"a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
2129	+	"s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
2130	+	"t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
2131	+	};
2132	+	#endif
2133	+	printf("%s %s register %s\n",
2134	+	transfer_size == SIZE_BYTE ? "byte" :
2135	+	transfer_size == SIZE_WORD ? "word" :
2136	+	transfer_size == SIZE_LONG ? "long" :
2137	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
2138	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
2139	+	mips_gpr_names[reg]);
2140		#endif
2141
2142	+	*pc_p += 4;
2143	+	return true;
2144	+	}
2145	+	#endif
2146	+
2147	+	// Decode and skip SPARC instruction
2148	+	#if (defined(sparc) || defined(__sparc__))
2149	+	enum {
2150	+	#if (defined(__sun__))
2151	+	SPARC_REG_G1 = REG_G1,
2152	+	SPARC_REG_O0 = REG_O0,
2153	+	SPARC_REG_PC = REG_PC,
2154	+	SPARC_REG_nPC = REG_nPC
2155	+	#endif
2156	+	};
2157	+	static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
2158	+	{
2159	+	unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
2160	+
2161	+	if (pc == 0)
2162	+	return false;
2163	+
2164	+	#if DEBUG
2165	+	printf("IP: %p [%08x]\n", pc, pc[0]);
2166	+	#endif
2167	+
2168	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
2169	+	transfer_size_t transfer_size = SIZE_LONG;
2170	+	bool register_pair = false;
2171	+
2172	+	const unsigned int opcode = pc[0];
2173	+	if ((opcode >> 30) != 3)
2174	+	return false;
2175	+	switch ((opcode >> 19) & 0x3f) {
2176	+	case 9: // Load Signed Byte
2177	+	case 1: // Load Unsigned Byte
2178	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2179	+	transfer_size = SIZE_BYTE;
2180	+	break;
2181	+	case 10:// Load Signed Halfword
2182	+	case 2: // Load Unsigned Word
2183	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2184	+	transfer_size = SIZE_WORD;
2185	+	break;
2186	+	case 8: // Load Word
2187	+	case 0: // Load Unsigned Word
2188	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2189	+	transfer_size = SIZE_LONG;
2190	+	break;
2191	+	case 11:// Load Extended Word
2192	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2193	+	transfer_size = SIZE_QUAD;
2194	+	break;
2195	+	case 3: // Load Doubleword
2196	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2197	+	transfer_size = SIZE_LONG;
2198	+	register_pair = true;
2199	+	break;
2200	+	case 5: // Store Byte
2201	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2202	+	transfer_size = SIZE_BYTE;
2203	+	break;
2204	+	case 6: // Store Halfword
2205	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2206	+	transfer_size = SIZE_WORD;
2207	+	break;
2208	+	case 4: // Store Word
2209	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2210	+	transfer_size = SIZE_LONG;
2211	+	break;
2212	+	case 14:// Store Extended Word
2213	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2214	+	transfer_size = SIZE_QUAD;
2215	+	break;
2216	+	case 7: // Store Doubleword
2217	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2218	+	transfer_size = SIZE_LONG;
2219	+	register_pair = true;
2220	+	break;
2221	+	}
2222	+
2223	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
2224	+	// Unknown machine code, let it crash. Then patch the decoder
2225	+	return false;
2226	+	}
2227	+
2228	+	const int reg = (opcode >> 25) & 0x1f;
2229	+
2230	+	#if DEBUG
2231	+	static const char * reg_names[] = {
2232	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2233	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2234	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2235	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
2236	+	};
2237	+	printf("%s %s register %s\n",
2238	+	transfer_size == SIZE_BYTE ? "byte" :
2239	+	transfer_size == SIZE_WORD ? "word" :
2240	+	transfer_size == SIZE_LONG ? "long" :
2241	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
2242	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
2243	+	reg_names[reg]);
2244	+	#endif
2245	+
2246	+	// Zero target register in case of a load operation
2247	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
2248	+	// FIXME: code to handle local & input registers is not tested
2249	+	if (reg >= 1 && reg < 8) {
2250	+	// global registers
2251	+	regs[reg - 1 + SPARC_REG_G1] = 0;
2252	+	}
2253	+	else if (reg >= 8 && reg < 16) {
2254	+	// output registers
2255	+	regs[reg - 8 + SPARC_REG_O0] = 0;
2256	+	}
2257	+	else if (reg >= 16 && reg < 24) {
2258	+	// local registers (in register windows)
2259	+	if (gwins)
2260	+	gwins->wbuf->rw_local[reg - 16] = 0;
2261	+	else
2262	+	rwin->rw_local[reg - 16] = 0;
2263	+	}
2264	+	else {
2265	+	// input registers (in register windows)
2266	+	if (gwins)
2267	+	gwins->wbuf->rw_in[reg - 24] = 0;
2268	+	else
2269	+	rwin->rw_in[reg - 24] = 0;
2270	+	}
2271	+	}
2272	+
2273	+	regs[SPARC_REG_PC] += 4;
2274	+	regs[SPARC_REG_nPC] += 4;
2275	+	return true;
2276	+	}
2277	+	#endif
2278	+	#endif
2279	+
2280	+	// Decode and skip ARM instruction
2281	+	#if (defined(arm) || defined(__arm__))
2282	+	enum {
2283	+	#if (defined(__linux__))
2284	+	ARM_REG_PC = 15,
2285	+	ARM_REG_CPSR = 16
2286	+	#endif
2287	+	};
2288	+	static bool arm_skip_instruction(unsigned long * regs)
2289	+	{
2290	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
2291	+
2292	+	if (pc == 0)
2293	+	return false;
2294	+
2295	+	#if DEBUG
2296	+	printf("IP: %p [%08x]\n", pc, pc[0]);
2297	+	#endif
2298	+
2299	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
2300	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
2301	+	enum { op_sdt = 1, op_sdth = 2 };
2302	+	int op = 0;
2303	+
2304	+	// Handle load/store instructions only
2305	+	const unsigned int opcode = pc[0];
2306	+	switch ((opcode >> 25) & 7) {
2307	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
2308	+	op = op_sdth;
2309	+	// Determine transfer size (S/H bits)
2310	+	switch ((opcode >> 5) & 3) {
2311	+	case 0: // SWP instruction
2312	+	break;
2313	+	case 1: // Unsigned halfwords
2314	+	case 3: // Signed halfwords
2315	+	transfer_size = SIZE_WORD;
2316	+	break;
2317	+	case 2: // Signed byte
2318	+	transfer_size = SIZE_BYTE;
2319	+	break;
2320	+	}
2321	+	break;
2322	+	case 2:
2323	+	case 3: // Single Data Transfer (LDR, STR)
2324	+	op = op_sdt;
2325	+	// Determine transfer size (B bit)
2326	+	if (((opcode >> 22) & 1) == 1)
2327	+	transfer_size = SIZE_BYTE;
2328	+	else
2329	+	transfer_size = SIZE_LONG;
2330	+	break;
2331	+	default:
2332	+	// FIXME: support load/store mutliple?
2333	+	return false;
2334	+	}
2335	+
2336	+	// Check for invalid transfer size (SWP instruction?)
2337	+	if (transfer_size == SIZE_UNKNOWN)
2338	+	return false;
2339	+
2340	+	// Determine transfer type (L bit)
2341	+	if (((opcode >> 20) & 1) == 1)
2342	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
2343	+	else
2344	+	transfer_type = SIGSEGV_TRANSFER_STORE;
2345	+
2346	+	// Compute offset
2347	+	int offset;
2348	+	if (((opcode >> 25) & 1) == 0) {
2349	+	if (op == op_sdt)
2350	+	offset = opcode & 0xfff;
2351	+	else if (op == op_sdth) {
2352	+	int rm = opcode & 0xf;
2353	+	if (((opcode >> 22) & 1) == 0) {
2354	+	// register offset
2355	+	offset = regs[rm];
2356	+	}
2357	+	else {
2358	+	// immediate offset
2359	+	offset = ((opcode >> 4) & 0xf0) | (opcode & 0x0f);
2360	+	}
2361	+	}
2362	+	}
2363	+	else {
2364	+	const int rm = opcode & 0xf;
2365	+	const int sh = (opcode >> 7) & 0x1f;
2366	+	if (((opcode >> 4) & 1) == 1) {
2367	+	// we expect only legal load/store instructions
2368	+	printf("FATAL: invalid shift operand\n");
2369	+	return false;
2370	+	}
2371	+	const unsigned int v = regs[rm];
2372	+	switch ((opcode >> 5) & 3) {
2373	+	case 0: // logical shift left
2374	+	offset = sh ? v << sh : v;
2375	+	break;
2376	+	case 1: // logical shift right
2377	+	offset = sh ? v >> sh : 0;
2378	+	break;
2379	+	case 2: // arithmetic shift right
2380	+	if (sh)
2381	+	offset = ((signed int)v) >> sh;
2382	+	else
2383	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
2384	+	break;
2385	+	case 3: // rotate right
2386	+	if (sh)
2387	+	offset = (v >> sh) | (v << (32 - sh));
2388	+	else
2389	+	offset = (v >> 1) | ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
2390	+	break;
2391	+	}
2392	+	}
2393	+	if (((opcode >> 23) & 1) == 0)
2394	+	offset = -offset;
2395	+
2396	+	int rd = (opcode >> 12) & 0xf;
2397	+	int rn = (opcode >> 16) & 0xf;
2398	+	#if DEBUG
2399	+	static const char * reg_names[] = {
2400	+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2401	+	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
2402	+	};
2403	+	printf("%s %s register %s\n",
2404	+	transfer_size == SIZE_BYTE ? "byte" :
2405	+	transfer_size == SIZE_WORD ? "word" :
2406	+	transfer_size == SIZE_LONG ? "long" : "unknown",
2407	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
2408	+	reg_names[rd]);
2409	+	#endif
2410	+
2411	+	unsigned int base = regs[rn];
2412	+	if (((opcode >> 24) & 1) == 1)
2413	+	base += offset;
2414	+
2415	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
2416	+	regs[rd] = 0;
2417	+
2418	+	if (((opcode >> 24) & 1) == 0)                // post-index addressing
2419	+	regs[rn] += offset;
2420	+	else if (((opcode >> 21) & 1) == 1)   // write-back address into base
2421	+	regs[rn] = base;
2422	+
2423	+	regs[ARM_REG_PC] += 4;
2424	+	return true;
2425	+	}
2426	+	#endif
2427	+
2428	+
2429		// Fallbacks
2430	+	#ifndef SIGSEGV_FAULT_ADDRESS_FAST
2431	+	#define SIGSEGV_FAULT_ADDRESS_FAST              SIGSEGV_FAULT_ADDRESS
2432	+	#endif
2433	+	#ifndef SIGSEGV_FAULT_INSTRUCTION_FAST
2434	+	#define SIGSEGV_FAULT_INSTRUCTION_FAST  SIGSEGV_FAULT_INSTRUCTION
2435	+	#endif
2436		#ifndef SIGSEGV_FAULT_INSTRUCTION
2437	<	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_INVALID_PC
2437	>	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_INVALID_ADDRESS
2438		#endif
2439		#ifndef SIGSEGV_FAULT_HANDLER_ARGLIST_1
2440		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 SIGSEGV_FAULT_HANDLER_ARGLIST
2441		#endif
2442	+	#ifndef SIGSEGV_FAULT_HANDLER_INVOKE
2443	+	#define SIGSEGV_FAULT_HANDLER_INVOKE(P) sigsegv_fault_handler(P)
2444	+	#endif
2445
2446		// SIGSEGV recovery supported ?
2447		#if defined(SIGSEGV_ALL_SIGNALS) && defined(SIGSEGV_FAULT_HANDLER_ARGLIST) && defined(SIGSEGV_FAULT_ADDRESS)
#	Line 795 | Line 2453 | static bool powerpc_skip_instruction(uns
2453		*  SIGSEGV global handler
2454		*/
2455
2456	<	#if defined(HAVE_SIGSEGV_RECOVERY) || defined(HAVE_MACH_EXCEPTIONS)
2456	>	struct sigsegv_info_t {
2457	>	sigsegv_address_t addr;
2458	>	sigsegv_address_t pc;
2459	>	#ifdef HAVE_MACH_EXCEPTIONS
2460	>	mach_port_t thread;
2461	>	bool has_exc_state;
2462	>	SIGSEGV_EXCEPTION_STATE_TYPE exc_state;
2463	>	mach_msg_type_number_t exc_state_count;
2464	>	bool has_thr_state;
2465	>	SIGSEGV_THREAD_STATE_TYPE thr_state;
2466	>	mach_msg_type_number_t thr_state_count;
2467	>	#endif
2468	>	};
2469	>
2470	>	#ifdef HAVE_MACH_EXCEPTIONS
2471	>	static void mach_get_exception_state(sigsegv_info_t *SIP)
2472	>	{
2473	>	SIP->exc_state_count = SIGSEGV_EXCEPTION_STATE_COUNT;
2474	>	kern_return_t krc = thread_get_state(SIP->thread,
2475	>	SIGSEGV_EXCEPTION_STATE_FLAVOR,
2476	>	(natural_t *)&SIP->exc_state,
2477	>	&SIP->exc_state_count);
2478	>	MACH_CHECK_ERROR(thread_get_state, krc);
2479	>	SIP->has_exc_state = true;
2480	>	}
2481	>
2482	>	static void mach_get_thread_state(sigsegv_info_t *SIP)
2483	>	{
2484	>	SIP->thr_state_count = SIGSEGV_THREAD_STATE_COUNT;
2485	>	kern_return_t krc = thread_get_state(SIP->thread,
2486	>	SIGSEGV_THREAD_STATE_FLAVOR,
2487	>	(natural_t *)&SIP->thr_state,
2488	>	&SIP->thr_state_count);
2489	>	MACH_CHECK_ERROR(thread_get_state, krc);
2490	>	SIP->has_thr_state = true;
2491	>	}
2492	>
2493	>	static void mach_set_thread_state(sigsegv_info_t *SIP)
2494	>	{
2495	>	kern_return_t krc = thread_set_state(SIP->thread,
2496	>	SIGSEGV_THREAD_STATE_FLAVOR,
2497	>	(natural_t *)&SIP->thr_state,
2498	>	SIP->thr_state_count);
2499	>	MACH_CHECK_ERROR(thread_set_state, krc);
2500	>	}
2501	>	#endif
2502	>
2503	>	// Return the address of the invalid memory reference
2504	>	sigsegv_address_t sigsegv_get_fault_address(sigsegv_info_t *SIP)
2505	>	{
2506	>	#ifdef HAVE_MACH_EXCEPTIONS
2507	>	static int use_fast_path = -1;
2508	>	if (use_fast_path != 1 && !SIP->has_exc_state) {
2509	>	mach_get_exception_state(SIP);
2510	>
2511	>	sigsegv_address_t addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
2512	>	if (use_fast_path < 0) {
2513	>	const char *machfault = getenv("SIGSEGV_MACH_FAULT");
2514	>	if (machfault) {
2515	>	if (strcmp(machfault, "fast") == 0)
2516	>	use_fast_path = 1;
2517	>	else if (strcmp(machfault, "slow") == 0)
2518	>	use_fast_path = 0;
2519	>	}
2520	>	if (use_fast_path < 0)
2521	>	use_fast_path = addr == SIP->addr;
2522	>	}
2523	>	SIP->addr = addr;
2524	>	}
2525	>	#endif
2526	>	return SIP->addr;
2527	>	}
2528	>
2529	>	// Return the address of the instruction that caused the fault, or
2530	>	// SIGSEGV_INVALID_ADDRESS if we could not retrieve this information
2531	>	sigsegv_address_t sigsegv_get_fault_instruction_address(sigsegv_info_t *SIP)
2532	>	{
2533	>	#ifdef HAVE_MACH_EXCEPTIONS
2534	>	if (!SIP->has_thr_state) {
2535	>	mach_get_thread_state(SIP);
2536	>
2537	>	SIP->pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
2538	>	}
2539	>	#endif
2540	>	return SIP->pc;
2541	>	}
2542	>
2543		// This function handles the badaccess to memory.
2544		// It is called from the signal handler or the exception handler.
2545		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
2546		{
2547	<	sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
2548	<	sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
2549	<
2547	>	sigsegv_info_t SI;
2548	>	SI.addr = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS_FAST;
2549	>	SI.pc = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION_FAST;
2550	>	#ifdef HAVE_MACH_EXCEPTIONS
2551	>	SI.thread = thread;
2552	>	SI.has_exc_state = false;
2553	>	SI.has_thr_state = false;
2554	>	#endif
2555	>	sigsegv_info_t * const SIP = &SI;
2556	>
2557		// Call user's handler and reinstall the global handler, if required
2558	<	switch (sigsegv_fault_handler(fault_address, fault_instruction)) {
2558	>	switch (SIGSEGV_FAULT_HANDLER_INVOKE(SIP)) {
2559		case SIGSEGV_RETURN_SUCCESS:
2560		return true;
2561
#	Line 812 | Line 2563 | static bool handle_badaccess(SIGSEGV_FAU
2563		case SIGSEGV_RETURN_SKIP_INSTRUCTION:
2564		// Call the instruction skipper with the register file
2565		// available
2566	+	#ifdef HAVE_MACH_EXCEPTIONS
2567	+	if (!SIP->has_thr_state)
2568	+	mach_get_thread_state(SIP);
2569	+	#endif
2570		if (SIGSEGV_SKIP_INSTRUCTION(SIGSEGV_REGISTER_FILE)) {
2571		#ifdef HAVE_MACH_EXCEPTIONS
2572		// Unlike UNIX signals where the thread state
2573		// is modified off of the stack, in Mach we
2574		// need to actually call thread_set_state to
2575		// have the register values updated.
2576	<	kern_return_t krc;
822	<
823	<	krc = thread_set_state(thread,
824	<	MACHINE_THREAD_STATE, (thread_state_t)state,
825	<	MACHINE_THREAD_STATE_COUNT);
826	<	MACH_CHECK_ERROR (thread_get_state, krc);
2576	>	mach_set_thread_state(SIP);
2577		#endif
2578		return true;
2579		}
2580		break;
2581		#endif
2582	+	case SIGSEGV_RETURN_FAILURE:
2583	+	// We can't do anything with the fault_address, dump state?
2584	+	if (sigsegv_state_dumper != 0)
2585	+	sigsegv_state_dumper(SIP);
2586	+	break;
2587		}
833	–
834	–	// We can't do anything with the fault_address, dump state?
835	–	if (sigsegv_state_dumper != 0)
836	–	sigsegv_state_dumper(fault_address, fault_instruction);
2588
2589		return false;
2590		}
840	–	#endif
2591
2592
2593		/*
#	Line 874 | Line 2624 | forward_exception(mach_port_t thread_por
2624		mach_port_t port;
2625		exception_behavior_t behavior;
2626		thread_state_flavor_t flavor;
2627	<	thread_state_t thread_state;
2627	>	thread_state_data_t thread_state;
2628		mach_msg_type_number_t thread_state_count;
2629
2630		for (portIndex = 0; portIndex < oldExceptionPorts->maskCount; portIndex++) {
#	Line 893 | Line 2643 | forward_exception(mach_port_t thread_por
2643		behavior = oldExceptionPorts->behaviors[portIndex];
2644		flavor = oldExceptionPorts->flavors[portIndex];
2645
2646	+	if (!VALID_THREAD_STATE_FLAVOR(flavor)) {
2647	+	fprintf(stderr, "Invalid thread_state flavor = %d. Not forwarding\n", flavor);
2648	+	return KERN_FAILURE;
2649	+	}
2650	+
2651		/*
2652		fprintf(stderr, "forwarding exception, port = 0x%x, behaviour = %d, flavor = %d\n", port, behavior, flavor);
2653		*/
2654
2655		if (behavior != EXCEPTION_DEFAULT) {
2656		thread_state_count = THREAD_STATE_MAX;
2657	<	kret = thread_get_state (thread_port, flavor, thread_state,
2657	>	kret = thread_get_state (thread_port, flavor, (natural_t *)&thread_state,
2658		&thread_state_count);
2659		MACH_CHECK_ERROR (thread_get_state, kret);
2660		}
#	Line 915 | Line 2670 | forward_exception(mach_port_t thread_por
2670		// fprintf(stderr, "forwarding to exception_raise_state\n");
2671		kret = exception_raise_state(port, exception_type, exception_data,
2672		data_count, &flavor,
2673	<	thread_state, thread_state_count,
2674	<	thread_state, &thread_state_count);
2673	>	(natural_t *)&thread_state, thread_state_count,
2674	>	(natural_t *)&thread_state, &thread_state_count);
2675		MACH_CHECK_ERROR (exception_raise_state, kret);
2676		break;
2677		case EXCEPTION_STATE_IDENTITY:
#	Line 924 | Line 2679 | forward_exception(mach_port_t thread_por
2679		kret = exception_raise_state_identity(port, thread_port, task_port,
2680		exception_type, exception_data,
2681		data_count, &flavor,
2682	<	thread_state, thread_state_count,
2683	<	thread_state, &thread_state_count);
2682	>	(natural_t *)&thread_state, thread_state_count,
2683	>	(natural_t *)&thread_state, &thread_state_count);
2684		MACH_CHECK_ERROR (exception_raise_state_identity, kret);
2685		break;
2686		default:
2687		fprintf(stderr, "forward_exception got unknown behavior\n");
2688	+	kret = KERN_FAILURE;
2689		break;
2690		}
2691
2692		if (behavior != EXCEPTION_DEFAULT) {
2693	<	kret = thread_set_state (thread_port, flavor, thread_state,
2693	>	kret = thread_set_state (thread_port, flavor, (natural_t *)&thread_state,
2694		thread_state_count);
2695		MACH_CHECK_ERROR (thread_set_state, kret);
2696		}
2697
2698	<	return KERN_SUCCESS;
2698	>	return kret;
2699		}
2700
2701		/*
#	Line 967 | Line 2723 | catch_exception_raise(mach_port_t except
2723		mach_port_t task,
2724		exception_type_t exception,
2725		exception_data_t code,
2726	<	mach_msg_type_number_t codeCount)
2726	>	mach_msg_type_number_t code_count)
2727		{
972	–	ppc_thread_state_t state;
2728		kern_return_t krc;
2729
2730	<	if ((exception == EXC_BAD_ACCESS)  && (codeCount >= 2)) {
2731	<	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
2732	<	return KERN_SUCCESS;
2730	>	if (exception == EXC_BAD_ACCESS) {
2731	>	switch (code[0]) {
2732	>	case KERN_PROTECTION_FAILURE:
2733	>	case KERN_INVALID_ADDRESS:
2734	>	if (handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGS))
2735	>	return KERN_SUCCESS;
2736	>	break;
2737	>	}
2738		}
2739
2740		// In Mach we do not need to remove the exception handler.
2741		// If we forward the exception, eventually some exception handler
2742		// will take care of this exception.
2743	<	krc = forward_exception(thread, task, exception, code, codeCount, &ports);
2743	>	krc = forward_exception(thread, task, exception, code, code_count, &ports);
2744
2745		return krc;
2746		}
#	Line 1108 | Line 2868 | static bool sigsegv_do_install_handler(s
2868		// addressing modes) used in PPC instructions, you will need the
2869		// GPR state anyway.
2870		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
2871	<	EXCEPTION_DEFAULT, MACHINE_THREAD_STATE);
2871	>	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
2872		if (krc != KERN_SUCCESS) {
2873		mach_error("thread_set_exception_ports", krc);
2874		return false;
#	Line 1131 | Line 2891 | static bool sigsegv_do_install_handler(s
2891		}
2892		#endif
2893
2894	+	#ifdef HAVE_WIN32_EXCEPTIONS
2895	+	static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo)
2896	+	{
2897	+	if (sigsegv_fault_handler != NULL
2898	+	&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
2899	+	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
2900	+	&& handle_badaccess(ExceptionInfo))
2901	+	return EXCEPTION_CONTINUE_EXECUTION;
2902	+
2903	+	return EXCEPTION_CONTINUE_SEARCH;
2904	+	}
2905	+
2906	+	#if defined __CYGWIN__ && defined __i386__
2907	+	/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin
2908	+	installs a global exception handler.  We have to dig deep in order to install
2909	+	our main_exception_filter.  */
2910	+
2911	+	/* Data structures for the current thread's exception handler chain.
2912	+	On the x86 Windows uses register fs, offset 0 to point to the current
2913	+	exception handler; Cygwin mucks with it, so we must do the same... :-/ */
2914	+
2915	+	/* Magic taken from winsup/cygwin/include/exceptions.h.  */
2916	+
2917	+	struct exception_list {
2918	+	struct exception_list *prev;
2919	+	int (*handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *);
2920	+	};
2921	+	typedef struct exception_list exception_list;
2922	+
2923	+	/* Magic taken from winsup/cygwin/exceptions.cc.  */
2924	+
2925	+	__asm__ (".equ __except_list,0");
2926	+
2927	+	extern exception_list *_except_list __asm__ ("%fs:__except_list");
2928	+
2929	+	/* For debugging.  _except_list is not otherwise accessible from gdb.  */
2930	+	static exception_list *
2931	+	debug_get_except_list ()
2932	+	{
2933	+	return _except_list;
2934	+	}
2935	+
2936	+	/* Cygwin's original exception handler.  */
2937	+	static int (*cygwin_exception_handler) (EXCEPTION_RECORD *, void *, CONTEXT *, void *);
2938	+
2939	+	/* Our exception handler.  */
2940	+	static int
2941	+	libsigsegv_exception_handler (EXCEPTION_RECORD *exception, void *frame, CONTEXT *context, void *dispatch)
2942	+	{
2943	+	EXCEPTION_POINTERS ExceptionInfo;
2944	+	ExceptionInfo.ExceptionRecord = exception;
2945	+	ExceptionInfo.ContextRecord = context;
2946	+	if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH)
2947	+	return cygwin_exception_handler (exception, frame, context, dispatch);
2948	+	else
2949	+	return 0;
2950	+	}
2951	+
2952	+	static void
2953	+	do_install_main_exception_filter ()
2954	+	{
2955	+	/* We cannot insert any handler into the chain, because such handlers
2956	+	must lie on the stack (?).  Instead, we have to replace(!) Cygwin's
2957	+	global exception handler.  */
2958	+	cygwin_exception_handler = _except_list->handler;
2959	+	_except_list->handler = libsigsegv_exception_handler;
2960	+	}
2961	+
2962	+	#else
2963	+
2964	+	static void
2965	+	do_install_main_exception_filter ()
2966	+	{
2967	+	SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter);
2968	+	}
2969	+	#endif
2970	+
2971	+	static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler)
2972	+	{
2973	+	static bool main_exception_filter_installed = false;
2974	+	if (!main_exception_filter_installed) {
2975	+	do_install_main_exception_filter();
2976	+	main_exception_filter_installed = true;
2977	+	}
2978	+	sigsegv_fault_handler = handler;
2979	+	return true;
2980	+	}
2981	+	#endif
2982	+
2983		bool sigsegv_install_handler(sigsegv_fault_handler_t handler)
2984		{
2985		#if defined(HAVE_SIGSEGV_RECOVERY)
#	Line 1141 | Line 2990 | bool sigsegv_install_handler(sigsegv_fau
2990		if (success)
2991		sigsegv_fault_handler = handler;
2992		return success;
2993	<	#elif defined(HAVE_MACH_EXCEPTIONS)
2993	>	#elif defined(HAVE_MACH_EXCEPTIONS) || defined(HAVE_WIN32_EXCEPTIONS)
2994		return sigsegv_do_install_handler(handler);
2995		#else
2996		// FAIL: no siginfo_t nor sigcontext subterfuge is available
#	Line 1167 | Line 3016 | void sigsegv_deinstall_handler(void)
3016		SIGSEGV_ALL_SIGNALS
3017		#undef FAULT_HANDLER
3018		#endif
3019	+	#ifdef HAVE_WIN32_EXCEPTIONS
3020	+	sigsegv_fault_handler = NULL;
3021	+	#endif
3022		}
3023
3024
#	Line 1188 | Line 3040 | void sigsegv_set_dump_state(sigsegv_stat
3040		#include <stdio.h>
3041		#include <stdlib.h>
3042		#include <fcntl.h>
3043	+	#ifdef HAVE_SYS_MMAN_H
3044		#include <sys/mman.h>
3045	+	#endif
3046		#include "vm_alloc.h"
3047
3048	<	static int page_size;
3048	>	const int REF_INDEX = 123;
3049	>	const int REF_VALUE = 45;
3050	>
3051	>	static sigsegv_uintptr_t page_size;
3052		static volatile char * page = 0;
3053		static volatile int handler_called = 0;
3054
3055	<	static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
3055	>	/* Barriers */
3056	>	#ifdef __GNUC__
3057	>	#define BARRIER() asm volatile ("" : : : "memory")
3058	>	#else
3059	>	#define BARRIER() /* nothing */
3060	>	#endif
3061	>
3062	>	#ifdef __GNUC__
3063	>	// Code range where we expect the fault to come from
3064	>	static void *b_region, *e_region;
3065	>	#endif
3066	>
3067	>	static sigsegv_return_t sigsegv_test_handler(sigsegv_info_t *sip)
3068		{
3069	+	const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip);
3070	+	const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip);
3071	+	#if DEBUG
3072	+	printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
3073	+	printf("expected fault at %p\n", page + REF_INDEX);
3074	+	#ifdef __GNUC__
3075	+	printf("expected instruction address range: %p-%p\n", b_region, e_region);
3076	+	#endif
3077	+	#endif
3078		handler_called++;
3079	<	if ((fault_address - 123) != page)
3079	>	if ((fault_address - REF_INDEX) != page)
3080		exit(10);
3081	<	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
3081	>	#ifdef __GNUC__
3082	>	// Make sure reported fault instruction address falls into
3083	>	// expected code range
3084	>	if (instruction_address != SIGSEGV_INVALID_ADDRESS
3085	>	&& ((instruction_address <  (sigsegv_address_t)b_region) ||
3086	>	(instruction_address >= (sigsegv_address_t)e_region)))
3087		exit(11);
3088	+	#endif
3089	+	if (vm_protect((char *)((sigsegv_uintptr_t)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
3090	+	exit(12);
3091		return SIGSEGV_RETURN_SUCCESS;
3092		}
3093
3094		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
3095	<	#ifdef __GNUC__
1210	<	// Code range where we expect the fault to come from
1211	<	static void *b_region, *e_region;
1212	<	#endif
1213	<
1214	<	static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
3095	>	static sigsegv_return_t sigsegv_insn_handler(sigsegv_info_t *sip)
3096		{
3097	<	if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
3097	>	const sigsegv_address_t fault_address = sigsegv_get_fault_address(sip);
3098	>	const sigsegv_address_t instruction_address = sigsegv_get_fault_instruction_address(sip);
3099	>	#if DEBUG
3100	>	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
3101	>	#endif
3102	>	if (((sigsegv_uintptr_t)fault_address - (sigsegv_uintptr_t)page) < page_size) {
3103		#ifdef __GNUC__
3104		// Make sure reported fault instruction address falls into
3105		// expected code range
3106	<	if (instruction_address != SIGSEGV_INVALID_PC
3106	>	if (instruction_address != SIGSEGV_INVALID_ADDRESS
3107		&& ((instruction_address <  (sigsegv_address_t)b_region) ||
3108		(instruction_address >= (sigsegv_address_t)e_region)))
3109		return SIGSEGV_RETURN_FAILURE;
#	Line 1227 | Line 3113 | static sigsegv_return_t sigsegv_insn_han
3113
3114		return SIGSEGV_RETURN_FAILURE;
3115		}
3116	+
3117	+	// More sophisticated tests for instruction skipper
3118	+	static bool arch_insn_skipper_tests()
3119	+	{
3120	+	#if (defined(i386) || defined(__i386__)) || (defined(__x86_64__) || defined(_M_X64))
3121	+	static const unsigned char code[] = {
3122	+	0x8a, 0x00,                    // mov    (%eax),%al
3123	+	0x8a, 0x2c, 0x18,              // mov    (%eax,%ebx,1),%ch
3124	+	0x88, 0x20,                    // mov    %ah,(%eax)
3125	+	0x88, 0x08,                    // mov    %cl,(%eax)
3126	+	0x66, 0x8b, 0x00,              // mov    (%eax),%ax
3127	+	0x66, 0x8b, 0x0c, 0x18,        // mov    (%eax,%ebx,1),%cx
3128	+	0x66, 0x89, 0x00,              // mov    %ax,(%eax)
3129	+	0x66, 0x89, 0x0c, 0x18,        // mov    %cx,(%eax,%ebx,1)
3130	+	0x8b, 0x00,                    // mov    (%eax),%eax
3131	+	0x8b, 0x0c, 0x18,              // mov    (%eax,%ebx,1),%ecx
3132	+	0x89, 0x00,                    // mov    %eax,(%eax)
3133	+	0x89, 0x0c, 0x18,              // mov    %ecx,(%eax,%ebx,1)
3134	+	#if defined(__x86_64__) || defined(_M_X64)
3135	+	0x44, 0x8a, 0x00,              // mov    (%rax),%r8b
3136	+	0x44, 0x8a, 0x20,              // mov    (%rax),%r12b
3137	+	0x42, 0x8a, 0x3c, 0x10,        // mov    (%rax,%r10,1),%dil
3138	+	0x44, 0x88, 0x00,              // mov    %r8b,(%rax)
3139	+	0x44, 0x88, 0x20,              // mov    %r12b,(%rax)
3140	+	0x42, 0x88, 0x3c, 0x10,        // mov    %dil,(%rax,%r10,1)
3141	+	0x66, 0x44, 0x8b, 0x00,        // mov    (%rax),%r8w
3142	+	0x66, 0x42, 0x8b, 0x0c, 0x10,  // mov    (%rax,%r10,1),%cx
3143	+	0x66, 0x44, 0x89, 0x00,        // mov    %r8w,(%rax)
3144	+	0x66, 0x42, 0x89, 0x0c, 0x10,  // mov    %cx,(%rax,%r10,1)
3145	+	0x44, 0x8b, 0x00,              // mov    (%rax),%r8d
3146	+	0x42, 0x8b, 0x0c, 0x10,        // mov    (%rax,%r10,1),%ecx
3147	+	0x44, 0x89, 0x00,              // mov    %r8d,(%rax)
3148	+	0x42, 0x89, 0x0c, 0x10,        // mov    %ecx,(%rax,%r10,1)
3149	+	0x48, 0x8b, 0x08,              // mov    (%rax),%rcx
3150	+	0x4c, 0x8b, 0x18,              // mov    (%rax),%r11
3151	+	0x4a, 0x8b, 0x0c, 0x10,        // mov    (%rax,%r10,1),%rcx
3152	+	0x4e, 0x8b, 0x1c, 0x10,        // mov    (%rax,%r10,1),%r11
3153	+	0x48, 0x89, 0x08,              // mov    %rcx,(%rax)
3154	+	0x4c, 0x89, 0x18,              // mov    %r11,(%rax)
3155	+	0x4a, 0x89, 0x0c, 0x10,        // mov    %rcx,(%rax,%r10,1)
3156	+	0x4e, 0x89, 0x1c, 0x10,        // mov    %r11,(%rax,%r10,1)
3157	+	0x63, 0x47, 0x04,              // movslq 4(%rdi),%eax
3158	+	0x48, 0x63, 0x47, 0x04,        // movslq 4(%rdi),%rax
3159	+	#endif
3160	+	0                              // end
3161	+	};
3162	+	const int N_REGS = 20;
3163	+	SIGSEGV_REGISTER_TYPE regs[N_REGS];
3164	+	for (int i = 0; i < N_REGS; i++)
3165	+	regs[i] = i;
3166	+	const sigsegv_uintptr_t start_code = (sigsegv_uintptr_t)&code;
3167	+	regs[X86_REG_EIP] = start_code;
3168	+	while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
3169	+	&& ix86_skip_instruction(regs))
3170	+	; /* simply iterate */
3171	+	return (regs[X86_REG_EIP] - start_code) == (sizeof(code) - 1);
3172	+	#endif
3173	+	return true;
3174	+	}
3175		#endif
3176
3177		int main(void)
#	Line 1234 | Line 3179 | int main(void)
3179		if (vm_init() < 0)
3180		return 1;
3181
3182	<	page_size = getpagesize();
3182	>	page_size = vm_get_page_size();
3183		if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED)
3184		return 2;
3185
3186	+	memset((void *)page, 0, page_size);
3187		if (vm_protect((char *)page, page_size, VM_PAGE_READ) < 0)
3188		return 3;
3189
3190		if (!sigsegv_install_handler(sigsegv_test_handler))
3191		return 4;
3192	<
3193	<	page[123] = 45;
3194	<	page[123] = 45;
3195	<
3192	>
3193	>	#ifdef __GNUC__
3194	>	b_region = &&L_b_region1;
3195	>	e_region = &&L_e_region1;
3196	>	#endif
3197	>	/* This is a really awful hack but otherwise gcc is smart enough
3198	>	* (or bug'ous enough?) to optimize the labels and place them
3199	>	* e.g. at the "main" entry point, which is wrong.
3200	>	*/
3201	>	volatile int label_hack = 1;
3202	>	switch (label_hack) {
3203	>	case 1:
3204	>	L_b_region1:
3205	>	page[REF_INDEX] = REF_VALUE;
3206	>	if (page[REF_INDEX] != REF_VALUE)
3207	>	exit(20);
3208	>	page[REF_INDEX] = REF_VALUE;
3209	>	BARRIER();
3210	>	// fall-through
3211	>	case 2:
3212	>	L_e_region1:
3213	>	BARRIER();
3214	>	break;
3215	>	}
3216	>
3217		if (handler_called != 1)
3218		return 5;
3219
#	Line 1264 | Line 3231 | int main(void)
3231		return 8;
3232
3233		#define TEST_SKIP_INSTRUCTION(TYPE) do {                                \
3234	<	const unsigned int TAG = 0x12345678;                    \
3234	>	const unsigned long TAG = 0x12345678 |                  \
3235	>	(sizeof(long) == 8 ? 0x9abcdef0UL << 31 : 0);   \
3236		TYPE data = *((TYPE *)(page + sizeof(TYPE)));   \
3237	<	volatile unsigned int effect = data + TAG;              \
3237	>	volatile unsigned long effect = data + TAG;             \
3238		if (effect != TAG)                                                              \
3239		return 9;                                                                       \
3240		} while (0)
3241
3242		#ifdef __GNUC__
3243	<	b_region = &&L_b_region;
3244	<	e_region = &&L_e_region;
3243	>	b_region = &&L_b_region2;
3244	>	e_region = &&L_e_region2;
3245		#endif
3246	<	L_b_region:
3247	<	TEST_SKIP_INSTRUCTION(unsigned char);
3248	<	TEST_SKIP_INSTRUCTION(unsigned short);
3249	<	TEST_SKIP_INSTRUCTION(unsigned int);
3250	<	L_e_region:
3246	>	switch (label_hack) {
3247	>	case 1:
3248	>	L_b_region2:
3249	>	TEST_SKIP_INSTRUCTION(unsigned char);
3250	>	TEST_SKIP_INSTRUCTION(unsigned short);
3251	>	TEST_SKIP_INSTRUCTION(unsigned int);
3252	>	TEST_SKIP_INSTRUCTION(unsigned long);
3253	>	TEST_SKIP_INSTRUCTION(signed char);
3254	>	TEST_SKIP_INSTRUCTION(signed short);
3255	>	TEST_SKIP_INSTRUCTION(signed int);
3256	>	TEST_SKIP_INSTRUCTION(signed long);
3257	>	BARRIER();
3258	>	// fall-through
3259	>	case 2:
3260	>	L_e_region2:
3261	>	BARRIER();
3262	>	break;
3263	>	}
3264	>	if (!arch_insn_skipper_tests())
3265	>	return 20;
3266		#endif
3267
3268		vm_exit();

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