[ViewVC] Diff of: cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.30 by gbeauche, 2003-10-13T19:56:17Z vs.
Revision 1.56 by gbeauche, 2005-06-12T21:47:46Z

#	Line 10 \| Line 10
10		* tjw@omnigroup.com Sun, 4 Jun 2000
11		* www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	* Basilisk II (C) 1997-2002 Christian Bauer
13	>	* Basilisk II (C) 1997-2005 Christian Bauer
14		*
15		* This program is free software; you can redistribute it and/or modify
16		* it under the terms of the GNU General Public License as published by
#	Line 36 \| Line 36
36		#endif
37
38		#include <list>
39	+	#include <stdio.h>
40		#include <signal.h>
41		#include "sigsegv.h"
42
#	Line 69 \| Line 70 \| static bool sigsegv_do_install_handler(i
70		enum transfer_size_t {
71		SIZE_UNKNOWN,
72		SIZE_BYTE,
73	<	SIZE_WORD,
74	<	SIZE_LONG
73	>	SIZE_WORD, // 2 bytes
74	>	SIZE_LONG, // 4 bytes
75	>	SIZE_QUAD, // 8 bytes
76		};
77
78		// Transfer type
#	Line 95 \| Line 97 \| struct instruction_t {
97		char ra, rd;
98		};
99
100	<	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned int gpr)
100	>	static void powerpc_decode_instruction(instruction_t instruction, unsigned int nip, unsigned long gpr)
101		{
102		// Get opcode and divide into fields
103	<	unsigned int opcode = ((unsigned int )nip);
103	>	unsigned int opcode = ((unsigned int )(unsigned long)nip);
104		unsigned int primop = opcode >> 26;
105		unsigned int exop = (opcode >> 1) & 0x3ff;
106		unsigned int ra = (opcode >> 16) & 0x1f;
#	Line 172 \| Line 174 \| static void powerpc_decode_instruction(i
174		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_NORM; break;
175		case 45: // sthu
176		transfer_type = SIGSEGV_TRANSFER_STORE; transfer_size = SIZE_WORD; addr_mode = MODE_U; break;
177	+	case 58: // ld, ldu, lwa
178	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
179	+	transfer_size = SIZE_QUAD;
180	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
181	+	imm &= ~3;
182	+	break;
183	+	case 62: // std, stdu, stq
184	+	transfer_type = SIGSEGV_TRANSFER_STORE;
185	+	transfer_size = SIZE_QUAD;
186	+	addr_mode = ((opcode & 3) == 1) ? MODE_U : MODE_NORM;
187	+	imm &= ~3;
188	+	break;
189		}
190
191		// Calculate effective address
#	Line 212 \| Line 226 \| static void powerpc_decode_instruction(i
226
227		#if HAVE_SIGINFO_T
228		// Generic extended signal handler
229	<	#define SIGSEGV_FAULT_HANDLER sigsegv_fault_handler
216	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
229	>	#if defined(__FreeBSD__)
230		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
231		#else
232		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
#	Line 222 \| Line 235 \| static void powerpc_decode_instruction(i
235		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t sip, void scp
236		#define SIGSEGV_FAULT_HANDLER_ARGS sip, scp
237		#define SIGSEGV_FAULT_ADDRESS sip->si_addr
238	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
238	>	#if (defined(sgi) \|\| defined(__sgi))
239	>	#include <ucontext.h>
240	>	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
241	>	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
242	>	#if (defined(mips) \|\| defined(__mips))
243	>	#define SIGSEGV_REGISTER_FILE SIGSEGV_CONTEXT_REGS
244	>	#define SIGSEGV_SKIP_INSTRUCTION mips_skip_instruction
245	>	#endif
246	>	#endif
247	>	#if defined(__sun__)
248	>	#if (defined(sparc) \|\| defined(__sparc__))
249	>	#include <sys/stack.h>
250	>	#include <sys/regset.h>
251	>	#include <sys/ucontext.h>
252	>	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
253	>	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[REG_PC]
254	>	#define SIGSEGV_SPARC_GWINDOWS (((ucontext_t *)scp)->uc_mcontext.gwins)
255	>	#define SIGSEGV_SPARC_RWINDOW (struct rwindow )((char )SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
256	>	#define SIGSEGV_REGISTER_FILE ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
257	>	#define SIGSEGV_SKIP_INSTRUCTION sparc_skip_instruction
258	>	#endif
259	>	#if defined(__i386__)
260	>	#include <sys/regset.h>
261	>	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
262	>	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[EIP]
263	>	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
264	>	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
265	>	#endif
266	>	#endif
267	>	#if defined(__FreeBSD__) \|\| defined(__OpenBSD__)
268		#if (defined(i386) \|\| defined(__i386__))
269		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext *)scp)->sc_eip)
270	<	#define SIGSEGV_REGISTER_FILE ((unsigned int )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
270	>	#define SIGSEGV_REGISTER_FILE ((unsigned long )&(((struct sigcontext )scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
271		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
272		#endif
273		#endif
274	+	#if defined(__NetBSD__)
275	+	#if (defined(i386) \|\| defined(__i386__))
276	+	#include <sys/ucontext.h>
277	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
278	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_EIP]
279	+	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
280	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
281	+	#endif
282	+	#if (defined(powerpc) \|\| defined(__powerpc__))
283	+	#include <sys/ucontext.h>
284	+	#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.__gregs)
285	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[_REG_PC]
286	+	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIGSEGV_CONTEXT_REGS[_REG_PC], (unsigned long )&SIGSEGV_CONTEXT_REGS[_REG_R0]
287	+	#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
288	+	#endif
289	+	#endif
290		#if defined(__linux__)
291		#if (defined(i386) \|\| defined(__i386__))
292		#include <sys/ucontext.h>
293		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
294		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
295	<	#define SIGSEGV_REGISTER_FILE (unsigned int *)SIGSEGV_CONTEXT_REGS
295	>	#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
296		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
297		#endif
298		#if (defined(x86_64) \|\| defined(__x86_64__))
#	Line 242 \| Line 300 \| static void powerpc_decode_instruction(i
300		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.gregs)
301		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
302		#define SIGSEGV_REGISTER_FILE (unsigned long *)SIGSEGV_CONTEXT_REGS
303	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
304		#endif
305		#if (defined(ia64) \|\| defined(__ia64__))
306		#define SIGSEGV_FAULT_INSTRUCTION (((struct sigcontext )scp)->sc_ip & ~0x3ULL) / slot number is in bits 0 and 1 */
#	Line 250 \| Line 309 \| static void powerpc_decode_instruction(i
309		#include <sys/ucontext.h>
310		#define SIGSEGV_CONTEXT_REGS (((ucontext_t *)scp)->uc_mcontext.regs)
311		#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS->nip)
312	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&SIGSEGV_CONTEXT_REGS->nip, (unsigned int )(SIGSEGV_CONTEXT_REGS->gpr)
312	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&SIGSEGV_CONTEXT_REGS->nip, (unsigned long )(SIGSEGV_CONTEXT_REGS->gpr)
313		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
314		#endif
315	+	#if (defined(hppa) \|\| defined(__hppa__))
316	+	#undef SIGSEGV_FAULT_ADDRESS
317	+	#define SIGSEGV_FAULT_ADDRESS sip->si_ptr
318	+	#endif
319	+	#if (defined(arm) \|\| defined(__arm__))
320	+	#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
321	+	#define SIGSEGV_CONTEXT_REGS (((struct ucontext *)scp)->uc_mcontext)
322	+	#define SIGSEGV_FAULT_INSTRUCTION (SIGSEGV_CONTEXT_REGS.arm_pc)
323	+	#define SIGSEGV_REGISTER_FILE (&SIGSEGV_CONTEXT_REGS.arm_r0)
324	+	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
325	+	#endif
326		#endif
327		#endif
328
329		#if HAVE_SIGCONTEXT_SUBTERFUGE
260	–	#define SIGSEGV_FAULT_HANDLER sigsegv_fault_handler
330		// Linux kernels prior to 2.4 ?
331		#if defined(__linux__)
332		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
#	Line 268 \| Line 337 \| static void powerpc_decode_instruction(i
337		#define SIGSEGV_FAULT_HANDLER_ARGS &scs
338		#define SIGSEGV_FAULT_ADDRESS scp->cr2
339		#define SIGSEGV_FAULT_INSTRUCTION scp->eip
340	<	#define SIGSEGV_REGISTER_FILE (unsigned int *)scp
340	>	#define SIGSEGV_REGISTER_FILE (unsigned long *)scp
341		#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
342		#endif
343		#if (defined(sparc) \|\| defined(__sparc__))
#	Line 283 \| Line 352 \| static void powerpc_decode_instruction(i
352		#define SIGSEGV_FAULT_HANDLER_ARGS sig, scp
353		#define SIGSEGV_FAULT_ADDRESS scp->regs->dar
354		#define SIGSEGV_FAULT_INSTRUCTION scp->regs->nip
355	<	#define SIGSEGV_REGISTER_FILE (unsigned int )&scp->regs->nip, (unsigned int )(scp->regs->gpr)
355	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&scp->regs->nip, (unsigned long )(scp->regs->gpr)
356		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
357		#endif
358		#if (defined(alpha) \|\| defined(__alpha__))
#	Line 292 \| Line 361 \| static void powerpc_decode_instruction(i
361		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp
362		#define SIGSEGV_FAULT_ADDRESS get_fault_address(scp)
363		#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
364	<
365	<	// From Boehm's GC 6.0alpha8
366	<	static sigsegv_address_t get_fault_address(struct sigcontext *scp)
367	<	{
368	<	unsigned int instruction = ((unsigned int )(scp->sc_pc));
369	<	unsigned long fault_address = scp->sc_regs[(instruction >> 16) & 0x1f];
370	<	fault_address += (signed long)(signed short)(instruction & 0xffff);
371	<	return (sigsegv_address_t)fault_address;
372	<	}
364	>	#endif
365	>	#if (defined(arm) \|\| defined(__arm__))
366	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int r1, int r2, int r3, struct sigcontext sc
367	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp
368	>	#define SIGSEGV_FAULT_HANDLER_ARGS &sc
369	>	#define SIGSEGV_FAULT_ADDRESS scp->fault_address
370	>	#define SIGSEGV_FAULT_INSTRUCTION scp->arm_pc
371	>	#define SIGSEGV_REGISTER_FILE &scp->arm_r0
372	>	#define SIGSEGV_SKIP_INSTRUCTION arm_skip_instruction
373		#endif
374		#endif
375
376		// Irix 5 or 6 on MIPS
377	<	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(__SYSTYPE_SVR4))
377	>	#if (defined(sgi) \|\| defined(__sgi)) && (defined(SYSTYPE_SVR4) \|\| defined(_SYSTYPE_SVR4))
378		#include <ucontext.h>
379		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp
380		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp
381	<	#define SIGSEGV_FAULT_ADDRESS scp->sc_badvaddr
381	>	#define SIGSEGV_FAULT_ADDRESS (unsigned long)scp->sc_badvaddr
382	>	#define SIGSEGV_FAULT_INSTRUCTION (unsigned long)scp->sc_pc
383		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
384		#endif
385
#	Line 338 \| Line 408 \| static sigsegv_address_t get_fault_addre
408		#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
409		#endif
410
411	<	// NetBSD or FreeBSD
412	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
411	>	// NetBSD
412	>	#if defined(__NetBSD__)
413		#if (defined(m68k) \|\| defined(__m68k__))
414		#include <m68k/frame.h>
415		#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp
#	Line 367 \| Line 437 \| static sigsegv_address_t get_fault_addre
437		}
438		return (sigsegv_address_t)fault_addr;
439		}
440	<	#else
441	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, void scp, char addr
440	>	#endif
441	>	#if (defined(alpha) \|\| defined(__alpha__))
442	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp
443	>	#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp
444	>	#define SIGSEGV_FAULT_ADDRESS get_fault_address(scp)
445	>	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
446	>	#endif
447	>	#if (defined(i386) \|\| defined(__i386__))
448	>	#error "FIXME: need to decode instruction and compute EA"
449	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext *scp
450	>	#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp
451	>	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
452	>	#endif
453	>	#endif
454	>	#if defined(__FreeBSD__)
455	>	#if (defined(i386) \|\| defined(__i386__))
456	>	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
457	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, int code, struct sigcontext scp, char addr
458		#define SIGSEGV_FAULT_HANDLER_ARGS sig, code, scp, addr
459		#define SIGSEGV_FAULT_ADDRESS addr
460	<	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGBUS)
460	>	#define SIGSEGV_FAULT_INSTRUCTION scp->sc_eip
461	>	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&scp->sc_edi)
462	>	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
463		#endif
464	+	#if (defined(alpha) \|\| defined(__alpha__))
465	+	#define SIGSEGV_ALL_SIGNALS FAULT_HANDLER(SIGSEGV)
466	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST int sig, char addr, struct sigcontext scp
467	+	#define SIGSEGV_FAULT_HANDLER_ARGS sig, addr, scp
468	+	#define SIGSEGV_FAULT_ADDRESS addr
469	+	#define SIGSEGV_FAULT_INSTRUCTION scp->sc_pc
470	+	#endif
471	+	#endif
472	+
473	+	// Extract fault address out of a sigcontext
474	+	#if (defined(alpha) \|\| defined(__alpha__))
475	+	// From Boehm's GC 6.0alpha8
476	+	static sigsegv_address_t get_fault_address(struct sigcontext *scp)
477	+	{
478	+	unsigned int instruction = ((unsigned int )(scp->sc_pc));
479	+	unsigned long fault_address = scp->sc_regs[(instruction >> 16) & 0x1f];
480	+	fault_address += (signed long)(signed short)(instruction & 0xffff);
481	+	return (sigsegv_address_t)fault_address;
482	+	}
483		#endif
484
485	+
486		// MacOS X, not sure which version this works in. Under 10.1
487		// vm_protect does not appear to work from a signal handler. Under
488		// 10.2 signal handlers get siginfo type arguments but the si_addr
#	Line 408 \| Line 516 \| static sigsegv_address_t get_fault_addre
516		#endif
517		#endif
518
519	+	#if HAVE_WIN32_EXCEPTIONS
520	+	#define WIN32_LEAN_AND_MEAN /* avoid including junk */
521	+	#include <windows.h>
522	+	#include <winerror.h>
523	+
524	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST EXCEPTION_POINTERS *ExceptionInfo
525	+	#define SIGSEGV_FAULT_HANDLER_ARGS ExceptionInfo
526	+	#define SIGSEGV_FAULT_ADDRESS ExceptionInfo->ExceptionRecord->ExceptionInformation[1]
527	+	#define SIGSEGV_CONTEXT_REGS ExceptionInfo->ContextRecord
528	+	#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_CONTEXT_REGS->Eip
529	+	#define SIGSEGV_REGISTER_FILE ((unsigned long *)&SIGSEGV_CONTEXT_REGS->Edi)
530	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
531	+	#endif
532	+
533		#if HAVE_MACH_EXCEPTIONS
534
535		// This can easily be extended to other Mach systems, but really who
#	Line 468 \| Line 590 \| if (ret != KERN_SUCCESS) { \
590		exit (1); \
591		}
592
593	<	#define SIGSEGV_FAULT_ADDRESS code[1]
594	<	#define SIGSEGV_FAULT_INSTRUCTION get_fault_instruction(thread, state)
595	<	#define SIGSEGV_FAULT_HANDLER (code[0] == KERN_PROTECTION_FAILURE) && sigsegv_fault_handler
596	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code, ppc_thread_state_t *state
597	<	#define SIGSEGV_FAULT_HANDLER_ARGS thread, code, &state
593	>	#ifdef __ppc__
594	>	#define SIGSEGV_THREAD_STATE_TYPE ppc_thread_state_t
595	>	#define SIGSEGV_THREAD_STATE_FLAVOR PPC_THREAD_STATE
596	>	#define SIGSEGV_THREAD_STATE_COUNT PPC_THREAD_STATE_COUNT
597	>	#define SIGSEGV_FAULT_INSTRUCTION state->srr0
598		#define SIGSEGV_SKIP_INSTRUCTION powerpc_skip_instruction
599	<	#define SIGSEGV_REGISTER_FILE &state->srr0, &state->r0
478	<
479	<	// Given a suspended thread, stuff the current instruction and
480	<	// registers into state.
481	<	//
482	<	// It would have been nice to have this be ppc/x86 independant which
483	<	// could have been done easily with a thread_state_t instead of
484	<	// ppc_thread_state_t, but because of the way this is called it is
485	<	// easier to do it this way.
486	<	#if (defined(ppc) \|\| defined(__ppc__))
487	<	static inline sigsegv_address_t get_fault_instruction(mach_port_t thread, ppc_thread_state_t *state)
488	<	{
489	<	kern_return_t krc;
490	<	mach_msg_type_number_t count;
491	<
492	<	count = MACHINE_THREAD_STATE_COUNT;
493	<	krc = thread_get_state(thread, MACHINE_THREAD_STATE, (thread_state_t)state, &count);
494	<	MACH_CHECK_ERROR (thread_get_state, krc);
495	<
496	<	return (sigsegv_address_t)state->srr0;
497	<	}
599	>	#define SIGSEGV_REGISTER_FILE (unsigned long )&state->srr0, (unsigned long )&state->r0
600		#endif
601	+	#ifdef __i386__
602	+	#define SIGSEGV_THREAD_STATE_TYPE struct i386_saved_state
603	+	#define SIGSEGV_THREAD_STATE_FLAVOR i386_SAVED_STATE
604	+	#define SIGSEGV_THREAD_STATE_COUNT i386_SAVED_STATE_COUNT
605	+	#define SIGSEGV_FAULT_INSTRUCTION state->eip
606	+	#define SIGSEGV_SKIP_INSTRUCTION ix86_skip_instruction
607	+	#define SIGSEGV_REGISTER_FILE ((unsigned long )&state->edi) / EDI is the first GPR we consider */
608	+	#endif
609	+	#define SIGSEGV_FAULT_ADDRESS code[1]
610	+	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) ((code[0] == KERN_PROTECTION_FAILURE) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE)
611	+	#define SIGSEGV_FAULT_HANDLER_ARGLIST mach_port_t thread, exception_data_t code, SIGSEGV_THREAD_STATE_TYPE *state
612	+	#define SIGSEGV_FAULT_HANDLER_ARGS thread, code, &state
613
614		// Since there can only be one exception thread running at any time
615		// this is not a problem.
#	Line 550 \| Line 664 \| *handleExceptions(void priv)**
664
665		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
666		// Decode and skip X86 instruction
667	<	#if (defined(i386) \|\| defined(__i386__))
667	>	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
668		#if defined(__linux__)
669		enum {
670	+	#if (defined(i386) \|\| defined(__i386__))
671		X86_REG_EIP = 14,
672		X86_REG_EAX = 11,
673		X86_REG_ECX = 10,
#	Line 562 \| Line 677 \| enum {
677		X86_REG_EBP = 6,
678		X86_REG_ESI = 5,
679		X86_REG_EDI = 4
680	+	#endif
681	+	#if defined(__x86_64__)
682	+	X86_REG_R8 = 0,
683	+	X86_REG_R9 = 1,
684	+	X86_REG_R10 = 2,
685	+	X86_REG_R11 = 3,
686	+	X86_REG_R12 = 4,
687	+	X86_REG_R13 = 5,
688	+	X86_REG_R14 = 6,
689	+	X86_REG_R15 = 7,
690	+	X86_REG_EDI = 8,
691	+	X86_REG_ESI = 9,
692	+	X86_REG_EBP = 10,
693	+	X86_REG_EBX = 11,
694	+	X86_REG_EDX = 12,
695	+	X86_REG_EAX = 13,
696	+	X86_REG_ECX = 14,
697	+	X86_REG_ESP = 15,
698	+	X86_REG_EIP = 16
699	+	#endif
700	+	};
701	+	#endif
702	+	#if defined(__NetBSD__)
703	+	enum {
704	+	#if (defined(i386) \|\| defined(__i386__))
705	+	X86_REG_EIP = _REG_EIP,
706	+	X86_REG_EAX = _REG_EAX,
707	+	X86_REG_ECX = _REG_ECX,
708	+	X86_REG_EDX = _REG_EDX,
709	+	X86_REG_EBX = _REG_EBX,
710	+	X86_REG_ESP = _REG_ESP,
711	+	X86_REG_EBP = _REG_EBP,
712	+	X86_REG_ESI = _REG_ESI,
713	+	X86_REG_EDI = _REG_EDI
714	+	#endif
715		};
716		#endif
717	<	#if defined(__NetBSD__) \|\| defined(__FreeBSD__)
717	>	#if defined(__FreeBSD__)
718		enum {
719	+	#if (defined(i386) \|\| defined(__i386__))
720		X86_REG_EIP = 10,
721		X86_REG_EAX = 7,
722		X86_REG_ECX = 6,
#	Line 575 \| Line 726 \| enum {
726		X86_REG_EBP = 2,
727		X86_REG_ESI = 1,
728		X86_REG_EDI = 0
729	+	#endif
730	+	};
731	+	#endif
732	+	#if defined(__OpenBSD__)
733	+	enum {
734	+	#if defined(__i386__)
735	+	// EDI is the first register we consider
736	+	#define OREG(REG) offsetof(struct sigcontext, sc_##REG)
737	+	#define DREG(REG) ((OREG(REG) - OREG(edi)) / 4)
738	+	X86_REG_EIP = DREG(eip), // 7
739	+	X86_REG_EAX = DREG(eax), // 6
740	+	X86_REG_ECX = DREG(ecx), // 5
741	+	X86_REG_EDX = DREG(edx), // 4
742	+	X86_REG_EBX = DREG(ebx), // 3
743	+	X86_REG_ESP = DREG(esp), // 10
744	+	X86_REG_EBP = DREG(ebp), // 2
745	+	X86_REG_ESI = DREG(esi), // 1
746	+	X86_REG_EDI = DREG(edi) // 0
747	+	#undef DREG
748	+	#undef OREG
749	+	#endif
750	+	};
751	+	#endif
752	+	#if defined(__sun__)
753	+	// Same as for Linux, need to check for x86-64
754	+	enum {
755	+	#if defined(__i386__)
756	+	X86_REG_EIP = EIP,
757	+	X86_REG_EAX = EAX,
758	+	X86_REG_ECX = ECX,
759	+	X86_REG_EDX = EDX,
760	+	X86_REG_EBX = EBX,
761	+	X86_REG_ESP = ESP,
762	+	X86_REG_EBP = EBP,
763	+	X86_REG_ESI = ESI,
764	+	X86_REG_EDI = EDI
765	+	#endif
766	+	};
767	+	#endif
768	+	#if defined(__APPLE__) && defined(__MACH__)
769	+	// expected to be the same as FreeBSD
770	+	enum {
771	+	X86_REG_EIP = 10,
772	+	X86_REG_EAX = 7,
773	+	X86_REG_ECX = 6,
774	+	X86_REG_EDX = 5,
775	+	X86_REG_EBX = 4,
776	+	X86_REG_ESP = 13,
777	+	X86_REG_EBP = 2,
778	+	X86_REG_ESI = 1,
779	+	X86_REG_EDI = 0
780	+	};
781	+	#endif
782	+	#if defined(_WIN32)
783	+	enum {
784	+	#if (defined(i386) \|\| defined(__i386__))
785	+	X86_REG_EIP = 7,
786	+	X86_REG_EAX = 5,
787	+	X86_REG_ECX = 4,
788	+	X86_REG_EDX = 3,
789	+	X86_REG_EBX = 2,
790	+	X86_REG_ESP = 10,
791	+	X86_REG_EBP = 6,
792	+	X86_REG_ESI = 1,
793	+	X86_REG_EDI = 0
794	+	#endif
795		};
796		#endif
797		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 611 \| Line 828 \| static inline int ix86_step_over_modrm(u
828		return offset;
829		}
830
831	<	static bool ix86_skip_instruction(unsigned int * regs)
831	>	static bool ix86_skip_instruction(unsigned long * regs)
832		{
833		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
834
835		if (eip == 0)
836		return false;
837	+	#ifdef _WIN32
838	+	if (IsBadCodePtr((FARPROC)eip))
839	+	return false;
840	+	#endif
841
842		transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
843		transfer_size_t transfer_size = SIZE_LONG;
844
845		int reg = -1;
846		int len = 0;
847	<
847	>
848	>	#if DEBUG
849	>	printf("IP: %p [%02x %02x %02x %02x...]\n",
850	>	eip, eip[0], eip[1], eip[2], eip[3]);
851	>	#endif
852	>
853		// Operand size prefix
854		if (*eip == 0x66) {
855		eip++;
#	Line 631 \| Line 857 \| static bool ix86_skip_instruction(unsign
857		transfer_size = SIZE_WORD;
858		}
859
860	+	// REX prefix
861	+	#if defined(__x86_64__)
862	+	struct rex_t {
863	+	unsigned char W;
864	+	unsigned char R;
865	+	unsigned char X;
866	+	unsigned char B;
867	+	};
868	+	rex_t rex = { 0, 0, 0, 0 };
869	+	bool has_rex = false;
870	+	if ((*eip & 0xf0) == 0x40) {
871	+	has_rex = true;
872	+	const unsigned char b = *eip;
873	+	rex.W = b & (1 << 3);
874	+	rex.R = b & (1 << 2);
875	+	rex.X = b & (1 << 1);
876	+	rex.B = b & (1 << 0);
877	+	#if DEBUG
878	+	printf("REX: %c,%c,%c,%c\n",
879	+	rex.W ? 'W' : '_',
880	+	rex.R ? 'R' : '_',
881	+	rex.X ? 'X' : '_',
882	+	rex.B ? 'B' : '_');
883	+	#endif
884	+	eip++;
885	+	len++;
886	+	if (rex.W)
887	+	transfer_size = SIZE_QUAD;
888	+	}
889	+	#else
890	+	const bool has_rex = false;
891	+	#endif
892	+
893		// Decode instruction
894	+	int target_size = SIZE_UNKNOWN;
895		switch (eip[0]) {
896		case 0x0f:
897	+	target_size = transfer_size;
898		switch (eip[1]) {
899	+	case 0xbe: // MOVSX r32, r/m8
900		case 0xb6: // MOVZX r32, r/m8
901	+	transfer_size = SIZE_BYTE;
902	+	goto do_mov_extend;
903	+	case 0xbf: // MOVSX r32, r/m16
904		case 0xb7: // MOVZX r32, r/m16
905	<	switch (eip[2] & 0xc0) {
906	<	case 0x80:
907	<	reg = (eip[2] >> 3) & 7;
908	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
909	<	break;
910	<	case 0x40:
911	<	reg = (eip[2] >> 3) & 7;
912	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
913	<	break;
914	<	case 0x00:
915	<	reg = (eip[2] >> 3) & 7;
916	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
917	<	break;
918	<	}
919	<	len += 3 + ix86_step_over_modrm(eip + 2);
920	<	break;
905	>	transfer_size = SIZE_WORD;
906	>	goto do_mov_extend;
907	>	do_mov_extend:
908	>	switch (eip[2] & 0xc0) {
909	>	case 0x80:
910	>	reg = (eip[2] >> 3) & 7;
911	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
912	>	break;
913	>	case 0x40:
914	>	reg = (eip[2] >> 3) & 7;
915	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
916	>	break;
917	>	case 0x00:
918	>	reg = (eip[2] >> 3) & 7;
919	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
920	>	break;
921	>	}
922	>	len += 3 + ix86_step_over_modrm(eip + 2);
923	>	break;
924		}
925		break;
926		case 0x8a: // MOV r8, r/m8
#	Line 694 \| Line 962 \| static bool ix86_skip_instruction(unsign
962		len += 2 + ix86_step_over_modrm(eip + 1);
963		break;
964		}
965	+	if (target_size == SIZE_UNKNOWN)
966	+	target_size = transfer_size;
967
968		if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
969		// Unknown machine code, let it crash. Then patch the decoder
970		return false;
971		}
972
973	+	#if defined(__x86_64__)
974	+	if (rex.R)
975	+	reg += 8;
976	+	#endif
977	+
978		if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
979	<	static const int x86_reg_map[8] = {
979	>	static const int x86_reg_map[] = {
980		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
981	<	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI
981	>	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
982	>	#if defined(__x86_64__)
983	>	X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11,
984	>	X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
985	>	#endif
986		};
987
988	<	if (reg < 0 \|\| reg >= 8)
988	>	if (reg < 0 \|\| reg >= (sizeof(x86_reg_map)/sizeof(x86_reg_map[0]) - 1))
989		return false;
990
991	+	// Set 0 to the relevant register part
992	+	// NOTE: this is only valid for MOV alike instructions
993		int rloc = x86_reg_map[reg];
994	<	switch (transfer_size) {
994	>	switch (target_size) {
995		case SIZE_BYTE:
996	<	regs[rloc] = (regs[rloc] & ~0xff);
996	>	if (has_rex \|\| reg < 4)
997	>	regs[rloc] = (regs[rloc] & ~0x00ffL);
998	>	else {
999	>	rloc = x86_reg_map[reg - 4];
1000	>	regs[rloc] = (regs[rloc] & ~0xff00L);
1001	>	}
1002		break;
1003		case SIZE_WORD:
1004	<	regs[rloc] = (regs[rloc] & ~0xffff);
1004	>	regs[rloc] = (regs[rloc] & ~0xffffL);
1005		break;
1006		case SIZE_LONG:
1007	+	case SIZE_QUAD: // zero-extension
1008		regs[rloc] = 0;
1009		break;
1010		}
#	Line 725 \| Line 1012 \| static bool ix86_skip_instruction(unsign
1012
1013		#if DEBUG
1014		printf("%08x: %s %s access", regs[X86_REG_EIP],
1015	<	transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : "long",
1015	>	transfer_size == SIZE_BYTE ? "byte" :
1016	>	transfer_size == SIZE_WORD ? "word" :
1017	>	transfer_size == SIZE_LONG ? "long" :
1018	>	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1019		transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1020
1021		if (reg != -1) {
1022	<	static const char * x86_reg_str_map[8] = {
1023	<	"eax", "ecx", "edx", "ebx",
1024	<	"esp", "ebp", "esi", "edi"
1022	>	static const char * x86_byte_reg_str_map[] = {
1023	>	"al", "cl", "dl", "bl",
1024	>	"spl", "bpl", "sil", "dil",
1025	>	"r8b", "r9b", "r10b", "r11b",
1026	>	"r12b", "r13b", "r14b", "r15b",
1027	>	"ah", "ch", "dh", "bh",
1028	>	};
1029	>	static const char * x86_word_reg_str_map[] = {
1030	>	"ax", "cx", "dx", "bx",
1031	>	"sp", "bp", "si", "di",
1032	>	"r8w", "r9w", "r10w", "r11w",
1033	>	"r12w", "r13w", "r14w", "r15w",
1034	>	};
1035	>	static const char *x86_long_reg_str_map[] = {
1036	>	"eax", "ecx", "edx", "ebx",
1037	>	"esp", "ebp", "esi", "edi",
1038	>	"r8d", "r9d", "r10d", "r11d",
1039	>	"r12d", "r13d", "r14d", "r15d",
1040		};
1041	<	printf(" %s register %%%s", transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from", x86_reg_str_map[reg]);
1041	>	static const char *x86_quad_reg_str_map[] = {
1042	>	"rax", "rcx", "rdx", "rbx",
1043	>	"rsp", "rbp", "rsi", "rdi",
1044	>	"r8", "r9", "r10", "r11",
1045	>	"r12", "r13", "r14", "r15",
1046	>	};
1047	>	const char * reg_str = NULL;
1048	>	switch (target_size) {
1049	>	case SIZE_BYTE:
1050	>	reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
1051	>	break;
1052	>	case SIZE_WORD: reg_str = x86_word_reg_str_map[reg]; break;
1053	>	case SIZE_LONG: reg_str = x86_long_reg_str_map[reg]; break;
1054	>	case SIZE_QUAD: reg_str = x86_quad_reg_str_map[reg]; break;
1055	>	}
1056	>	if (reg_str)
1057	>	printf(" %s register %%%s",
1058	>	transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from",
1059	>	reg_str);
1060		}
1061		printf(", %d bytes instruction\n", len);
1062		#endif
#	Line 745 \| Line 1068 \| static bool ix86_skip_instruction(unsign
1068
1069		// Decode and skip PPC instruction
1070		#if (defined(powerpc) \|\| defined(__powerpc__) \|\| defined(__ppc__))
1071	<	static bool powerpc_skip_instruction(unsigned int * nip_p, unsigned int * regs)
1071	>	static bool powerpc_skip_instruction(unsigned long * nip_p, unsigned long * regs)
1072		{
1073		instruction_t instr;
1074		powerpc_decode_instruction(&instr, *nip_p, regs);
#	Line 757 \| Line 1080 \| static bool powerpc_skip_instruction(uns
1080
1081		#if DEBUG
1082		printf("%08x: %s %s access", *nip_p,
1083	<	instr.transfer_size == SIZE_BYTE ? "byte" : instr.transfer_size == SIZE_WORD ? "word" : "long",
1083	>	instr.transfer_size == SIZE_BYTE ? "byte" :
1084	>	instr.transfer_size == SIZE_WORD ? "word" :
1085	>	instr.transfer_size == SIZE_LONG ? "long" : "quad",
1086		instr.transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
1087
1088		if (instr.addr_mode == MODE_U \|\| instr.addr_mode == MODE_UX)
#	Line 775 \| Line 1100 \| static bool powerpc_skip_instruction(uns
1100		return true;
1101		}
1102		#endif
1103	+
1104	+	// Decode and skip MIPS instruction
1105	+	#if (defined(mips) \|\| defined(__mips))
1106	+	enum {
1107	+	#if (defined(sgi) \|\| defined(__sgi))
1108	+	MIPS_REG_EPC = 35,
1109	+	#endif
1110	+	};
1111	+	static bool mips_skip_instruction(greg_t * regs)
1112	+	{
1113	+	unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC];
1114	+
1115	+	if (epc == 0)
1116	+	return false;
1117	+
1118	+	#if DEBUG
1119	+	printf("IP: %p [%08x]\n", epc, epc[0]);
1120	+	#endif
1121	+
1122	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1123	+	transfer_size_t transfer_size = SIZE_LONG;
1124	+	int direction = 0;
1125	+
1126	+	const unsigned int opcode = epc[0];
1127	+	switch (opcode >> 26) {
1128	+	case 32: // Load Byte
1129	+	case 36: // Load Byte Unsigned
1130	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1131	+	transfer_size = SIZE_BYTE;
1132	+	break;
1133	+	case 33: // Load Halfword
1134	+	case 37: // Load Halfword Unsigned
1135	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1136	+	transfer_size = SIZE_WORD;
1137	+	break;
1138	+	case 35: // Load Word
1139	+	case 39: // Load Word Unsigned
1140	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1141	+	transfer_size = SIZE_LONG;
1142	+	break;
1143	+	case 34: // Load Word Left
1144	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1145	+	transfer_size = SIZE_LONG;
1146	+	direction = -1;
1147	+	break;
1148	+	case 38: // Load Word Right
1149	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1150	+	transfer_size = SIZE_LONG;
1151	+	direction = 1;
1152	+	break;
1153	+	case 55: // Load Doubleword
1154	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1155	+	transfer_size = SIZE_QUAD;
1156	+	break;
1157	+	case 26: // Load Doubleword Left
1158	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1159	+	transfer_size = SIZE_QUAD;
1160	+	direction = -1;
1161	+	break;
1162	+	case 27: // Load Doubleword Right
1163	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1164	+	transfer_size = SIZE_QUAD;
1165	+	direction = 1;
1166	+	break;
1167	+	case 40: // Store Byte
1168	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1169	+	transfer_size = SIZE_BYTE;
1170	+	break;
1171	+	case 41: // Store Halfword
1172	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1173	+	transfer_size = SIZE_WORD;
1174	+	break;
1175	+	case 43: // Store Word
1176	+	case 42: // Store Word Left
1177	+	case 46: // Store Word Right
1178	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1179	+	transfer_size = SIZE_LONG;
1180	+	break;
1181	+	case 63: // Store Doubleword
1182	+	case 44: // Store Doubleword Left
1183	+	case 45: // Store Doubleword Right
1184	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1185	+	transfer_size = SIZE_QUAD;
1186	+	break;
1187	+	/* Misc instructions unlikely to be used within CPU emulators */
1188	+	case 48: // Load Linked Word
1189	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1190	+	transfer_size = SIZE_LONG;
1191	+	break;
1192	+	case 52: // Load Linked Doubleword
1193	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1194	+	transfer_size = SIZE_QUAD;
1195	+	break;
1196	+	case 56: // Store Conditional Word
1197	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1198	+	transfer_size = SIZE_LONG;
1199	+	break;
1200	+	case 60: // Store Conditional Doubleword
1201	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1202	+	transfer_size = SIZE_QUAD;
1203	+	break;
1204	+	}
1205	+
1206	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1207	+	// Unknown machine code, let it crash. Then patch the decoder
1208	+	return false;
1209	+	}
1210	+
1211	+	// Zero target register in case of a load operation
1212	+	const int reg = (opcode >> 16) & 0x1f;
1213	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD) {
1214	+	if (direction == 0)
1215	+	regs[reg] = 0;
1216	+	else {
1217	+	// FIXME: untested code
1218	+	unsigned long ea = regs[(opcode >> 21) & 0x1f];
1219	+	ea += (signed long)(signed int)(signed short)(opcode & 0xffff);
1220	+	const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7);
1221	+	unsigned long value;
1222	+	if (direction > 0) {
1223	+	const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1);
1224	+	value = regs[reg] & rmask;
1225	+	}
1226	+	else {
1227	+	const unsigned long lmask = (1L << (offset * 8)) - 1;
1228	+	value = regs[reg] & lmask;
1229	+	}
1230	+	// restore most significant bits
1231	+	if (transfer_size == SIZE_LONG)
1232	+	value = (signed long)(signed int)value;
1233	+	regs[reg] = value;
1234	+	}
1235	+	}
1236	+
1237	+	#if DEBUG
1238	+	#if (defined(_ABIN32) \|\| defined(_ABI64))
1239	+	static const char * mips_gpr_names[32] = {
1240	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1241	+	"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1242	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1243	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1244	+	};
1245	+	#else
1246	+	static const char * mips_gpr_names[32] = {
1247	+	"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1248	+	"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
1249	+	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1250	+	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
1251	+	};
1252	+	#endif
1253	+	printf("%s %s register %s\n",
1254	+	transfer_size == SIZE_BYTE ? "byte" :
1255	+	transfer_size == SIZE_WORD ? "word" :
1256	+	transfer_size == SIZE_LONG ? "long" :
1257	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1258	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1259	+	mips_gpr_names[reg]);
1260		#endif
1261
1262	+	regs[MIPS_REG_EPC] += 4;
1263	+	return true;
1264	+	}
1265	+	#endif
1266	+
1267	+	// Decode and skip SPARC instruction
1268	+	#if (defined(sparc) \|\| defined(__sparc__))
1269	+	enum {
1270	+	#if (defined(__sun__))
1271	+	SPARC_REG_G1 = REG_G1,
1272	+	SPARC_REG_O0 = REG_O0,
1273	+	SPARC_REG_PC = REG_PC,
1274	+	#endif
1275	+	};
1276	+	static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
1277	+	{
1278	+	unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
1279	+
1280	+	if (pc == 0)
1281	+	return false;
1282	+
1283	+	#if DEBUG
1284	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1285	+	#endif
1286	+
1287	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1288	+	transfer_size_t transfer_size = SIZE_LONG;
1289	+	bool register_pair = false;
1290	+
1291	+	const unsigned int opcode = pc[0];
1292	+	if ((opcode >> 30) != 3)
1293	+	return false;
1294	+	switch ((opcode >> 19) & 0x3f) {
1295	+	case 9: // Load Signed Byte
1296	+	case 1: // Load Unsigned Byte
1297	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1298	+	transfer_size = SIZE_BYTE;
1299	+	break;
1300	+	case 10:// Load Signed Halfword
1301	+	case 2: // Load Unsigned Word
1302	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1303	+	transfer_size = SIZE_WORD;
1304	+	break;
1305	+	case 8: // Load Word
1306	+	case 0: // Load Unsigned Word
1307	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1308	+	transfer_size = SIZE_LONG;
1309	+	break;
1310	+	case 11:// Load Extended Word
1311	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1312	+	transfer_size = SIZE_QUAD;
1313	+	break;
1314	+	case 3: // Load Doubleword
1315	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1316	+	transfer_size = SIZE_LONG;
1317	+	register_pair = true;
1318	+	break;
1319	+	case 5: // Store Byte
1320	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1321	+	transfer_size = SIZE_BYTE;
1322	+	break;
1323	+	case 6: // Store Halfword
1324	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1325	+	transfer_size = SIZE_WORD;
1326	+	break;
1327	+	case 4: // Store Word
1328	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1329	+	transfer_size = SIZE_LONG;
1330	+	break;
1331	+	case 14:// Store Extended Word
1332	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1333	+	transfer_size = SIZE_QUAD;
1334	+	break;
1335	+	case 7: // Store Doubleword
1336	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1337	+	transfer_size = SIZE_WORD;
1338	+	register_pair = true;
1339	+	break;
1340	+	}
1341	+
1342	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1343	+	// Unknown machine code, let it crash. Then patch the decoder
1344	+	return false;
1345	+	}
1346	+
1347	+	// Zero target register in case of a load operation
1348	+	const int reg = (opcode >> 25) & 0x1f;
1349	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1350	+	// FIXME: code to handle local & input registers is not tested
1351	+	if (reg >= 1 && reg <= 7) {
1352	+	// global registers
1353	+	regs[reg - 1 + SPARC_REG_G1] = 0;
1354	+	}
1355	+	else if (reg >= 8 && reg <= 15) {
1356	+	// output registers
1357	+	regs[reg - 8 + SPARC_REG_O0] = 0;
1358	+	}
1359	+	else if (reg >= 16 && reg <= 23) {
1360	+	// local registers (in register windows)
1361	+	if (gwins)
1362	+	gwins->wbuf->rw_local[reg - 16] = 0;
1363	+	else
1364	+	rwin->rw_local[reg - 16] = 0;
1365	+	}
1366	+	else {
1367	+	// input registers (in register windows)
1368	+	if (gwins)
1369	+	gwins->wbuf->rw_in[reg - 24] = 0;
1370	+	else
1371	+	rwin->rw_in[reg - 24] = 0;
1372	+	}
1373	+	}
1374	+
1375	+	#if DEBUG
1376	+	static const char * reg_names[] = {
1377	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1378	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1379	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1380	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1381	+	};
1382	+	printf("%s %s register %s\n",
1383	+	transfer_size == SIZE_BYTE ? "byte" :
1384	+	transfer_size == SIZE_WORD ? "word" :
1385	+	transfer_size == SIZE_LONG ? "long" :
1386	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1387	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1388	+	reg_names[reg]);
1389	+	#endif
1390	+
1391	+	regs[SPARC_REG_PC] += 4;
1392	+	return true;
1393	+	}
1394	+	#endif
1395	+	#endif
1396	+
1397	+	// Decode and skip ARM instruction
1398	+	#if (defined(arm) \|\| defined(__arm__))
1399	+	enum {
1400	+	#if (defined(__linux__))
1401	+	ARM_REG_PC = 15,
1402	+	ARM_REG_CPSR = 16
1403	+	#endif
1404	+	};
1405	+	static bool arm_skip_instruction(unsigned long * regs)
1406	+	{
1407	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
1408	+
1409	+	if (pc == 0)
1410	+	return false;
1411	+
1412	+	#if DEBUG
1413	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1414	+	#endif
1415	+
1416	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1417	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1418	+	enum { op_sdt = 1, op_sdth = 2 };
1419	+	int op = 0;
1420	+
1421	+	// Handle load/store instructions only
1422	+	const unsigned int opcode = pc[0];
1423	+	switch ((opcode >> 25) & 7) {
1424	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
1425	+	op = op_sdth;
1426	+	// Determine transfer size (S/H bits)
1427	+	switch ((opcode >> 5) & 3) {
1428	+	case 0: // SWP instruction
1429	+	break;
1430	+	case 1: // Unsigned halfwords
1431	+	case 3: // Signed halfwords
1432	+	transfer_size = SIZE_WORD;
1433	+	break;
1434	+	case 2: // Signed byte
1435	+	transfer_size = SIZE_BYTE;
1436	+	break;
1437	+	}
1438	+	break;
1439	+	case 2:
1440	+	case 3: // Single Data Transfer (LDR, STR)
1441	+	op = op_sdt;
1442	+	// Determine transfer size (B bit)
1443	+	if (((opcode >> 22) & 1) == 1)
1444	+	transfer_size = SIZE_BYTE;
1445	+	else
1446	+	transfer_size = SIZE_LONG;
1447	+	break;
1448	+	default:
1449	+	// FIXME: support load/store mutliple?
1450	+	return false;
1451	+	}
1452	+
1453	+	// Check for invalid transfer size (SWP instruction?)
1454	+	if (transfer_size == SIZE_UNKNOWN)
1455	+	return false;
1456	+
1457	+	// Determine transfer type (L bit)
1458	+	if (((opcode >> 20) & 1) == 1)
1459	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1460	+	else
1461	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1462	+
1463	+	// Compute offset
1464	+	int offset;
1465	+	if (((opcode >> 25) & 1) == 0) {
1466	+	if (op == op_sdt)
1467	+	offset = opcode & 0xfff;
1468	+	else if (op == op_sdth) {
1469	+	int rm = opcode & 0xf;
1470	+	if (((opcode >> 22) & 1) == 0) {
1471	+	// register offset
1472	+	offset = regs[rm];
1473	+	}
1474	+	else {
1475	+	// immediate offset
1476	+	offset = ((opcode >> 4) & 0xf0) \| (opcode & 0x0f);
1477	+	}
1478	+	}
1479	+	}
1480	+	else {
1481	+	const int rm = opcode & 0xf;
1482	+	const int sh = (opcode >> 7) & 0x1f;
1483	+	if (((opcode >> 4) & 1) == 1) {
1484	+	// we expect only legal load/store instructions
1485	+	printf("FATAL: invalid shift operand\n");
1486	+	return false;
1487	+	}
1488	+	const unsigned int v = regs[rm];
1489	+	switch ((opcode >> 5) & 3) {
1490	+	case 0: // logical shift left
1491	+	offset = sh ? v << sh : v;
1492	+	break;
1493	+	case 1: // logical shift right
1494	+	offset = sh ? v >> sh : 0;
1495	+	break;
1496	+	case 2: // arithmetic shift right
1497	+	if (sh)
1498	+	offset = ((signed int)v) >> sh;
1499	+	else
1500	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
1501	+	break;
1502	+	case 3: // rotate right
1503	+	if (sh)
1504	+	offset = (v >> sh) \| (v << (32 - sh));
1505	+	else
1506	+	offset = (v >> 1) \| ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
1507	+	break;
1508	+	}
1509	+	}
1510	+	if (((opcode >> 23) & 1) == 0)
1511	+	offset = -offset;
1512	+
1513	+	int rd = (opcode >> 12) & 0xf;
1514	+	int rn = (opcode >> 16) & 0xf;
1515	+	#if DEBUG
1516	+	static const char * reg_names[] = {
1517	+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1518	+	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
1519	+	};
1520	+	printf("%s %s register %s\n",
1521	+	transfer_size == SIZE_BYTE ? "byte" :
1522	+	transfer_size == SIZE_WORD ? "word" :
1523	+	transfer_size == SIZE_LONG ? "long" : "unknown",
1524	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1525	+	reg_names[rd]);
1526	+	#endif
1527	+
1528	+	unsigned int base = regs[rn];
1529	+	if (((opcode >> 24) & 1) == 1)
1530	+	base += offset;
1531	+
1532	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
1533	+	regs[rd] = 0;
1534	+
1535	+	if (((opcode >> 24) & 1) == 0) // post-index addressing
1536	+	regs[rn] += offset;
1537	+	else if (((opcode >> 21) & 1) == 1) // write-back address into base
1538	+	regs[rn] = base;
1539	+
1540	+	regs[ARM_REG_PC] += 4;
1541	+	return true;
1542	+	}
1543	+	#endif
1544	+
1545	+
1546		// Fallbacks
1547		#ifndef SIGSEGV_FAULT_INSTRUCTION
1548		#define SIGSEGV_FAULT_INSTRUCTION SIGSEGV_INVALID_PC
#	Line 784 \| Line 1550 \| static bool powerpc_skip_instruction(uns
1550		#ifndef SIGSEGV_FAULT_HANDLER_ARGLIST_1
1551		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 SIGSEGV_FAULT_HANDLER_ARGLIST
1552		#endif
1553	+	#ifndef SIGSEGV_FAULT_HANDLER_INVOKE
1554	+	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP) sigsegv_fault_handler(ADDR, IP)
1555	+	#endif
1556
1557		// SIGSEGV recovery supported ?
1558		#if defined(SIGSEGV_ALL_SIGNALS) && defined(SIGSEGV_FAULT_HANDLER_ARGLIST) && defined(SIGSEGV_FAULT_ADDRESS)
#	Line 795 \| Line 1564 \| static bool powerpc_skip_instruction(uns
1564		* SIGSEGV global handler
1565		*/
1566
798	–	#if defined(HAVE_SIGSEGV_RECOVERY) \|\| defined(HAVE_MACH_EXCEPTIONS)
1567		// This function handles the badaccess to memory.
1568		// It is called from the signal handler or the exception handler.
1569		static bool handle_badaccess(SIGSEGV_FAULT_HANDLER_ARGLIST_1)
1570		{
1571	+	#ifdef HAVE_MACH_EXCEPTIONS
1572	+	// We must match the initial count when writing back the CPU state registers
1573	+	kern_return_t krc;
1574	+	mach_msg_type_number_t count;
1575	+
1576	+	count = SIGSEGV_THREAD_STATE_COUNT;
1577	+	krc = thread_get_state(thread, SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state, &count);
1578	+	MACH_CHECK_ERROR (thread_get_state, krc);
1579	+	#endif
1580	+
1581		sigsegv_address_t fault_address = (sigsegv_address_t)SIGSEGV_FAULT_ADDRESS;
1582		sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
1583
1584		// Call user's handler and reinstall the global handler, if required
1585	<	switch (sigsegv_fault_handler(fault_address, fault_instruction)) {
1585	>	switch (SIGSEGV_FAULT_HANDLER_INVOKE(fault_address, fault_instruction)) {
1586		case SIGSEGV_RETURN_SUCCESS:
1587		return true;
1588
#	Line 818 \| Line 1596 \| static bool handle_badaccess(SIGSEGV_FAU
1596		// is modified off of the stack, in Mach we
1597		// need to actually call thread_set_state to
1598		// have the register values updated.
821	–	kern_return_t krc;
822	–
1599		krc = thread_set_state(thread,
1600	<	MACHINE_THREAD_STATE, (thread_state_t)state,
1601	<	MACHINE_THREAD_STATE_COUNT);
1602	<	MACH_CHECK_ERROR (thread_get_state, krc);
1600	>	SIGSEGV_THREAD_STATE_FLAVOR, (thread_state_t)state,
1601	>	count);
1602	>	MACH_CHECK_ERROR (thread_set_state, krc);
1603		#endif
1604		return true;
1605		}
1606		break;
1607		#endif
1608	+	case SIGSEGV_RETURN_FAILURE:
1609	+	// We can't do anything with the fault_address, dump state?
1610	+	if (sigsegv_state_dumper != 0)
1611	+	sigsegv_state_dumper(fault_address, fault_instruction);
1612	+	break;
1613		}
833	–
834	–	// We can't do anything with the fault_address, dump state?
835	–	if (sigsegv_state_dumper != 0)
836	–	sigsegv_state_dumper(fault_address, fault_instruction);
1614
1615		return false;
1616		}
840	–	#endif
1617
1618
1619		/*
#	Line 969 \| Line 1745 \| catch_exception_raise(mach_port_t except
1745		exception_data_t code,
1746		mach_msg_type_number_t codeCount)
1747		{
1748	<	ppc_thread_state_t state;
1748	>	SIGSEGV_THREAD_STATE_TYPE state;
1749		kern_return_t krc;
1750
1751		if ((exception == EXC_BAD_ACCESS) && (codeCount >= 2)) {
#	Line 1108 \| Line 1884 \| static bool sigsegv_do_install_handler(s
1884		// addressing modes) used in PPC instructions, you will need the
1885		// GPR state anyway.
1886		krc = thread_set_exception_ports(mach_thread_self(), EXC_MASK_BAD_ACCESS, _exceptionPort,
1887	<	EXCEPTION_DEFAULT, MACHINE_THREAD_STATE);
1887	>	EXCEPTION_DEFAULT, SIGSEGV_THREAD_STATE_FLAVOR);
1888		if (krc != KERN_SUCCESS) {
1889		mach_error("thread_set_exception_ports", krc);
1890		return false;
#	Line 1131 \| Line 1907 \| static bool sigsegv_do_install_handler(s
1907		}
1908		#endif
1909
1910	+	#ifdef HAVE_WIN32_EXCEPTIONS
1911	+	static LONG WINAPI main_exception_filter(EXCEPTION_POINTERS *ExceptionInfo)
1912	+	{
1913	+	if (sigsegv_fault_handler != NULL
1914	+	&& ExceptionInfo->ExceptionRecord->ExceptionCode == EXCEPTION_ACCESS_VIOLATION
1915	+	&& ExceptionInfo->ExceptionRecord->NumberParameters == 2
1916	+	&& handle_badaccess(ExceptionInfo))
1917	+	return EXCEPTION_CONTINUE_EXECUTION;
1918	+
1919	+	return EXCEPTION_CONTINUE_SEARCH;
1920	+	}
1921	+
1922	+	#if defined __CYGWIN__ && defined __i386__
1923	+	/* In Cygwin programs, SetUnhandledExceptionFilter has no effect because Cygwin
1924	+	installs a global exception handler. We have to dig deep in order to install
1925	+	our main_exception_filter. */
1926	+
1927	+	/* Data structures for the current thread's exception handler chain.
1928	+	On the x86 Windows uses register fs, offset 0 to point to the current
1929	+	exception handler; Cygwin mucks with it, so we must do the same... :-/ */
1930	+
1931	+	/* Magic taken from winsup/cygwin/include/exceptions.h. */
1932	+
1933	+	struct exception_list {
1934	+	struct exception_list *prev;
1935	+	int (handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
1936	+	};
1937	+	typedef struct exception_list exception_list;
1938	+
1939	+	/* Magic taken from winsup/cygwin/exceptions.cc. */
1940	+
1941	+	__asm__ (".equ __except_list,0");
1942	+
1943	+	extern exception_list *_except_list __asm__ ("%fs:__except_list");
1944	+
1945	+	/* For debugging. _except_list is not otherwise accessible from gdb. */
1946	+	static exception_list *
1947	+	debug_get_except_list ()
1948	+	{
1949	+	return _except_list;
1950	+	}
1951	+
1952	+	/* Cygwin's original exception handler. */
1953	+	static int (cygwin_exception_handler) (EXCEPTION_RECORD , void , CONTEXT , void *);
1954	+
1955	+	/* Our exception handler. */
1956	+	static int
1957	+	libsigsegv_exception_handler (EXCEPTION_RECORD exception, void frame, CONTEXT context, void dispatch)
1958	+	{
1959	+	EXCEPTION_POINTERS ExceptionInfo;
1960	+	ExceptionInfo.ExceptionRecord = exception;
1961	+	ExceptionInfo.ContextRecord = context;
1962	+	if (main_exception_filter (&ExceptionInfo) == EXCEPTION_CONTINUE_SEARCH)
1963	+	return cygwin_exception_handler (exception, frame, context, dispatch);
1964	+	else
1965	+	return 0;
1966	+	}
1967	+
1968	+	static void
1969	+	do_install_main_exception_filter ()
1970	+	{
1971	+	/* We cannot insert any handler into the chain, because such handlers
1972	+	must lie on the stack (?). Instead, we have to replace(!) Cygwin's
1973	+	global exception handler. */
1974	+	cygwin_exception_handler = _except_list->handler;
1975	+	_except_list->handler = libsigsegv_exception_handler;
1976	+	}
1977	+
1978	+	#else
1979	+
1980	+	static void
1981	+	do_install_main_exception_filter ()
1982	+	{
1983	+	SetUnhandledExceptionFilter ((LPTOP_LEVEL_EXCEPTION_FILTER) &main_exception_filter);
1984	+	}
1985	+	#endif
1986	+
1987	+	static bool sigsegv_do_install_handler(sigsegv_fault_handler_t handler)
1988	+	{
1989	+	static bool main_exception_filter_installed = false;
1990	+	if (!main_exception_filter_installed) {
1991	+	do_install_main_exception_filter();
1992	+	main_exception_filter_installed = true;
1993	+	}
1994	+	sigsegv_fault_handler = handler;
1995	+	return true;
1996	+	}
1997	+	#endif
1998	+
1999		bool sigsegv_install_handler(sigsegv_fault_handler_t handler)
2000		{
2001		#if defined(HAVE_SIGSEGV_RECOVERY)
#	Line 1141 \| Line 2006 \| bool sigsegv_install_handler(sigsegv_fau
2006		if (success)
2007		sigsegv_fault_handler = handler;
2008		return success;
2009	<	#elif defined(HAVE_MACH_EXCEPTIONS)
2009	>	#elif defined(HAVE_MACH_EXCEPTIONS) \|\| defined(HAVE_WIN32_EXCEPTIONS)
2010		return sigsegv_do_install_handler(handler);
2011		#else
2012		// FAIL: no siginfo_t nor sigcontext subterfuge is available
#	Line 1167 \| Line 2032 \| void sigsegv_deinstall_handler(void)
2032		SIGSEGV_ALL_SIGNALS
2033		#undef FAULT_HANDLER
2034		#endif
2035	+	#ifdef HAVE_WIN32_EXCEPTIONS
2036	+	sigsegv_fault_handler = NULL;
2037	+	#endif
2038		}
2039
2040
#	Line 1188 \| Line 2056 \| void sigsegv_set_dump_state(sigsegv_stat
2056		#include <stdio.h>
2057		#include <stdlib.h>
2058		#include <fcntl.h>
2059	+	#ifdef HAVE_SYS_MMAN_H
2060		#include <sys/mman.h>
2061	+	#endif
2062		#include "vm_alloc.h"
2063
2064	+	const int REF_INDEX = 123;
2065	+	const int REF_VALUE = 45;
2066	+
2067		static int page_size;
2068		static volatile char * page = 0;
2069		static volatile int handler_called = 0;
2070
2071	+	#ifdef __GNUC__
2072	+	// Code range where we expect the fault to come from
2073	+	static void b_region, e_region;
2074	+	#endif
2075	+
2076		static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2077		{
2078	+	#if DEBUG
2079	+	printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
2080	+	printf("expected fault at %p\n", page + REF_INDEX);
2081	+	#ifdef __GNUC__
2082	+	printf("expected instruction address range: %p-%p\n", b_region, e_region);
2083	+	#endif
2084	+	#endif
2085		handler_called++;
2086	<	if ((fault_address - 123) != page)
2086	>	if ((fault_address - REF_INDEX) != page)
2087		exit(10);
2088	<	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ \| VM_PAGE_WRITE) != 0)
2088	>	#ifdef __GNUC__
2089	>	// Make sure reported fault instruction address falls into
2090	>	// expected code range
2091	>	if (instruction_address != SIGSEGV_INVALID_PC
2092	>	&& ((instruction_address < (sigsegv_address_t)b_region) \|\|
2093	>	(instruction_address >= (sigsegv_address_t)e_region)))
2094		exit(11);
2095	+	#endif
2096	+	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ \| VM_PAGE_WRITE) != 0)
2097	+	exit(12);
2098		return SIGSEGV_RETURN_SUCCESS;
2099		}
2100
2101		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
1209	–	#ifdef __GNUC__
1210	–	// Code range where we expect the fault to come from
1211	–	static void b_region, e_region;
1212	–	#endif
1213	–
2102		static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
2103		{
2104	+	#if DEBUG
2105	+	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
2106	+	#endif
2107		if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
2108		#ifdef __GNUC__
2109		// Make sure reported fault instruction address falls into
#	Line 1227 \| Line 2118 \| static sigsegv_return_t sigsegv_insn_han
2118
2119		return SIGSEGV_RETURN_FAILURE;
2120		}
2121	+
2122	+	// More sophisticated tests for instruction skipper
2123	+	static bool arch_insn_skipper_tests()
2124	+	{
2125	+	#if (defined(i386) \|\| defined(__i386__)) \|\| defined(__x86_64__)
2126	+	static const unsigned char code[] = {
2127	+	0x8a, 0x00, // mov (%eax),%al
2128	+	0x8a, 0x2c, 0x18, // mov (%eax,%ebx,1),%ch
2129	+	0x88, 0x20, // mov %ah,(%eax)
2130	+	0x88, 0x08, // mov %cl,(%eax)
2131	+	0x66, 0x8b, 0x00, // mov (%eax),%ax
2132	+	0x66, 0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%cx
2133	+	0x66, 0x89, 0x00, // mov %ax,(%eax)
2134	+	0x66, 0x89, 0x0c, 0x18, // mov %cx,(%eax,%ebx,1)
2135	+	0x8b, 0x00, // mov (%eax),%eax
2136	+	0x8b, 0x0c, 0x18, // mov (%eax,%ebx,1),%ecx
2137	+	0x89, 0x00, // mov %eax,(%eax)
2138	+	0x89, 0x0c, 0x18, // mov %ecx,(%eax,%ebx,1)
2139	+	#if defined(__x86_64__)
2140	+	0x44, 0x8a, 0x00, // mov (%rax),%r8b
2141	+	0x44, 0x8a, 0x20, // mov (%rax),%r12b
2142	+	0x42, 0x8a, 0x3c, 0x10, // mov (%rax,%r10,1),%dil
2143	+	0x44, 0x88, 0x00, // mov %r8b,(%rax)
2144	+	0x44, 0x88, 0x20, // mov %r12b,(%rax)
2145	+	0x42, 0x88, 0x3c, 0x10, // mov %dil,(%rax,%r10,1)
2146	+	0x66, 0x44, 0x8b, 0x00, // mov (%rax),%r8w
2147	+	0x66, 0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%cx
2148	+	0x66, 0x44, 0x89, 0x00, // mov %r8w,(%rax)
2149	+	0x66, 0x42, 0x89, 0x0c, 0x10, // mov %cx,(%rax,%r10,1)
2150	+	0x44, 0x8b, 0x00, // mov (%rax),%r8d
2151	+	0x42, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%ecx
2152	+	0x44, 0x89, 0x00, // mov %r8d,(%rax)
2153	+	0x42, 0x89, 0x0c, 0x10, // mov %ecx,(%rax,%r10,1)
2154	+	0x48, 0x8b, 0x08, // mov (%rax),%rcx
2155	+	0x4c, 0x8b, 0x18, // mov (%rax),%r11
2156	+	0x4a, 0x8b, 0x0c, 0x10, // mov (%rax,%r10,1),%rcx
2157	+	0x4e, 0x8b, 0x1c, 0x10, // mov (%rax,%r10,1),%r11
2158	+	0x48, 0x89, 0x08, // mov %rcx,(%rax)
2159	+	0x4c, 0x89, 0x18, // mov %r11,(%rax)
2160	+	0x4a, 0x89, 0x0c, 0x10, // mov %rcx,(%rax,%r10,1)
2161	+	0x4e, 0x89, 0x1c, 0x10, // mov %r11,(%rax,%r10,1)
2162	+	#endif
2163	+	0 // end
2164	+	};
2165	+	const int N_REGS = 20;
2166	+	unsigned long regs[N_REGS];
2167	+	for (int i = 0; i < N_REGS; i++)
2168	+	regs[i] = i;
2169	+	const unsigned long start_code = (unsigned long)&code;
2170	+	regs[X86_REG_EIP] = start_code;
2171	+	while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
2172	+	&& ix86_skip_instruction(regs))
2173	+	; /* simply iterate */
2174	+	return (regs[X86_REG_EIP] - start_code) == (sizeof(code) - 1);
2175	+	#endif
2176	+	return true;
2177	+	}
2178		#endif
2179
2180		int main(void)
#	Line 1234 \| Line 2182 \| int main(void)
2182		if (vm_init() < 0)
2183		return 1;
2184
2185	<	page_size = getpagesize();
2185	>	page_size = vm_get_page_size();
2186		if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED)
2187		return 2;
2188
2189	+	memset((void *)page, 0, page_size);
2190		if (vm_protect((char *)page, page_size, VM_PAGE_READ) < 0)
2191		return 3;
2192
2193		if (!sigsegv_install_handler(sigsegv_test_handler))
2194		return 4;
2195
2196	<	page[123] = 45;
2197	<	page[123] = 45;
2198	<
2196	>	#ifdef __GNUC__
2197	>	b_region = &&L_b_region1;
2198	>	e_region = &&L_e_region1;
2199	>	#endif
2200	>	L_b_region1:
2201	>	page[REF_INDEX] = REF_VALUE;
2202	>	if (page[REF_INDEX] != REF_VALUE)
2203	>	exit(20);
2204	>	page[REF_INDEX] = REF_VALUE;
2205	>	L_e_region1:
2206	>
2207		if (handler_called != 1)
2208		return 5;
2209
#	Line 1264 \| Line 2221 \| int main(void)
2221		return 8;
2222
2223		#define TEST_SKIP_INSTRUCTION(TYPE) do { \
2224	<	const unsigned int TAG = 0x12345678; \
2224	>	const unsigned long TAG = 0x12345678 \| \
2225	>	(sizeof(long) == 8 ? 0x9abcdef0UL << 31 : 0); \
2226		TYPE data = ((TYPE )(page + sizeof(TYPE))); \
2227	<	volatile unsigned int effect = data + TAG; \
2227	>	volatile unsigned long effect = data + TAG; \
2228		if (effect != TAG) \
2229		return 9; \
2230		} while (0)
2231
2232		#ifdef __GNUC__
2233	<	b_region = &&L_b_region;
2234	<	e_region = &&L_e_region;
2233	>	b_region = &&L_b_region2;
2234	>	e_region = &&L_e_region2;
2235		#endif
2236	<	L_b_region:
2236	>	L_b_region2:
2237		TEST_SKIP_INSTRUCTION(unsigned char);
2238		TEST_SKIP_INSTRUCTION(unsigned short);
2239		TEST_SKIP_INSTRUCTION(unsigned int);
2240	<	L_e_region:
2240	>	TEST_SKIP_INSTRUCTION(unsigned long);
2241	>	TEST_SKIP_INSTRUCTION(signed char);
2242	>	TEST_SKIP_INSTRUCTION(signed short);
2243	>	TEST_SKIP_INSTRUCTION(signed int);
2244	>	TEST_SKIP_INSTRUCTION(signed long);
2245	>	L_e_region2:
2246	>
2247	>	if (!arch_insn_skipper_tests())
2248	>	return 20;
2249		#endif
2250
2251		vm_exit();

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Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents): Revision 1.30 by gbeauche, 2003-10-13T19:56:17Z vs. Revision 1.56 by gbeauche, 2005-06-12T21:47:46Z

Diff Legend

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.30 by gbeauche, 2003-10-13T19:56:17Z vs.
Revision 1.56 by gbeauche, 2005-06-12T21:47:46Z