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root/cebix/BasiliskII/src/Unix/sigsegv.cpp

Comparing BasiliskII/src/Unix/sigsegv.cpp (file contents):
Revision 1.30 by gbeauche, 2003-10-13T19:56:17Z vs.
Revision 1.46 by gbeauche, 2004-01-22T00:00:55Z

#	Line 10 | Line 10
10		*    tjw@omnigroup.com Sun, 4 Jun 2000
11		*    www.omnigroup.com/mailman/archive/macosx-dev/2000-June/002030.html
12		*
13	<	*  Basilisk II (C) 1997-2002 Christian Bauer
13	>	*  Basilisk II (C) 1997-2004 Christian Bauer
14		*
15		*  This program is free software; you can redistribute it and/or modify
16		*  it under the terms of the GNU General Public License as published by
#	Line 36 | Line 36
36		#endif
37
38		#include <list>
39	+	#include <stdio.h>
40		#include <signal.h>
41		#include "sigsegv.h"
42
#	Line 69 | Line 70 | static bool sigsegv_do_install_handler(i
70		enum transfer_size_t {
71		SIZE_UNKNOWN,
72		SIZE_BYTE,
73	<	SIZE_WORD,
74	<	SIZE_LONG
73	>	SIZE_WORD, // 2 bytes
74	>	SIZE_LONG, // 4 bytes
75	>	SIZE_QUAD, // 8 bytes
76		};
77
78		// Transfer type
#	Line 212 | Line 214 | static void powerpc_decode_instruction(i
214
215		#if HAVE_SIGINFO_T
216		// Generic extended signal handler
215	–	#define SIGSEGV_FAULT_HANDLER                   sigsegv_fault_handler
217		#if defined(__NetBSD__) || defined(__FreeBSD__)
218		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
219		#else
#	Line 222 | Line 223 | static void powerpc_decode_instruction(i
223		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 siginfo_t *sip, void *scp
224		#define SIGSEGV_FAULT_HANDLER_ARGS              sip, scp
225		#define SIGSEGV_FAULT_ADDRESS                   sip->si_addr
226	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
226	>	#if (defined(sgi) || defined(__sgi))
227	>	#include <ucontext.h>
228	>	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
229	>	#define SIGSEGV_FAULT_INSTRUCTION               (unsigned long)SIGSEGV_CONTEXT_REGS[CTX_EPC]
230	>	#if (defined(mips) || defined(__mips))
231	>	#define SIGSEGV_REGISTER_FILE                   SIGSEGV_CONTEXT_REGS
232	>	#define SIGSEGV_SKIP_INSTRUCTION                mips_skip_instruction
233	>	#endif
234	>	#endif
235	>	#if defined(__sun__)
236	>	#if (defined(sparc) || defined(__sparc__))
237	>	#include <sys/stack.h>
238	>	#include <sys/regset.h>
239	>	#include <sys/ucontext.h>
240	>	#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
241	>	#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[REG_PC]
242	>	#define SIGSEGV_SPARC_GWINDOWS                  (((ucontext_t *)scp)->uc_mcontext.gwins)
243	>	#define SIGSEGV_SPARC_RWINDOW                   (struct rwindow *)((char *)SIGSEGV_CONTEXT_REGS[REG_SP] + STACK_BIAS)
244	>	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)SIGSEGV_CONTEXT_REGS), SIGSEGV_SPARC_GWINDOWS, SIGSEGV_SPARC_RWINDOW
245	>	#define SIGSEGV_SKIP_INSTRUCTION                sparc_skip_instruction
246	>	#endif
247	>	#endif
248	>	#if defined(__FreeBSD__)
249		#if (defined(i386) || defined(__i386__))
250		#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_eip)
251	<	#define SIGSEGV_REGISTER_FILE                   ((unsigned int *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
251	>	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&(((struct sigcontext *)scp)->sc_edi)) /* EDI is the first GPR (even below EIP) in sigcontext */
252		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
253		#endif
254		#endif
#	Line 234 | Line 257 | static void powerpc_decode_instruction(i
257		#include <sys/ucontext.h>
258		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
259		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[14] /* should use REG_EIP instead */
260	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)SIGSEGV_CONTEXT_REGS
260	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
261		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
262		#endif
263		#if (defined(x86_64) || defined(__x86_64__))
#	Line 242 | Line 265 | static void powerpc_decode_instruction(i
265		#define SIGSEGV_CONTEXT_REGS                    (((ucontext_t *)scp)->uc_mcontext.gregs)
266		#define SIGSEGV_FAULT_INSTRUCTION               SIGSEGV_CONTEXT_REGS[16] /* should use REG_RIP instead */
267		#define SIGSEGV_REGISTER_FILE                   (unsigned long *)SIGSEGV_CONTEXT_REGS
268	+	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
269		#endif
270		#if (defined(ia64) || defined(__ia64__))
271		#define SIGSEGV_FAULT_INSTRUCTION               (((struct sigcontext *)scp)->sc_ip & ~0x3ULL) /* slot number is in bits 0 and 1 */
#	Line 253 | Line 277 | static void powerpc_decode_instruction(i
277		#define SIGSEGV_REGISTER_FILE                   (unsigned int *)&SIGSEGV_CONTEXT_REGS->nip, (unsigned int *)(SIGSEGV_CONTEXT_REGS->gpr)
278		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
279		#endif
280	+	#if (defined(hppa) || defined(__hppa__))
281	+	#undef  SIGSEGV_FAULT_ADDRESS
282	+	#define SIGSEGV_FAULT_ADDRESS                   sip->si_ptr
283	+	#endif
284	+	#if (defined(arm) || defined(__arm__))
285	+	#include <asm/ucontext.h> /* use kernel structure, glibc may not be in sync */
286	+	#define SIGSEGV_CONTEXT_REGS                    (((struct ucontext *)scp)->uc_mcontext)
287	+	#define SIGSEGV_FAULT_INSTRUCTION               (SIGSEGV_CONTEXT_REGS.arm_pc)
288	+	#define SIGSEGV_REGISTER_FILE                   (&SIGSEGV_CONTEXT_REGS.arm_r0)
289	+	#define SIGSEGV_SKIP_INSTRUCTION                arm_skip_instruction
290	+	#endif
291		#endif
292		#endif
293
294		#if HAVE_SIGCONTEXT_SUBTERFUGE
260	–	#define SIGSEGV_FAULT_HANDLER                   sigsegv_fault_handler
295		// Linux kernels prior to 2.4 ?
296		#if defined(__linux__)
297		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
#	Line 268 | Line 302 | static void powerpc_decode_instruction(i
302		#define SIGSEGV_FAULT_HANDLER_ARGS              &scs
303		#define SIGSEGV_FAULT_ADDRESS                   scp->cr2
304		#define SIGSEGV_FAULT_INSTRUCTION               scp->eip
305	<	#define SIGSEGV_REGISTER_FILE                   (unsigned int *)scp
305	>	#define SIGSEGV_REGISTER_FILE                   (unsigned long *)scp
306		#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
307		#endif
308		#if (defined(sparc) || defined(__sparc__))
#	Line 292 | Line 326 | static void powerpc_decode_instruction(i
326		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
327		#define SIGSEGV_FAULT_ADDRESS                   get_fault_address(scp)
328		#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_pc
329	<
330	<	// From Boehm's GC 6.0alpha8
331	<	static sigsegv_address_t get_fault_address(struct sigcontext *scp)
332	<	{
333	<	unsigned int instruction = *((unsigned int *)(scp->sc_pc));
334	<	unsigned long fault_address = scp->sc_regs[(instruction >> 16) & 0x1f];
335	<	fault_address += (signed long)(signed short)(instruction & 0xffff);
336	<	return (sigsegv_address_t)fault_address;
337	<	}
329	>	#endif
330	>	#if (defined(arm) || defined(__arm__))
331	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int r1, int r2, int r3, struct sigcontext sc
332	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 struct sigcontext *scp
333	>	#define SIGSEGV_FAULT_HANDLER_ARGS              &sc
334	>	#define SIGSEGV_FAULT_ADDRESS                   scp->fault_address
335	>	#define SIGSEGV_FAULT_INSTRUCTION               scp->arm_pc
336	>	#define SIGSEGV_REGISTER_FILE                   &scp->arm_r0
337	>	#define SIGSEGV_SKIP_INSTRUCTION                arm_skip_instruction
338		#endif
339		#endif
340
341		// Irix 5 or 6 on MIPS
342	<	#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(__SYSTYPE_SVR4))
342	>	#if (defined(sgi) || defined(__sgi)) && (defined(SYSTYPE_SVR4) || defined(_SYSTYPE_SVR4))
343		#include <ucontext.h>
344		#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
345		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
346	<	#define SIGSEGV_FAULT_ADDRESS                   scp->sc_badvaddr
346	>	#define SIGSEGV_FAULT_ADDRESS                   (unsigned long)scp->sc_badvaddr
347	>	#define SIGSEGV_FAULT_INSTRUCTION               (unsigned long)scp->sc_pc
348		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
349		#endif
350
#	Line 338 | Line 373 | static sigsegv_address_t get_fault_addre
373		#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
374		#endif
375
376	<	// NetBSD or FreeBSD
377	<	#if defined(__NetBSD__) || defined(__FreeBSD__)
376	>	// NetBSD
377	>	#if defined(__NetBSD__)
378		#if (defined(m68k) || defined(__m68k__))
379		#include <m68k/frame.h>
380		#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
#	Line 367 | Line 402 | static sigsegv_address_t get_fault_addre
402		}
403		return (sigsegv_address_t)fault_addr;
404		}
405	<	#else
406	<	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, void *scp, char *addr
405	>	#endif
406	>	#if (defined(alpha) || defined(__alpha__))
407	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
408	>	#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
409	>	#define SIGSEGV_FAULT_ADDRESS                   get_fault_address(scp)
410	>	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
411	>	#endif
412	>	#if (defined(i386) || defined(__i386__))
413	>	#error "FIXME: need to decode instruction and compute EA"
414	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp
415	>	#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp
416	>	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
417	>	#endif
418	>	#endif
419	>	#if defined(__FreeBSD__)
420	>	#if (defined(i386) || defined(__i386__))
421	>	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
422	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, int code, struct sigcontext *scp, char *addr
423		#define SIGSEGV_FAULT_HANDLER_ARGS              sig, code, scp, addr
424		#define SIGSEGV_FAULT_ADDRESS                   addr
425	<	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGBUS)
425	>	#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_eip
426	>	#define SIGSEGV_REGISTER_FILE                   ((unsigned long *)&scp->sc_edi)
427	>	#define SIGSEGV_SKIP_INSTRUCTION                ix86_skip_instruction
428	>	#endif
429	>	#if (defined(alpha) || defined(__alpha__))
430	>	#define SIGSEGV_ALL_SIGNALS                             FAULT_HANDLER(SIGSEGV)
431	>	#define SIGSEGV_FAULT_HANDLER_ARGLIST   int sig, char *addr, struct sigcontext *scp
432	>	#define SIGSEGV_FAULT_HANDLER_ARGS              sig, addr, scp
433	>	#define SIGSEGV_FAULT_ADDRESS                   addr
434	>	#define SIGSEGV_FAULT_INSTRUCTION               scp->sc_pc
435		#endif
436		#endif
437
438	+	// Extract fault address out of a sigcontext
439	+	#if (defined(alpha) || defined(__alpha__))
440	+	// From Boehm's GC 6.0alpha8
441	+	static sigsegv_address_t get_fault_address(struct sigcontext *scp)
442	+	{
443	+	unsigned int instruction = *((unsigned int *)(scp->sc_pc));
444	+	unsigned long fault_address = scp->sc_regs[(instruction >> 16) & 0x1f];
445	+	fault_address += (signed long)(signed short)(instruction & 0xffff);
446	+	return (sigsegv_address_t)fault_address;
447	+	}
448	+	#endif
449	+
450	+
451		// MacOS X, not sure which version this works in. Under 10.1
452		// vm_protect does not appear to work from a signal handler. Under
453		// 10.2 signal handlers get siginfo type arguments but the si_addr
#	Line 470 | Line 543 | if (ret != KERN_SUCCESS) { \
543
544		#define SIGSEGV_FAULT_ADDRESS                   code[1]
545		#define SIGSEGV_FAULT_INSTRUCTION               get_fault_instruction(thread, state)
546	<	#define SIGSEGV_FAULT_HANDLER                   (code[0] == KERN_PROTECTION_FAILURE) && sigsegv_fault_handler
546	>	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP)  ((code[0] == KERN_PROTECTION_FAILURE) ? sigsegv_fault_handler(ADDR, IP) : SIGSEGV_RETURN_FAILURE)
547		#define SIGSEGV_FAULT_HANDLER_ARGLIST   mach_port_t thread, exception_data_t code, ppc_thread_state_t *state
548		#define SIGSEGV_FAULT_HANDLER_ARGS              thread, code, &state
549		#define SIGSEGV_SKIP_INSTRUCTION                powerpc_skip_instruction
#	Line 550 | Line 623 | handleExceptions(void *priv)
623
624		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
625		// Decode and skip X86 instruction
626	<	#if (defined(i386) || defined(__i386__))
626	>	#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
627		#if defined(__linux__)
628		enum {
629	+	#if (defined(i386) || defined(__i386__))
630		X86_REG_EIP = 14,
631		X86_REG_EAX = 11,
632		X86_REG_ECX = 10,
#	Line 562 | Line 636 | enum {
636		X86_REG_EBP = 6,
637		X86_REG_ESI = 5,
638		X86_REG_EDI = 4
639	+	#endif
640	+	#if defined(__x86_64__)
641	+	X86_REG_R8  = 0,
642	+	X86_REG_R9  = 1,
643	+	X86_REG_R10 = 2,
644	+	X86_REG_R11 = 3,
645	+	X86_REG_R12 = 4,
646	+	X86_REG_R13 = 5,
647	+	X86_REG_R14 = 6,
648	+	X86_REG_R15 = 7,
649	+	X86_REG_EDI = 8,
650	+	X86_REG_ESI = 9,
651	+	X86_REG_EBP = 10,
652	+	X86_REG_EBX = 11,
653	+	X86_REG_EDX = 12,
654	+	X86_REG_EAX = 13,
655	+	X86_REG_ECX = 14,
656	+	X86_REG_ESP = 15,
657	+	X86_REG_EIP = 16
658	+	#endif
659		};
660		#endif
661		#if defined(__NetBSD__) || defined(__FreeBSD__)
662		enum {
663	+	#if (defined(i386) || defined(__i386__))
664		X86_REG_EIP = 10,
665		X86_REG_EAX = 7,
666		X86_REG_ECX = 6,
#	Line 575 | Line 670 | enum {
670		X86_REG_EBP = 2,
671		X86_REG_ESI = 1,
672		X86_REG_EDI = 0
673	+	#endif
674		};
675		#endif
676		// FIXME: this is partly redundant with the instruction decoding phase
#	Line 611 | Line 707 | static inline int ix86_step_over_modrm(u
707		return offset;
708		}
709
710	<	static bool ix86_skip_instruction(unsigned int * regs)
710	>	static bool ix86_skip_instruction(unsigned long * regs)
711		{
712		unsigned char * eip = (unsigned char *)regs[X86_REG_EIP];
713
#	Line 623 | Line 719 | static bool ix86_skip_instruction(unsign
719
720		int reg = -1;
721		int len = 0;
722	<
722	>
723	>	#if DEBUG
724	>	printf("IP: %p [%02x %02x %02x %02x...]\n",
725	>	eip, eip[0], eip[1], eip[2], eip[3]);
726	>	#endif
727	>
728		// Operand size prefix
729		if (*eip == 0x66) {
730		eip++;
#	Line 631 | Line 732 | static bool ix86_skip_instruction(unsign
732		transfer_size = SIZE_WORD;
733		}
734
735	+	// REX prefix
736	+	#if defined(__x86_64__)
737	+	struct rex_t {
738	+	unsigned char W;
739	+	unsigned char R;
740	+	unsigned char X;
741	+	unsigned char B;
742	+	};
743	+	rex_t rex = { 0, 0, 0, 0 };
744	+	bool has_rex = false;
745	+	if ((*eip & 0xf0) == 0x40) {
746	+	has_rex = true;
747	+	const unsigned char b = *eip;
748	+	rex.W = b & (1 << 3);
749	+	rex.R = b & (1 << 2);
750	+	rex.X = b & (1 << 1);
751	+	rex.B = b & (1 << 0);
752	+	#if DEBUG
753	+	printf("REX: %c,%c,%c,%c\n",
754	+	rex.W ? 'W' : '_',
755	+	rex.R ? 'R' : '_',
756	+	rex.X ? 'X' : '_',
757	+	rex.B ? 'B' : '_');
758	+	#endif
759	+	eip++;
760	+	len++;
761	+	if (rex.W)
762	+	transfer_size = SIZE_QUAD;
763	+	}
764	+	#else
765	+	const bool has_rex = false;
766	+	#endif
767	+
768		// Decode instruction
769	+	int target_size = SIZE_UNKNOWN;
770		switch (eip[0]) {
771		case 0x0f:
772	+	target_size = transfer_size;
773		switch (eip[1]) {
774	+	case 0xbe: // MOVSX r32, r/m8
775		case 0xb6: // MOVZX r32, r/m8
776	+	transfer_size = SIZE_BYTE;
777	+	goto do_mov_extend;
778		case 0xb7: // MOVZX r32, r/m16
779	<	switch (eip[2] & 0xc0) {
780	<	case 0x80:
781	<	reg = (eip[2] >> 3) & 7;
782	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
783	<	break;
784	<	case 0x40:
785	<	reg = (eip[2] >> 3) & 7;
786	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
787	<	break;
788	<	case 0x00:
789	<	reg = (eip[2] >> 3) & 7;
790	<	transfer_type = SIGSEGV_TRANSFER_LOAD;
791	<	break;
792	<	}
793	<	len += 3 + ix86_step_over_modrm(eip + 2);
794	<	break;
779	>	transfer_size = SIZE_WORD;
780	>	goto do_mov_extend;
781	>	do_mov_extend:
782	>	switch (eip[2] & 0xc0) {
783	>	case 0x80:
784	>	reg = (eip[2] >> 3) & 7;
785	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
786	>	break;
787	>	case 0x40:
788	>	reg = (eip[2] >> 3) & 7;
789	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
790	>	break;
791	>	case 0x00:
792	>	reg = (eip[2] >> 3) & 7;
793	>	transfer_type = SIGSEGV_TRANSFER_LOAD;
794	>	break;
795	>	}
796	>	len += 3 + ix86_step_over_modrm(eip + 2);
797	>	break;
798		}
799		break;
800		case 0x8a: // MOV r8, r/m8
#	Line 694 | Line 836 | static bool ix86_skip_instruction(unsign
836		len += 2 + ix86_step_over_modrm(eip + 1);
837		break;
838		}
839	+	if (target_size == SIZE_UNKNOWN)
840	+	target_size = transfer_size;
841
842		if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
843		// Unknown machine code, let it crash. Then patch the decoder
844		return false;
845		}
846
847	+	#if defined(__x86_64__)
848	+	if (rex.R)
849	+	reg += 8;
850	+	#endif
851	+
852		if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != -1) {
853	<	static const int x86_reg_map[8] = {
853	>	static const int x86_reg_map[] = {
854		X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, X86_REG_EBX,
855	<	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI
855	>	X86_REG_ESP, X86_REG_EBP, X86_REG_ESI, X86_REG_EDI,
856	>	#if defined(__x86_64__)
857	>	X86_REG_R8,  X86_REG_R9,  X86_REG_R10, X86_REG_R11,
858	>	X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15,
859	>	#endif
860		};
861
862	<	if (reg < 0 || reg >= 8)
862	>	if (reg < 0 || reg >= (sizeof(x86_reg_map)/sizeof(x86_reg_map[0]) - 1))
863		return false;
864
865	+	// Set 0 to the relevant register part
866	+	// NOTE: this is only valid for MOV alike instructions
867		int rloc = x86_reg_map[reg];
868	<	switch (transfer_size) {
868	>	switch (target_size) {
869		case SIZE_BYTE:
870	<	regs[rloc] = (regs[rloc] & ~0xff);
870	>	if (has_rex || reg < 4)
871	>	regs[rloc] = (regs[rloc] & ~0x00ffL);
872	>	else {
873	>	rloc = x86_reg_map[reg - 4];
874	>	regs[rloc] = (regs[rloc] & ~0xff00L);
875	>	}
876		break;
877		case SIZE_WORD:
878	<	regs[rloc] = (regs[rloc] & ~0xffff);
878	>	regs[rloc] = (regs[rloc] & ~0xffffL);
879		break;
880		case SIZE_LONG:
881	+	case SIZE_QUAD: // zero-extension
882		regs[rloc] = 0;
883		break;
884		}
#	Line 725 | Line 886 | static bool ix86_skip_instruction(unsign
886
887		#if DEBUG
888		printf("%08x: %s %s access", regs[X86_REG_EIP],
889	<	transfer_size == SIZE_BYTE ? "byte" : transfer_size == SIZE_WORD ? "word" : "long",
889	>	transfer_size == SIZE_BYTE ? "byte" :
890	>	transfer_size == SIZE_WORD ? "word" :
891	>	transfer_size == SIZE_LONG ? "long" :
892	>	transfer_size == SIZE_QUAD ? "quad" : "unknown",
893		transfer_type == SIGSEGV_TRANSFER_LOAD ? "read" : "write");
894
895		if (reg != -1) {
896	<	static const char * x86_reg_str_map[8] = {
897	<	"eax", "ecx", "edx", "ebx",
898	<	"esp", "ebp", "esi", "edi"
896	>	static const char * x86_byte_reg_str_map[] = {
897	>	"al",   "cl",   "dl",   "bl",
898	>	"spl",  "bpl",  "sil",  "dil",
899	>	"r8b",  "r9b",  "r10b", "r11b",
900	>	"r12b", "r13b", "r14b", "r15b",
901	>	"ah",   "ch",   "dh",   "bh",
902	>	};
903	>	static const char * x86_word_reg_str_map[] = {
904	>	"ax",   "cx",   "dx",   "bx",
905	>	"sp",   "bp",   "si",   "di",
906	>	"r8w",  "r9w",  "r10w", "r11w",
907	>	"r12w", "r13w", "r14w", "r15w",
908		};
909	<	printf(" %s register %%%s", transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from", x86_reg_str_map[reg]);
909	>	static const char *x86_long_reg_str_map[] = {
910	>	"eax",  "ecx",  "edx",  "ebx",
911	>	"esp",  "ebp",  "esi",  "edi",
912	>	"r8d",  "r9d",  "r10d", "r11d",
913	>	"r12d", "r13d", "r14d", "r15d",
914	>	};
915	>	static const char *x86_quad_reg_str_map[] = {
916	>	"rax", "rcx", "rdx", "rbx",
917	>	"rsp", "rbp", "rsi", "rdi",
918	>	"r8",  "r9",  "r10", "r11",
919	>	"r12", "r13", "r14", "r15",
920	>	};
921	>	const char * reg_str = NULL;
922	>	switch (target_size) {
923	>	case SIZE_BYTE:
924	>	reg_str = x86_byte_reg_str_map[(!has_rex && reg >= 4 ? 12 : 0) + reg];
925	>	break;
926	>	case SIZE_WORD: reg_str = x86_word_reg_str_map[reg]; break;
927	>	case SIZE_LONG: reg_str = x86_long_reg_str_map[reg]; break;
928	>	case SIZE_QUAD: reg_str = x86_quad_reg_str_map[reg]; break;
929	>	}
930	>	if (reg_str)
931	>	printf(" %s register %%%s",
932	>	transfer_type == SIGSEGV_TRANSFER_LOAD ? "to" : "from",
933	>	reg_str);
934		}
935		printf(", %d bytes instruction\n", len);
936		#endif
#	Line 775 | Line 972 | static bool powerpc_skip_instruction(uns
972		return true;
973		}
974		#endif
975	+
976	+	// Decode and skip MIPS instruction
977	+	#if (defined(mips) || defined(__mips))
978	+	enum {
979	+	#if (defined(sgi) || defined(__sgi))
980	+	MIPS_REG_EPC = 35,
981		#endif
982	+	};
983	+	static bool mips_skip_instruction(greg_t * regs)
984	+	{
985	+	unsigned int * epc = (unsigned int *)(unsigned long)regs[MIPS_REG_EPC];
986	+
987	+	if (epc == 0)
988	+	return false;
989	+
990	+	#if DEBUG
991	+	printf("IP: %p [%08x]\n", epc, epc[0]);
992	+	#endif
993	+
994	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
995	+	transfer_size_t transfer_size = SIZE_LONG;
996	+	int direction = 0;
997	+
998	+	const unsigned int opcode = epc[0];
999	+	switch (opcode >> 26) {
1000	+	case 32: // Load Byte
1001	+	case 36: // Load Byte Unsigned
1002	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1003	+	transfer_size = SIZE_BYTE;
1004	+	break;
1005	+	case 33: // Load Halfword
1006	+	case 37: // Load Halfword Unsigned
1007	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1008	+	transfer_size = SIZE_WORD;
1009	+	break;
1010	+	case 35: // Load Word
1011	+	case 39: // Load Word Unsigned
1012	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1013	+	transfer_size = SIZE_LONG;
1014	+	break;
1015	+	case 34: // Load Word Left
1016	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1017	+	transfer_size = SIZE_LONG;
1018	+	direction = -1;
1019	+	break;
1020	+	case 38: // Load Word Right
1021	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1022	+	transfer_size = SIZE_LONG;
1023	+	direction = 1;
1024	+	break;
1025	+	case 55: // Load Doubleword
1026	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1027	+	transfer_size = SIZE_QUAD;
1028	+	break;
1029	+	case 26: // Load Doubleword Left
1030	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1031	+	transfer_size = SIZE_QUAD;
1032	+	direction = -1;
1033	+	break;
1034	+	case 27: // Load Doubleword Right
1035	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1036	+	transfer_size = SIZE_QUAD;
1037	+	direction = 1;
1038	+	break;
1039	+	case 40: // Store Byte
1040	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1041	+	transfer_size = SIZE_BYTE;
1042	+	break;
1043	+	case 41: // Store Halfword
1044	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1045	+	transfer_size = SIZE_WORD;
1046	+	break;
1047	+	case 43: // Store Word
1048	+	case 42: // Store Word Left
1049	+	case 46: // Store Word Right
1050	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1051	+	transfer_size = SIZE_LONG;
1052	+	break;
1053	+	case 63: // Store Doubleword
1054	+	case 44: // Store Doubleword Left
1055	+	case 45: // Store Doubleword Right
1056	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1057	+	transfer_size = SIZE_QUAD;
1058	+	break;
1059	+	/* Misc instructions unlikely to be used within CPU emulators */
1060	+	case 48: // Load Linked Word
1061	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1062	+	transfer_size = SIZE_LONG;
1063	+	break;
1064	+	case 52: // Load Linked Doubleword
1065	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1066	+	transfer_size = SIZE_QUAD;
1067	+	break;
1068	+	case 56: // Store Conditional Word
1069	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1070	+	transfer_size = SIZE_LONG;
1071	+	break;
1072	+	case 60: // Store Conditional Doubleword
1073	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1074	+	transfer_size = SIZE_QUAD;
1075	+	break;
1076	+	}
1077	+
1078	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1079	+	// Unknown machine code, let it crash. Then patch the decoder
1080	+	return false;
1081	+	}
1082	+
1083	+	// Zero target register in case of a load operation
1084	+	const int reg = (opcode >> 16) & 0x1f;
1085	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD) {
1086	+	if (direction == 0)
1087	+	regs[reg] = 0;
1088	+	else {
1089	+	// FIXME: untested code
1090	+	unsigned long ea = regs[(opcode >> 21) & 0x1f];
1091	+	ea += (signed long)(signed int)(signed short)(opcode & 0xffff);
1092	+	const int offset = ea & (transfer_size == SIZE_LONG ? 3 : 7);
1093	+	unsigned long value;
1094	+	if (direction > 0) {
1095	+	const unsigned long rmask = ~((1L << ((offset + 1) * 8)) - 1);
1096	+	value = regs[reg] & rmask;
1097	+	}
1098	+	else {
1099	+	const unsigned long lmask = (1L << (offset * 8)) - 1;
1100	+	value = regs[reg] & lmask;
1101	+	}
1102	+	// restore most significant bits
1103	+	if (transfer_size == SIZE_LONG)
1104	+	value = (signed long)(signed int)value;
1105	+	regs[reg] = value;
1106	+	}
1107	+	}
1108	+
1109	+	#if DEBUG
1110	+	#if (defined(_ABIN32) || defined(_ABI64))
1111	+	static const char * mips_gpr_names[32] = {
1112	+	"zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
1113	+	"t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
1114	+	"s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
1115	+	"t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
1116	+	};
1117	+	#else
1118	+	static const char * mips_gpr_names[32] = {
1119	+	"zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
1120	+	"a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
1121	+	"s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
1122	+	"t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
1123	+	};
1124	+	#endif
1125	+	printf("%s %s register %s\n",
1126	+	transfer_size == SIZE_BYTE ? "byte" :
1127	+	transfer_size == SIZE_WORD ? "word" :
1128	+	transfer_size == SIZE_LONG ? "long" :
1129	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1130	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1131	+	mips_gpr_names[reg]);
1132	+	#endif
1133	+
1134	+	regs[MIPS_REG_EPC] += 4;
1135	+	return true;
1136	+	}
1137	+	#endif
1138	+
1139	+	// Decode and skip SPARC instruction
1140	+	#if (defined(sparc) || defined(__sparc__))
1141	+	enum {
1142	+	#if (defined(__sun__))
1143	+	SPARC_REG_G1 = REG_G1,
1144	+	SPARC_REG_O0 = REG_O0,
1145	+	SPARC_REG_PC = REG_PC,
1146	+	#endif
1147	+	};
1148	+	static bool sparc_skip_instruction(unsigned long * regs, gwindows_t * gwins, struct rwindow * rwin)
1149	+	{
1150	+	unsigned int * pc = (unsigned int *)regs[SPARC_REG_PC];
1151	+
1152	+	if (pc == 0)
1153	+	return false;
1154	+
1155	+	#if DEBUG
1156	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1157	+	#endif
1158	+
1159	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1160	+	transfer_size_t transfer_size = SIZE_LONG;
1161	+	bool register_pair = false;
1162	+
1163	+	const unsigned int opcode = pc[0];
1164	+	if ((opcode >> 30) != 3)
1165	+	return false;
1166	+	switch ((opcode >> 19) & 0x3f) {
1167	+	case 9: // Load Signed Byte
1168	+	case 1: // Load Unsigned Byte
1169	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1170	+	transfer_size = SIZE_BYTE;
1171	+	break;
1172	+	case 10:// Load Signed Halfword
1173	+	case 2: // Load Unsigned Word
1174	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1175	+	transfer_size = SIZE_WORD;
1176	+	break;
1177	+	case 8: // Load Word
1178	+	case 0: // Load Unsigned Word
1179	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1180	+	transfer_size = SIZE_LONG;
1181	+	break;
1182	+	case 11:// Load Extended Word
1183	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1184	+	transfer_size = SIZE_QUAD;
1185	+	break;
1186	+	case 3: // Load Doubleword
1187	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1188	+	transfer_size = SIZE_LONG;
1189	+	register_pair = true;
1190	+	break;
1191	+	case 5: // Store Byte
1192	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1193	+	transfer_size = SIZE_BYTE;
1194	+	break;
1195	+	case 6: // Store Halfword
1196	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1197	+	transfer_size = SIZE_WORD;
1198	+	break;
1199	+	case 4: // Store Word
1200	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1201	+	transfer_size = SIZE_LONG;
1202	+	break;
1203	+	case 14:// Store Extended Word
1204	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1205	+	transfer_size = SIZE_QUAD;
1206	+	break;
1207	+	case 7: // Store Doubleword
1208	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1209	+	transfer_size = SIZE_WORD;
1210	+	register_pair = true;
1211	+	break;
1212	+	}
1213	+
1214	+	if (transfer_type == SIGSEGV_TRANSFER_UNKNOWN) {
1215	+	// Unknown machine code, let it crash. Then patch the decoder
1216	+	return false;
1217	+	}
1218	+
1219	+	// Zero target register in case of a load operation
1220	+	const int reg = (opcode >> 25) & 0x1f;
1221	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD && reg != 0) {
1222	+	// FIXME: code to handle local & input registers is not tested
1223	+	if (reg >= 1 && reg <= 7) {
1224	+	// global registers
1225	+	regs[reg - 1 + SPARC_REG_G1] = 0;
1226	+	}
1227	+	else if (reg >= 8 && reg <= 15) {
1228	+	// output registers
1229	+	regs[reg - 8 + SPARC_REG_O0] = 0;
1230	+	}
1231	+	else if (reg >= 16 && reg <= 23) {
1232	+	// local registers (in register windows)
1233	+	if (gwins)
1234	+	gwins->wbuf->rw_local[reg - 16] = 0;
1235	+	else
1236	+	rwin->rw_local[reg - 16] = 0;
1237	+	}
1238	+	else {
1239	+	// input registers (in register windows)
1240	+	if (gwins)
1241	+	gwins->wbuf->rw_in[reg - 24] = 0;
1242	+	else
1243	+	rwin->rw_in[reg - 24] = 0;
1244	+	}
1245	+	}
1246	+
1247	+	#if DEBUG
1248	+	static const char * reg_names[] = {
1249	+	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
1250	+	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
1251	+	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
1252	+	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7"
1253	+	};
1254	+	printf("%s %s register %s\n",
1255	+	transfer_size == SIZE_BYTE ? "byte" :
1256	+	transfer_size == SIZE_WORD ? "word" :
1257	+	transfer_size == SIZE_LONG ? "long" :
1258	+	transfer_size == SIZE_QUAD ? "quad" : "unknown",
1259	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1260	+	reg_names[reg]);
1261	+	#endif
1262	+
1263	+	regs[SPARC_REG_PC] += 4;
1264	+	return true;
1265	+	}
1266	+	#endif
1267	+	#endif
1268	+
1269	+	// Decode and skip ARM instruction
1270	+	#if (defined(arm) || defined(__arm__))
1271	+	enum {
1272	+	#if (defined(__linux__))
1273	+	ARM_REG_PC = 15,
1274	+	ARM_REG_CPSR = 16
1275	+	#endif
1276	+	};
1277	+	static bool arm_skip_instruction(unsigned long * regs)
1278	+	{
1279	+	unsigned int * pc = (unsigned int *)regs[ARM_REG_PC];
1280	+
1281	+	if (pc == 0)
1282	+	return false;
1283	+
1284	+	#if DEBUG
1285	+	printf("IP: %p [%08x]\n", pc, pc[0]);
1286	+	#endif
1287	+
1288	+	transfer_type_t transfer_type = SIGSEGV_TRANSFER_UNKNOWN;
1289	+	transfer_size_t transfer_size = SIZE_UNKNOWN;
1290	+	enum { op_sdt = 1, op_sdth = 2 };
1291	+	int op = 0;
1292	+
1293	+	// Handle load/store instructions only
1294	+	const unsigned int opcode = pc[0];
1295	+	switch ((opcode >> 25) & 7) {
1296	+	case 0: // Halfword and Signed Data Transfer (LDRH, STRH, LDRSB, LDRSH)
1297	+	op = op_sdth;
1298	+	// Determine transfer size (S/H bits)
1299	+	switch ((opcode >> 5) & 3) {
1300	+	case 0: // SWP instruction
1301	+	break;
1302	+	case 1: // Unsigned halfwords
1303	+	case 3: // Signed halfwords
1304	+	transfer_size = SIZE_WORD;
1305	+	break;
1306	+	case 2: // Signed byte
1307	+	transfer_size = SIZE_BYTE;
1308	+	break;
1309	+	}
1310	+	break;
1311	+	case 2:
1312	+	case 3: // Single Data Transfer (LDR, STR)
1313	+	op = op_sdt;
1314	+	// Determine transfer size (B bit)
1315	+	if (((opcode >> 22) & 1) == 1)
1316	+	transfer_size = SIZE_BYTE;
1317	+	else
1318	+	transfer_size = SIZE_LONG;
1319	+	break;
1320	+	default:
1321	+	// FIXME: support load/store mutliple?
1322	+	return false;
1323	+	}
1324	+
1325	+	// Check for invalid transfer size (SWP instruction?)
1326	+	if (transfer_size == SIZE_UNKNOWN)
1327	+	return false;
1328	+
1329	+	// Determine transfer type (L bit)
1330	+	if (((opcode >> 20) & 1) == 1)
1331	+	transfer_type = SIGSEGV_TRANSFER_LOAD;
1332	+	else
1333	+	transfer_type = SIGSEGV_TRANSFER_STORE;
1334	+
1335	+	// Compute offset
1336	+	int offset;
1337	+	if (((opcode >> 25) & 1) == 0) {
1338	+	if (op == op_sdt)
1339	+	offset = opcode & 0xfff;
1340	+	else if (op == op_sdth) {
1341	+	int rm = opcode & 0xf;
1342	+	if (((opcode >> 22) & 1) == 0) {
1343	+	// register offset
1344	+	offset = regs[rm];
1345	+	}
1346	+	else {
1347	+	// immediate offset
1348	+	offset = ((opcode >> 4) & 0xf0) | (opcode & 0x0f);
1349	+	}
1350	+	}
1351	+	}
1352	+	else {
1353	+	const int rm = opcode & 0xf;
1354	+	const int sh = (opcode >> 7) & 0x1f;
1355	+	if (((opcode >> 4) & 1) == 1) {
1356	+	// we expect only legal load/store instructions
1357	+	printf("FATAL: invalid shift operand\n");
1358	+	return false;
1359	+	}
1360	+	const unsigned int v = regs[rm];
1361	+	switch ((opcode >> 5) & 3) {
1362	+	case 0: // logical shift left
1363	+	offset = sh ? v << sh : v;
1364	+	break;
1365	+	case 1: // logical shift right
1366	+	offset = sh ? v >> sh : 0;
1367	+	break;
1368	+	case 2: // arithmetic shift right
1369	+	if (sh)
1370	+	offset = ((signed int)v) >> sh;
1371	+	else
1372	+	offset = (v & 0x80000000) ? 0xffffffff : 0;
1373	+	break;
1374	+	case 3: // rotate right
1375	+	if (sh)
1376	+	offset = (v >> sh) | (v << (32 - sh));
1377	+	else
1378	+	offset = (v >> 1) | ((regs[ARM_REG_CPSR] << 2) & 0x80000000);
1379	+	break;
1380	+	}
1381	+	}
1382	+	if (((opcode >> 23) & 1) == 0)
1383	+	offset = -offset;
1384	+
1385	+	int rd = (opcode >> 12) & 0xf;
1386	+	int rn = (opcode >> 16) & 0xf;
1387	+	#if DEBUG
1388	+	static const char * reg_names[] = {
1389	+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1390	+	"r9", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
1391	+	};
1392	+	printf("%s %s register %s\n",
1393	+	transfer_size == SIZE_BYTE ? "byte" :
1394	+	transfer_size == SIZE_WORD ? "word" :
1395	+	transfer_size == SIZE_LONG ? "long" : "unknown",
1396	+	transfer_type == SIGSEGV_TRANSFER_LOAD ? "load to" : "store from",
1397	+	reg_names[rd]);
1398	+	#endif
1399	+
1400	+	unsigned int base = regs[rn];
1401	+	if (((opcode >> 24) & 1) == 1)
1402	+	base += offset;
1403	+
1404	+	if (transfer_type == SIGSEGV_TRANSFER_LOAD)
1405	+	regs[rd] = 0;
1406	+
1407	+	if (((opcode >> 24) & 1) == 0)                // post-index addressing
1408	+	regs[rn] += offset;
1409	+	else if (((opcode >> 21) & 1) == 1)   // write-back address into base
1410	+	regs[rn] = base;
1411	+
1412	+	regs[ARM_REG_PC] += 4;
1413	+	return true;
1414	+	}
1415	+	#endif
1416	+
1417
1418		// Fallbacks
1419		#ifndef SIGSEGV_FAULT_INSTRUCTION
#	Line 784 | Line 1422 | static bool powerpc_skip_instruction(uns
1422		#ifndef SIGSEGV_FAULT_HANDLER_ARGLIST_1
1423		#define SIGSEGV_FAULT_HANDLER_ARGLIST_1 SIGSEGV_FAULT_HANDLER_ARGLIST
1424		#endif
1425	+	#ifndef SIGSEGV_FAULT_HANDLER_INVOKE
1426	+	#define SIGSEGV_FAULT_HANDLER_INVOKE(ADDR, IP)  sigsegv_fault_handler(ADDR, IP)
1427	+	#endif
1428
1429		// SIGSEGV recovery supported ?
1430		#if defined(SIGSEGV_ALL_SIGNALS) && defined(SIGSEGV_FAULT_HANDLER_ARGLIST) && defined(SIGSEGV_FAULT_ADDRESS)
#	Line 804 | Line 1445 | static bool handle_badaccess(SIGSEGV_FAU
1445		sigsegv_address_t fault_instruction = (sigsegv_address_t)SIGSEGV_FAULT_INSTRUCTION;
1446
1447		// Call user's handler and reinstall the global handler, if required
1448	<	switch (sigsegv_fault_handler(fault_address, fault_instruction)) {
1448	>	switch (SIGSEGV_FAULT_HANDLER_INVOKE(fault_address, fault_instruction)) {
1449		case SIGSEGV_RETURN_SUCCESS:
1450		return true;
1451
#	Line 829 | Line 1470 | static bool handle_badaccess(SIGSEGV_FAU
1470		}
1471		break;
1472		#endif
1473	+	case SIGSEGV_RETURN_FAILURE:
1474	+	return false;
1475		}
1476
1477		// We can't do anything with the fault_address, dump state?
#	Line 1191 | Line 1834 | void sigsegv_set_dump_state(sigsegv_stat
1834		#include <sys/mman.h>
1835		#include "vm_alloc.h"
1836
1837	+	const int REF_INDEX = 123;
1838	+	const int REF_VALUE = 45;
1839	+
1840		static int page_size;
1841		static volatile char * page = 0;
1842		static volatile int handler_called = 0;
1843
1844	+	#ifdef __GNUC__
1845	+	// Code range where we expect the fault to come from
1846	+	static void *b_region, *e_region;
1847	+	#endif
1848	+
1849		static sigsegv_return_t sigsegv_test_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
1850		{
1851	+	#if DEBUG
1852	+	printf("sigsegv_test_handler(%p, %p)\n", fault_address, instruction_address);
1853	+	printf("expected fault at %p\n", page + REF_INDEX);
1854	+	#ifdef __GNUC__
1855	+	printf("expected instruction address range: %p-%p\n", b_region, e_region);
1856	+	#endif
1857	+	#endif
1858		handler_called++;
1859	<	if ((fault_address - 123) != page)
1859	>	if ((fault_address - REF_INDEX) != page)
1860		exit(10);
1861	<	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
1861	>	#ifdef __GNUC__
1862	>	// Make sure reported fault instruction address falls into
1863	>	// expected code range
1864	>	if (instruction_address != SIGSEGV_INVALID_PC
1865	>	&& ((instruction_address <  (sigsegv_address_t)b_region) ||
1866	>	(instruction_address >= (sigsegv_address_t)e_region)))
1867		exit(11);
1868	+	#endif
1869	+	if (vm_protect((char *)((unsigned long)fault_address & -page_size), page_size, VM_PAGE_READ | VM_PAGE_WRITE) != 0)
1870	+	exit(12);
1871		return SIGSEGV_RETURN_SUCCESS;
1872		}
1873
1874		#ifdef HAVE_SIGSEGV_SKIP_INSTRUCTION
1209	–	#ifdef __GNUC__
1210	–	// Code range where we expect the fault to come from
1211	–	static void *b_region, *e_region;
1212	–	#endif
1213	–
1875		static sigsegv_return_t sigsegv_insn_handler(sigsegv_address_t fault_address, sigsegv_address_t instruction_address)
1876		{
1877	+	#if DEBUG
1878	+	printf("sigsegv_insn_handler(%p, %p)\n", fault_address, instruction_address);
1879	+	#endif
1880		if (((unsigned long)fault_address - (unsigned long)page) < page_size) {
1881		#ifdef __GNUC__
1882		// Make sure reported fault instruction address falls into
#	Line 1227 | Line 1891 | static sigsegv_return_t sigsegv_insn_han
1891
1892		return SIGSEGV_RETURN_FAILURE;
1893		}
1894	+
1895	+	// More sophisticated tests for instruction skipper
1896	+	static bool arch_insn_skipper_tests()
1897	+	{
1898	+	#if (defined(i386) || defined(__i386__)) || defined(__x86_64__)
1899	+	static const unsigned char code[] = {
1900	+	0x8a, 0x00,                    // mov    (%eax),%al
1901	+	0x8a, 0x2c, 0x18,              // mov    (%eax,%ebx,1),%ch
1902	+	0x88, 0x20,                    // mov    %ah,(%eax)
1903	+	0x88, 0x08,                    // mov    %cl,(%eax)
1904	+	0x66, 0x8b, 0x00,              // mov    (%eax),%ax
1905	+	0x66, 0x8b, 0x0c, 0x18,        // mov    (%eax,%ebx,1),%cx
1906	+	0x66, 0x89, 0x00,              // mov    %ax,(%eax)
1907	+	0x66, 0x89, 0x0c, 0x18,        // mov    %cx,(%eax,%ebx,1)
1908	+	0x8b, 0x00,                    // mov    (%eax),%eax
1909	+	0x8b, 0x0c, 0x18,              // mov    (%eax,%ebx,1),%ecx
1910	+	0x89, 0x00,                    // mov    %eax,(%eax)
1911	+	0x89, 0x0c, 0x18,              // mov    %ecx,(%eax,%ebx,1)
1912	+	#if defined(__x86_64__)
1913	+	0x44, 0x8a, 0x00,              // mov    (%rax),%r8b
1914	+	0x44, 0x8a, 0x20,              // mov    (%rax),%r12b
1915	+	0x42, 0x8a, 0x3c, 0x10,        // mov    (%rax,%r10,1),%dil
1916	+	0x44, 0x88, 0x00,              // mov    %r8b,(%rax)
1917	+	0x44, 0x88, 0x20,              // mov    %r12b,(%rax)
1918	+	0x42, 0x88, 0x3c, 0x10,        // mov    %dil,(%rax,%r10,1)
1919	+	0x66, 0x44, 0x8b, 0x00,        // mov    (%rax),%r8w
1920	+	0x66, 0x42, 0x8b, 0x0c, 0x10,  // mov    (%rax,%r10,1),%cx
1921	+	0x66, 0x44, 0x89, 0x00,        // mov    %r8w,(%rax)
1922	+	0x66, 0x42, 0x89, 0x0c, 0x10,  // mov    %cx,(%rax,%r10,1)
1923	+	0x44, 0x8b, 0x00,              // mov    (%rax),%r8d
1924	+	0x42, 0x8b, 0x0c, 0x10,        // mov    (%rax,%r10,1),%ecx
1925	+	0x44, 0x89, 0x00,              // mov    %r8d,(%rax)
1926	+	0x42, 0x89, 0x0c, 0x10,        // mov    %ecx,(%rax,%r10,1)
1927	+	0x48, 0x8b, 0x08,              // mov    (%rax),%rcx
1928	+	0x4c, 0x8b, 0x18,              // mov    (%rax),%r11
1929	+	0x4a, 0x8b, 0x0c, 0x10,        // mov    (%rax,%r10,1),%rcx
1930	+	0x4e, 0x8b, 0x1c, 0x10,        // mov    (%rax,%r10,1),%r11
1931	+	0x48, 0x89, 0x08,              // mov    %rcx,(%rax)
1932	+	0x4c, 0x89, 0x18,              // mov    %r11,(%rax)
1933	+	0x4a, 0x89, 0x0c, 0x10,        // mov    %rcx,(%rax,%r10,1)
1934	+	0x4e, 0x89, 0x1c, 0x10,        // mov    %r11,(%rax,%r10,1)
1935	+	#endif
1936	+	0                              // end
1937	+	};
1938	+	const int N_REGS = 20;
1939	+	unsigned long regs[N_REGS];
1940	+	for (int i = 0; i < N_REGS; i++)
1941	+	regs[i] = i;
1942	+	const unsigned long start_code = (unsigned long)&code;
1943	+	regs[X86_REG_EIP] = start_code;
1944	+	while ((regs[X86_REG_EIP] - start_code) < (sizeof(code) - 1)
1945	+	&& ix86_skip_instruction(regs))
1946	+	; /* simply iterate */
1947	+	return (regs[X86_REG_EIP] - start_code) == (sizeof(code) - 1);
1948	+	#endif
1949	+	return true;
1950	+	}
1951		#endif
1952
1953		int main(void)
#	Line 1238 | Line 1959 | int main(void)
1959		if ((page = (char *)vm_acquire(page_size)) == VM_MAP_FAILED)
1960		return 2;
1961
1962	+	memset((void *)page, 0, page_size);
1963		if (vm_protect((char *)page, page_size, VM_PAGE_READ) < 0)
1964		return 3;
1965
1966		if (!sigsegv_install_handler(sigsegv_test_handler))
1967		return 4;
1968
1969	<	page[123] = 45;
1970	<	page[123] = 45;
1971	<
1969	>	#ifdef __GNUC__
1970	>	b_region = &&L_b_region1;
1971	>	e_region = &&L_e_region1;
1972	>	#endif
1973	>	L_b_region1:
1974	>	page[REF_INDEX] = REF_VALUE;
1975	>	if (page[REF_INDEX] != REF_VALUE)
1976	>	exit(20);
1977	>	page[REF_INDEX] = REF_VALUE;
1978	>	L_e_region1:
1979	>
1980		if (handler_called != 1)
1981		return 5;
1982
#	Line 1264 | Line 1994 | int main(void)
1994		return 8;
1995
1996		#define TEST_SKIP_INSTRUCTION(TYPE) do {                                \
1997	<	const unsigned int TAG = 0x12345678;                    \
1997	>	const unsigned long TAG = 0x12345678 |                  \
1998	>	(sizeof(long) == 8 ? 0x9abcdef0UL << 31 : 0);   \
1999		TYPE data = *((TYPE *)(page + sizeof(TYPE)));   \
2000	<	volatile unsigned int effect = data + TAG;              \
2000	>	volatile unsigned long effect = data + TAG;             \
2001		if (effect != TAG)                                                              \
2002		return 9;                                                                       \
2003		} while (0)
2004
2005		#ifdef __GNUC__
2006	<	b_region = &&L_b_region;
2007	<	e_region = &&L_e_region;
2006	>	b_region = &&L_b_region2;
2007	>	e_region = &&L_e_region2;
2008		#endif
2009	<	L_b_region:
2009	>	L_b_region2:
2010		TEST_SKIP_INSTRUCTION(unsigned char);
2011		TEST_SKIP_INSTRUCTION(unsigned short);
2012		TEST_SKIP_INSTRUCTION(unsigned int);
2013	<	L_e_region:
2013	>	TEST_SKIP_INSTRUCTION(unsigned long);
2014	>	TEST_SKIP_INSTRUCTION(signed char);
2015	>	TEST_SKIP_INSTRUCTION(signed short);
2016	>	TEST_SKIP_INSTRUCTION(signed int);
2017	>	TEST_SKIP_INSTRUCTION(signed long);
2018	>	L_e_region2:
2019	>
2020	>	if (!arch_insn_skipper_tests())
2021	>	return 20;
2022		#endif
2023
2024		vm_exit();

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