421 |
|
printf("WARNING: Cannot detect CPU type, assuming 68020\n"); |
422 |
|
CPUType = 2; |
423 |
|
} |
424 |
< |
FPUType = 0; //!! |
424 |
> |
FPUType = 1; // NetBSD has an FPU emulation, so the FPU ought to be available at all times |
425 |
|
TwentyFourBitAddressing = false; |
426 |
|
#endif |
427 |
|
|
946 |
|
|
947 |
|
#define STORE_SR(v) \ |
948 |
|
scp->sc_ps = (v) & 0xff; \ |
949 |
< |
EmulatedSR = (v) & 0x2700; \ |
949 |
> |
EmulatedSR = (v) & 0xe700; \ |
950 |
|
if (((v) & 0x0700) == 0 && InterruptFlags) \ |
951 |
|
TriggerInterrupt(); |
952 |
|
|
1009 |
|
case 0x007c: { // ori #xxxx,sr |
1010 |
|
uint16 sr = GET_SR | pc[1]; |
1011 |
|
scp->sc_ps = sr & 0xff; // oring bits into the sr can't enable interrupts, so we don't need to call STORE_SR |
1012 |
< |
EmulatedSR = sr & 0x2700; |
1012 |
> |
EmulatedSR = sr & 0xe700; |
1013 |
|
INC_PC(4); |
1014 |
|
break; |
1015 |
|
} |
1086 |
|
} |
1087 |
|
|
1088 |
|
case 0xf327: // fsave -(sp) |
1089 |
< |
goto ill; //!! |
1089 |
> |
if (CPUIs68060) { |
1090 |
> |
regs->a[7] -= 4; |
1091 |
> |
WriteMacInt32(regs->a[7], 0x60000000); // Idle frame |
1092 |
> |
regs->a[7] -= 4; |
1093 |
> |
WriteMacInt32(regs->a[7], 0); |
1094 |
> |
regs->a[7] -= 4; |
1095 |
> |
WriteMacInt32(regs->a[7], 0); |
1096 |
> |
} else { |
1097 |
> |
regs->a[7] -= 4; |
1098 |
> |
WriteMacInt32(regs->a[7], 0x41000000); // Idle frame |
1099 |
> |
} |
1100 |
> |
scp->sc_sp = regs->a[7]; |
1101 |
> |
INC_PC(2); |
1102 |
> |
break; |
1103 |
|
|
1104 |
|
case 0xf35f: // frestore (sp)+ |
1105 |
< |
goto ill; //!! |
1105 |
> |
if (CPUIs68060) |
1106 |
> |
regs->a[7] += 12; |
1107 |
> |
else |
1108 |
> |
regs->a[7] += 4; |
1109 |
> |
scp->sc_sp = regs->a[7]; |
1110 |
> |
INC_PC(2); |
1111 |
> |
break; |
1112 |
|
|
1113 |
< |
case 0x4e73: { // rte (only handles format 0) |
1113 |
> |
case 0x4e73: { // rte |
1114 |
|
uint32 a7 = regs->a[7]; |
1115 |
|
uint16 sr = ReadMacInt16(a7); |
1116 |
|
a7 += 2; |
1117 |
|
scp->sc_ps = sr & 0xff; |
1118 |
< |
EmulatedSR = sr & 0x2700; |
1118 |
> |
EmulatedSR = sr & 0xe700; |
1119 |
|
scp->sc_pc = ReadMacInt32(a7); |
1120 |
< |
a7 += 6; |
1121 |
< |
scp->sc_sp = regs->a[7] = a7; |
1120 |
> |
a7 += 4; |
1121 |
> |
uint16 format = ReadMacInt16(a7) >> 12; |
1122 |
> |
a7 += 2; |
1123 |
> |
static const int frame_adj[16] = { |
1124 |
> |
0, 0, 4, 4, 8, 0, 0, 52, 50, 12, 24, 84, 16, 0, 0, 0 |
1125 |
> |
}; |
1126 |
> |
scp->sc_sp = regs->a[7] = a7 + frame_adj[format]; |
1127 |
|
break; |
1128 |
|
} |
1129 |
|
|
1130 |
|
case 0x4e7a: // movec cr,x |
1131 |
|
switch (pc[1]) { |
1108 |
– |
case 0x8801: // movec vbr,a0 |
1109 |
– |
regs->a[0] = 0; |
1110 |
– |
break; |
1111 |
– |
case 0x9801: // movec vbr,a1 |
1112 |
– |
regs->a[1] = 0; |
1113 |
– |
break; |
1132 |
|
case 0x0002: // movec cacr,d0 |
1133 |
|
regs->d[0] = 0x3111; |
1134 |
|
break; |
1136 |
|
regs->d[1] = 0x3111; |
1137 |
|
break; |
1138 |
|
case 0x0003: // movec tc,d0 |
1139 |
+ |
case 0x0004: // movec itt0,d0 |
1140 |
+ |
case 0x0005: // movec itt1,d0 |
1141 |
+ |
case 0x0006: // movec dtt0,d0 |
1142 |
+ |
case 0x0007: // movec dtt1,d0 |
1143 |
+ |
case 0x0806: // movec urp,d0 |
1144 |
+ |
case 0x0807: // movec srp,d0 |
1145 |
|
regs->d[0] = 0; |
1146 |
|
break; |
1147 |
+ |
case 0x1000: // movec sfc,d1 |
1148 |
+ |
case 0x1001: // movec dfc,d1 |
1149 |
|
case 0x1003: // movec tc,d1 |
1150 |
+ |
case 0x1801: // movec vbr,d1 |
1151 |
|
regs->d[1] = 0; |
1152 |
|
break; |
1153 |
+ |
case 0x8801: // movec vbr,a0 |
1154 |
+ |
regs->a[0] = 0; |
1155 |
+ |
break; |
1156 |
+ |
case 0x9801: // movec vbr,a1 |
1157 |
+ |
regs->a[1] = 0; |
1158 |
+ |
break; |
1159 |
|
default: |
1160 |
|
goto ill; |
1161 |
|
} |
1164 |
|
|
1165 |
|
case 0x4e7b: // movec x,cr |
1166 |
|
switch (pc[1]) { |
1167 |
+ |
case 0x1000: // movec d1,sfc |
1168 |
+ |
case 0x1001: // movec d1,dfc |
1169 |
|
case 0x0801: // movec d0,vbr |
1170 |
+ |
case 0x1801: // movec d1,vbr |
1171 |
|
break; |
1172 |
|
case 0x0002: // movec d0,cacr |
1173 |
|
case 0x1002: // movec d1,cacr |