| 28 |
|
XDEF _AtomicAnd |
| 29 |
|
XDEF _AtomicOr |
| 30 |
|
XDEF _MoveVBR |
| 31 |
< |
XDEF _TimevalTo64 |
| 32 |
< |
XDEF _TimevalToMacTime |
| 31 |
> |
XDEF _DisableSuperBypass |
| 32 |
|
XDEF _Execute68k |
| 33 |
|
XDEF _Execute68kTrap |
| 34 |
|
XDEF _TrapHandlerAsm |
| 36 |
|
XDEF _Scod060Patch1 |
| 37 |
|
XDEF _Scod060Patch2 |
| 38 |
|
XDEF _ThInitFPUPatch |
| 39 |
+ |
XDEF _AsmTriggerNMI |
| 40 |
|
|
| 41 |
|
XREF _OldTrapHandler |
| 42 |
|
XREF _OldExceptionHandler |
| 51 |
|
|
| 52 |
|
SECTION text,CODE |
| 53 |
|
|
| 54 |
+ |
MACHINE 68020 |
| 55 |
+ |
|
| 56 |
|
* |
| 57 |
|
* Atomic bit operations (don't trust the compiler) |
| 58 |
|
* |
| 110 |
|
rte |
| 111 |
|
|
| 112 |
|
* |
| 113 |
< |
* Convert timeval to 64 bit microseconds |
| 113 |
> |
* Disable 68060 Super Bypass mode |
| 114 |
|
* |
| 115 |
|
|
| 116 |
< |
_TimevalTo64 move.l 4(sp),a0 ;Pointer to timeval |
| 117 |
< |
move.l 8(sp),a1 ;Pointer to high longword of result, low longword is returned in d0 |
| 118 |
< |
|
| 117 |
< |
move.l d2,-(sp) |
| 116 |
> |
_DisableSuperBypass |
| 117 |
> |
movem.l d0-d1/a0-a1/a5-a6,-(sp) |
| 118 |
> |
move.l _SysBase,a6 |
| 119 |
|
|
| 120 |
< |
move.l TV_SECS(a0),d0 ;Convert to 64 bit microseconds |
| 121 |
< |
mulu.l #1000000,d1:d0 |
| 121 |
< |
add.l TV_MICRO(a0),d0 |
| 122 |
< |
moveq #0,d2 |
| 123 |
< |
addx.l d2,d1 |
| 124 |
< |
move.l d1,(a1) |
| 120 |
> |
lea dissb,a5 |
| 121 |
> |
JSRLIB Supervisor |
| 122 |
|
|
| 123 |
< |
move.l (sp)+,d2 |
| 123 |
> |
movem.l (sp)+,d0-d1/a0-a1/a5-a6 |
| 124 |
|
rts |
| 125 |
|
|
| 126 |
< |
* |
| 130 |
< |
* Convert timeval to Mac time value (>0: milliseconds, <0: microseconds) |
| 131 |
< |
* |
| 132 |
< |
|
| 133 |
< |
_TimevalToMacTime |
| 134 |
< |
move.l 4(sp),a0 ;Pointer to timeval |
| 126 |
> |
MACHINE 68060 |
| 127 |
|
|
| 128 |
< |
move.l d2,-(sp) |
| 129 |
< |
|
| 130 |
< |
move.l TV_SECS(a0),d0 ;Convert to 64 bit microseconds |
| 131 |
< |
mulu.l #1000000,d1:d0 |
| 140 |
< |
add.l TV_MICRO(a0),d0 |
| 141 |
< |
moveq #0,d2 |
| 142 |
< |
addx.l d2,d1 |
| 143 |
< |
|
| 144 |
< |
tst.l d1 ;Too large for 32 bit microseconds? |
| 145 |
< |
bne.s 1$ |
| 146 |
< |
cmp.l #$7fffffff,d0 |
| 147 |
< |
bhi.s 1$ |
| 148 |
< |
|
| 149 |
< |
neg.l d0 ;No, return negative microseconds |
| 150 |
< |
bra.s 2$ |
| 128 |
> |
dissb movec pcr,d0 |
| 129 |
> |
bset #5,d0 |
| 130 |
> |
movec d0,pcr |
| 131 |
> |
rte |
| 132 |
|
|
| 133 |
< |
1$ divu.l #1000,d1:d0 ;Yes, return milliseconds |
| 153 |
< |
|
| 154 |
< |
2$ move.l (sp)+,d2 |
| 155 |
< |
rts |
| 133 |
> |
MACHINE 68020 |
| 134 |
|
|
| 135 |
|
* |
| 136 |
|
* Execute 68k subroutine (must be ended with rts) |
| 210 |
|
pea 1$ |
| 211 |
|
move.w _EmulatedSR,d0 |
| 212 |
|
move.w d0,-(sp) |
| 213 |
< |
or.w #$0100,d0 ;Set interrupt level in SR |
| 213 |
> |
or.w #$2100,d0 ;Set interrupt level in SR, enter (virtual) supervisor mode |
| 214 |
|
move.w d0,_EmulatedSR |
| 215 |
< |
move.l $64.w,a0 ;Jump to MacOS interrupt handler |
| 216 |
< |
jmp (a0) |
| 215 |
> |
move.l $64.w,-(sp) ;Jump to MacOS interrupt handler |
| 216 |
> |
rts |
| 217 |
|
|
| 218 |
|
1$ move.l (sp)+,d0 ;Restore d0 |
| 219 |
|
rts |
| 304 |
|
* Trap handler of main task |
| 305 |
|
* |
| 306 |
|
|
| 307 |
< |
_TrapHandlerAsm cmp.l #4,(sp) ;Illegal instruction? |
| 307 |
> |
_TrapHandlerAsm: |
| 308 |
> |
cmp.l #4,(sp) ;Illegal instruction? |
| 309 |
|
beq.s doillinstr |
| 310 |
|
cmp.l #10,(sp) ;A-Line exception? |
| 311 |
|
beq.s doaline |
| 312 |
|
cmp.l #8,(sp) ;Privilege violation? |
| 313 |
|
beq.s doprivviol |
| 314 |
+ |
cmp.l #9,(sp) ;Trace? |
| 315 |
+ |
beq dotrace |
| 316 |
+ |
cmp.l #3,(sp) ;Illegal Address? |
| 317 |
+ |
beq.s doilladdr |
| 318 |
+ |
|
| 319 |
+ |
cmp.l #32,(sp) |
| 320 |
+ |
blt 1$ |
| 321 |
+ |
cmp.l #47,(sp) |
| 322 |
+ |
ble doTrapXX ; Vector 32-47 : TRAP #0 - 15 Instruction Vectors |
| 323 |
+ |
|
| 324 |
+ |
1$ move.l _OldTrapHandler,-(sp) ;No, jump to old trap handler |
| 325 |
+ |
rts |
| 326 |
+ |
|
| 327 |
+ |
* |
| 328 |
+ |
* TRAP #0 - 15 Instruction Vectors |
| 329 |
+ |
* |
| 330 |
+ |
|
| 331 |
+ |
doTrapXX move.l a0,(sp) ;Save a0 |
| 332 |
+ |
move.l usp,a0 ;Get user stack pointer |
| 333 |
+ |
move.l 2*4(sp),-(a0) ;Copy 4-word stack frame to user stack |
| 334 |
+ |
move.l 1*4(sp),-(a0) |
| 335 |
+ |
move.l a0,usp ;Update USP |
| 336 |
+ |
move.l (sp)+,a0 ;Restore a0 |
| 337 |
+ |
|
| 338 |
+ |
addq.l #4*2,sp ;Remove exception frame from supervisor stack |
| 339 |
+ |
andi #$d8ff,sr ;Switch to user mode, enable interrupts |
| 340 |
|
|
| 341 |
< |
move.l _OldTrapHandler,-(sp) ;No, jump to old trap handler |
| 341 |
> |
move.l $2d*4.w,-(sp) ;Jump to MacOS exception handler |
| 342 |
|
rts |
| 343 |
|
|
| 344 |
+ |
|
| 345 |
+ |
* |
| 346 |
+ |
* trace Vector |
| 347 |
+ |
* |
| 348 |
+ |
|
| 349 |
+ |
dotrace move.l a0,(sp) ;Save a0 |
| 350 |
+ |
|
| 351 |
+ |
move.l usp,a0 ;Get user stack pointer |
| 352 |
+ |
move.l 3*4(sp),-(a0) ;Copy 6-word stack frame to user stack |
| 353 |
+ |
move.l 2*4(sp),-(a0) |
| 354 |
+ |
move.l 1*4(sp),-(a0) |
| 355 |
+ |
move.l a0,usp ;Update USP |
| 356 |
+ |
move.l (sp)+,a0 ;Restore a0 |
| 357 |
+ |
|
| 358 |
+ |
lea 6*2(sp),sp ;Remove exception frame from supervisor stack |
| 359 |
+ |
andi #$18ff,sr ;Switch to user mode, enable interrupts, disable trace |
| 360 |
+ |
|
| 361 |
+ |
move.l $24.w,-(sp) ;Jump to MacOS exception handler |
| 362 |
+ |
rts |
| 363 |
+ |
|
| 364 |
+ |
|
| 365 |
|
* |
| 366 |
|
* A-Line handler: call MacOS A-Line handler |
| 367 |
|
* |
| 380 |
|
rts |
| 381 |
|
|
| 382 |
|
* |
| 383 |
+ |
* Illegal address handler |
| 384 |
+ |
* |
| 385 |
+ |
|
| 386 |
+ |
doilladdr move.l a0,(sp) ;Save a0 |
| 387 |
+ |
|
| 388 |
+ |
move.l usp,a0 ;Get user stack pointer |
| 389 |
+ |
move.l 3*4(sp),-(a0) ;Copy 6-word stack frame to user stack |
| 390 |
+ |
move.l 2*4(sp),-(a0) |
| 391 |
+ |
move.l 1*4(sp),-(a0) |
| 392 |
+ |
move.l a0,usp ;Update USP |
| 393 |
+ |
move.l (sp)+,a0 ;Restore a0 |
| 394 |
+ |
|
| 395 |
+ |
lea 6*2(sp),sp ;Remove exception frame from supervisor stack |
| 396 |
+ |
andi #$d8ff,sr ;Switch to user mode, enable interrupts |
| 397 |
+ |
|
| 398 |
+ |
move.l $0c.w,-(sp) ;Jump to MacOS exception handler |
| 399 |
+ |
rts |
| 400 |
+ |
|
| 401 |
+ |
|
| 402 |
+ |
* |
| 403 |
|
* Illegal instruction handler: call IllInstrHandler() (which calls EmulOp()) |
| 404 |
|
* to execute extended opcodes (see emul_op.h) |
| 405 |
|
* |
| 406 |
|
|
| 407 |
< |
doillinstr move.l a6,(sp) ;Save a6 |
| 407 |
> |
doillinstr movem.l a0/d0,-(sp) |
| 408 |
> |
move.w ([6+2*4,sp]),d0 |
| 409 |
> |
and.w #$ff00,d0 |
| 410 |
> |
cmp.w #$7100,d0 |
| 411 |
> |
movem.l (sp)+,a0/d0 |
| 412 |
> |
beq 1$ |
| 413 |
> |
|
| 414 |
> |
move.l a0,(sp) ;Save a0 |
| 415 |
> |
move.l usp,a0 ;Get user stack pointer |
| 416 |
> |
move.l 8(sp),-(a0) ;Copy stack frame to user stack |
| 417 |
> |
move.l 4(sp),-(a0) |
| 418 |
> |
move.l a0,usp ;Update USP |
| 419 |
> |
move.l (sp)+,a0 ;Restore a0 |
| 420 |
> |
|
| 421 |
> |
add.w #3*4,sp ;Remove exception frame from supervisor stack |
| 422 |
> |
andi #$d8ff,sr ;Switch to user mode, enable interrupts |
| 423 |
> |
|
| 424 |
> |
move.l $10.w,-(sp) ;Jump to MacOS exception handler |
| 425 |
> |
rts |
| 426 |
> |
|
| 427 |
> |
1$ move.l a6,(sp) ;Save a6 |
| 428 |
|
move.l usp,a6 ;Get user stack pointer |
| 429 |
|
|
| 430 |
|
move.l a6,-10(a6) ;Push USP (a7) |
| 479 |
|
cmp.w #$40d0,d0 ;move sr,(a0)? |
| 480 |
|
beq movefromsra0 |
| 481 |
|
cmp.w #$40d7,d0 ;move sr,(sp)? |
| 482 |
< |
beq movefromsra0 |
| 482 |
> |
beq movefromsrsp |
| 483 |
|
|
| 484 |
|
cmp.w #$f327,d0 ;fsave -(sp)? |
| 485 |
|
beq fsavepush |
| 486 |
|
cmp.w #$f35f,d0 ;frestore (sp)+? |
| 487 |
|
beq frestorepop |
| 488 |
+ |
cmp.w #$f32d,d0 ;fsave xxx(a5) ? |
| 489 |
+ |
beq fsavea5 |
| 490 |
+ |
cmp.w #$f36d,d0 ;frestore xxx(a5) ? |
| 491 |
+ |
beq frestorea5 |
| 492 |
|
|
| 493 |
|
cmp.w #$4e73,d0 ;rte? |
| 494 |
|
beq pvrte |
| 537 |
|
cmp.w #$f4f8,d0 ;cpusha dc/ic? |
| 538 |
|
beq cpushadcic |
| 539 |
|
|
| 540 |
+ |
cmp.w #$4e69,d0 ;move usp,a1 |
| 541 |
+ |
beq moveuspa1 |
| 542 |
+ |
cmp.w #$4e68,d0 ;move usp,a0 |
| 543 |
+ |
beq moveuspa0 |
| 544 |
+ |
|
| 545 |
+ |
cmp.w #$4e61,d0 ;move a1,usp |
| 546 |
+ |
beq moved1usp |
| 547 |
+ |
|
| 548 |
|
pv_unhandled move.l (sp),d0 ;Unhandled instruction, jump to handler in main.cpp |
| 549 |
|
move.l a6,(sp) ;Save a6 |
| 550 |
|
move.l usp,a6 ;Get user stack pointer |
| 586 |
|
move.w (a0)+,d0 ;Get SR from user stack |
| 587 |
|
move.w d0,8(sp) ;Store into CCR on exception stack frame |
| 588 |
|
and.w #$00ff,8(sp) |
| 589 |
< |
and.w #$2700,d0 ;Extract supervisor bits |
| 589 |
> |
and.w #$e700,d0 ;Extract supervisor bits |
| 590 |
|
move.w d0,_EmulatedSR ;And save them |
| 591 |
|
|
| 592 |
|
and.w #$0700,d0 ;Rethrow exception if interrupts are pending and reenabled |
| 612 |
|
or.w ([6,sp],2),d0 ;Or with immediate value |
| 613 |
|
move.w d0,4(sp) ;Store into CCR on stack |
| 614 |
|
and.w #$00ff,4(sp) |
| 615 |
< |
and.w #$2700,d0 ;Extract supervisor bits |
| 615 |
> |
and.w #$e700,d0 ;Extract supervisor bits |
| 616 |
|
move.w d0,_EmulatedSR ;And save them |
| 617 |
|
move.l (sp)+,d0 ;Restore d0 |
| 618 |
|
addq.l #4,2(sp) ;Skip instruction |
| 624 |
|
and.w ([6,sp],2),d0 ;And with immediate value |
| 625 |
|
storesr4 move.w d0,4(sp) ;Store into CCR on stack |
| 626 |
|
and.w #$00ff,4(sp) |
| 627 |
< |
and.w #$2700,d0 ;Extract supervisor bits |
| 627 |
> |
and.w #$e700,d0 ;Extract supervisor bits |
| 628 |
|
move.w d0,_EmulatedSR ;And save them |
| 629 |
|
|
| 630 |
|
and.w #$0700,d0 ;Rethrow exception if interrupts are pending and reenabled |
| 711 |
|
addq.l #2,2(sp) ;Skip instruction |
| 712 |
|
rte |
| 713 |
|
|
| 714 |
< |
; rte (only handles format 0) |
| 715 |
< |
pvrte move.l a0,-(sp) ;Save a0 |
| 714 |
> |
; frestore xxx(a5) +jl+ |
| 715 |
> |
frestorea5 move.l (sp),d0 ;Restore d0 |
| 716 |
> |
move.l a0,(sp) ;Save a0 |
| 717 |
> |
move.l a5,a0 ;Get base register |
| 718 |
> |
add.w ([6,sp],2),a0 ;Add offset to base register |
| 719 |
> |
frestore (a0) ;Restore FP state from (a0) |
| 720 |
> |
move.l (sp)+,a0 ;Restore a0 |
| 721 |
> |
addq.l #4,2(sp) ;Skip instruction |
| 722 |
> |
rte |
| 723 |
> |
|
| 724 |
> |
; fsave xxx(a5) +jl+ |
| 725 |
> |
fsavea5 move.l (sp),d0 ;Restore d0 |
| 726 |
> |
move.l a0,(sp) ;Save a0 |
| 727 |
> |
move.l a5,a0 ;Get base register |
| 728 |
> |
add.w ([6,sp],2),a0 ;Add offset to base register |
| 729 |
> |
fsave (a0) ;Push FP state to (a0) |
| 730 |
> |
move.l (sp)+,a0 ;Restore a0 |
| 731 |
> |
addq.l #4,2(sp) ;Skip instruction |
| 732 |
> |
rte |
| 733 |
> |
|
| 734 |
> |
; rte |
| 735 |
> |
pvrte movem.l a0/a1,-(sp) ;Save a0 and a1 |
| 736 |
|
move.l usp,a0 ;Get user stack pointer |
| 737 |
+ |
|
| 738 |
|
move.w (a0)+,d0 ;Get SR from user stack |
| 739 |
< |
move.w d0,8(sp) ;Store into CCR on exception stack frame |
| 740 |
< |
and.w #$00ff,8(sp) |
| 741 |
< |
and.w #$2700,d0 ;Extract supervisor bits |
| 739 |
> |
move.w d0,8+4(sp) ;Store into CCR on exception stack frame |
| 740 |
> |
and.w #$c0ff,8+4(sp) |
| 741 |
> |
and.w #$e700,d0 ;Extract supervisor bits |
| 742 |
|
move.w d0,_EmulatedSR ;And save them |
| 743 |
< |
move.l (a0)+,10(sp) ;Store return address in exception stack frame |
| 744 |
< |
addq.l #2,a0 ;Skip format word |
| 743 |
> |
move.l (a0)+,10+4(sp) ;Store return address in exception stack frame |
| 744 |
> |
|
| 745 |
> |
move.w (a0)+,d0 ;get format word |
| 746 |
> |
lsr.w #7,d0 ;get stack frame Id |
| 747 |
> |
lsr.w #4,d0 |
| 748 |
> |
and.w #$001e,d0 |
| 749 |
> |
move.w (StackFormatTable,pc,d0.w),d0 ; get total stack frame length |
| 750 |
> |
subq.w #4,d0 ; count only extra words |
| 751 |
> |
lea 16+4(sp),a1 ; destination address (in supervisor stack) |
| 752 |
> |
bra 1$ |
| 753 |
> |
|
| 754 |
> |
2$ move.w (a0)+,(a1)+ ; copy additional stack words back to supervisor stack |
| 755 |
> |
1$ dbf d0,2$ |
| 756 |
> |
|
| 757 |
|
move.l a0,usp ;Update USP |
| 758 |
< |
move.l (sp)+,a0 ;Restore a0 |
| 758 |
> |
movem.l (sp)+,a0/a1 ;Restore a0 and a1 |
| 759 |
|
move.l (sp)+,d0 ;Restore d0 |
| 760 |
|
rte |
| 761 |
|
|
| 762 |
+ |
; sizes of exceptions stack frames |
| 763 |
+ |
StackFormatTable: |
| 764 |
+ |
dc.w 4 ; Four-word stack frame, format $0 |
| 765 |
+ |
dc.w 4 ; Throwaway four-word stack frame, format $1 |
| 766 |
+ |
dc.w 6 ; Six-word stack frame, format $2 |
| 767 |
+ |
dc.w 6 ; MC68040 floating-point post-instruction stack frame, format $3 |
| 768 |
+ |
dc.w 8 ; MC68EC040 and MC68LC040 floating-point unimplemented stack frame, format $4 |
| 769 |
+ |
dc.w 4 ; Format $5 |
| 770 |
+ |
dc.w 4 ; Format $6 |
| 771 |
+ |
dc.w 30 ; MC68040 access error stack frame, Format $7 |
| 772 |
+ |
dc.w 29 ; MC68010 bus and address error stack frame, format $8 |
| 773 |
+ |
dc.w 10 ; MC68020 and MC68030 coprocessor mid-instruction stack frame, format $9 |
| 774 |
+ |
dc.w 16 ; MC68020 and MC68030 short bus cycle stack frame, format $a |
| 775 |
+ |
dc.w 46 ; MC68020 and MC68030 long bus cycle stack frame, format $b |
| 776 |
+ |
dc.w 12 ; CPU32 bus error for prefetches and operands stack frame, format $c |
| 777 |
+ |
dc.w 4 ; Format $d |
| 778 |
+ |
dc.w 4 ; Format $e |
| 779 |
+ |
dc.w 4 ; Format $f |
| 780 |
+ |
|
| 781 |
|
; move sr,dx |
| 782 |
|
movefromsrd0 addq.l #4,sp ;Skip saved d0 |
| 783 |
|
moveq #0,d0 |
| 839 |
|
movetosrd0 move.l (sp),d0 |
| 840 |
|
storesr2 move.w d0,4(sp) |
| 841 |
|
and.w #$00ff,4(sp) |
| 842 |
< |
and.w #$2700,d0 |
| 842 |
> |
and.w #$e700,d0 |
| 843 |
|
move.w d0,_EmulatedSR |
| 844 |
|
|
| 845 |
|
and.w #$0700,d0 ;Rethrow exception if interrupts are pending and reenabled |
| 884 |
|
beq.s movecvbra0 |
| 885 |
|
cmp.w #$9801,d0 ;movec vbr,a1? |
| 886 |
|
beq.s movecvbra1 |
| 887 |
+ |
cmp.w #$1801,d0 ;movec vbr,d1? |
| 888 |
+ |
beq movecvbrd1 |
| 889 |
|
cmp.w #$0002,d0 ;movec cacr,d0? |
| 890 |
|
beq.s moveccacrd0 |
| 891 |
|
cmp.w #$1002,d0 ;movec cacr,d1? |
| 894 |
|
beq.s movectcd0 |
| 895 |
|
cmp.w #$1003,d0 ;movec tc,d1? |
| 896 |
|
beq.s movectcd1 |
| 897 |
+ |
cmp.w #$1000,d0 ;movec sfc,d1? |
| 898 |
+ |
beq movecsfcd1 |
| 899 |
+ |
cmp.w #$1001,d0 ;movec dfc,d1? |
| 900 |
+ |
beq movecdfcd1 |
| 901 |
+ |
cmp.w #$0806,d0 ;movec urp,d0? |
| 902 |
+ |
beq movecurpd0 |
| 903 |
+ |
cmp.w #$0807,d0 ;movec srp,d0? |
| 904 |
+ |
beq.s movecsrpd0 |
| 905 |
+ |
cmp.w #$0004,d0 ;movec itt0,d0 |
| 906 |
+ |
beq.s movecitt0d0 |
| 907 |
+ |
cmp.w #$0005,d0 ;movec itt1,d0 |
| 908 |
+ |
beq.s movecitt1d0 |
| 909 |
+ |
cmp.w #$0006,d0 ;movec dtt0,d0 |
| 910 |
+ |
beq.s movecdtt0d0 |
| 911 |
+ |
cmp.w #$0007,d0 ;movec dtt1,d0 |
| 912 |
+ |
beq.s movecdtt1d0 |
| 913 |
|
|
| 914 |
|
bra pv_unhandled |
| 915 |
|
|
| 937 |
|
addq.l #4,2(sp) |
| 938 |
|
rte |
| 939 |
|
|
| 940 |
+ |
; movec vbr,d1 |
| 941 |
+ |
movecvbrd1 move.l (sp)+,d0 |
| 942 |
+ |
moveq.l #0,d1 ;VBR always appears to be at 0 |
| 943 |
+ |
addq.l #4,2(sp) |
| 944 |
+ |
rte |
| 945 |
+ |
|
| 946 |
|
; movec tc,d0 |
| 947 |
|
movectcd0 addq.l #4,sp |
| 948 |
|
moveq #0,d0 ;MMU is always off |
| 949 |
|
addq.l #4,2(sp) |
| 950 |
|
rte |
| 951 |
|
|
| 952 |
< |
; movec tc,d1 |
| 953 |
< |
movectcd1 addq.l #4,sp |
| 952 |
> |
; movec tc,d1 +jl+ |
| 953 |
> |
movectcd1 move.l (sp)+,d0 ;Restore d0 |
| 954 |
|
moveq #0,d1 ;MMU is always off |
| 955 |
|
addq.l #4,2(sp) |
| 956 |
|
rte |
| 957 |
|
|
| 958 |
+ |
; movec sfc,d1 +jl+ |
| 959 |
+ |
movecsfcd1 move.l (sp)+,d0 ;Restore d0 |
| 960 |
+ |
moveq #0,d1 |
| 961 |
+ |
addq.l #4,2(sp) |
| 962 |
+ |
rte |
| 963 |
+ |
|
| 964 |
+ |
; movec dfc,d1 +jl+ |
| 965 |
+ |
movecdfcd1 move.l (sp)+,d0 ;Restore d0 |
| 966 |
+ |
moveq #0,d1 |
| 967 |
+ |
addq.l #4,2(sp) |
| 968 |
+ |
rte |
| 969 |
+ |
|
| 970 |
+ |
movecurpd0 ; movec urp,d0 +jl+ |
| 971 |
+ |
movecsrpd0 ; movec srp,d0 |
| 972 |
+ |
movecitt0d0 ; movec itt0,d0 |
| 973 |
+ |
movecitt1d0 ; movec itt1,d0 |
| 974 |
+ |
movecdtt0d0 ; movec dtt0,d0 |
| 975 |
+ |
movecdtt1d0 ; movec dtt1,d0 |
| 976 |
+ |
addq.l #4,sp |
| 977 |
+ |
moveq.l #0,d0 ;MMU is always off |
| 978 |
+ |
addq.l #4,2(sp) ;skip instruction |
| 979 |
+ |
rte |
| 980 |
+ |
|
| 981 |
|
; movec x,cr |
| 982 |
|
movectocr move.w ([6,sp],2),d0 ;Get next instruction word |
| 983 |
|
|
| 984 |
|
cmp.w #$0801,d0 ;movec d0,vbr? |
| 985 |
|
beq.s movectovbr |
| 986 |
+ |
cmp.w #$1801,d0 ;movec d1,vbr? |
| 987 |
+ |
beq.s movectovbr |
| 988 |
|
cmp.w #$0002,d0 ;movec d0,cacr? |
| 989 |
|
beq.s movectocacr |
| 990 |
|
cmp.w #$1002,d0 ;movec d1,cacr? |
| 991 |
|
beq.s movectocacr |
| 992 |
+ |
cmp.w #$1000,d0 ;movec d1,sfc? |
| 993 |
+ |
beq.s movectoxfc |
| 994 |
+ |
cmp.w #$1001,d0 ;movec d1,dfc? |
| 995 |
+ |
beq.s movectoxfc |
| 996 |
|
|
| 997 |
|
bra pv_unhandled |
| 998 |
|
|
| 1010 |
|
addq.l #4,2(sp) |
| 1011 |
|
rte |
| 1012 |
|
|
| 1013 |
+ |
; movec x,sfc |
| 1014 |
+ |
; movec x,dfc |
| 1015 |
+ |
movectoxfc move.l (sp)+,d0 ;Ignore moves to SFC, DFC |
| 1016 |
+ |
addq.l #4,2(sp) |
| 1017 |
+ |
rte |
| 1018 |
+ |
|
| 1019 |
|
; cpusha |
| 1020 |
|
cpushadc |
| 1021 |
|
cpushadcic movem.l d1/a0-a1/a6,-(sp) ;Clear caches |
| 1026 |
|
addq.l #2,2(sp) |
| 1027 |
|
rte |
| 1028 |
|
|
| 1029 |
+ |
; move usp,a1 +jl+ |
| 1030 |
+ |
moveuspa1 move.l (sp)+,d0 |
| 1031 |
+ |
move usp,a1 |
| 1032 |
+ |
addq.l #2,2(sp) |
| 1033 |
+ |
rte |
| 1034 |
+ |
|
| 1035 |
+ |
; move usp,a0 +jl+ |
| 1036 |
+ |
moveuspa0 move.l (sp)+,d0 |
| 1037 |
+ |
move usp,a0 |
| 1038 |
+ |
addq.l #2,2(sp) |
| 1039 |
+ |
rte |
| 1040 |
+ |
|
| 1041 |
+ |
; move a1,usp +jl+ |
| 1042 |
+ |
moved1usp move.l (sp)+,d0 |
| 1043 |
+ |
move a1,usp |
| 1044 |
+ |
addq.l #2,2(sp) |
| 1045 |
+ |
rte |
| 1046 |
+ |
|
| 1047 |
+ |
; |
| 1048 |
+ |
; Trigger NMI (Pop up debugger) |
| 1049 |
+ |
; |
| 1050 |
+ |
|
| 1051 |
+ |
_AsmTriggerNMI move.l d0,-(sp) ;Save d0 |
| 1052 |
+ |
move.w #$007c,-(sp) ;Yes, fake NMI stack frame |
| 1053 |
+ |
pea 1$ |
| 1054 |
+ |
move.w _EmulatedSR,d0 |
| 1055 |
+ |
and.w #$f8ff,d0 ;Set interrupt level in SR |
| 1056 |
+ |
move.w d0,-(sp) |
| 1057 |
+ |
move.w d0,_EmulatedSR |
| 1058 |
+ |
|
| 1059 |
+ |
move.l $7c.w,-(sp) ;Jump to MacOS NMI handler |
| 1060 |
+ |
rts |
| 1061 |
+ |
|
| 1062 |
+ |
1$ move.l (sp)+,d0 ;Restore d0 |
| 1063 |
+ |
rts |
| 1064 |
+ |
|
| 1065 |
+ |
|
| 1066 |
|
END |
