[ViewVC] Diff of: cebix/BasiliskII/src/AmigaOS/asm

Comparing BasiliskII/src/AmigaOS/asm_support.asm (file contents):
Revision 1.8 by cebix, 2001-01-25T22:24:36Z vs.
Revision 1.14 by cebix, 2002-09-01T12:01:46Z

#	Line 1 \| Line 1
1		*
2		* asm_support.asm - AmigaOS utility functions in assembly language
3		*
4	<	* Basilisk II (C) 1997-1999 Christian Bauer
4	>	* Basilisk II (C) 1997-2001 Christian Bauer
5		*
6		* This program is free software; you can redistribute it and/or modify
7		* it under the terms of the GNU General Public License as published by
#	Line 18 \| Line 18
18		* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19		*
20
21	+	DEBUG_DETAIL SET 1
22	+
23		INCLUDE "exec/types.i"
24		INCLUDE "exec/macros.i"
25		INCLUDE "exec/memory.i"
#	Line 25 \| Line 27
27		INCLUDE "dos/dos.i"
28		INCLUDE "devices/timer.i"
29
30	+	; INCLUDE "asmsupp.i"
31	+
32		XDEF _AtomicAnd
33		XDEF _AtomicOr
34		XDEF _MoveVBR
#	Line 33 \| Line 37
37		XDEF _Execute68kTrap
38		XDEF _TrapHandlerAsm
39		XDEF _ExceptionHandlerAsm
36	–	XDEF _Scod060Patch1
37	–	XDEF _Scod060Patch2
38	–	XDEF _ThInitFPUPatch
40		XDEF _AsmTriggerNMI
41
42		XREF _OldTrapHandler
#	Line 49 \| Line 50
50		XREF _SysBase
51		XREF _quit_emulator
52
53	+	INFO_LEVEL equ 0
54	+
55		SECTION text,CODE
56
57		MACHINE 68020
58
59	+	IFGE INFO_LEVEL
60	+	subSysName: dc.b '+',0
61	+	ENDIF
62	+
63		*
64		* Atomic bit operations (don't trust the compiler)
65		*
#	Line 194 \| Line 201 \| _Execute68kTrap
201		rts
202
203		*
204	<	* Exception handler of main task (for 60Hz interrupts)
204	>	* Exception handler of main task (for interrupts)
205		*
206
207		_ExceptionHandlerAsm
#	Line 244 \| Line 251 \| _ExceptionHandlerAsm
251		rts
252
253		*
247	–	* Process Manager 68060 FPU patches
248	–	*
249	–
250	–	_Scod060Patch1 fsave -(sp) ;Save FPU state
251	–	tst.b 2(sp) ;Null?
252	–	beq.s 1$
253	–	fmovem.x fp0-fp7,-(sp) ;No, save FPU registers
254	–	fmove.l fpiar,-(sp)
255	–	fmove.l fpsr,-(sp)
256	–	fmove.l fpcr,-(sp)
257	–	pea -1 ;Push "FPU state saved" flag
258	–	1$ move.l d1,-(sp)
259	–	move.l d0,-(sp)
260	–	bsr.s 3$ ;Switch integer registers and stack
261	–	addq.l #8,sp
262	–	tst.b 2(sp) ;New FPU state null or "FPU state saved" flag set?
263	–	beq.s 2$
264	–	addq.l #4,sp ;Flag set, skip it
265	–	fmove.l (sp)+,fpcr ;Restore FPU registers and state
266	–	fmove.l (sp)+,fpsr
267	–	fmove.l (sp)+,fpiar
268	–	fmovem.x (sp)+,fp0-fp7
269	–	2$ frestore (sp)+
270	–	movem.l (sp)+,d0-d1
271	–	rts
272	–
273	–	3$ move.l 4(sp),a0 ;Switch integer registers and stack
274	–	move sr,-(sp)
275	–	movem.l d2-d7/a2-a6,-(sp)
276	–	cmp.w #0,a0
277	–	beq.s 4$
278	–	move.l sp,(a0)
279	–	4$ move.l $36(sp),a0
280	–	movem.l (a0)+,d2-d7/a2-a6
281	–	move (a0)+,sr
282	–	move.l a0,sp
283	–	rts
284	–
285	–	_Scod060Patch2 move.l d0,-(sp) ;Create 68060 null frame on stack
286	–	move.l d0,-(sp)
287	–	move.l d0,-(sp)
288	–	frestore (sp)+ ;and load it
289	–	rts
290	–
291	–	*
292	–	* Thread Manager 68060 FPU patches
293	–	*
294	–
295	–	_ThInitFPUPatch tst.b $40(a4)
296	–	bne.s 1$
297	–	moveq #0,d0 ;Create 68060 null frame on stack
298	–	move.l d0,-(a3)
299	–	move.l d0,-(a3)
300	–	move.l d0,-(a3)
301	–	1$ rts
302	–
303	–	*
254		* Trap handler of main task
255		*
256
257		_TrapHandlerAsm:
258	+	IFEQ INFO_LEVEL-1002
259	+	move.w ([6,a0]),-(sp)
260	+	move.w #0,-(sp)
261	+	move.l (4+6,a0),-(sp)
262	+	PUTMSG 0,'%s/TrapHandlerAsm: addr=%08lx opcode=%04lx'
263	+	lea (2*4,sp),sp
264	+	ENDC
265	+
266		cmp.l #4,(sp) ;Illegal instruction?
267		beq.s doillinstr
268		cmp.l #10,(sp) ;A-Line exception?
269		beq.s doaline
270		cmp.l #8,(sp) ;Privilege violation?
271		beq.s doprivviol
272	+
273		cmp.l #9,(sp) ;Trace?
274		beq dotrace
275		cmp.l #3,(sp) ;Illegal Address?
276		beq.s doilladdr
277	+	cmp.l #11,(sp) ;F-Line exception
278	+	beq.s dofline
279
280		cmp.l #32,(sp)
281		blt 1$
282		cmp.l #47,(sp)
283		ble doTrapXX ; Vector 32-47 : TRAP #0 - 15 Instruction Vectors
284
285	<	1$ move.l _OldTrapHandler,-(sp) ;No, jump to old trap handler
285	>	1$:
286	>	cmp.l #48,(sp)
287	>	blt 2$
288	>	cmp.l #55,(sp)
289	>	ble doTrapFPU
290	>	2$:
291	>	IFEQ INFO_LEVEL-1009
292	>	PUTMSG 0,'%s/TrapHandlerAsm: stack=%08lx %08lx %08lx %08lx'
293	>	ENDC
294	>
295	>	move.l _OldTrapHandler,-(sp) ;No, jump to old trap handler
296		rts
297
298		*
299		* TRAP #0 - 15 Instruction Vectors
300		*
301
302	<	doTrapXX move.l a0,(sp) ;Save a0
302	>	doTrapXX:
303	>	IFEQ INFO_LEVEL-1009
304	>	PUTMSG 0,'%s/doTrapXX: stack=%08lx %08lx %08lx %08lx'
305	>	ENDC
306	>
307	>	movem.l a0/d0,-(sp) ;Save a0,d0
308	>	move.l (2*4,sp),d0 ;vector number 32-47
309	>
310		move.l usp,a0 ;Get user stack pointer
311	<	move.l 2*4(sp),-(a0) ;Copy 4-word stack frame to user stack
312	<	move.l 1*4(sp),-(a0)
311	>	move.l (4*4,sp),-(a0) ;Copy 4-word stack frame to user stack
312	>	move.l (3*4,sp),-(a0)
313		move.l a0,usp ;Update USP
314	<	move.l (sp)+,a0 ;Restore a0
314	>	or.w #$2000,(a0) ;set Supervisor bit in SR
315
316	+	lsl.l #2,d0 ;convert vector number to vector offset
317	+	move.l d0,a0
318	+	move.l (a0),d0 ;get mac trap vector
319	+
320	+	move.l usp,a0 ;Get user stack pointer
321	+	move.l d0,-(a0) ;store vector offset as return address
322	+	move.l a0,usp ;Update USP
323	+
324	+	movem.l (sp)+,a0/d0 ;Restore a0,d0
325		addq.l #4*2,sp ;Remove exception frame from supervisor stack
339	–	andi #$d8ff,sr ;Switch to user mode, enable interrupts
326
327	<	move.l $2d*4.w,-(sp) ;Jump to MacOS exception handler
327	>	andi #$d8ff,sr ;Switch to user mode, enable interrupts
328		rts
329
330
331		*
332	+	* FPU Exception Instruction Vectors
333	+	*
334	+
335	+	doTrapFPU:
336	+	move.l d0,(sp)
337	+	fmove.l fpcr,d0
338	+	and.w #$00ff,d0 ;disable FPU exceptions
339	+	fmove.l d0,fpcr
340	+	move.l (sp)+,d0 ;Restore d0
341	+	rte
342	+
343	+
344	+	*
345		* trace Vector
346		*
347
348	<	dotrace move.l a0,(sp) ;Save a0
348	>	dotrace
349	>	IFEQ INFO_LEVEL-1009
350	>	PUTMSG 0,'%s/dotrace: stack=%08lx %08lx %08lx %08lx'
351	>	ENDC
352
353	+	move.l a0,(sp) ;Save a0
354		move.l usp,a0 ;Get user stack pointer
355	+
356	+	IFEQ INFO_LEVEL-1009
357	+	move.l (12,a0),-(sp)
358	+	move.l (8,a0),-(sp)
359	+	move.l (4,a0),-(sp)
360	+	move.l (0,a0),-(sp)
361	+	move.l a0,-(sp)
362	+	move.l a7,-(sp)
363	+	PUTMSG 0,'%s/dotrace: sp=%08lx usp=%08lx (%08lx %08lx %08lx %08lx)'
364	+	lea (6*4,sp),sp
365	+	ENDC
366	+
367		move.l 3*4(sp),-(a0) ;Copy 6-word stack frame to user stack
368		move.l 2*4(sp),-(a0)
369		move.l 1*4(sp),-(a0)
370		move.l a0,usp ;Update USP
371	+	or.w #$2000,(a0) ;set Supervisor bit in SR
372		move.l (sp)+,a0 ;Restore a0
373
374		lea 6*2(sp),sp ;Remove exception frame from supervisor stack
#	Line 371 \| Line 387 \| doaline move.l a0,(sp) ;Save a0
387		move.l 8(sp),-(a0) ;Copy stack frame to user stack
388		move.l 4(sp),-(a0)
389		move.l a0,usp ;Update USP
390	+
391	+	or.w #$2000,(a0) ;set Supervisor bit in SR
392		move.l (sp)+,a0 ;Restore a0
393
394		addq.l #8,sp ;Remove exception frame from supervisor stack
395		andi #$d8ff,sr ;Switch to user mode, enable interrupts
396
397	+	; and.w #$f8ff,_EmulatedSR ;enable interrupts in EmulatedSR
398	+
399		move.l $28.w,-(sp) ;Jump to MacOS exception handler
400		rts
401
402		*
403	+	* F-Line handler: call F-Line exception handler
404	+	*
405	+
406	+	dofline move.l a0,(sp) ;Save a0
407	+	move.l usp,a0 ;Get user stack pointer
408	+	move.l 8(sp),-(a0) ;Copy stack frame to user stack
409	+	move.l 4(sp),-(a0)
410	+	move.l a0,usp ;Update USP
411	+	or.w #$2000,(a0) ;set Supervisor bit in SR
412	+	move.l (sp)+,a0 ;Restore a0
413	+
414	+	addq.l #8,sp ;Remove exception frame from supervisor stack
415	+	andi #$d8ff,sr ;Switch to user mode, enable interrupts
416	+
417	+	and.w #$f8ff,_EmulatedSR ;enable interrupts in EmulatedSR
418	+
419	+	move.l $2c.w,-(sp) ;Jump to MacOS exception handler
420	+	rts
421	+
422	+	*
423		* Illegal address handler
424		*
425
426	<	doilladdr move.l a0,(sp) ;Save a0
426	>	doilladdr:
427	>	IFEQ INFO_LEVEL-1009
428	>	PUTMSG 0,'%s/doilladdr: stack=%08lx %08lx %08lx %08lx'
429	>	ENDC
430	>
431	>	move.l a0,(sp) ;Save a0
432
433		move.l usp,a0 ;Get user stack pointer
434		move.l 3*4(sp),-(a0) ;Copy 6-word stack frame to user stack
435		move.l 2*4(sp),-(a0)
436		move.l 1*4(sp),-(a0)
437		move.l a0,usp ;Update USP
438	+	or.w #$2000,(a0) ;set Supervisor bit in SR
439		move.l (sp)+,a0 ;Restore a0
440
441		lea 6*2(sp),sp ;Remove exception frame from supervisor stack
#	Line 408 \| Line 454 \| doillinstr movem.l a0/d0,-(sp)
454		move.w ([6+2*4,sp]),d0
455		and.w #$ff00,d0
456		cmp.w #$7100,d0
457	+
458	+	IFEQ INFO_LEVEL-1009
459	+	move.l d0,-(sp)
460	+	PUTMSG 0,'%s/doillinst: d0=%08lx stack=%08lx %08lx %08lx %08lx'
461	+	lea (1*4,sp),sp
462	+	ENDC
463		movem.l (sp)+,a0/d0
464		beq 1$
465
#	Line 416 \| Line 468 \| doillinstr movem.l a0/d0,-(sp)
468		move.l 8(sp),-(a0) ;Copy stack frame to user stack
469		move.l 4(sp),-(a0)
470		move.l a0,usp ;Update USP
471	+	or.w #$2000,(a0) ;set Supervisor bit in SR
472		move.l (sp)+,a0 ;Restore a0
473
474		add.w #3*4,sp ;Remove exception frame from supervisor stack
#	Line 424 \| Line 477 \| doillinstr movem.l a0/d0,-(sp)
477		move.l $10.w,-(sp) ;Jump to MacOS exception handler
478		rts
479
480	<	1$ move.l a6,(sp) ;Save a6
480	>	1$:
481	>	move.l a6,(sp) ;Save a6
482		move.l usp,a6 ;Get user stack pointer
483
484		move.l a6,-10(a6) ;Push USP (a7)
#	Line 454 \| Line 508 \| doillinstr movem.l a0/d0,-(sp)
508		doprivviol move.l d0,(sp) ;Save d0
509		move.w ([6,sp]),d0 ;Get instruction word
510
511	+	IFEQ INFO_LEVEL-1001
512	+	move.w ([6,a0]),-(sp)
513	+	move.w #0,-(sp)
514	+	PUTMSG 0,'%s/doprivviol: opcode=%04lx'
515	+	lea (1*4,sp),sp
516	+	ENDC
517	+
518		cmp.w #$40e7,d0 ;move sr,-(sp)?
519		beq pushsr
520		cmp.w #$46df,d0 ;move (sp)+,sr?
#	Line 578 \| Line 639 \| pushsr move.l a0,-(sp) ;Save a0
639		move.l (sp)+,a0 ;Restore a0
640		move.l (sp)+,d0 ;Restore d0
641		addq.l #2,2(sp) ;Skip instruction
642	+
643	+	IFEQ INFO_LEVEL-1001
644	+	move.l (4),-(sp)
645	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
646	+	lea (1*4,sp),sp
647	+	ENDC
648		rte
649
650		; move (sp)+,sr
#	Line 604 \| Line 671 \| popsr move.l a0,-(sp) ;Save a0
671		move.l (sp)+,a0 ;Restore a0
672		move.l (sp)+,d0 ;Restore d0
673		addq.l #2,2(sp) ;Skip instruction
674	+
675	+	IFEQ INFO_LEVEL-1001
676	+	move.l (4),-(sp)
677	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
678	+	lea (1*4,sp),sp
679	+	ENDC
680		rte
681
682		; ori #xxxx,sr
#	Line 616 \| Line 689 \| orisr move.w 4(sp),d0 ;Get CCR from st
689		move.w d0,_EmulatedSR ;And save them
690		move.l (sp)+,d0 ;Restore d0
691		addq.l #4,2(sp) ;Skip instruction
692	+
693	+	IFEQ INFO_LEVEL-1001
694	+	move.l (4),-(sp)
695	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
696	+	lea (1*4,sp),sp
697	+	ENDC
698		rte
699
700		; andi #xxxx,sr
#	Line 639 \| Line 718 \| storesr4 move.w d0,4(sp) ;Store into CC
718		movem.l (sp)+,d0-d1/a0-a1/a6
719		1$ move.l (sp)+,d0 ;Restore d0
720		addq.l #4,2(sp) ;Skip instruction
721	+
722	+	IFEQ INFO_LEVEL-1001
723	+	move.l (4),-(sp)
724	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
725	+	lea (1*4,sp),sp
726	+	ENDC
727		rte
728
729		; move #xxxx,sr
#	Line 670 \| Line 755 \| movefromsrabs move.l a0,-(sp) ;Save a0
755		move.l (sp)+,a0 ;Restore a0
756		move.l (sp)+,d0 ;Restore d0
757		addq.l #4,2(sp) ;Skip instruction
758	+
759	+	IFEQ INFO_LEVEL-1001
760	+	move.l (4),-(sp)
761	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
762	+	lea (1*4,sp),sp
763	+	ENDC
764		rte
765
766		; move sr,(a0)
#	Line 678 \| Line 769 \| movefromsra0 move.w 4(sp),d0 ;Get CCR
769		move.w d0,(a0) ;Store SR
770		move.l (sp)+,d0 ;Restore d0
771		addq.l #2,2(sp) ;Skip instruction
772	+
773	+	IFEQ INFO_LEVEL-1001
774	+	move.l (4),-(sp)
775	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
776	+	lea (1*4,sp),sp
777	+	ENDC
778		rte
779
780		; move sr,(sp)
#	Line 689 \| Line 786 \| movefromsrsp move.l a0,-(sp) ;Save a0
786		move.l (sp)+,a0 ;Restore a0
787		move.l (sp)+,d0 ;Restore d0
788		addq.l #2,2(sp) ;Skip instruction
789	+
790	+	IFEQ INFO_LEVEL-1001
791	+	move.l (4),-(sp)
792	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
793	+	lea (1*4,sp),sp
794	+	ENDC
795		rte
796
797		; fsave -(sp)
798		fsavepush move.l (sp),d0 ;Restore d0
799		move.l a0,(sp) ;Save a0
800		move.l usp,a0 ;Get user stack pointer
801	<	fsave -(a0) ;Push FP state
801	>	move.l #$41000000,-(a0) ;Push idle frame
802		move.l a0,usp ;Update USP
803		move.l (sp)+,a0 ;Restore a0
804		addq.l #2,2(sp) ;Skip instruction
805	+
806	+	IFEQ INFO_LEVEL-1001
807	+	move.l (4),-(sp)
808	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
809	+	lea (1*4,sp),sp
810	+	ENDC
811	+	rte
812	+
813	+	; fsave xxx(a5)
814	+	fsavea5 move.l (sp),d0 ;Restore d0
815	+	move.l a0,(sp) ;Save a0
816	+	move.l a5,a0 ;Get base register
817	+	add.w ([6,sp],2),a0 ;Add offset to base register
818	+	move.l #$41000000,(a0) ;Push idle frame
819	+	move.l (sp)+,a0 ;Restore a0
820	+	addq.l #4,2(sp) ;Skip instruction
821	+
822	+	IFEQ INFO_LEVEL-1001
823	+	move.l (4),-(sp)
824	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
825	+	lea (1*4,sp),sp
826	+	ENDC
827		rte
828
829		; frestore (sp)+
830		frestorepop move.l (sp),d0 ;Restore d0
831		move.l a0,(sp) ;Save a0
832		move.l usp,a0 ;Get user stack pointer
833	<	frestore (a0)+ ;Restore FP state
833	>	addq.l #4,a0 ;Nothing to do...
834		move.l a0,usp ;Update USP
835		move.l (sp)+,a0 ;Restore a0
836		addq.l #2,2(sp) ;Skip instruction
837	+
838	+	IFEQ INFO_LEVEL-1001
839	+	move.l (4),-(sp)
840	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
841	+	lea (1*4,sp),sp
842	+	ENDC
843		rte
844
845	<	; frestore xxx(a5) +jl+
845	>	; frestore xxx(a5)
846		frestorea5 move.l (sp),d0 ;Restore d0
847		move.l a0,(sp) ;Save a0
717	–	move.l a5,a0 ;Get base register
718	–	add.w ([6,sp],2),a0 ;Add offset to base register
719	–	frestore (a0) ;Restore FP state from (a0)
848		move.l (sp)+,a0 ;Restore a0
849		addq.l #4,2(sp) ;Skip instruction
722	–	rte
850
851	<	; fsave xxx(a5) +jl+
852	<	fsavea5 move.l (sp),d0 ;Restore d0
853	<	move.l a0,(sp) ;Save a0
854	<	move.l a5,a0 ;Get base register
855	<	add.w ([6,sp],2),a0 ;Add offset to base register
729	<	fsave (a0) ;Push FP state to (a0)
730	<	move.l (sp)+,a0 ;Restore a0
731	<	addq.l #4,2(sp) ;Skip instruction
851	>	IFEQ INFO_LEVEL-1001
852	>	move.l (4),-(sp)
853	>	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
854	>	lea (1*4,sp),sp
855	>	ENDC
856		rte
857
858		; rte
#	Line 757 \| Line 881 \| pvrte movem.l a0/a1,-(sp) ;Save a0 and
881		move.l a0,usp ;Update USP
882		movem.l (sp)+,a0/a1 ;Restore a0 and a1
883		move.l (sp)+,d0 ;Restore d0
884	+
885	+	IFEQ INFO_LEVEL-1001
886	+	move.l (4),-(sp)
887	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
888	+	lea (1*4,sp),sp
889	+	ENDC
890		rte
891
892		; sizes of exceptions stack frames
#	Line 784 \| Line 914 \| movefromsrd0 addq.l #4,sp ;Skip saved
914		move.w (sp),d0 ;Get CCR
915		or.w _EmulatedSR,d0 ;Add emulated supervisor bits
916		addq.l #2,2(sp) ;Skip instruction
917	+
918	+	IFEQ INFO_LEVEL-1001
919	+	move.l (4),-(sp)
920	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
921	+	lea (1*4,sp),sp
922	+	ENDC
923		rte
924
925		movefromsrd1 move.l (sp)+,d0
#	Line 791 \| Line 927 \| movefromsrd1 move.l (sp)+,d0
927		move.w (sp),d1
928		or.w _EmulatedSR,d1
929		addq.l #2,2(sp)
930	+
931	+	IFEQ INFO_LEVEL-1001
932	+	move.l (4),-(sp)
933	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
934	+	lea (1*4,sp),sp
935	+	ENDC
936		rte
937
938		movefromsrd2 move.l (sp)+,d0
#	Line 798 \| Line 940 \| movefromsrd2 move.l (sp)+,d0
940		move.w (sp),d2
941		or.w _EmulatedSR,d2
942		addq.l #2,2(sp)
943	+
944	+	IFEQ INFO_LEVEL-1001
945	+	move.l (4),-(sp)
946	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
947	+	lea (1*4,sp),sp
948	+	ENDC
949		rte
950
951		movefromsrd3 move.l (sp)+,d0
#	Line 805 \| Line 953 \| movefromsrd3 move.l (sp)+,d0
953		move.w (sp),d3
954		or.w _EmulatedSR,d3
955		addq.l #2,2(sp)
956	+
957	+	IFEQ INFO_LEVEL-1001
958	+	move.l (4),-(sp)
959	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
960	+	lea (1*4,sp),sp
961	+	ENDC
962		rte
963
964		movefromsrd4 move.l (sp)+,d0
#	Line 812 \| Line 966 \| movefromsrd4 move.l (sp)+,d0
966		move.w (sp),d4
967		or.w _EmulatedSR,d4
968		addq.l #2,2(sp)
969	+
970	+	IFEQ INFO_LEVEL-1001
971	+	move.l (4),-(sp)
972	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
973	+	lea (1*4,sp),sp
974	+	ENDC
975		rte
976
977		movefromsrd5 move.l (sp)+,d0
#	Line 819 \| Line 979 \| movefromsrd5 move.l (sp)+,d0
979		move.w (sp),d5
980		or.w _EmulatedSR,d5
981		addq.l #2,2(sp)
982	+
983	+	IFEQ INFO_LEVEL-1001
984	+	move.l (4),-(sp)
985	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
986	+	lea (1*4,sp),sp
987	+	ENDC
988		rte
989
990		movefromsrd6 move.l (sp)+,d0
#	Line 826 \| Line 992 \| movefromsrd6 move.l (sp)+,d0
992		move.w (sp),d6
993		or.w _EmulatedSR,d6
994		addq.l #2,2(sp)
995	+
996	+	IFEQ INFO_LEVEL-1001
997	+	move.l (4),-(sp)
998	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
999	+	lea (1*4,sp),sp
1000	+	ENDC
1001		rte
1002
1003		movefromsrd7 move.l (sp)+,d0
#	Line 833 \| Line 1005 \| movefromsrd7 move.l (sp)+,d0
1005		move.w (sp),d7
1006		or.w _EmulatedSR,d7
1007		addq.l #2,2(sp)
1008	+
1009	+	IFEQ INFO_LEVEL-1001
1010	+	move.l (4),-(sp)
1011	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1012	+	lea (1*4,sp),sp
1013	+	ENDC
1014		rte
1015
1016		; move dx,sr
#	Line 854 \| Line 1032 \| storesr2 move.w d0,4(sp)
1032		movem.l (sp)+,d0-d1/a0-a1/a6
1033		1$ move.l (sp)+,d0
1034		addq.l #2,2(sp)
1035	+
1036	+	IFEQ INFO_LEVEL-1001
1037	+	move.l (4),-(sp)
1038	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1039	+	lea (1*4,sp),sp
1040	+	ENDC
1041		rte
1042
1043		movetosrd1 move.l d1,d0
#	Line 884 \| Line 1068 \| movecfromcr move.w ([6,sp],2),d0 ;Get n
1068		beq.s movecvbra0
1069		cmp.w #$9801,d0 ;movec vbr,a1?
1070		beq.s movecvbra1
1071	+	cmp.w #$A801,d0 ;movec vbr,a2?
1072	+	beq.s movecvbra2
1073		cmp.w #$1801,d0 ;movec vbr,d1?
1074		beq movecvbrd1
1075		cmp.w #$0002,d0 ;movec cacr,d0?
#	Line 917 \| Line 1103 \| movecfromcr move.w ([6,sp],2),d0 ;Get n
1103		moveccacrd0 move.l (sp)+,d0
1104		move.l #$3111,d0 ;All caches and bursts on
1105		addq.l #4,2(sp)
1106	+
1107	+	IFEQ INFO_LEVEL-1001
1108	+	move.l (4),-(sp)
1109	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1110	+	lea (1*4,sp),sp
1111	+	ENDC
1112		rte
1113
1114		; movec cacr,d1
1115		moveccacrd1 move.l (sp)+,d0
1116		move.l #$3111,d1 ;All caches and bursts on
1117		addq.l #4,2(sp)
1118	+
1119	+	IFEQ INFO_LEVEL-1001
1120	+	move.l (4),-(sp)
1121	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1122	+	lea (1*4,sp),sp
1123	+	ENDC
1124		rte
1125
1126		; movec vbr,a0
1127		movecvbra0 move.l (sp)+,d0
1128		sub.l a0,a0 ;VBR always appears to be at 0
1129		addq.l #4,2(sp)
1130	+
1131	+	IFEQ INFO_LEVEL-1001
1132	+	move.l (4),-(sp)
1133	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1134	+	lea (1*4,sp),sp
1135	+	ENDC
1136		rte
1137
1138		; movec vbr,a1
1139		movecvbra1 move.l (sp)+,d0
1140		sub.l a1,a1 ;VBR always appears to be at 0
1141		addq.l #4,2(sp)
1142	+
1143	+	IFEQ INFO_LEVEL-1001
1144	+	move.l (4),-(sp)
1145	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1146	+	lea (1*4,sp),sp
1147	+	ENDC
1148	+	rte
1149	+
1150	+	; movec vbr,a2
1151	+	movecvbra2 move.l (sp)+,d0
1152	+	sub.l a2,a2 ;VBR always appears to be at 0
1153	+	addq.l #4,2(sp)
1154	+
1155	+	IFEQ INFO_LEVEL-1001
1156	+	move.l (4),-(sp)
1157	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1158	+	lea (1*4,sp),sp
1159	+	ENDC
1160		rte
1161
1162		; movec vbr,d1
1163		movecvbrd1 move.l (sp)+,d0
1164		moveq.l #0,d1 ;VBR always appears to be at 0
1165		addq.l #4,2(sp)
1166	+
1167	+	IFEQ INFO_LEVEL-1001
1168	+	move.l (4),-(sp)
1169	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1170	+	lea (1*4,sp),sp
1171	+	ENDC
1172		rte
1173
1174		; movec tc,d0
1175		movectcd0 addq.l #4,sp
1176		moveq #0,d0 ;MMU is always off
1177		addq.l #4,2(sp)
1178	+
1179	+	IFEQ INFO_LEVEL-1001
1180	+	move.l (4),-(sp)
1181	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1182	+	lea (1*4,sp),sp
1183	+	ENDC
1184		rte
1185
1186		; movec tc,d1 +jl+
1187		movectcd1 move.l (sp)+,d0 ;Restore d0
1188		moveq #0,d1 ;MMU is always off
1189		addq.l #4,2(sp)
1190	+
1191	+	IFEQ INFO_LEVEL-1001
1192	+	move.l (4),-(sp)
1193	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1194	+	lea (1*4,sp),sp
1195	+	ENDC
1196		rte
1197
1198		; movec sfc,d1 +jl+
1199		movecsfcd1 move.l (sp)+,d0 ;Restore d0
1200		moveq #0,d1
1201		addq.l #4,2(sp)
1202	+
1203	+	IFEQ INFO_LEVEL-1001
1204	+	move.l (4),-(sp)
1205	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1206	+	lea (1*4,sp),sp
1207	+	ENDC
1208		rte
1209
1210		; movec dfc,d1 +jl+
1211		movecdfcd1 move.l (sp)+,d0 ;Restore d0
1212		moveq #0,d1
1213		addq.l #4,2(sp)
1214	+
1215	+	IFEQ INFO_LEVEL-1001
1216	+	move.l (4),-(sp)
1217	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1218	+	lea (1*4,sp),sp
1219	+	ENDC
1220		rte
1221
1222		movecurpd0 ; movec urp,d0 +jl+
#	Line 976 \| Line 1228 \| movecdtt1d0 ; movec dtt1,d0
1228		addq.l #4,sp
1229		moveq.l #0,d0 ;MMU is always off
1230		addq.l #4,2(sp) ;skip instruction
1231	+
1232	+	IFEQ INFO_LEVEL-1001
1233	+	move.l (4),-(sp)
1234	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1235	+	lea (1*4,sp),sp
1236	+	ENDC
1237		rte
1238
1239		; movec x,cr
#	Line 985 \| Line 1243 \| movectocr move.w ([6,sp],2),d0 ;Get nex
1243		beq.s movectovbr
1244		cmp.w #$1801,d0 ;movec d1,vbr?
1245		beq.s movectovbr
1246	+	cmp.w #$A801,d0 ;movec a2,vbr?
1247	+	beq.s movectovbr
1248		cmp.w #$0002,d0 ;movec d0,cacr?
1249		beq.s movectocacr
1250		cmp.w #$1002,d0 ;movec d1,cacr?
#	Line 999 \| Line 1259 \| movectocr move.w ([6,sp],2),d0 ;Get nex
1259		; movec x,vbr
1260		movectovbr move.l (sp)+,d0 ;Ignore moves to VBR
1261		addq.l #4,2(sp)
1262	+
1263	+	IFEQ INFO_LEVEL-1001
1264	+	move.l (4),-(sp)
1265	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1266	+	lea (1*4,sp),sp
1267	+	ENDC
1268		rte
1269
1270		; movec dx,cacr
#	Line 1008 \| Line 1274 \| movectocacr movem.l d1/a0-a1/a6,-(sp) ;M
1274		movem.l (sp)+,d1/a0-a1/a6
1275		move.l (sp)+,d0
1276		addq.l #4,2(sp)
1277	+
1278	+	IFEQ INFO_LEVEL-1001
1279	+	move.l (4),-(sp)
1280	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1281	+	lea (1*4,sp),sp
1282	+	ENDC
1283		rte
1284
1285		; movec x,sfc
1286		; movec x,dfc
1287		movectoxfc move.l (sp)+,d0 ;Ignore moves to SFC, DFC
1288		addq.l #4,2(sp)
1289	+
1290	+	IFEQ INFO_LEVEL-1001
1291	+	move.l (4),-(sp)
1292	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1293	+	lea (1*4,sp),sp
1294	+	ENDC
1295		rte
1296
1297		; cpusha
1298		cpushadc
1299	<	cpushadcic movem.l d1/a0-a1/a6,-(sp) ;Clear caches
1299	>	cpushadcic
1300	>	IFEQ INFO_LEVEL-1003
1301	>	move.l (4),-(sp)
1302	>	move.l d0,-(sp)
1303	>	PUTMSG 0,'%s/cpushadc: opcode=%04lx Execbase=%08lx'
1304	>	lea (2*4,sp),sp
1305	>	ENDC
1306	>	movem.l d1/a0-a1/a6,-(sp) ;Clear caches
1307		move.l _SysBase,a6
1308		JSRLIB CacheClearU
1309		movem.l (sp)+,d1/a0-a1/a6
#	Line 1030 \| Line 1315 \| cpushadcic movem.l d1/a0-a1/a6,-(sp) ;Cl
1315		moveuspa1 move.l (sp)+,d0
1316		move usp,a1
1317		addq.l #2,2(sp)
1318	+
1319	+	IFEQ INFO_LEVEL-1009
1320	+	move.l a1,-(sp)
1321	+	move.l a7,-(sp)
1322	+	PUTMSG 0,'%s/moveuspa1: a7=%08lx a1=%08lx'
1323	+	lea (2*4,sp),sp
1324	+	ENDC
1325	+
1326		rte
1327
1328		; move usp,a0 +jl+
1329		moveuspa0 move.l (sp)+,d0
1330		move usp,a0
1331		addq.l #2,2(sp)
1332	+
1333	+	IFEQ INFO_LEVEL-1009
1334	+	move.l a0,-(sp)
1335	+	move.l a7,-(sp)
1336	+	PUTMSG 0,'%s/moveuspa0: a7=%08lx a0=%08lx'
1337	+	lea (2*4,sp),sp
1338	+	ENDC
1339	+
1340		rte
1341
1342		; move a1,usp +jl+
1343		moved1usp move.l (sp)+,d0
1344		move a1,usp
1345		addq.l #2,2(sp)
1346	+
1347	+	IFEQ INFO_LEVEL-1001
1348	+	move.l (4),-(sp)
1349	+	PUTMSG 0,'%s/doprivviol END: Execbase=%08lx'
1350	+	lea (1*4,sp),sp
1351	+	ENDC
1352		rte
1353
1354		;
#	Line 1063 \| Line 1370 \| _AsmTriggerNMI move.l d0,-(sp) ;Save d0
1370		rts
1371
1372
1373	+	CopyTrapStack:
1374	+	movem.l d0/a0/a1,-(sp)
1375	+
1376	+	move.w (5*4+6,sp),d0 ;get format word
1377	+	lsr.w #7,d0 ;get stack frame Id
1378	+	lsr.w #4,d0
1379	+	and.w #$001e,d0
1380	+	move.w (StackFormatTable,pc,d0.w),d0 ; get total stack frame length
1381	+
1382	+	lea (5*4,sp),a0 ;get start of exception stack frame
1383	+	move.l usp,a1 ;Get user stack pointer
1384	+	bra 1$
1385	+
1386	+	2$ move.w (a0)+,(a1)+ ; copy additional stack words back to supervisor stack
1387	+	1$ dbf d0,2$
1388	+
1389	+	move.l (3*4,sp),-(a0) ;copy return address to new top of stack
1390	+	move.l a0,sp
1391	+	rts
1392	+
1393		END

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Comparing BasiliskII/src/AmigaOS/asm_support.asm (file contents): Revision 1.8 by cebix, 2001-01-25T22:24:36Z vs. Revision 1.14 by cebix, 2002-09-01T12:01:46Z

Diff Legend

Comparing BasiliskII/src/AmigaOS/asm_support.asm (file contents):
Revision 1.8 by cebix, 2001-01-25T22:24:36Z vs.
Revision 1.14 by cebix, 2002-09-01T12:01:46Z