| 1 |
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* |
| 2 |
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* asm_support.asm - AmigaOS utility functions in assembly language |
| 3 |
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* |
| 4 |
< |
* Basilisk II (C) 1997-1999 Christian Bauer |
| 4 |
> |
* Basilisk II (C) 1997-2001 Christian Bauer |
| 5 |
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* |
| 6 |
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* This program is free software; you can redistribute it and/or modify |
| 7 |
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* it under the terms of the GNU General Public License as published by |
| 28 |
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XDEF _AtomicAnd |
| 29 |
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XDEF _AtomicOr |
| 30 |
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XDEF _MoveVBR |
| 31 |
+ |
XDEF _DisableSuperBypass |
| 32 |
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XDEF _Execute68k |
| 33 |
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XDEF _Execute68kTrap |
| 34 |
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XDEF _TrapHandlerAsm |
| 35 |
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XDEF _ExceptionHandlerAsm |
| 36 |
< |
XDEF _Scod060Patch1 |
| 36 |
< |
XDEF _Scod060Patch2 |
| 37 |
< |
XDEF _ThInitFPUPatch |
| 36 |
> |
XDEF _AsmTriggerNMI |
| 37 |
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|
| 38 |
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XREF _OldTrapHandler |
| 39 |
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XREF _OldExceptionHandler |
| 48 |
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|
| 49 |
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SECTION text,CODE |
| 50 |
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|
| 51 |
+ |
MACHINE 68020 |
| 52 |
+ |
|
| 53 |
|
* |
| 54 |
|
* Atomic bit operations (don't trust the compiler) |
| 55 |
|
* |
| 107 |
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rte |
| 108 |
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|
| 109 |
|
* |
| 110 |
+ |
* Disable 68060 Super Bypass mode |
| 111 |
+ |
* |
| 112 |
+ |
|
| 113 |
+ |
_DisableSuperBypass |
| 114 |
+ |
movem.l d0-d1/a0-a1/a5-a6,-(sp) |
| 115 |
+ |
move.l _SysBase,a6 |
| 116 |
+ |
|
| 117 |
+ |
lea dissb,a5 |
| 118 |
+ |
JSRLIB Supervisor |
| 119 |
+ |
|
| 120 |
+ |
movem.l (sp)+,d0-d1/a0-a1/a5-a6 |
| 121 |
+ |
rts |
| 122 |
+ |
|
| 123 |
+ |
MACHINE 68060 |
| 124 |
+ |
|
| 125 |
+ |
dissb movec pcr,d0 |
| 126 |
+ |
bset #5,d0 |
| 127 |
+ |
movec d0,pcr |
| 128 |
+ |
rte |
| 129 |
+ |
|
| 130 |
+ |
MACHINE 68020 |
| 131 |
+ |
|
| 132 |
+ |
* |
| 133 |
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* Execute 68k subroutine (must be ended with rts) |
| 134 |
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* r->a[7] and r->sr are unused! |
| 135 |
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* |
| 207 |
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pea 1$ |
| 208 |
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move.w _EmulatedSR,d0 |
| 209 |
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move.w d0,-(sp) |
| 210 |
< |
or.w #$0100,d0 ;Set interrupt level in SR |
| 210 |
> |
or.w #$2100,d0 ;Set interrupt level in SR, enter (virtual) supervisor mode |
| 211 |
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move.w d0,_EmulatedSR |
| 212 |
< |
move.l $64.w,a0 ;Jump to MacOS interrupt handler |
| 213 |
< |
jmp (a0) |
| 212 |
> |
move.l $64.w,-(sp) ;Jump to MacOS interrupt handler |
| 213 |
> |
rts |
| 214 |
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|
| 215 |
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1$ move.l (sp)+,d0 ;Restore d0 |
| 216 |
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rts |
| 241 |
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rts |
| 242 |
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|
| 243 |
|
* |
| 244 |
< |
* Process Manager 68060 FPU patches |
| 244 |
> |
* Trap handler of main task |
| 245 |
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* |
| 246 |
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|
| 247 |
< |
_Scod060Patch1 fsave -(sp) ;Save FPU state |
| 248 |
< |
tst.b 2(sp) ;Null? |
| 249 |
< |
beq.s 1$ |
| 250 |
< |
fmovem.x fp0-fp7,-(sp) ;No, save FPU registers |
| 251 |
< |
fmove.l fpiar,-(sp) |
| 252 |
< |
fmove.l fpsr,-(sp) |
| 253 |
< |
fmove.l fpcr,-(sp) |
| 254 |
< |
pea -1 ;Push "FPU state saved" flag |
| 255 |
< |
1$ move.l d1,-(sp) |
| 256 |
< |
move.l d0,-(sp) |
| 257 |
< |
bsr.s 3$ ;Switch integer registers and stack |
| 258 |
< |
addq.l #8,sp |
| 259 |
< |
tst.b 2(sp) ;New FPU state null or "FPU state saved" flag set? |
| 260 |
< |
beq.s 2$ |
| 261 |
< |
addq.l #4,sp ;Flag set, skip it |
| 262 |
< |
fmove.l (sp)+,fpcr ;Restore FPU registers and state |
| 263 |
< |
fmove.l (sp)+,fpsr |
| 264 |
< |
fmove.l (sp)+,fpiar |
| 241 |
< |
fmovem.x (sp)+,fp0-fp7 |
| 242 |
< |
2$ frestore (sp)+ |
| 243 |
< |
movem.l (sp)+,d0-d1 |
| 244 |
< |
rts |
| 245 |
< |
|
| 246 |
< |
3$ move.l 4(sp),a0 ;Switch integer registers and stack |
| 247 |
< |
move sr,-(sp) |
| 248 |
< |
movem.l d2-d7/a2-a6,-(sp) |
| 249 |
< |
cmp.w #0,a0 |
| 250 |
< |
beq.s 4$ |
| 251 |
< |
move.l sp,(a0) |
| 252 |
< |
4$ move.l $36(sp),a0 |
| 253 |
< |
movem.l (a0)+,d2-d7/a2-a6 |
| 254 |
< |
move (a0)+,sr |
| 255 |
< |
move.l a0,sp |
| 256 |
< |
rts |
| 257 |
< |
|
| 258 |
< |
_Scod060Patch2 move.l d0,-(sp) ;Create 68060 null frame on stack |
| 259 |
< |
move.l d0,-(sp) |
| 260 |
< |
move.l d0,-(sp) |
| 261 |
< |
frestore (sp)+ ;and load it |
| 247 |
> |
_TrapHandlerAsm: |
| 248 |
> |
cmp.l #4,(sp) ;Illegal instruction? |
| 249 |
> |
beq.s doillinstr |
| 250 |
> |
cmp.l #10,(sp) ;A-Line exception? |
| 251 |
> |
beq.s doaline |
| 252 |
> |
cmp.l #8,(sp) ;Privilege violation? |
| 253 |
> |
beq.s doprivviol |
| 254 |
> |
cmp.l #9,(sp) ;Trace? |
| 255 |
> |
beq dotrace |
| 256 |
> |
cmp.l #3,(sp) ;Illegal Address? |
| 257 |
> |
beq.s doilladdr |
| 258 |
> |
|
| 259 |
> |
cmp.l #32,(sp) |
| 260 |
> |
blt 1$ |
| 261 |
> |
cmp.l #47,(sp) |
| 262 |
> |
ble doTrapXX ; Vector 32-47 : TRAP #0 - 15 Instruction Vectors |
| 263 |
> |
|
| 264 |
> |
1$ move.l _OldTrapHandler,-(sp) ;No, jump to old trap handler |
| 265 |
|
rts |
| 266 |
|
|
| 267 |
|
* |
| 268 |
< |
* Thread Manager 68060 FPU patches |
| 268 |
> |
* TRAP #0 - 15 Instruction Vectors |
| 269 |
|
* |
| 270 |
|
|
| 271 |
< |
_ThInitFPUPatch tst.b $40(a4) |
| 272 |
< |
bne.s 1$ |
| 273 |
< |
moveq #0,d0 ;Create 68060 null frame on stack |
| 274 |
< |
move.l d0,-(a3) |
| 275 |
< |
move.l d0,-(a3) |
| 276 |
< |
move.l d0,-(a3) |
| 277 |
< |
1$ rts |
| 271 |
> |
doTrapXX move.l a0,(sp) ;Save a0 |
| 272 |
> |
move.l usp,a0 ;Get user stack pointer |
| 273 |
> |
move.l 2*4(sp),-(a0) ;Copy 4-word stack frame to user stack |
| 274 |
> |
move.l 1*4(sp),-(a0) |
| 275 |
> |
move.l a0,usp ;Update USP |
| 276 |
> |
move.l (sp)+,a0 ;Restore a0 |
| 277 |
> |
|
| 278 |
> |
addq.l #4*2,sp ;Remove exception frame from supervisor stack |
| 279 |
> |
andi #$d8ff,sr ;Switch to user mode, enable interrupts |
| 280 |
> |
|
| 281 |
> |
move.l $2d*4.w,-(sp) ;Jump to MacOS exception handler |
| 282 |
> |
rts |
| 283 |
> |
|
| 284 |
|
|
| 285 |
|
* |
| 286 |
< |
* Trap handler of main task |
| 286 |
> |
* trace Vector |
| 287 |
|
* |
| 288 |
|
|
| 289 |
< |
_TrapHandlerAsm cmp.l #4,(sp) ;Illegal instruction? |
| 281 |
< |
beq.s doillinstr |
| 282 |
< |
cmp.l #10,(sp) ;A-Line exception? |
| 283 |
< |
beq.s doaline |
| 284 |
< |
cmp.l #8,(sp) ;Privilege violation? |
| 285 |
< |
beq.s doprivviol |
| 289 |
> |
dotrace move.l a0,(sp) ;Save a0 |
| 290 |
|
|
| 291 |
< |
move.l _OldTrapHandler,-(sp) ;No, jump to old trap handler |
| 291 |
> |
move.l usp,a0 ;Get user stack pointer |
| 292 |
> |
move.l 3*4(sp),-(a0) ;Copy 6-word stack frame to user stack |
| 293 |
> |
move.l 2*4(sp),-(a0) |
| 294 |
> |
move.l 1*4(sp),-(a0) |
| 295 |
> |
move.l a0,usp ;Update USP |
| 296 |
> |
move.l (sp)+,a0 ;Restore a0 |
| 297 |
> |
|
| 298 |
> |
lea 6*2(sp),sp ;Remove exception frame from supervisor stack |
| 299 |
> |
andi #$18ff,sr ;Switch to user mode, enable interrupts, disable trace |
| 300 |
> |
|
| 301 |
> |
move.l $24.w,-(sp) ;Jump to MacOS exception handler |
| 302 |
|
rts |
| 303 |
|
|
| 304 |
+ |
|
| 305 |
|
* |
| 306 |
|
* A-Line handler: call MacOS A-Line handler |
| 307 |
|
* |
| 320 |
|
rts |
| 321 |
|
|
| 322 |
|
* |
| 323 |
+ |
* Illegal address handler |
| 324 |
+ |
* |
| 325 |
+ |
|
| 326 |
+ |
doilladdr move.l a0,(sp) ;Save a0 |
| 327 |
+ |
|
| 328 |
+ |
move.l usp,a0 ;Get user stack pointer |
| 329 |
+ |
move.l 3*4(sp),-(a0) ;Copy 6-word stack frame to user stack |
| 330 |
+ |
move.l 2*4(sp),-(a0) |
| 331 |
+ |
move.l 1*4(sp),-(a0) |
| 332 |
+ |
move.l a0,usp ;Update USP |
| 333 |
+ |
move.l (sp)+,a0 ;Restore a0 |
| 334 |
+ |
|
| 335 |
+ |
lea 6*2(sp),sp ;Remove exception frame from supervisor stack |
| 336 |
+ |
andi #$d8ff,sr ;Switch to user mode, enable interrupts |
| 337 |
+ |
|
| 338 |
+ |
move.l $0c.w,-(sp) ;Jump to MacOS exception handler |
| 339 |
+ |
rts |
| 340 |
+ |
|
| 341 |
+ |
|
| 342 |
+ |
* |
| 343 |
|
* Illegal instruction handler: call IllInstrHandler() (which calls EmulOp()) |
| 344 |
|
* to execute extended opcodes (see emul_op.h) |
| 345 |
|
* |
| 346 |
|
|
| 347 |
< |
doillinstr move.l a6,(sp) ;Save a6 |
| 347 |
> |
doillinstr movem.l a0/d0,-(sp) |
| 348 |
> |
move.w ([6+2*4,sp]),d0 |
| 349 |
> |
and.w #$ff00,d0 |
| 350 |
> |
cmp.w #$7100,d0 |
| 351 |
> |
movem.l (sp)+,a0/d0 |
| 352 |
> |
beq 1$ |
| 353 |
> |
|
| 354 |
> |
move.l a0,(sp) ;Save a0 |
| 355 |
> |
move.l usp,a0 ;Get user stack pointer |
| 356 |
> |
move.l 8(sp),-(a0) ;Copy stack frame to user stack |
| 357 |
> |
move.l 4(sp),-(a0) |
| 358 |
> |
move.l a0,usp ;Update USP |
| 359 |
> |
move.l (sp)+,a0 ;Restore a0 |
| 360 |
> |
|
| 361 |
> |
add.w #3*4,sp ;Remove exception frame from supervisor stack |
| 362 |
> |
andi #$d8ff,sr ;Switch to user mode, enable interrupts |
| 363 |
> |
|
| 364 |
> |
move.l $10.w,-(sp) ;Jump to MacOS exception handler |
| 365 |
> |
rts |
| 366 |
> |
|
| 367 |
> |
1$ move.l a6,(sp) ;Save a6 |
| 368 |
|
move.l usp,a6 ;Get user stack pointer |
| 369 |
|
|
| 370 |
|
move.l a6,-10(a6) ;Push USP (a7) |
| 419 |
|
cmp.w #$40d0,d0 ;move sr,(a0)? |
| 420 |
|
beq movefromsra0 |
| 421 |
|
cmp.w #$40d7,d0 ;move sr,(sp)? |
| 422 |
< |
beq movefromsra0 |
| 422 |
> |
beq movefromsrsp |
| 423 |
|
|
| 424 |
|
cmp.w #$f327,d0 ;fsave -(sp)? |
| 425 |
|
beq fsavepush |
| 426 |
|
cmp.w #$f35f,d0 ;frestore (sp)+? |
| 427 |
|
beq frestorepop |
| 428 |
+ |
cmp.w #$f32d,d0 ;fsave xxx(a5) ? |
| 429 |
+ |
beq fsavea5 |
| 430 |
+ |
cmp.w #$f36d,d0 ;frestore xxx(a5) ? |
| 431 |
+ |
beq frestorea5 |
| 432 |
|
|
| 433 |
|
cmp.w #$4e73,d0 ;rte? |
| 434 |
|
beq pvrte |
| 477 |
|
cmp.w #$f4f8,d0 ;cpusha dc/ic? |
| 478 |
|
beq cpushadcic |
| 479 |
|
|
| 480 |
+ |
cmp.w #$4e69,d0 ;move usp,a1 |
| 481 |
+ |
beq moveuspa1 |
| 482 |
+ |
cmp.w #$4e68,d0 ;move usp,a0 |
| 483 |
+ |
beq moveuspa0 |
| 484 |
+ |
|
| 485 |
+ |
cmp.w #$4e61,d0 ;move a1,usp |
| 486 |
+ |
beq moved1usp |
| 487 |
+ |
|
| 488 |
|
pv_unhandled move.l (sp),d0 ;Unhandled instruction, jump to handler in main.cpp |
| 489 |
|
move.l a6,(sp) ;Save a6 |
| 490 |
|
move.l usp,a6 ;Get user stack pointer |
| 526 |
|
move.w (a0)+,d0 ;Get SR from user stack |
| 527 |
|
move.w d0,8(sp) ;Store into CCR on exception stack frame |
| 528 |
|
and.w #$00ff,8(sp) |
| 529 |
< |
and.w #$2700,d0 ;Extract supervisor bits |
| 529 |
> |
and.w #$e700,d0 ;Extract supervisor bits |
| 530 |
|
move.w d0,_EmulatedSR ;And save them |
| 531 |
|
|
| 532 |
|
and.w #$0700,d0 ;Rethrow exception if interrupts are pending and reenabled |
| 552 |
|
or.w ([6,sp],2),d0 ;Or with immediate value |
| 553 |
|
move.w d0,4(sp) ;Store into CCR on stack |
| 554 |
|
and.w #$00ff,4(sp) |
| 555 |
< |
and.w #$2700,d0 ;Extract supervisor bits |
| 555 |
> |
and.w #$e700,d0 ;Extract supervisor bits |
| 556 |
|
move.w d0,_EmulatedSR ;And save them |
| 557 |
|
move.l (sp)+,d0 ;Restore d0 |
| 558 |
|
addq.l #4,2(sp) ;Skip instruction |
| 564 |
|
and.w ([6,sp],2),d0 ;And with immediate value |
| 565 |
|
storesr4 move.w d0,4(sp) ;Store into CCR on stack |
| 566 |
|
and.w #$00ff,4(sp) |
| 567 |
< |
and.w #$2700,d0 ;Extract supervisor bits |
| 567 |
> |
and.w #$e700,d0 ;Extract supervisor bits |
| 568 |
|
move.w d0,_EmulatedSR ;And save them |
| 569 |
|
|
| 570 |
|
and.w #$0700,d0 ;Rethrow exception if interrupts are pending and reenabled |
| 635 |
|
fsavepush move.l (sp),d0 ;Restore d0 |
| 636 |
|
move.l a0,(sp) ;Save a0 |
| 637 |
|
move.l usp,a0 ;Get user stack pointer |
| 638 |
< |
fsave -(a0) ;Push FP state |
| 638 |
> |
move.l #$41000000,-(a0) ;Push idle frame |
| 639 |
|
move.l a0,usp ;Update USP |
| 640 |
|
move.l (sp)+,a0 ;Restore a0 |
| 641 |
|
addq.l #2,2(sp) ;Skip instruction |
| 642 |
|
rte |
| 643 |
|
|
| 644 |
+ |
; fsave xxx(a5) |
| 645 |
+ |
fsavea5 move.l (sp),d0 ;Restore d0 |
| 646 |
+ |
move.l a0,(sp) ;Save a0 |
| 647 |
+ |
move.l a5,a0 ;Get base register |
| 648 |
+ |
add.w ([6,sp],2),a0 ;Add offset to base register |
| 649 |
+ |
move.l #$41000000,(a0) ;Push idle frame |
| 650 |
+ |
move.l (sp)+,a0 ;Restore a0 |
| 651 |
+ |
addq.l #4,2(sp) ;Skip instruction |
| 652 |
+ |
rte |
| 653 |
+ |
|
| 654 |
|
; frestore (sp)+ |
| 655 |
|
frestorepop move.l (sp),d0 ;Restore d0 |
| 656 |
|
move.l a0,(sp) ;Save a0 |
| 657 |
|
move.l usp,a0 ;Get user stack pointer |
| 658 |
< |
frestore (a0)+ ;Restore FP state |
| 658 |
> |
addq.l #4,a0 ;Nothing to do... |
| 659 |
|
move.l a0,usp ;Update USP |
| 660 |
|
move.l (sp)+,a0 ;Restore a0 |
| 661 |
|
addq.l #2,2(sp) ;Skip instruction |
| 662 |
|
rte |
| 663 |
|
|
| 664 |
< |
; rte (only handles format 0) |
| 665 |
< |
pvrte move.l a0,-(sp) ;Save a0 |
| 664 |
> |
; frestore xxx(a5) |
| 665 |
> |
frestorea5 move.l (sp),d0 ;Restore d0 |
| 666 |
> |
move.l a0,(sp) ;Save a0 |
| 667 |
> |
move.l (sp)+,a0 ;Restore a0 |
| 668 |
> |
addq.l #4,2(sp) ;Skip instruction |
| 669 |
> |
rte |
| 670 |
> |
|
| 671 |
> |
; rte |
| 672 |
> |
pvrte movem.l a0/a1,-(sp) ;Save a0 and a1 |
| 673 |
|
move.l usp,a0 ;Get user stack pointer |
| 674 |
+ |
|
| 675 |
|
move.w (a0)+,d0 ;Get SR from user stack |
| 676 |
< |
move.w d0,8(sp) ;Store into CCR on exception stack frame |
| 677 |
< |
and.w #$00ff,8(sp) |
| 678 |
< |
and.w #$2700,d0 ;Extract supervisor bits |
| 676 |
> |
move.w d0,8+4(sp) ;Store into CCR on exception stack frame |
| 677 |
> |
and.w #$c0ff,8+4(sp) |
| 678 |
> |
and.w #$e700,d0 ;Extract supervisor bits |
| 679 |
|
move.w d0,_EmulatedSR ;And save them |
| 680 |
< |
move.l (a0)+,10(sp) ;Store return address in exception stack frame |
| 681 |
< |
addq.l #2,a0 ;Skip format word |
| 680 |
> |
move.l (a0)+,10+4(sp) ;Store return address in exception stack frame |
| 681 |
> |
|
| 682 |
> |
move.w (a0)+,d0 ;get format word |
| 683 |
> |
lsr.w #7,d0 ;get stack frame Id |
| 684 |
> |
lsr.w #4,d0 |
| 685 |
> |
and.w #$001e,d0 |
| 686 |
> |
move.w (StackFormatTable,pc,d0.w),d0 ; get total stack frame length |
| 687 |
> |
subq.w #4,d0 ; count only extra words |
| 688 |
> |
lea 16+4(sp),a1 ; destination address (in supervisor stack) |
| 689 |
> |
bra 1$ |
| 690 |
> |
|
| 691 |
> |
2$ move.w (a0)+,(a1)+ ; copy additional stack words back to supervisor stack |
| 692 |
> |
1$ dbf d0,2$ |
| 693 |
> |
|
| 694 |
|
move.l a0,usp ;Update USP |
| 695 |
< |
move.l (sp)+,a0 ;Restore a0 |
| 695 |
> |
movem.l (sp)+,a0/a1 ;Restore a0 and a1 |
| 696 |
|
move.l (sp)+,d0 ;Restore d0 |
| 697 |
|
rte |
| 698 |
|
|
| 699 |
+ |
; sizes of exceptions stack frames |
| 700 |
+ |
StackFormatTable: |
| 701 |
+ |
dc.w 4 ; Four-word stack frame, format $0 |
| 702 |
+ |
dc.w 4 ; Throwaway four-word stack frame, format $1 |
| 703 |
+ |
dc.w 6 ; Six-word stack frame, format $2 |
| 704 |
+ |
dc.w 6 ; MC68040 floating-point post-instruction stack frame, format $3 |
| 705 |
+ |
dc.w 8 ; MC68EC040 and MC68LC040 floating-point unimplemented stack frame, format $4 |
| 706 |
+ |
dc.w 4 ; Format $5 |
| 707 |
+ |
dc.w 4 ; Format $6 |
| 708 |
+ |
dc.w 30 ; MC68040 access error stack frame, Format $7 |
| 709 |
+ |
dc.w 29 ; MC68010 bus and address error stack frame, format $8 |
| 710 |
+ |
dc.w 10 ; MC68020 and MC68030 coprocessor mid-instruction stack frame, format $9 |
| 711 |
+ |
dc.w 16 ; MC68020 and MC68030 short bus cycle stack frame, format $a |
| 712 |
+ |
dc.w 46 ; MC68020 and MC68030 long bus cycle stack frame, format $b |
| 713 |
+ |
dc.w 12 ; CPU32 bus error for prefetches and operands stack frame, format $c |
| 714 |
+ |
dc.w 4 ; Format $d |
| 715 |
+ |
dc.w 4 ; Format $e |
| 716 |
+ |
dc.w 4 ; Format $f |
| 717 |
+ |
|
| 718 |
|
; move sr,dx |
| 719 |
|
movefromsrd0 addq.l #4,sp ;Skip saved d0 |
| 720 |
|
moveq #0,d0 |
| 776 |
|
movetosrd0 move.l (sp),d0 |
| 777 |
|
storesr2 move.w d0,4(sp) |
| 778 |
|
and.w #$00ff,4(sp) |
| 779 |
< |
and.w #$2700,d0 |
| 779 |
> |
and.w #$e700,d0 |
| 780 |
|
move.w d0,_EmulatedSR |
| 781 |
|
|
| 782 |
|
and.w #$0700,d0 ;Rethrow exception if interrupts are pending and reenabled |
| 821 |
|
beq.s movecvbra0 |
| 822 |
|
cmp.w #$9801,d0 ;movec vbr,a1? |
| 823 |
|
beq.s movecvbra1 |
| 824 |
+ |
cmp.w #$1801,d0 ;movec vbr,d1? |
| 825 |
+ |
beq movecvbrd1 |
| 826 |
|
cmp.w #$0002,d0 ;movec cacr,d0? |
| 827 |
|
beq.s moveccacrd0 |
| 828 |
|
cmp.w #$1002,d0 ;movec cacr,d1? |
| 831 |
|
beq.s movectcd0 |
| 832 |
|
cmp.w #$1003,d0 ;movec tc,d1? |
| 833 |
|
beq.s movectcd1 |
| 834 |
+ |
cmp.w #$1000,d0 ;movec sfc,d1? |
| 835 |
+ |
beq movecsfcd1 |
| 836 |
+ |
cmp.w #$1001,d0 ;movec dfc,d1? |
| 837 |
+ |
beq movecdfcd1 |
| 838 |
+ |
cmp.w #$0806,d0 ;movec urp,d0? |
| 839 |
+ |
beq movecurpd0 |
| 840 |
+ |
cmp.w #$0807,d0 ;movec srp,d0? |
| 841 |
+ |
beq.s movecsrpd0 |
| 842 |
+ |
cmp.w #$0004,d0 ;movec itt0,d0 |
| 843 |
+ |
beq.s movecitt0d0 |
| 844 |
+ |
cmp.w #$0005,d0 ;movec itt1,d0 |
| 845 |
+ |
beq.s movecitt1d0 |
| 846 |
+ |
cmp.w #$0006,d0 ;movec dtt0,d0 |
| 847 |
+ |
beq.s movecdtt0d0 |
| 848 |
+ |
cmp.w #$0007,d0 ;movec dtt1,d0 |
| 849 |
+ |
beq.s movecdtt1d0 |
| 850 |
|
|
| 851 |
|
bra pv_unhandled |
| 852 |
|
|
| 874 |
|
addq.l #4,2(sp) |
| 875 |
|
rte |
| 876 |
|
|
| 877 |
+ |
; movec vbr,d1 |
| 878 |
+ |
movecvbrd1 move.l (sp)+,d0 |
| 879 |
+ |
moveq.l #0,d1 ;VBR always appears to be at 0 |
| 880 |
+ |
addq.l #4,2(sp) |
| 881 |
+ |
rte |
| 882 |
+ |
|
| 883 |
|
; movec tc,d0 |
| 884 |
|
movectcd0 addq.l #4,sp |
| 885 |
|
moveq #0,d0 ;MMU is always off |
| 886 |
|
addq.l #4,2(sp) |
| 887 |
|
rte |
| 888 |
|
|
| 889 |
< |
; movec tc,d1 |
| 890 |
< |
movectcd1 addq.l #4,sp |
| 889 |
> |
; movec tc,d1 +jl+ |
| 890 |
> |
movectcd1 move.l (sp)+,d0 ;Restore d0 |
| 891 |
|
moveq #0,d1 ;MMU is always off |
| 892 |
|
addq.l #4,2(sp) |
| 893 |
|
rte |
| 894 |
|
|
| 895 |
+ |
; movec sfc,d1 +jl+ |
| 896 |
+ |
movecsfcd1 move.l (sp)+,d0 ;Restore d0 |
| 897 |
+ |
moveq #0,d1 |
| 898 |
+ |
addq.l #4,2(sp) |
| 899 |
+ |
rte |
| 900 |
+ |
|
| 901 |
+ |
; movec dfc,d1 +jl+ |
| 902 |
+ |
movecdfcd1 move.l (sp)+,d0 ;Restore d0 |
| 903 |
+ |
moveq #0,d1 |
| 904 |
+ |
addq.l #4,2(sp) |
| 905 |
+ |
rte |
| 906 |
+ |
|
| 907 |
+ |
movecurpd0 ; movec urp,d0 +jl+ |
| 908 |
+ |
movecsrpd0 ; movec srp,d0 |
| 909 |
+ |
movecitt0d0 ; movec itt0,d0 |
| 910 |
+ |
movecitt1d0 ; movec itt1,d0 |
| 911 |
+ |
movecdtt0d0 ; movec dtt0,d0 |
| 912 |
+ |
movecdtt1d0 ; movec dtt1,d0 |
| 913 |
+ |
addq.l #4,sp |
| 914 |
+ |
moveq.l #0,d0 ;MMU is always off |
| 915 |
+ |
addq.l #4,2(sp) ;skip instruction |
| 916 |
+ |
rte |
| 917 |
+ |
|
| 918 |
|
; movec x,cr |
| 919 |
|
movectocr move.w ([6,sp],2),d0 ;Get next instruction word |
| 920 |
|
|
| 921 |
|
cmp.w #$0801,d0 ;movec d0,vbr? |
| 922 |
|
beq.s movectovbr |
| 923 |
+ |
cmp.w #$1801,d0 ;movec d1,vbr? |
| 924 |
+ |
beq.s movectovbr |
| 925 |
|
cmp.w #$0002,d0 ;movec d0,cacr? |
| 926 |
|
beq.s movectocacr |
| 927 |
|
cmp.w #$1002,d0 ;movec d1,cacr? |
| 928 |
|
beq.s movectocacr |
| 929 |
+ |
cmp.w #$1000,d0 ;movec d1,sfc? |
| 930 |
+ |
beq.s movectoxfc |
| 931 |
+ |
cmp.w #$1001,d0 ;movec d1,dfc? |
| 932 |
+ |
beq.s movectoxfc |
| 933 |
|
|
| 934 |
|
bra pv_unhandled |
| 935 |
|
|
| 947 |
|
addq.l #4,2(sp) |
| 948 |
|
rte |
| 949 |
|
|
| 950 |
+ |
; movec x,sfc |
| 951 |
+ |
; movec x,dfc |
| 952 |
+ |
movectoxfc move.l (sp)+,d0 ;Ignore moves to SFC, DFC |
| 953 |
+ |
addq.l #4,2(sp) |
| 954 |
+ |
rte |
| 955 |
+ |
|
| 956 |
|
; cpusha |
| 957 |
|
cpushadc |
| 958 |
|
cpushadcic movem.l d1/a0-a1/a6,-(sp) ;Clear caches |
| 963 |
|
addq.l #2,2(sp) |
| 964 |
|
rte |
| 965 |
|
|
| 966 |
+ |
; move usp,a1 +jl+ |
| 967 |
+ |
moveuspa1 move.l (sp)+,d0 |
| 968 |
+ |
move usp,a1 |
| 969 |
+ |
addq.l #2,2(sp) |
| 970 |
+ |
rte |
| 971 |
+ |
|
| 972 |
+ |
; move usp,a0 +jl+ |
| 973 |
+ |
moveuspa0 move.l (sp)+,d0 |
| 974 |
+ |
move usp,a0 |
| 975 |
+ |
addq.l #2,2(sp) |
| 976 |
+ |
rte |
| 977 |
+ |
|
| 978 |
+ |
; move a1,usp +jl+ |
| 979 |
+ |
moved1usp move.l (sp)+,d0 |
| 980 |
+ |
move a1,usp |
| 981 |
+ |
addq.l #2,2(sp) |
| 982 |
+ |
rte |
| 983 |
+ |
|
| 984 |
+ |
; |
| 985 |
+ |
; Trigger NMI (Pop up debugger) |
| 986 |
+ |
; |
| 987 |
+ |
|
| 988 |
+ |
_AsmTriggerNMI move.l d0,-(sp) ;Save d0 |
| 989 |
+ |
move.w #$007c,-(sp) ;Yes, fake NMI stack frame |
| 990 |
+ |
pea 1$ |
| 991 |
+ |
move.w _EmulatedSR,d0 |
| 992 |
+ |
and.w #$f8ff,d0 ;Set interrupt level in SR |
| 993 |
+ |
move.w d0,-(sp) |
| 994 |
+ |
move.w d0,_EmulatedSR |
| 995 |
+ |
|
| 996 |
+ |
move.l $7c.w,-(sp) ;Jump to MacOS NMI handler |
| 997 |
+ |
rts |
| 998 |
+ |
|
| 999 |
+ |
1$ move.l (sp)+,d0 ;Restore d0 |
| 1000 |
+ |
rts |
| 1001 |
+ |
|
| 1002 |
+ |
|
| 1003 |
|
END |
