ViewVC Help
View File | Revision Log | Show Annotations | Revision Graph | Root Listing
root/cebix/mon/src/mon_z80.cpp
Revision: 1.6
Committed: 2004-02-12T17:18:03Z (20 years, 9 months ago) by cebix
Branch: MAIN
CVS Tags: release_3-1
Changes since 1.5: +1 -1 lines
Log Message: 
Happy New Year! :-)

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * mon_z80.cpp - Z80 disassembler
3     *
4 cebix 1.6 * cxmon (C) 1997-2004 Christian Bauer, Marc Hellwig
5 cebix 1.1 *
6     * This program is free software; you can redistribute it and/or modify
7     * it under the terms of the GNU General Public License as published by
8     * the Free Software Foundation; either version 2 of the License, or
9     * (at your option) any later version.
10     *
11     * This program is distributed in the hope that it will be useful,
12     * but WITHOUT ANY WARRANTY; without even the implied warranty of
13     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14     * GNU General Public License for more details.
15     *
16     * You should have received a copy of the GNU General Public License
17     * along with this program; if not, write to the Free Software
18     * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19     */
20    
21     #include "sysdeps.h"
22    
23     #include <stdarg.h>
24    
25     #include "mon.h"
26     #include "mon_disass.h"
27    
28    
29     // Addressing modes
30     enum {
31     A_IMPL,
32     A_IMM8, // xx
33     A_IMM16, // xxxx
34     A_ABS8, // (xx)
35     A_ABS16, // (xxxx)
36     A_REL, // relative
37     A_A, // a
38     A_HL, // hl or ix or iy
39     A_SP, // sp
40     A_REG1, // 8-bit register (bits 0..2 of opcode) or (hl)/(ix+d)/(iy+d)
41     A_REG1X, // 8-bit register (bits 0..2 of opcode) or (hl)/(ix+d)/(iy+d), don't substitute h or l on prefixes
42     A_REG2, // 8-bit register (bits 3..5 of opcode) or (hl)/(ix+d)/(iy+d)
43     A_REG2X, // 8-bit register (bits 3..5 of opcode) or (hl)/(ix+d)/(iy+d), don't substitute h or l on prefixes
44     A_REG3, // 16-bit register (bits 4..5 of opcode) bc/de/hl/sp
45     A_REG4, // 16-bit register (bits 4..5 of opcode) bc/de/hl/af
46     A_COND, // condition code (bits 3..5 of opcode)
47     A_COND2, // condition code (bits 3..4 of opcode)
48     A_BIT, // bit number (bits 3..5 of opcode)
49 cebix 1.4 A_BIT_REG1, // bit number (bits 3..5 of opcode) followed by 8-bit register (bits 0..2 of opcode)
50 cebix 1.1 A_RST, // restart
51     A_BC_IND, // (bc)
52     A_DE_IND, // (de)
53     A_HL_IND, // (hl) or (ix) or (iy)
54 cebix 1.4 A_XY_IND, // (ix+d) or (iy+d)
55 cebix 1.1 A_SP_IND, // (sp)
56     A_DE_HL, // de,hl
57     A_AF_AF, // af,af'
58     };
59    
60     // Mnemonics
61     enum {
62     M_ADC, M_ADD, M_AND, M_BIT, M_CALL, M_CCF, M_CP, M_CPD, M_CPDR, M_CPI,
63     M_CPIR, M_CPL, M_DAA, M_DEC, M_DI, M_DJNZ, M_EI, M_EX, M_EXX, M_HALT,
64     M_IM0, M_IM1, M_IM2, M_IN, M_INC, M_IND, M_INDR, M_INI, M_INIR, M_JP,
65     M_JR, M_LD, M_LDD, M_LDDR, M_LDI, M_LDIR, M_NEG, M_NOP, M_OR, M_OTDR,
66     M_OTIR, M_OUT, M_OUTD, M_OUTI, M_POP, M_PUSH, M_RES, M_RET, M_RETI,
67     M_RETN, M_RL, M_RLA, M_RLC, M_RLCA, M_RLD, M_RR, M_RRA, M_RRC, M_RRCA,
68     M_RRD, M_RST, M_SBC, M_SCF, M_SET, M_SL1, M_SLA, M_SRA, M_SRL, M_SUB,
69     M_XOR,
70     M_ILLEGAL,
71    
72     M_MAXIMUM
73     };
74    
75     // Chars for each mnemonic
76     static const char mnem_1[] = "aaabccccccccddddeeehiiiiiiiiijjlllllnnoooooopprrrrrrrrrrrrrrrssssssssx?";
77     static const char mnem_2[] = "ddniacppppppaeijixxammmnnnnnnprdddddeorttuuuoueeeelllllrrrrrsbcellrruo ";
78     static const char mnem_3[] = "cddtlf ddiilac n xl cddii ddiigp ditttpssttt accd accdtcft1aalbr ";
79     static const char mnem_4[] = " l r r z t012 r r r r rr di h in a a ";
80    
81     // Mnemonic for each opcode
82     static const char mnemonic[256] = {
83     M_NOP , M_LD , M_LD , M_INC , M_INC , M_DEC , M_LD , M_RLCA, // 00
84     M_EX , M_ADD, M_LD , M_DEC , M_INC , M_DEC , M_LD , M_RRCA,
85     M_DJNZ, M_LD , M_LD , M_INC , M_INC , M_DEC , M_LD , M_RLA , // 10
86     M_JR , M_ADD, M_LD , M_DEC , M_INC , M_DEC , M_LD , M_RRA ,
87     M_JR , M_LD , M_LD , M_INC , M_INC , M_DEC , M_LD , M_DAA , // 20
88     M_JR , M_ADD, M_LD , M_DEC , M_INC , M_DEC , M_LD , M_CPL ,
89     M_JR , M_LD , M_LD , M_INC , M_INC , M_DEC , M_LD , M_SCF , // 30
90     M_JR , M_ADD, M_LD , M_DEC , M_INC , M_DEC , M_LD , M_CCF ,
91     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , // 40
92     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD ,
93     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , // 50
94     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD ,
95     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , // 60
96     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD ,
97     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_HALT, M_LD , // 70
98     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD ,
99     M_ADD , M_ADD, M_ADD, M_ADD , M_ADD , M_ADD , M_ADD , M_ADD , // 80
100     M_ADC , M_ADC, M_ADC, M_ADC , M_ADC , M_ADC , M_ADC , M_ADC ,
101     M_SUB , M_SUB, M_SUB, M_SUB , M_SUB , M_SUB , M_SUB , M_SUB , // 90
102     M_SBC , M_SBC, M_SBC, M_SBC , M_SBC , M_SBC , M_SBC , M_SBC ,
103     M_AND , M_AND, M_AND, M_AND , M_AND , M_AND , M_AND , M_AND , // a0
104     M_XOR , M_XOR, M_XOR, M_XOR , M_XOR , M_XOR , M_XOR , M_XOR ,
105     M_OR , M_OR , M_OR , M_OR , M_OR , M_OR , M_OR , M_OR , // b0
106     M_CP , M_CP , M_CP , M_CP , M_CP , M_CP , M_CP , M_CP ,
107     M_RET , M_POP, M_JP , M_JP , M_CALL, M_PUSH , M_ADD , M_RST , // c0
108     M_RET , M_RET, M_JP , M_ILLEGAL, M_CALL, M_CALL , M_ADC , M_RST ,
109     M_RET , M_POP, M_JP , M_OUT , M_CALL, M_PUSH , M_SUB , M_RST , // d0
110     M_RET , M_EXX, M_JP , M_IN , M_CALL, M_ILLEGAL, M_SBC , M_RST ,
111     M_RET , M_POP, M_JP , M_EX , M_CALL, M_PUSH , M_AND , M_RST , // e0
112     M_RET , M_JP , M_JP , M_EX , M_CALL, M_ILLEGAL, M_XOR , M_RST ,
113     M_RET , M_POP, M_JP , M_DI , M_CALL, M_PUSH , M_OR , M_RST , // f0
114     M_RET , M_LD , M_JP , M_EI , M_CALL, M_ILLEGAL, M_CP , M_RST
115     };
116    
117     // Source/destination addressing modes for each opcode
118     #define A(d,s) (((A_ ## d) << 8) | (A_ ## s))
119    
120     static const short adr_mode[256] = {
121     A(IMPL,IMPL) , A(REG3,IMM16) , A(BC_IND,A) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) , // 00
122     A(AF_AF,IMPL) , A(HL,REG3) , A(A,BC_IND) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) ,
123     A(REL,IMPL) , A(REG3,IMM16) , A(DE_IND,A) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) , // 10
124     A(REL,IMPL) , A(HL,REG3) , A(A,DE_IND) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) ,
125     A(COND2,REL) , A(REG3,IMM16) , A(ABS16,HL) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) , // 20
126     A(COND2,REL) , A(HL,REG3) , A(HL,ABS16) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) ,
127     A(COND2,REL) , A(REG3,IMM16) , A(ABS16,A) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) , // 30
128     A(COND2,REL) , A(HL,REG3) , A(A,ABS16) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) ,
129     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) , // 40
130     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) ,
131     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) , // 50
132     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) ,
133     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) , // 60
134     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) ,
135     A(REG2,REG1X) , A(REG2,REG1X) , A(REG2,REG1X), A(REG2,REG1X), A(REG2,REG1X), A(REG2,REG1X), A(IMPL,IMPL) , A(REG2,REG1X), // 70
136     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) ,
137     A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , // 80
138     A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) ,
139     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , // 90
140     A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) ,
141     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , // a0
142     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) ,
143     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , // b0
144     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) ,
145     A(COND,IMPL) , A(REG4,IMPL) , A(COND,IMM16), A(IMM16,IMPL), A(COND,IMM16), A(REG4,IMPL) , A(A,IMM8) , A(RST,IMPL) , // c0
146     A(COND,IMPL) , A(IMPL,IMPL) , A(COND,IMM16), A(IMPL,IMPL) , A(COND,IMM16), A(IMM16,IMPL), A(A,IMM8) , A(RST,IMPL) ,
147     A(COND,IMPL) , A(REG4,IMPL) , A(COND,IMM16), A(ABS8,A) , A(COND,IMM16), A(REG4,IMPL) , A(IMM8,IMPL) , A(RST,IMPL) , // d0
148     A(COND,IMPL) , A(IMPL,IMPL) , A(COND,IMM16), A(A,ABS8) , A(COND,IMM16), A(IMPL,IMPL) , A(A,IMM8) , A(RST,IMPL) ,
149     A(COND,IMPL) , A(REG4,IMPL) , A(COND,IMM16), A(SP_IND,HL) , A(COND,IMM16), A(REG4,IMPL) , A(IMM8,IMPL) , A(RST,IMPL) , // e0
150     A(COND,IMPL) , A(HL_IND,IMPL), A(COND,IMM16), A(DE_HL,IMPL), A(COND,IMM16), A(IMPL,IMPL) , A(IMM8,IMPL) , A(RST,IMPL) ,
151     A(COND,IMPL) , A(REG4,IMPL) , A(COND,IMM16), A(IMPL,IMPL) , A(COND,IMM16), A(REG4,IMPL) , A(IMM8,IMPL) , A(RST,IMPL) , // f0
152     A(COND,IMPL) , A(SP,HL) , A(COND,IMM16), A(IMPL,IMPL) , A(COND,IMM16), A(IMPL,IMPL) , A(IMM8,IMPL) , A(RST,IMPL)
153     };
154    
155    
156     /*
157     * sprintf into a "stream"
158     */
159    
160     struct SFILE {
161     char *buffer;
162     char *current;
163     };
164    
165     static int mon_sprintf(SFILE *f, const char *format, ...)
166     {
167     int n;
168     va_list args;
169     va_start(args, format);
170     vsprintf(f->current, format, args);
171     f->current += n = strlen(f->current);
172     va_end(args);
173     return n;
174     }
175    
176    
177     /*
178     * Disassemble one instruction, return number of bytes
179     */
180    
181     static const char *reg_name[] = {"b", "c", "d", "e", "h", "l", "*", "a"};
182     static const char *reg_name_ix[] = {"b", "c", "d", "e", "hx", "lx", "*", "a"}; // undoc
183     static const char *reg_name_iy[] = {"b", "c", "d", "e", "hy", "ly", "*", "a"}; // undoc
184     static const char *reg_name_16[] = {"bc", "de", "hl", "sp"};
185     static const char *reg_name_16_2[] = {"bc", "de", "hl", "af"};
186     static const char *cond_name[] = {"nz", "z", "nc", "c", "po", "pe", "p", "m"};
187    
188     static void operand(SFILE *f, char mode, uint32 &adr, uint8 op, bool ix, bool iy)
189     {
190     switch (mode) {
191     case A_IMPL:
192     break;
193    
194     case A_IMM8:
195     mon_sprintf(f, "$%02x", mon_read_byte(adr)); adr++;
196     break;
197    
198     case A_IMM16:
199     mon_sprintf(f, "$%04x", (mon_read_byte(adr + 1) << 8) | mon_read_byte(adr)); adr += 2;
200     break;
201    
202     case A_ABS8:
203     mon_sprintf(f, "($%02x)", mon_read_byte(adr)); adr++;
204     break;
205    
206     case A_ABS16:
207     mon_sprintf(f, "($%04x)", (mon_read_byte(adr + 1) << 8) | mon_read_byte(adr)); adr += 2;
208     break;
209    
210     case A_REL:
211     mon_sprintf(f, "$%04x", (adr + 2 + (int8)mon_read_byte(adr)) & 0xffff); adr++;
212     break;
213    
214     case A_A:
215     mon_sprintf(f, "a");
216     break;
217    
218     case A_HL:
219     mon_sprintf(f, ix ? "ix" : (iy ? "iy" : "hl"));
220     break;
221    
222     case A_SP:
223     mon_sprintf(f, "sp");
224     break;
225    
226     case A_REG1:
227     case A_REG1X: {
228     int reg = op & 7;
229     if (reg == 6) {
230     if (ix || iy) {
231     mon_sprintf(f, "(%s+$%02x)", ix ? "ix" : "iy", mon_read_byte(adr)); adr++;
232     } else
233     mon_sprintf(f, "(hl)");
234     } else if (mode == A_REG1)
235     mon_sprintf(f, "%s", ix ? reg_name_ix[reg] : (iy ? reg_name_iy[reg] : reg_name[reg]));
236     else
237     mon_sprintf(f, "%s", reg_name[reg]);
238     break;
239     }
240    
241     case A_REG2:
242     case A_REG2X: {
243     int reg = (op >> 3) & 7;
244     if (reg == 6) {
245     if (ix || iy) {
246     mon_sprintf(f, "(%s+$%02x)", ix ? "ix" : "iy", mon_read_byte(adr)); adr++;
247     } else
248     mon_sprintf(f, "(hl)");
249     } else if (mode == A_REG2)
250     mon_sprintf(f, "%s", ix ? reg_name_ix[reg] : (iy ? reg_name_iy[reg] : reg_name[reg]));
251     else
252     mon_sprintf(f, "%s", reg_name[reg]);
253     break;
254     }
255    
256     case A_REG3:
257     mon_sprintf(f, reg_name_16[(op >> 4) & 3]);
258     break;
259    
260     case A_REG4:
261     mon_sprintf(f, reg_name_16_2[(op >> 4) & 3]);
262     break;
263    
264     case A_COND:
265     mon_sprintf(f, cond_name[(op >> 3) & 7]);
266     break;
267    
268     case A_COND2:
269     mon_sprintf(f, cond_name[(op >> 3) & 3]);
270     break;
271    
272     case A_BIT:
273     mon_sprintf(f, "%d", (op >> 3) & 7);
274     break;
275    
276 cebix 1.4 case A_BIT_REG1: { // undoc
277     int reg = op & 7;
278     if (reg == 6)
279     mon_sprintf(f, "%d", (op >> 3) & 7);
280     else
281     mon_sprintf(f, "%d,%s", (op >> 3) & 7, reg_name[reg]);
282     break;
283     }
284    
285 cebix 1.1 case A_RST:
286     mon_sprintf(f, "$%02x", op & 0x38);
287     break;
288    
289     case A_BC_IND:
290     mon_sprintf(f, "(bc)");
291     break;
292    
293     case A_DE_IND:
294     mon_sprintf(f, "(de)");
295     break;
296    
297     case A_HL_IND:
298     mon_sprintf(f, ix ? "(ix)" : (iy ? "(iy)" : "(hl)"));
299     break;
300    
301 cebix 1.4 case A_XY_IND: // undoc
302     mon_sprintf(f, "(%s+$%02x)", ix ? "ix" : "iy", mon_read_byte(adr)); adr++;
303     break;
304    
305 cebix 1.1 case A_SP_IND:
306     mon_sprintf(f, "(sp)");
307     break;
308    
309     case A_DE_HL:
310     mon_sprintf(f, "de,hl");
311     break;
312    
313     case A_AF_AF:
314     mon_sprintf(f, "af,af'");
315     break;
316     }
317     }
318    
319     static int print_instr(SFILE *f, char mnem, char dst_mode, char src_mode, uint32 adr, uint8 op, bool ix, bool iy)
320     {
321     uint32 orig_adr = adr;
322    
323     // Print mnemonic
324     mon_sprintf(f, "%c%c%c%c ", mnem_1[mnem], mnem_2[mnem], mnem_3[mnem], mnem_4[mnem]);
325    
326     // Print destination operand
327     operand(f, dst_mode, adr, op, ix, iy);
328    
329     // Print source operand
330     if (src_mode != A_IMPL)
331     mon_sprintf(f, ",");
332     operand(f, src_mode, adr, op, ix, iy);
333    
334     return adr - orig_adr;
335     }
336    
337     static int disass_cb(SFILE *f, uint32 adr, bool ix, bool iy)
338     {
339     int num;
340    
341     // Fetch opcode
342     uint8 op;
343     if (ix || iy) {
344     op = mon_read_byte(adr + 1);
345     num = 2;
346     } else {
347     op = mon_read_byte(adr);
348     num = 1;
349     }
350    
351     // Decode mnemonic and addressing modes
352 cebix 1.2 char mnem = M_ILLEGAL, dst_mode = A_IMPL, src_mode = A_IMPL;
353 cebix 1.1 switch (op & 0xc0) {
354     case 0x00:
355 cebix 1.4 dst_mode = A_REG1X;
356     if ((ix || iy) && ((op & 7) != 6))
357     src_mode = A_XY_IND;
358 cebix 1.1 switch ((op >> 3) & 7) {
359     case 0: mnem = M_RLC; break;
360     case 1: mnem = M_RRC; break;
361     case 2: mnem = M_RL; break;
362     case 3: mnem = M_RR; break;
363     case 4: mnem = M_SLA; break;
364     case 5: mnem = M_SRA; break;
365     case 6: mnem = M_SL1; break;
366     case 7: mnem = M_SRL; break;
367     }
368     break;
369     case 0x40:
370 cebix 1.4 mnem = M_BIT; dst_mode = A_BIT;
371     if (ix || iy)
372     src_mode = A_XY_IND;
373     else
374     src_mode = A_REG1;
375 cebix 1.1 break;
376     case 0x80:
377 cebix 1.4 mnem = M_RES;
378     if (ix || iy) {
379     dst_mode = A_BIT_REG1;
380     src_mode = A_XY_IND;
381     } else {
382     dst_mode = A_BIT;
383     src_mode = A_REG1;
384     }
385 cebix 1.1 break;
386     case 0xc0:
387 cebix 1.4 mnem = M_SET;
388     if (ix || iy) {
389     dst_mode = A_BIT_REG1;
390     src_mode = A_XY_IND;
391     } else {
392     dst_mode = A_BIT;
393     src_mode = A_REG1;
394     }
395 cebix 1.1 break;
396     }
397    
398     // Print instruction
399     print_instr(f, mnem, dst_mode, src_mode, adr, op, ix, iy);
400     return num;
401     }
402    
403     static int disass_ed(SFILE *f, uint32 adr)
404     {
405     // Fetch opcode
406     uint8 op = mon_read_byte(adr);
407    
408     // Decode mnemonic and addressing modes
409     char mnem, dst_mode = A_IMPL, src_mode = A_IMPL;
410     switch (op) {
411     case 0x40:
412     case 0x48:
413     case 0x50:
414     case 0x58:
415     case 0x60:
416     case 0x68:
417     case 0x78:
418 cebix 1.4 mon_sprintf(f, "in %s,(c)", reg_name[(op >> 3) & 7]);
419 cebix 1.1 return 1;
420     case 0x70:
421 cebix 1.4 mon_sprintf(f, "in (c)");
422 cebix 1.1 return 1;
423    
424     case 0x41:
425     case 0x49:
426     case 0x51:
427     case 0x59:
428     case 0x61:
429     case 0x69:
430     case 0x79:
431 cebix 1.4 mon_sprintf(f, "out (c),%s", reg_name[(op >> 3) & 7]);
432 cebix 1.1 return 1;
433     case 0x71: // undoc
434 cebix 1.4 mon_sprintf(f, "out (c),0");
435 cebix 1.1 return 1;
436    
437     case 0x42:
438     case 0x52:
439     case 0x62:
440     case 0x72:
441     mnem = M_SBC; dst_mode = A_HL; src_mode = A_REG3;
442     break;
443    
444     case 0x43:
445     case 0x53:
446     case 0x63:
447     case 0x73:
448     mnem = M_LD; dst_mode = A_ABS16; src_mode = A_REG3;
449     break;
450    
451     case 0x4a:
452     case 0x5a:
453     case 0x6a:
454     case 0x7a:
455     mnem = M_ADC; dst_mode = A_HL; src_mode = A_REG3;
456     break;
457    
458     case 0x4b:
459     case 0x5b:
460     case 0x6b:
461     case 0x7b:
462     mnem = M_LD; dst_mode = A_REG3; src_mode = A_ABS16;
463     break;
464    
465     case 0x44:
466     case 0x4c: // undoc
467     case 0x54: // undoc
468     case 0x5c: // undoc
469     case 0x64: // undoc
470     case 0x6c: // undoc
471     case 0x74: // undoc
472     case 0x7c: // undoc
473     mnem = M_NEG;
474     break;
475    
476     case 0x45:
477     case 0x55: // undoc
478     case 0x5d: // undoc
479     case 0x65: // undoc
480     case 0x6d: // undoc
481     case 0x75: // undoc
482     case 0x7d: // undoc
483     mnem = M_RETN;
484     break;
485     case 0x4d: mnem = M_RETI; break;
486    
487     case 0x46:
488     case 0x4e: // undoc
489     case 0x66: // undoc
490     case 0x6e: // undoc
491     mnem = M_IM0;
492     break;
493     case 0x56:
494     case 0x76: // undoc
495     mnem = M_IM1;
496     break;
497     case 0x5e:
498     case 0x7e: // undoc
499     mnem = M_IM2;
500     break;
501    
502     case 0x47:
503 cebix 1.4 mon_sprintf(f, "ld i,a");
504 cebix 1.1 return 1;
505     case 0x4f:
506 cebix 1.4 mon_sprintf(f, "ld r,a");
507 cebix 1.1 return 1;
508     case 0x57:
509 cebix 1.4 mon_sprintf(f, "ld a,i");
510 cebix 1.1 return 1;
511     case 0x5f:
512 cebix 1.4 mon_sprintf(f, "ld a,r");
513 cebix 1.1 return 1;
514    
515     case 0x67: mnem = M_RRD; break;
516     case 0x6f: mnem = M_RLD; break;
517    
518     case 0xa0: mnem = M_LDI; break;
519     case 0xa1: mnem = M_CPI; break;
520     case 0xa2: mnem = M_INI; break;
521     case 0xa3: mnem = M_OUTI; break;
522     case 0xa8: mnem = M_LDD; break;
523     case 0xa9: mnem = M_CPD; break;
524     case 0xaa: mnem = M_IND; break;
525     case 0xab: mnem = M_OUTD; break;
526     case 0xb0: mnem = M_LDIR; break;
527     case 0xb1: mnem = M_CPIR; break;
528     case 0xb2: mnem = M_INIR; break;
529     case 0xb3: mnem = M_OTIR; break;
530     case 0xb8: mnem = M_LDDR; break;
531     case 0xb9: mnem = M_CPDR; break;
532     case 0xba: mnem = M_INDR; break;
533     case 0xbb: mnem = M_OTDR; break;
534    
535     default:
536 cebix 1.4 mnem = M_NOP;
537 cebix 1.1 break;
538     }
539    
540     // Print instruction
541     return print_instr(f, mnem, dst_mode, src_mode, adr + 1, op, false, false) + 1;
542     }
543    
544     static int disass(SFILE *f, uint32 adr, bool ix, bool iy)
545     {
546     uint8 op = mon_read_byte(adr);
547     if (op == 0xcb)
548     return disass_cb(f, adr + 1, ix, iy) + 1;
549     else
550     return print_instr(f, mnemonic[op], adr_mode[op] >> 8, adr_mode[op] & 0xff, adr + 1, op, ix, iy) + 1;
551     }
552    
553     int disass_z80(FILE *f, uint32 adr)
554     {
555     int num;
556     char buf[64];
557     SFILE sfile = {buf, buf};
558    
559     switch (mon_read_byte(adr)) {
560     case 0xdd: // ix prefix
561     num = disass(&sfile, adr + 1, true, false) + 1;
562     break;
563     case 0xed:
564     num = disass_ed(&sfile, adr + 1) + 1;
565     break;
566     case 0xfd: // iy prefix
567     num = disass(&sfile, adr + 1, false, true) + 1;
568     break;
569     default:
570     num = disass(&sfile, adr, false, false);
571     break;
572     }
573    
574     for (int i=0; i<4; i++) {
575     if (num > i)
576     fprintf(f, "%02x ", mon_read_byte(adr + i));
577     else
578     fprintf(f, " ");
579     }
580    
581     fprintf(f, "\t%s\n", buf);
582     return num;
583     }