| 1 |
gbeauche |
1.1 |
/* mips.h. Mips opcode list for GDB, the GNU debugger. |
| 2 |
|
|
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
| 3 |
|
|
2003, 2004, 2005 |
| 4 |
|
|
Free Software Foundation, Inc. |
| 5 |
|
|
Contributed by Ralph Campbell and OSF |
| 6 |
|
|
Commented and modified by Ian Lance Taylor, Cygnus Support |
| 7 |
|
|
|
| 8 |
|
|
This file is part of GDB, GAS, and the GNU binutils. |
| 9 |
|
|
|
| 10 |
|
|
GDB, GAS, and the GNU binutils are free software; you can redistribute |
| 11 |
|
|
them and/or modify them under the terms of the GNU General Public |
| 12 |
|
|
License as published by the Free Software Foundation; either version |
| 13 |
|
|
1, or (at your option) any later version. |
| 14 |
|
|
|
| 15 |
|
|
GDB, GAS, and the GNU binutils are distributed in the hope that they |
| 16 |
|
|
will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| 17 |
|
|
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| 18 |
|
|
the GNU General Public License for more details. |
| 19 |
|
|
|
| 20 |
|
|
You should have received a copy of the GNU General Public License |
| 21 |
|
|
along with this file; see the file COPYING. If not, write to the Free |
| 22 |
|
|
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
| 23 |
|
|
|
| 24 |
|
|
#ifndef _MIPS_H_ |
| 25 |
|
|
#define _MIPS_H_ |
| 26 |
|
|
|
| 27 |
|
|
/* These are bit masks and shift counts to use to access the various |
| 28 |
|
|
fields of an instruction. To retrieve the X field of an |
| 29 |
|
|
instruction, use the expression |
| 30 |
|
|
(i >> OP_SH_X) & OP_MASK_X |
| 31 |
|
|
To set the same field (to j), use |
| 32 |
|
|
i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) |
| 33 |
|
|
|
| 34 |
|
|
Make sure you use fields that are appropriate for the instruction, |
| 35 |
|
|
of course. |
| 36 |
|
|
|
| 37 |
|
|
The 'i' format uses OP, RS, RT and IMMEDIATE. |
| 38 |
|
|
|
| 39 |
|
|
The 'j' format uses OP and TARGET. |
| 40 |
|
|
|
| 41 |
|
|
The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. |
| 42 |
|
|
|
| 43 |
|
|
The 'b' format uses OP, RS, RT and DELTA. |
| 44 |
|
|
|
| 45 |
|
|
The floating point 'i' format uses OP, RS, RT and IMMEDIATE. |
| 46 |
|
|
|
| 47 |
|
|
The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. |
| 48 |
|
|
|
| 49 |
|
|
A breakpoint instruction uses OP, CODE and SPEC (10 bits of the |
| 50 |
|
|
breakpoint instruction are not defined; Kane says the breakpoint |
| 51 |
|
|
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers |
| 52 |
|
|
only use ten bits). An optional two-operand form of break/sdbbp |
| 53 |
|
|
allows the lower ten bits to be set too, and MIPS32 and later |
| 54 |
|
|
architectures allow 20 bits to be set with a signal operand |
| 55 |
|
|
(using CODE20). |
| 56 |
|
|
|
| 57 |
|
|
The syscall instruction uses CODE20. |
| 58 |
|
|
|
| 59 |
|
|
The general coprocessor instructions use COPZ. */ |
| 60 |
|
|
|
| 61 |
|
|
#define OP_MASK_OP 0x3f |
| 62 |
|
|
#define OP_SH_OP 26 |
| 63 |
|
|
#define OP_MASK_RS 0x1f |
| 64 |
|
|
#define OP_SH_RS 21 |
| 65 |
|
|
#define OP_MASK_FR 0x1f |
| 66 |
|
|
#define OP_SH_FR 21 |
| 67 |
|
|
#define OP_MASK_FMT 0x1f |
| 68 |
|
|
#define OP_SH_FMT 21 |
| 69 |
|
|
#define OP_MASK_BCC 0x7 |
| 70 |
|
|
#define OP_SH_BCC 18 |
| 71 |
|
|
#define OP_MASK_CODE 0x3ff |
| 72 |
|
|
#define OP_SH_CODE 16 |
| 73 |
|
|
#define OP_MASK_CODE2 0x3ff |
| 74 |
|
|
#define OP_SH_CODE2 6 |
| 75 |
|
|
#define OP_MASK_RT 0x1f |
| 76 |
|
|
#define OP_SH_RT 16 |
| 77 |
|
|
#define OP_MASK_FT 0x1f |
| 78 |
|
|
#define OP_SH_FT 16 |
| 79 |
|
|
#define OP_MASK_CACHE 0x1f |
| 80 |
|
|
#define OP_SH_CACHE 16 |
| 81 |
|
|
#define OP_MASK_RD 0x1f |
| 82 |
|
|
#define OP_SH_RD 11 |
| 83 |
|
|
#define OP_MASK_FS 0x1f |
| 84 |
|
|
#define OP_SH_FS 11 |
| 85 |
|
|
#define OP_MASK_PREFX 0x1f |
| 86 |
|
|
#define OP_SH_PREFX 11 |
| 87 |
|
|
#define OP_MASK_CCC 0x7 |
| 88 |
|
|
#define OP_SH_CCC 8 |
| 89 |
|
|
#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ |
| 90 |
|
|
#define OP_SH_CODE20 6 |
| 91 |
|
|
#define OP_MASK_SHAMT 0x1f |
| 92 |
|
|
#define OP_SH_SHAMT 6 |
| 93 |
|
|
#define OP_MASK_FD 0x1f |
| 94 |
|
|
#define OP_SH_FD 6 |
| 95 |
|
|
#define OP_MASK_TARGET 0x3ffffff |
| 96 |
|
|
#define OP_SH_TARGET 0 |
| 97 |
|
|
#define OP_MASK_COPZ 0x1ffffff |
| 98 |
|
|
#define OP_SH_COPZ 0 |
| 99 |
|
|
#define OP_MASK_IMMEDIATE 0xffff |
| 100 |
|
|
#define OP_SH_IMMEDIATE 0 |
| 101 |
|
|
#define OP_MASK_DELTA 0xffff |
| 102 |
|
|
#define OP_SH_DELTA 0 |
| 103 |
|
|
#define OP_MASK_FUNCT 0x3f |
| 104 |
|
|
#define OP_SH_FUNCT 0 |
| 105 |
|
|
#define OP_MASK_SPEC 0x3f |
| 106 |
|
|
#define OP_SH_SPEC 0 |
| 107 |
|
|
#define OP_SH_LOCC 8 /* FP condition code. */ |
| 108 |
|
|
#define OP_SH_HICC 18 /* FP condition code. */ |
| 109 |
|
|
#define OP_MASK_CC 0x7 |
| 110 |
|
|
#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ |
| 111 |
|
|
#define OP_MASK_COP1NORM 0x1 /* a single bit. */ |
| 112 |
|
|
#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ |
| 113 |
|
|
#define OP_MASK_COP1SPEC 0xf |
| 114 |
|
|
#define OP_MASK_COP1SCLR 0x4 |
| 115 |
|
|
#define OP_MASK_COP1CMP 0x3 |
| 116 |
|
|
#define OP_SH_COP1CMP 4 |
| 117 |
|
|
#define OP_SH_FORMAT 21 /* FP short format field. */ |
| 118 |
|
|
#define OP_MASK_FORMAT 0x7 |
| 119 |
|
|
#define OP_SH_TRUE 16 |
| 120 |
|
|
#define OP_MASK_TRUE 0x1 |
| 121 |
|
|
#define OP_SH_GE 17 |
| 122 |
|
|
#define OP_MASK_GE 0x01 |
| 123 |
|
|
#define OP_SH_UNSIGNED 16 |
| 124 |
|
|
#define OP_MASK_UNSIGNED 0x1 |
| 125 |
|
|
#define OP_SH_HINT 16 |
| 126 |
|
|
#define OP_MASK_HINT 0x1f |
| 127 |
|
|
#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ |
| 128 |
|
|
#define OP_MASK_MMI 0x3f |
| 129 |
|
|
#define OP_SH_MMISUB 6 |
| 130 |
|
|
#define OP_MASK_MMISUB 0x1f |
| 131 |
|
|
#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ |
| 132 |
|
|
#define OP_SH_PERFREG 1 |
| 133 |
|
|
#define OP_SH_SEL 0 /* Coprocessor select field. */ |
| 134 |
|
|
#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ |
| 135 |
|
|
#define OP_SH_CODE19 6 /* 19 bit wait code. */ |
| 136 |
|
|
#define OP_MASK_CODE19 0x7ffff |
| 137 |
|
|
#define OP_SH_ALN 21 |
| 138 |
|
|
#define OP_MASK_ALN 0x7 |
| 139 |
|
|
#define OP_SH_VSEL 21 |
| 140 |
|
|
#define OP_MASK_VSEL 0x1f |
| 141 |
|
|
#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
| 142 |
|
|
but 0x8-0xf don't select bytes. */ |
| 143 |
|
|
#define OP_SH_VECBYTE 22 |
| 144 |
|
|
#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ |
| 145 |
|
|
#define OP_SH_VECALIGN 21 |
| 146 |
|
|
#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
| 147 |
|
|
#define OP_SH_INSMSB 11 |
| 148 |
|
|
#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ |
| 149 |
|
|
#define OP_SH_EXTMSBD 11 |
| 150 |
|
|
|
| 151 |
|
|
/* MIPS DSP ASE */ |
| 152 |
|
|
#define OP_SH_DSPACC 11 |
| 153 |
|
|
#define OP_MASK_DSPACC 0x3 |
| 154 |
|
|
#define OP_SH_DSPACC_S 21 |
| 155 |
|
|
#define OP_MASK_DSPACC_S 0x3 |
| 156 |
|
|
#define OP_SH_DSPSFT 20 |
| 157 |
|
|
#define OP_MASK_DSPSFT 0x3f |
| 158 |
|
|
#define OP_SH_DSPSFT_7 19 |
| 159 |
|
|
#define OP_MASK_DSPSFT_7 0x7f |
| 160 |
|
|
#define OP_SH_SA3 21 |
| 161 |
|
|
#define OP_MASK_SA3 0x7 |
| 162 |
|
|
#define OP_SH_SA4 21 |
| 163 |
|
|
#define OP_MASK_SA4 0xf |
| 164 |
|
|
#define OP_SH_IMM8 16 |
| 165 |
|
|
#define OP_MASK_IMM8 0xff |
| 166 |
|
|
#define OP_SH_IMM10 16 |
| 167 |
|
|
#define OP_MASK_IMM10 0x3ff |
| 168 |
|
|
#define OP_SH_WRDSP 11 |
| 169 |
|
|
#define OP_MASK_WRDSP 0x3f |
| 170 |
|
|
#define OP_SH_RDDSP 16 |
| 171 |
|
|
#define OP_MASK_RDDSP 0x3f |
| 172 |
|
|
|
| 173 |
|
|
/* MIPS MT ASE */ |
| 174 |
|
|
#define OP_SH_MT_U 5 |
| 175 |
|
|
#define OP_MASK_MT_U 0x1 |
| 176 |
|
|
#define OP_SH_MT_H 4 |
| 177 |
|
|
#define OP_MASK_MT_H 0x1 |
| 178 |
|
|
#define OP_SH_MTACC_T 18 |
| 179 |
|
|
#define OP_MASK_MTACC_T 0x3 |
| 180 |
|
|
#define OP_SH_MTACC_D 13 |
| 181 |
|
|
#define OP_MASK_MTACC_D 0x3 |
| 182 |
|
|
|
| 183 |
|
|
#define OP_OP_COP0 0x10 |
| 184 |
|
|
#define OP_OP_COP1 0x11 |
| 185 |
|
|
#define OP_OP_COP2 0x12 |
| 186 |
|
|
#define OP_OP_COP3 0x13 |
| 187 |
|
|
#define OP_OP_LWC1 0x31 |
| 188 |
|
|
#define OP_OP_LWC2 0x32 |
| 189 |
|
|
#define OP_OP_LWC3 0x33 /* a.k.a. pref */ |
| 190 |
|
|
#define OP_OP_LDC1 0x35 |
| 191 |
|
|
#define OP_OP_LDC2 0x36 |
| 192 |
|
|
#define OP_OP_LDC3 0x37 /* a.k.a. ld */ |
| 193 |
|
|
#define OP_OP_SWC1 0x39 |
| 194 |
|
|
#define OP_OP_SWC2 0x3a |
| 195 |
|
|
#define OP_OP_SWC3 0x3b |
| 196 |
|
|
#define OP_OP_SDC1 0x3d |
| 197 |
|
|
#define OP_OP_SDC2 0x3e |
| 198 |
|
|
#define OP_OP_SDC3 0x3f /* a.k.a. sd */ |
| 199 |
|
|
|
| 200 |
|
|
/* Values in the 'VSEL' field. */ |
| 201 |
|
|
#define MDMX_FMTSEL_IMM_QH 0x1d |
| 202 |
|
|
#define MDMX_FMTSEL_IMM_OB 0x1e |
| 203 |
|
|
#define MDMX_FMTSEL_VEC_QH 0x15 |
| 204 |
|
|
#define MDMX_FMTSEL_VEC_OB 0x16 |
| 205 |
|
|
|
| 206 |
|
|
/* UDI */ |
| 207 |
|
|
#define OP_SH_UDI1 6 |
| 208 |
|
|
#define OP_MASK_UDI1 0x1f |
| 209 |
|
|
#define OP_SH_UDI2 6 |
| 210 |
|
|
#define OP_MASK_UDI2 0x3ff |
| 211 |
|
|
#define OP_SH_UDI3 6 |
| 212 |
|
|
#define OP_MASK_UDI3 0x7fff |
| 213 |
|
|
#define OP_SH_UDI4 6 |
| 214 |
|
|
#define OP_MASK_UDI4 0xfffff |
| 215 |
|
|
|
| 216 |
|
|
/* This structure holds information for a particular instruction. */ |
| 217 |
|
|
|
| 218 |
|
|
struct mips_opcode |
| 219 |
|
|
{ |
| 220 |
|
|
/* The name of the instruction. */ |
| 221 |
|
|
const char *name; |
| 222 |
|
|
/* A string describing the arguments for this instruction. */ |
| 223 |
|
|
const char *args; |
| 224 |
|
|
/* The basic opcode for the instruction. When assembling, this |
| 225 |
|
|
opcode is modified by the arguments to produce the actual opcode |
| 226 |
|
|
that is used. If pinfo is INSN_MACRO, then this is 0. */ |
| 227 |
|
|
unsigned long match; |
| 228 |
|
|
/* If pinfo is not INSN_MACRO, then this is a bit mask for the |
| 229 |
|
|
relevant portions of the opcode when disassembling. If the |
| 230 |
|
|
actual opcode anded with the match field equals the opcode field, |
| 231 |
|
|
then we have found the correct instruction. If pinfo is |
| 232 |
|
|
INSN_MACRO, then this field is the macro identifier. */ |
| 233 |
|
|
unsigned long mask; |
| 234 |
|
|
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection |
| 235 |
|
|
of bits describing the instruction, notably any relevant hazard |
| 236 |
|
|
information. */ |
| 237 |
|
|
unsigned long pinfo; |
| 238 |
|
|
/* A collection of additional bits describing the instruction. */ |
| 239 |
|
|
unsigned long pinfo2; |
| 240 |
|
|
/* A collection of bits describing the instruction sets of which this |
| 241 |
|
|
instruction or macro is a member. */ |
| 242 |
|
|
unsigned long membership; |
| 243 |
|
|
}; |
| 244 |
|
|
|
| 245 |
|
|
/* These are the characters which may appear in the args field of an |
| 246 |
|
|
instruction. They appear in the order in which the fields appear |
| 247 |
|
|
when the instruction is used. Commas and parentheses in the args |
| 248 |
|
|
string are ignored when assembling, and written into the output |
| 249 |
|
|
when disassembling. |
| 250 |
|
|
|
| 251 |
|
|
Each of these characters corresponds to a mask field defined above. |
| 252 |
|
|
|
| 253 |
|
|
"<" 5 bit shift amount (OP_*_SHAMT) |
| 254 |
|
|
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) |
| 255 |
|
|
"a" 26 bit target address (OP_*_TARGET) |
| 256 |
|
|
"b" 5 bit base register (OP_*_RS) |
| 257 |
|
|
"c" 10 bit breakpoint code (OP_*_CODE) |
| 258 |
|
|
"d" 5 bit destination register specifier (OP_*_RD) |
| 259 |
|
|
"h" 5 bit prefx hint (OP_*_PREFX) |
| 260 |
|
|
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE) |
| 261 |
|
|
"j" 16 bit signed immediate (OP_*_DELTA) |
| 262 |
|
|
"k" 5 bit cache opcode in target register position (OP_*_CACHE) |
| 263 |
|
|
Also used for immediate operands in vr5400 vector insns. |
| 264 |
|
|
"o" 16 bit signed offset (OP_*_DELTA) |
| 265 |
|
|
"p" 16 bit PC relative branch target address (OP_*_DELTA) |
| 266 |
|
|
"q" 10 bit extra breakpoint code (OP_*_CODE2) |
| 267 |
|
|
"r" 5 bit same register used as both source and target (OP_*_RS) |
| 268 |
|
|
"s" 5 bit source register specifier (OP_*_RS) |
| 269 |
|
|
"t" 5 bit target register (OP_*_RT) |
| 270 |
|
|
"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) |
| 271 |
|
|
"v" 5 bit same register used as both source and destination (OP_*_RS) |
| 272 |
|
|
"w" 5 bit same register used as both target and destination (OP_*_RT) |
| 273 |
|
|
"U" 5 bit same destination register in both OP_*_RD and OP_*_RT |
| 274 |
|
|
(used by clo and clz) |
| 275 |
|
|
"C" 25 bit coprocessor function code (OP_*_COPZ) |
| 276 |
|
|
"B" 20 bit syscall/breakpoint function code (OP_*_CODE20) |
| 277 |
|
|
"J" 19 bit wait function code (OP_*_CODE19) |
| 278 |
|
|
"x" accept and ignore register name |
| 279 |
|
|
"z" must be zero register |
| 280 |
|
|
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) |
| 281 |
|
|
"+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes |
| 282 |
|
|
LSB (OP_*_SHAMT). |
| 283 |
|
|
Enforces: 0 <= pos < 32. |
| 284 |
|
|
"+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). |
| 285 |
|
|
Requires that "+A" or "+E" occur first to set position. |
| 286 |
|
|
Enforces: 0 < (pos+size) <= 32. |
| 287 |
|
|
"+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). |
| 288 |
|
|
Requires that "+A" or "+E" occur first to set position. |
| 289 |
|
|
Enforces: 0 < (pos+size) <= 32. |
| 290 |
|
|
(Also used by "dext" w/ different limits, but limits for |
| 291 |
|
|
that are checked by the M_DEXT macro.) |
| 292 |
|
|
"+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). |
| 293 |
|
|
Enforces: 32 <= pos < 64. |
| 294 |
|
|
"+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). |
| 295 |
|
|
Requires that "+A" or "+E" occur first to set position. |
| 296 |
|
|
Enforces: 32 < (pos+size) <= 64. |
| 297 |
|
|
"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). |
| 298 |
|
|
Requires that "+A" or "+E" occur first to set position. |
| 299 |
|
|
Enforces: 32 < (pos+size) <= 64. |
| 300 |
|
|
"+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). |
| 301 |
|
|
Requires that "+A" or "+E" occur first to set position. |
| 302 |
|
|
Enforces: 32 < (pos+size) <= 64. |
| 303 |
|
|
|
| 304 |
|
|
Floating point instructions: |
| 305 |
|
|
"D" 5 bit destination register (OP_*_FD) |
| 306 |
|
|
"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) |
| 307 |
|
|
"N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) |
| 308 |
|
|
"S" 5 bit fs source 1 register (OP_*_FS) |
| 309 |
|
|
"T" 5 bit ft source 2 register (OP_*_FT) |
| 310 |
|
|
"R" 5 bit fr source 3 register (OP_*_FR) |
| 311 |
|
|
"V" 5 bit same register used as floating source and destination (OP_*_FS) |
| 312 |
|
|
"W" 5 bit same register used as floating target and destination (OP_*_FT) |
| 313 |
|
|
|
| 314 |
|
|
Coprocessor instructions: |
| 315 |
|
|
"E" 5 bit target register (OP_*_RT) |
| 316 |
|
|
"G" 5 bit destination register (OP_*_RD) |
| 317 |
|
|
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) |
| 318 |
|
|
"P" 5 bit performance-monitor register (OP_*_PERFREG) |
| 319 |
|
|
"e" 5 bit vector register byte specifier (OP_*_VECBYTE) |
| 320 |
|
|
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) |
| 321 |
|
|
see also "k" above |
| 322 |
|
|
"+D" Combined destination register ("G") and sel ("H") for CP0 ops, |
| 323 |
|
|
for pretty-printing in disassembly only. |
| 324 |
|
|
|
| 325 |
|
|
Macro instructions: |
| 326 |
|
|
"A" General 32 bit expression |
| 327 |
|
|
"I" 32 bit immediate (value placed in imm_expr). |
| 328 |
|
|
"+I" 32 bit immediate (value placed in imm2_expr). |
| 329 |
|
|
"F" 64 bit floating point constant in .rdata |
| 330 |
|
|
"L" 64 bit floating point constant in .lit8 |
| 331 |
|
|
"f" 32 bit floating point constant |
| 332 |
|
|
"l" 32 bit floating point constant in .lit4 |
| 333 |
|
|
|
| 334 |
|
|
MDMX instruction operands (note that while these use the FP register |
| 335 |
|
|
fields, they accept both $fN and $vN names for the registers): |
| 336 |
|
|
"O" MDMX alignment offset (OP_*_ALN) |
| 337 |
|
|
"Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) |
| 338 |
|
|
"X" MDMX destination register (OP_*_FD) |
| 339 |
|
|
"Y" MDMX source register (OP_*_FS) |
| 340 |
|
|
"Z" MDMX source register (OP_*_FT) |
| 341 |
|
|
|
| 342 |
|
|
DSP ASE usage: |
| 343 |
|
|
"3" 3 bit unsigned immediate (OP_*_SA3) |
| 344 |
|
|
"4" 4 bit unsigned immediate (OP_*_SA4) |
| 345 |
|
|
"5" 8 bit unsigned immediate (OP_*_IMM8) |
| 346 |
|
|
"6" 5 bit unsigned immediate (OP_*_RS) |
| 347 |
|
|
"7" 2 bit dsp accumulator register (OP_*_DSPACC) |
| 348 |
|
|
"8" 6 bit unsigned immediate (OP_*_WRDSP) |
| 349 |
|
|
"9" 2 bit dsp accumulator register (OP_*_DSPACC_S) |
| 350 |
|
|
"0" 6 bit signed immediate (OP_*_DSPSFT) |
| 351 |
|
|
":" 7 bit signed immediate (OP_*_DSPSFT_7) |
| 352 |
|
|
"'" 6 bit unsigned immediate (OP_*_RDDSP) |
| 353 |
|
|
"@" 10 bit signed immediate (OP_*_IMM10) |
| 354 |
|
|
|
| 355 |
|
|
MT ASE usage: |
| 356 |
|
|
"!" 1 bit usermode flag (OP_*_MT_U) |
| 357 |
|
|
"$" 1 bit load high flag (OP_*_MT_H) |
| 358 |
|
|
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) |
| 359 |
|
|
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) |
| 360 |
|
|
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) |
| 361 |
|
|
"+t" 5 bit coprocessor 0 destination register (OP_*_RT) |
| 362 |
|
|
"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only |
| 363 |
|
|
|
| 364 |
|
|
UDI immediates: |
| 365 |
|
|
"+1" UDI immediate bits 6-10 |
| 366 |
|
|
"+2" UDI immediate bits 6-15 |
| 367 |
|
|
"+3" UDI immediate bits 6-20 |
| 368 |
|
|
"+4" UDI immediate bits 6-25 |
| 369 |
|
|
|
| 370 |
|
|
Other: |
| 371 |
|
|
"()" parens surrounding optional value |
| 372 |
|
|
"," separates operands |
| 373 |
|
|
"[]" brackets around index for vector-op scalar operand specifier (vr5400) |
| 374 |
|
|
"+" Start of extension sequence. |
| 375 |
|
|
|
| 376 |
|
|
Characters used so far, for quick reference when adding more: |
| 377 |
|
|
"34567890" |
| 378 |
|
|
"%[]<>(),+:'@!$*&" |
| 379 |
|
|
"ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
| 380 |
|
|
"abcdefghijklopqrstuvwxz" |
| 381 |
|
|
|
| 382 |
|
|
Extension character sequences used so far ("+" followed by the |
| 383 |
|
|
following), for quick reference when adding more: |
| 384 |
|
|
"1234" |
| 385 |
|
|
"ABCDEFGHIT" |
| 386 |
|
|
"t" |
| 387 |
|
|
*/ |
| 388 |
|
|
|
| 389 |
|
|
/* These are the bits which may be set in the pinfo field of an |
| 390 |
|
|
instructions, if it is not equal to INSN_MACRO. */ |
| 391 |
|
|
|
| 392 |
|
|
/* Modifies the general purpose register in OP_*_RD. */ |
| 393 |
|
|
#define INSN_WRITE_GPR_D 0x00000001 |
| 394 |
|
|
/* Modifies the general purpose register in OP_*_RT. */ |
| 395 |
|
|
#define INSN_WRITE_GPR_T 0x00000002 |
| 396 |
|
|
/* Modifies general purpose register 31. */ |
| 397 |
|
|
#define INSN_WRITE_GPR_31 0x00000004 |
| 398 |
|
|
/* Modifies the floating point register in OP_*_FD. */ |
| 399 |
|
|
#define INSN_WRITE_FPR_D 0x00000008 |
| 400 |
|
|
/* Modifies the floating point register in OP_*_FS. */ |
| 401 |
|
|
#define INSN_WRITE_FPR_S 0x00000010 |
| 402 |
|
|
/* Modifies the floating point register in OP_*_FT. */ |
| 403 |
|
|
#define INSN_WRITE_FPR_T 0x00000020 |
| 404 |
|
|
/* Reads the general purpose register in OP_*_RS. */ |
| 405 |
|
|
#define INSN_READ_GPR_S 0x00000040 |
| 406 |
|
|
/* Reads the general purpose register in OP_*_RT. */ |
| 407 |
|
|
#define INSN_READ_GPR_T 0x00000080 |
| 408 |
|
|
/* Reads the floating point register in OP_*_FS. */ |
| 409 |
|
|
#define INSN_READ_FPR_S 0x00000100 |
| 410 |
|
|
/* Reads the floating point register in OP_*_FT. */ |
| 411 |
|
|
#define INSN_READ_FPR_T 0x00000200 |
| 412 |
|
|
/* Reads the floating point register in OP_*_FR. */ |
| 413 |
|
|
#define INSN_READ_FPR_R 0x00000400 |
| 414 |
|
|
/* Modifies coprocessor condition code. */ |
| 415 |
|
|
#define INSN_WRITE_COND_CODE 0x00000800 |
| 416 |
|
|
/* Reads coprocessor condition code. */ |
| 417 |
|
|
#define INSN_READ_COND_CODE 0x00001000 |
| 418 |
|
|
/* TLB operation. */ |
| 419 |
|
|
#define INSN_TLB 0x00002000 |
| 420 |
|
|
/* Reads coprocessor register other than floating point register. */ |
| 421 |
|
|
#define INSN_COP 0x00004000 |
| 422 |
|
|
/* Instruction loads value from memory, requiring delay. */ |
| 423 |
|
|
#define INSN_LOAD_MEMORY_DELAY 0x00008000 |
| 424 |
|
|
/* Instruction loads value from coprocessor, requiring delay. */ |
| 425 |
|
|
#define INSN_LOAD_COPROC_DELAY 0x00010000 |
| 426 |
|
|
/* Instruction has unconditional branch delay slot. */ |
| 427 |
|
|
#define INSN_UNCOND_BRANCH_DELAY 0x00020000 |
| 428 |
|
|
/* Instruction has conditional branch delay slot. */ |
| 429 |
|
|
#define INSN_COND_BRANCH_DELAY 0x00040000 |
| 430 |
|
|
/* Conditional branch likely: if branch not taken, insn nullified. */ |
| 431 |
|
|
#define INSN_COND_BRANCH_LIKELY 0x00080000 |
| 432 |
|
|
/* Moves to coprocessor register, requiring delay. */ |
| 433 |
|
|
#define INSN_COPROC_MOVE_DELAY 0x00100000 |
| 434 |
|
|
/* Loads coprocessor register from memory, requiring delay. */ |
| 435 |
|
|
#define INSN_COPROC_MEMORY_DELAY 0x00200000 |
| 436 |
|
|
/* Reads the HI register. */ |
| 437 |
|
|
#define INSN_READ_HI 0x00400000 |
| 438 |
|
|
/* Reads the LO register. */ |
| 439 |
|
|
#define INSN_READ_LO 0x00800000 |
| 440 |
|
|
/* Modifies the HI register. */ |
| 441 |
|
|
#define INSN_WRITE_HI 0x01000000 |
| 442 |
|
|
/* Modifies the LO register. */ |
| 443 |
|
|
#define INSN_WRITE_LO 0x02000000 |
| 444 |
|
|
/* Takes a trap (easier to keep out of delay slot). */ |
| 445 |
|
|
#define INSN_TRAP 0x04000000 |
| 446 |
|
|
/* Instruction stores value into memory. */ |
| 447 |
|
|
#define INSN_STORE_MEMORY 0x08000000 |
| 448 |
|
|
/* Instruction uses single precision floating point. */ |
| 449 |
|
|
#define FP_S 0x10000000 |
| 450 |
|
|
/* Instruction uses double precision floating point. */ |
| 451 |
|
|
#define FP_D 0x20000000 |
| 452 |
|
|
/* Instruction is part of the tx39's integer multiply family. */ |
| 453 |
|
|
#define INSN_MULT 0x40000000 |
| 454 |
|
|
/* Instruction synchronize shared memory. */ |
| 455 |
|
|
#define INSN_SYNC 0x80000000 |
| 456 |
|
|
|
| 457 |
|
|
/* These are the bits which may be set in the pinfo2 field of an |
| 458 |
|
|
instruction. */ |
| 459 |
|
|
|
| 460 |
|
|
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ |
| 461 |
|
|
#define INSN2_ALIAS 0x00000001 |
| 462 |
|
|
/* Instruction reads MDMX accumulator. */ |
| 463 |
|
|
#define INSN2_READ_MDMX_ACC 0x00000002 |
| 464 |
|
|
/* Instruction writes MDMX accumulator. */ |
| 465 |
|
|
#define INSN2_WRITE_MDMX_ACC 0x00000004 |
| 466 |
|
|
|
| 467 |
|
|
/* Instruction is actually a macro. It should be ignored by the |
| 468 |
|
|
disassembler, and requires special treatment by the assembler. */ |
| 469 |
|
|
#define INSN_MACRO 0xffffffff |
| 470 |
|
|
|
| 471 |
|
|
/* Masks used to mark instructions to indicate which MIPS ISA level |
| 472 |
|
|
they were introduced in. ISAs, as defined below, are logical |
| 473 |
|
|
ORs of these bits, indicating that they support the instructions |
| 474 |
|
|
defined at the given level. */ |
| 475 |
|
|
|
| 476 |
|
|
#define INSN_ISA_MASK 0x00000fff |
| 477 |
|
|
#define INSN_ISA1 0x00000001 |
| 478 |
|
|
#define INSN_ISA2 0x00000002 |
| 479 |
|
|
#define INSN_ISA3 0x00000004 |
| 480 |
|
|
#define INSN_ISA4 0x00000008 |
| 481 |
|
|
#define INSN_ISA5 0x00000010 |
| 482 |
|
|
#define INSN_ISA32 0x00000020 |
| 483 |
|
|
#define INSN_ISA64 0x00000040 |
| 484 |
|
|
#define INSN_ISA32R2 0x00000080 |
| 485 |
|
|
#define INSN_ISA64R2 0x00000100 |
| 486 |
|
|
|
| 487 |
|
|
/* Masks used for MIPS-defined ASEs. */ |
| 488 |
|
|
#define INSN_ASE_MASK 0x1c00f000 |
| 489 |
|
|
|
| 490 |
|
|
/* DSP ASE */ |
| 491 |
|
|
#define INSN_DSP 0x00001000 |
| 492 |
|
|
#define INSN_DSP64 0x00002000 |
| 493 |
|
|
/* MIPS 16 ASE */ |
| 494 |
|
|
#define INSN_MIPS16 0x00004000 |
| 495 |
|
|
/* MIPS-3D ASE */ |
| 496 |
|
|
#define INSN_MIPS3D 0x00008000 |
| 497 |
|
|
|
| 498 |
|
|
/* Chip specific instructions. These are bitmasks. */ |
| 499 |
|
|
|
| 500 |
|
|
/* MIPS R4650 instruction. */ |
| 501 |
|
|
#define INSN_4650 0x00010000 |
| 502 |
|
|
/* LSI R4010 instruction. */ |
| 503 |
|
|
#define INSN_4010 0x00020000 |
| 504 |
|
|
/* NEC VR4100 instruction. */ |
| 505 |
|
|
#define INSN_4100 0x00040000 |
| 506 |
|
|
/* Toshiba R3900 instruction. */ |
| 507 |
|
|
#define INSN_3900 0x00080000 |
| 508 |
|
|
/* MIPS R10000 instruction. */ |
| 509 |
|
|
#define INSN_10000 0x00100000 |
| 510 |
|
|
/* Broadcom SB-1 instruction. */ |
| 511 |
|
|
#define INSN_SB1 0x00200000 |
| 512 |
|
|
/* NEC VR4111/VR4181 instruction. */ |
| 513 |
|
|
#define INSN_4111 0x00400000 |
| 514 |
|
|
/* NEC VR4120 instruction. */ |
| 515 |
|
|
#define INSN_4120 0x00800000 |
| 516 |
|
|
/* NEC VR5400 instruction. */ |
| 517 |
|
|
#define INSN_5400 0x01000000 |
| 518 |
|
|
/* NEC VR5500 instruction. */ |
| 519 |
|
|
#define INSN_5500 0x02000000 |
| 520 |
|
|
|
| 521 |
|
|
/* MDMX ASE */ |
| 522 |
|
|
#define INSN_MDMX 0x04000000 |
| 523 |
|
|
/* MT ASE */ |
| 524 |
|
|
#define INSN_MT 0x08000000 |
| 525 |
|
|
/* SmartMIPS ASE. */ |
| 526 |
|
|
#define INSN_SMARTMIPS 0x10000000 |
| 527 |
|
|
|
| 528 |
|
|
/* MIPS ISA defines, use instead of hardcoding ISA level. */ |
| 529 |
|
|
|
| 530 |
|
|
#define ISA_UNKNOWN 0 /* Gas internal use. */ |
| 531 |
|
|
#define ISA_MIPS1 (INSN_ISA1) |
| 532 |
|
|
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) |
| 533 |
|
|
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) |
| 534 |
|
|
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) |
| 535 |
|
|
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) |
| 536 |
|
|
|
| 537 |
|
|
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) |
| 538 |
|
|
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) |
| 539 |
|
|
|
| 540 |
|
|
#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) |
| 541 |
|
|
#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) |
| 542 |
|
|
|
| 543 |
|
|
|
| 544 |
|
|
/* CPU defines, use instead of hardcoding processor number. Keep this |
| 545 |
|
|
in sync with bfd/archures.c in order for machine selection to work. */ |
| 546 |
|
|
#define CPU_UNKNOWN 0 /* Gas internal use. */ |
| 547 |
|
|
#define CPU_R3000 3000 |
| 548 |
|
|
#define CPU_R3900 3900 |
| 549 |
|
|
#define CPU_R4000 4000 |
| 550 |
|
|
#define CPU_R4010 4010 |
| 551 |
|
|
#define CPU_VR4100 4100 |
| 552 |
|
|
#define CPU_R4111 4111 |
| 553 |
|
|
#define CPU_VR4120 4120 |
| 554 |
|
|
#define CPU_R4300 4300 |
| 555 |
|
|
#define CPU_R4400 4400 |
| 556 |
|
|
#define CPU_R4600 4600 |
| 557 |
|
|
#define CPU_R4650 4650 |
| 558 |
|
|
#define CPU_R5000 5000 |
| 559 |
|
|
#define CPU_VR5400 5400 |
| 560 |
|
|
#define CPU_VR5500 5500 |
| 561 |
|
|
#define CPU_R6000 6000 |
| 562 |
|
|
#define CPU_RM7000 7000 |
| 563 |
|
|
#define CPU_R8000 8000 |
| 564 |
|
|
#define CPU_RM9000 9000 |
| 565 |
|
|
#define CPU_R10000 10000 |
| 566 |
|
|
#define CPU_R12000 12000 |
| 567 |
|
|
#define CPU_MIPS16 16 |
| 568 |
|
|
#define CPU_MIPS32 32 |
| 569 |
|
|
#define CPU_MIPS32R2 33 |
| 570 |
|
|
#define CPU_MIPS5 5 |
| 571 |
|
|
#define CPU_MIPS64 64 |
| 572 |
|
|
#define CPU_MIPS64R2 65 |
| 573 |
|
|
#define CPU_SB1 12310201 /* octal 'SB', 01. */ |
| 574 |
|
|
|
| 575 |
|
|
/* Test for membership in an ISA including chip specific ISAs. INSN |
| 576 |
|
|
is pointer to an element of the opcode table; ISA is the specified |
| 577 |
|
|
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to |
| 578 |
|
|
test, or zero if no CPU specific ISA test is desired. */ |
| 579 |
|
|
|
| 580 |
|
|
#define OPCODE_IS_MEMBER(insn, isa, cpu) \ |
| 581 |
|
|
(((insn)->membership & isa) != 0 \ |
| 582 |
|
|
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ |
| 583 |
|
|
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ |
| 584 |
|
|
|| (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ |
| 585 |
|
|
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ |
| 586 |
|
|
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ |
| 587 |
|
|
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ |
| 588 |
|
|
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \ |
| 589 |
|
|
&& ((insn)->membership & INSN_10000) != 0) \ |
| 590 |
|
|
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ |
| 591 |
|
|
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ |
| 592 |
|
|
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ |
| 593 |
|
|
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ |
| 594 |
|
|
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ |
| 595 |
|
|
|| 0) /* Please keep this term for easier source merging. */ |
| 596 |
|
|
|
| 597 |
|
|
/* This is a list of macro expanded instructions. |
| 598 |
|
|
|
| 599 |
|
|
_I appended means immediate |
| 600 |
|
|
_A appended means address |
| 601 |
|
|
_AB appended means address with base register |
| 602 |
|
|
_D appended means 64 bit floating point constant |
| 603 |
|
|
_S appended means 32 bit floating point constant. */ |
| 604 |
|
|
|
| 605 |
|
|
enum |
| 606 |
|
|
{ |
| 607 |
|
|
M_ABS, |
| 608 |
|
|
M_ADD_I, |
| 609 |
|
|
M_ADDU_I, |
| 610 |
|
|
M_AND_I, |
| 611 |
|
|
M_BEQ, |
| 612 |
|
|
M_BEQ_I, |
| 613 |
|
|
M_BEQL_I, |
| 614 |
|
|
M_BGE, |
| 615 |
|
|
M_BGEL, |
| 616 |
|
|
M_BGE_I, |
| 617 |
|
|
M_BGEL_I, |
| 618 |
|
|
M_BGEU, |
| 619 |
|
|
M_BGEUL, |
| 620 |
|
|
M_BGEU_I, |
| 621 |
|
|
M_BGEUL_I, |
| 622 |
|
|
M_BGT, |
| 623 |
|
|
M_BGTL, |
| 624 |
|
|
M_BGT_I, |
| 625 |
|
|
M_BGTL_I, |
| 626 |
|
|
M_BGTU, |
| 627 |
|
|
M_BGTUL, |
| 628 |
|
|
M_BGTU_I, |
| 629 |
|
|
M_BGTUL_I, |
| 630 |
|
|
M_BLE, |
| 631 |
|
|
M_BLEL, |
| 632 |
|
|
M_BLE_I, |
| 633 |
|
|
M_BLEL_I, |
| 634 |
|
|
M_BLEU, |
| 635 |
|
|
M_BLEUL, |
| 636 |
|
|
M_BLEU_I, |
| 637 |
|
|
M_BLEUL_I, |
| 638 |
|
|
M_BLT, |
| 639 |
|
|
M_BLTL, |
| 640 |
|
|
M_BLT_I, |
| 641 |
|
|
M_BLTL_I, |
| 642 |
|
|
M_BLTU, |
| 643 |
|
|
M_BLTUL, |
| 644 |
|
|
M_BLTU_I, |
| 645 |
|
|
M_BLTUL_I, |
| 646 |
|
|
M_BNE, |
| 647 |
|
|
M_BNE_I, |
| 648 |
|
|
M_BNEL_I, |
| 649 |
|
|
M_CACHE_AB, |
| 650 |
|
|
M_DABS, |
| 651 |
|
|
M_DADD_I, |
| 652 |
|
|
M_DADDU_I, |
| 653 |
|
|
M_DDIV_3, |
| 654 |
|
|
M_DDIV_3I, |
| 655 |
|
|
M_DDIVU_3, |
| 656 |
|
|
M_DDIVU_3I, |
| 657 |
|
|
M_DEXT, |
| 658 |
|
|
M_DINS, |
| 659 |
|
|
M_DIV_3, |
| 660 |
|
|
M_DIV_3I, |
| 661 |
|
|
M_DIVU_3, |
| 662 |
|
|
M_DIVU_3I, |
| 663 |
|
|
M_DLA_AB, |
| 664 |
|
|
M_DLCA_AB, |
| 665 |
|
|
M_DLI, |
| 666 |
|
|
M_DMUL, |
| 667 |
|
|
M_DMUL_I, |
| 668 |
|
|
M_DMULO, |
| 669 |
|
|
M_DMULO_I, |
| 670 |
|
|
M_DMULOU, |
| 671 |
|
|
M_DMULOU_I, |
| 672 |
|
|
M_DREM_3, |
| 673 |
|
|
M_DREM_3I, |
| 674 |
|
|
M_DREMU_3, |
| 675 |
|
|
M_DREMU_3I, |
| 676 |
|
|
M_DSUB_I, |
| 677 |
|
|
M_DSUBU_I, |
| 678 |
|
|
M_DSUBU_I_2, |
| 679 |
|
|
M_J_A, |
| 680 |
|
|
M_JAL_1, |
| 681 |
|
|
M_JAL_2, |
| 682 |
|
|
M_JAL_A, |
| 683 |
|
|
M_L_DOB, |
| 684 |
|
|
M_L_DAB, |
| 685 |
|
|
M_LA_AB, |
| 686 |
|
|
M_LB_A, |
| 687 |
|
|
M_LB_AB, |
| 688 |
|
|
M_LBU_A, |
| 689 |
|
|
M_LBU_AB, |
| 690 |
|
|
M_LCA_AB, |
| 691 |
|
|
M_LD_A, |
| 692 |
|
|
M_LD_OB, |
| 693 |
|
|
M_LD_AB, |
| 694 |
|
|
M_LDC1_AB, |
| 695 |
|
|
M_LDC2_AB, |
| 696 |
|
|
M_LDC3_AB, |
| 697 |
|
|
M_LDL_AB, |
| 698 |
|
|
M_LDR_AB, |
| 699 |
|
|
M_LH_A, |
| 700 |
|
|
M_LH_AB, |
| 701 |
|
|
M_LHU_A, |
| 702 |
|
|
M_LHU_AB, |
| 703 |
|
|
M_LI, |
| 704 |
|
|
M_LI_D, |
| 705 |
|
|
M_LI_DD, |
| 706 |
|
|
M_LI_S, |
| 707 |
|
|
M_LI_SS, |
| 708 |
|
|
M_LL_AB, |
| 709 |
|
|
M_LLD_AB, |
| 710 |
|
|
M_LS_A, |
| 711 |
|
|
M_LW_A, |
| 712 |
|
|
M_LW_AB, |
| 713 |
|
|
M_LWC0_A, |
| 714 |
|
|
M_LWC0_AB, |
| 715 |
|
|
M_LWC1_A, |
| 716 |
|
|
M_LWC1_AB, |
| 717 |
|
|
M_LWC2_A, |
| 718 |
|
|
M_LWC2_AB, |
| 719 |
|
|
M_LWC3_A, |
| 720 |
|
|
M_LWC3_AB, |
| 721 |
|
|
M_LWL_A, |
| 722 |
|
|
M_LWL_AB, |
| 723 |
|
|
M_LWR_A, |
| 724 |
|
|
M_LWR_AB, |
| 725 |
|
|
M_LWU_AB, |
| 726 |
|
|
M_MOVE, |
| 727 |
|
|
M_MUL, |
| 728 |
|
|
M_MUL_I, |
| 729 |
|
|
M_MULO, |
| 730 |
|
|
M_MULO_I, |
| 731 |
|
|
M_MULOU, |
| 732 |
|
|
M_MULOU_I, |
| 733 |
|
|
M_NOR_I, |
| 734 |
|
|
M_OR_I, |
| 735 |
|
|
M_REM_3, |
| 736 |
|
|
M_REM_3I, |
| 737 |
|
|
M_REMU_3, |
| 738 |
|
|
M_REMU_3I, |
| 739 |
|
|
M_DROL, |
| 740 |
|
|
M_ROL, |
| 741 |
|
|
M_DROL_I, |
| 742 |
|
|
M_ROL_I, |
| 743 |
|
|
M_DROR, |
| 744 |
|
|
M_ROR, |
| 745 |
|
|
M_DROR_I, |
| 746 |
|
|
M_ROR_I, |
| 747 |
|
|
M_S_DA, |
| 748 |
|
|
M_S_DOB, |
| 749 |
|
|
M_S_DAB, |
| 750 |
|
|
M_S_S, |
| 751 |
|
|
M_SC_AB, |
| 752 |
|
|
M_SCD_AB, |
| 753 |
|
|
M_SD_A, |
| 754 |
|
|
M_SD_OB, |
| 755 |
|
|
M_SD_AB, |
| 756 |
|
|
M_SDC1_AB, |
| 757 |
|
|
M_SDC2_AB, |
| 758 |
|
|
M_SDC3_AB, |
| 759 |
|
|
M_SDL_AB, |
| 760 |
|
|
M_SDR_AB, |
| 761 |
|
|
M_SEQ, |
| 762 |
|
|
M_SEQ_I, |
| 763 |
|
|
M_SGE, |
| 764 |
|
|
M_SGE_I, |
| 765 |
|
|
M_SGEU, |
| 766 |
|
|
M_SGEU_I, |
| 767 |
|
|
M_SGT, |
| 768 |
|
|
M_SGT_I, |
| 769 |
|
|
M_SGTU, |
| 770 |
|
|
M_SGTU_I, |
| 771 |
|
|
M_SLE, |
| 772 |
|
|
M_SLE_I, |
| 773 |
|
|
M_SLEU, |
| 774 |
|
|
M_SLEU_I, |
| 775 |
|
|
M_SLT_I, |
| 776 |
|
|
M_SLTU_I, |
| 777 |
|
|
M_SNE, |
| 778 |
|
|
M_SNE_I, |
| 779 |
|
|
M_SB_A, |
| 780 |
|
|
M_SB_AB, |
| 781 |
|
|
M_SH_A, |
| 782 |
|
|
M_SH_AB, |
| 783 |
|
|
M_SW_A, |
| 784 |
|
|
M_SW_AB, |
| 785 |
|
|
M_SWC0_A, |
| 786 |
|
|
M_SWC0_AB, |
| 787 |
|
|
M_SWC1_A, |
| 788 |
|
|
M_SWC1_AB, |
| 789 |
|
|
M_SWC2_A, |
| 790 |
|
|
M_SWC2_AB, |
| 791 |
|
|
M_SWC3_A, |
| 792 |
|
|
M_SWC3_AB, |
| 793 |
|
|
M_SWL_A, |
| 794 |
|
|
M_SWL_AB, |
| 795 |
|
|
M_SWR_A, |
| 796 |
|
|
M_SWR_AB, |
| 797 |
|
|
M_SUB_I, |
| 798 |
|
|
M_SUBU_I, |
| 799 |
|
|
M_SUBU_I_2, |
| 800 |
|
|
M_TEQ_I, |
| 801 |
|
|
M_TGE_I, |
| 802 |
|
|
M_TGEU_I, |
| 803 |
|
|
M_TLT_I, |
| 804 |
|
|
M_TLTU_I, |
| 805 |
|
|
M_TNE_I, |
| 806 |
|
|
M_TRUNCWD, |
| 807 |
|
|
M_TRUNCWS, |
| 808 |
|
|
M_ULD, |
| 809 |
|
|
M_ULD_A, |
| 810 |
|
|
M_ULH, |
| 811 |
|
|
M_ULH_A, |
| 812 |
|
|
M_ULHU, |
| 813 |
|
|
M_ULHU_A, |
| 814 |
|
|
M_ULW, |
| 815 |
|
|
M_ULW_A, |
| 816 |
|
|
M_USH, |
| 817 |
|
|
M_USH_A, |
| 818 |
|
|
M_USW, |
| 819 |
|
|
M_USW_A, |
| 820 |
|
|
M_USD, |
| 821 |
|
|
M_USD_A, |
| 822 |
|
|
M_XOR_I, |
| 823 |
|
|
M_COP0, |
| 824 |
|
|
M_COP1, |
| 825 |
|
|
M_COP2, |
| 826 |
|
|
M_COP3, |
| 827 |
|
|
M_NUM_MACROS |
| 828 |
|
|
}; |
| 829 |
|
|
|
| 830 |
|
|
|
| 831 |
|
|
/* The order of overloaded instructions matters. Label arguments and |
| 832 |
|
|
register arguments look the same. Instructions that can have either |
| 833 |
|
|
for arguments must apear in the correct order in this table for the |
| 834 |
|
|
assembler to pick the right one. In other words, entries with |
| 835 |
|
|
immediate operands must apear after the same instruction with |
| 836 |
|
|
registers. |
| 837 |
|
|
|
| 838 |
|
|
Many instructions are short hand for other instructions (i.e., The |
| 839 |
|
|
jal <register> instruction is short for jalr <register>). */ |
| 840 |
|
|
|
| 841 |
|
|
extern const struct mips_opcode mips_builtin_opcodes[]; |
| 842 |
|
|
extern const int bfd_mips_num_builtin_opcodes; |
| 843 |
|
|
extern struct mips_opcode *mips_opcodes; |
| 844 |
|
|
extern int bfd_mips_num_opcodes; |
| 845 |
|
|
#define NUMOPCODES bfd_mips_num_opcodes |
| 846 |
|
|
|
| 847 |
|
|
|
| 848 |
|
|
/* The rest of this file adds definitions for the mips16 TinyRISC |
| 849 |
|
|
processor. */ |
| 850 |
|
|
|
| 851 |
|
|
/* These are the bitmasks and shift counts used for the different |
| 852 |
|
|
fields in the instruction formats. Other than OP, no masks are |
| 853 |
|
|
provided for the fixed portions of an instruction, since they are |
| 854 |
|
|
not needed. |
| 855 |
|
|
|
| 856 |
|
|
The I format uses IMM11. |
| 857 |
|
|
|
| 858 |
|
|
The RI format uses RX and IMM8. |
| 859 |
|
|
|
| 860 |
|
|
The RR format uses RX, and RY. |
| 861 |
|
|
|
| 862 |
|
|
The RRI format uses RX, RY, and IMM5. |
| 863 |
|
|
|
| 864 |
|
|
The RRR format uses RX, RY, and RZ. |
| 865 |
|
|
|
| 866 |
|
|
The RRI_A format uses RX, RY, and IMM4. |
| 867 |
|
|
|
| 868 |
|
|
The SHIFT format uses RX, RY, and SHAMT. |
| 869 |
|
|
|
| 870 |
|
|
The I8 format uses IMM8. |
| 871 |
|
|
|
| 872 |
|
|
The I8_MOVR32 format uses RY and REGR32. |
| 873 |
|
|
|
| 874 |
|
|
The IR_MOV32R format uses REG32R and MOV32Z. |
| 875 |
|
|
|
| 876 |
|
|
The I64 format uses IMM8. |
| 877 |
|
|
|
| 878 |
|
|
The RI64 format uses RY and IMM5. |
| 879 |
|
|
*/ |
| 880 |
|
|
|
| 881 |
|
|
#define MIPS16OP_MASK_OP 0x1f |
| 882 |
|
|
#define MIPS16OP_SH_OP 11 |
| 883 |
|
|
#define MIPS16OP_MASK_IMM11 0x7ff |
| 884 |
|
|
#define MIPS16OP_SH_IMM11 0 |
| 885 |
|
|
#define MIPS16OP_MASK_RX 0x7 |
| 886 |
|
|
#define MIPS16OP_SH_RX 8 |
| 887 |
|
|
#define MIPS16OP_MASK_IMM8 0xff |
| 888 |
|
|
#define MIPS16OP_SH_IMM8 0 |
| 889 |
|
|
#define MIPS16OP_MASK_RY 0x7 |
| 890 |
|
|
#define MIPS16OP_SH_RY 5 |
| 891 |
|
|
#define MIPS16OP_MASK_IMM5 0x1f |
| 892 |
|
|
#define MIPS16OP_SH_IMM5 0 |
| 893 |
|
|
#define MIPS16OP_MASK_RZ 0x7 |
| 894 |
|
|
#define MIPS16OP_SH_RZ 2 |
| 895 |
|
|
#define MIPS16OP_MASK_IMM4 0xf |
| 896 |
|
|
#define MIPS16OP_SH_IMM4 0 |
| 897 |
|
|
#define MIPS16OP_MASK_REGR32 0x1f |
| 898 |
|
|
#define MIPS16OP_SH_REGR32 0 |
| 899 |
|
|
#define MIPS16OP_MASK_REG32R 0x1f |
| 900 |
|
|
#define MIPS16OP_SH_REG32R 3 |
| 901 |
|
|
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) |
| 902 |
|
|
#define MIPS16OP_MASK_MOVE32Z 0x7 |
| 903 |
|
|
#define MIPS16OP_SH_MOVE32Z 0 |
| 904 |
|
|
#define MIPS16OP_MASK_IMM6 0x3f |
| 905 |
|
|
#define MIPS16OP_SH_IMM6 5 |
| 906 |
|
|
|
| 907 |
|
|
/* These are the characters which may appears in the args field of an |
| 908 |
|
|
instruction. They appear in the order in which the fields appear |
| 909 |
|
|
when the instruction is used. Commas and parentheses in the args |
| 910 |
|
|
string are ignored when assembling, and written into the output |
| 911 |
|
|
when disassembling. |
| 912 |
|
|
|
| 913 |
|
|
"y" 3 bit register (MIPS16OP_*_RY) |
| 914 |
|
|
"x" 3 bit register (MIPS16OP_*_RX) |
| 915 |
|
|
"z" 3 bit register (MIPS16OP_*_RZ) |
| 916 |
|
|
"Z" 3 bit register (MIPS16OP_*_MOVE32Z) |
| 917 |
|
|
"v" 3 bit same register as source and destination (MIPS16OP_*_RX) |
| 918 |
|
|
"w" 3 bit same register as source and destination (MIPS16OP_*_RY) |
| 919 |
|
|
"0" zero register ($0) |
| 920 |
|
|
"S" stack pointer ($sp or $29) |
| 921 |
|
|
"P" program counter |
| 922 |
|
|
"R" return address register ($ra or $31) |
| 923 |
|
|
"X" 5 bit MIPS register (MIPS16OP_*_REGR32) |
| 924 |
|
|
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R) |
| 925 |
|
|
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6) |
| 926 |
|
|
"a" 26 bit jump address |
| 927 |
|
|
"e" 11 bit extension value |
| 928 |
|
|
"l" register list for entry instruction |
| 929 |
|
|
"L" register list for exit instruction |
| 930 |
|
|
|
| 931 |
|
|
The remaining codes may be extended. Except as otherwise noted, |
| 932 |
|
|
the full extended operand is a 16 bit signed value. |
| 933 |
|
|
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) |
| 934 |
|
|
">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) |
| 935 |
|
|
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) |
| 936 |
|
|
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) |
| 937 |
|
|
"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) |
| 938 |
|
|
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) |
| 939 |
|
|
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) |
| 940 |
|
|
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) |
| 941 |
|
|
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) |
| 942 |
|
|
"j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) |
| 943 |
|
|
"8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) |
| 944 |
|
|
"V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) |
| 945 |
|
|
"C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) |
| 946 |
|
|
"U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) |
| 947 |
|
|
"k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) |
| 948 |
|
|
"K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) |
| 949 |
|
|
"p" 8 bit conditional branch address (MIPS16OP_*_IMM8) |
| 950 |
|
|
"q" 11 bit branch address (MIPS16OP_*_IMM11) |
| 951 |
|
|
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) |
| 952 |
|
|
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) |
| 953 |
|
|
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) |
| 954 |
|
|
"m" 7 bit register list for save instruction (18 bit extended) |
| 955 |
|
|
"M" 7 bit register list for restore instruction (18 bit extended) |
| 956 |
|
|
*/ |
| 957 |
|
|
|
| 958 |
|
|
/* Save/restore encoding for the args field when all 4 registers are |
| 959 |
|
|
either saved as arguments or saved/restored as statics. */ |
| 960 |
|
|
#define MIPS16_ALL_ARGS 0xe |
| 961 |
|
|
#define MIPS16_ALL_STATICS 0xb |
| 962 |
|
|
|
| 963 |
|
|
/* For the mips16, we use the same opcode table format and a few of |
| 964 |
|
|
the same flags. However, most of the flags are different. */ |
| 965 |
|
|
|
| 966 |
|
|
/* Modifies the register in MIPS16OP_*_RX. */ |
| 967 |
|
|
#define MIPS16_INSN_WRITE_X 0x00000001 |
| 968 |
|
|
/* Modifies the register in MIPS16OP_*_RY. */ |
| 969 |
|
|
#define MIPS16_INSN_WRITE_Y 0x00000002 |
| 970 |
|
|
/* Modifies the register in MIPS16OP_*_RZ. */ |
| 971 |
|
|
#define MIPS16_INSN_WRITE_Z 0x00000004 |
| 972 |
|
|
/* Modifies the T ($24) register. */ |
| 973 |
|
|
#define MIPS16_INSN_WRITE_T 0x00000008 |
| 974 |
|
|
/* Modifies the SP ($29) register. */ |
| 975 |
|
|
#define MIPS16_INSN_WRITE_SP 0x00000010 |
| 976 |
|
|
/* Modifies the RA ($31) register. */ |
| 977 |
|
|
#define MIPS16_INSN_WRITE_31 0x00000020 |
| 978 |
|
|
/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ |
| 979 |
|
|
#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 |
| 980 |
|
|
/* Reads the register in MIPS16OP_*_RX. */ |
| 981 |
|
|
#define MIPS16_INSN_READ_X 0x00000080 |
| 982 |
|
|
/* Reads the register in MIPS16OP_*_RY. */ |
| 983 |
|
|
#define MIPS16_INSN_READ_Y 0x00000100 |
| 984 |
|
|
/* Reads the register in MIPS16OP_*_MOVE32Z. */ |
| 985 |
|
|
#define MIPS16_INSN_READ_Z 0x00000200 |
| 986 |
|
|
/* Reads the T ($24) register. */ |
| 987 |
|
|
#define MIPS16_INSN_READ_T 0x00000400 |
| 988 |
|
|
/* Reads the SP ($29) register. */ |
| 989 |
|
|
#define MIPS16_INSN_READ_SP 0x00000800 |
| 990 |
|
|
/* Reads the RA ($31) register. */ |
| 991 |
|
|
#define MIPS16_INSN_READ_31 0x00001000 |
| 992 |
|
|
/* Reads the program counter. */ |
| 993 |
|
|
#define MIPS16_INSN_READ_PC 0x00002000 |
| 994 |
|
|
/* Reads the general purpose register in MIPS16OP_*_REGR32. */ |
| 995 |
|
|
#define MIPS16_INSN_READ_GPR_X 0x00004000 |
| 996 |
|
|
/* Is a branch insn. */ |
| 997 |
|
|
#define MIPS16_INSN_BRANCH 0x00010000 |
| 998 |
|
|
|
| 999 |
|
|
/* The following flags have the same value for the mips16 opcode |
| 1000 |
|
|
table: |
| 1001 |
|
|
INSN_UNCOND_BRANCH_DELAY |
| 1002 |
|
|
INSN_COND_BRANCH_DELAY |
| 1003 |
|
|
INSN_COND_BRANCH_LIKELY (never used) |
| 1004 |
|
|
INSN_READ_HI |
| 1005 |
|
|
INSN_READ_LO |
| 1006 |
|
|
INSN_WRITE_HI |
| 1007 |
|
|
INSN_WRITE_LO |
| 1008 |
|
|
INSN_TRAP |
| 1009 |
|
|
INSN_ISA3 |
| 1010 |
|
|
*/ |
| 1011 |
|
|
|
| 1012 |
|
|
extern const struct mips_opcode mips16_opcodes[]; |
| 1013 |
|
|
extern const int bfd_mips16_num_opcodes; |
| 1014 |
|
|
|
| 1015 |
|
|
#endif /* _MIPS_H_ */ |
