72 |
|
#define POWERPC_ROM 1 |
73 |
|
|
74 |
|
#if EMULATED_PPC |
75 |
– |
// Handle interrupts asynchronously? |
76 |
– |
#define ASYNC_IRQ 0 |
75 |
|
// Mac ROM is write protected when banked memory is used |
76 |
|
#if REAL_ADDRESSING || DIRECT_ADDRESSING |
77 |
|
# define ROM_IS_WRITE_PROTECTED 0 |
80 |
|
# define ROM_IS_WRITE_PROTECTED 1 |
81 |
|
#endif |
82 |
|
// Configure PowerPC emulator |
83 |
< |
#define PPC_CHECK_INTERRUPTS (ASYNC_IRQ ? 0 : 1) |
83 |
> |
#define PPC_REENTRANT_JIT 1 |
84 |
> |
#define PPC_CHECK_INTERRUPTS 1 |
85 |
|
#define PPC_DECODE_CACHE 1 |
86 |
|
#define PPC_FLIGHT_RECORDER 1 |
87 |
|
#define PPC_PROFILE_COMPILE_TIME 0 |
88 |
|
#define PPC_PROFILE_GENERIC_CALLS 0 |
89 |
|
#define KPX_MAX_CPUS 1 |
90 |
+ |
#if defined(__i386__) |
91 |
+ |
#define DYNGEN_ASM_OPTS 1 |
92 |
+ |
#endif |
93 |
|
#else |
94 |
|
// Mac ROM is write protected |
95 |
|
#define ROM_IS_WRITE_PROTECTED 1 |
249 |
|
} |
250 |
|
#endif |
251 |
|
|
252 |
< |
#ifdef __i386__ |
252 |
> |
#if defined(__i386__) || defined(__x86_64__) |
253 |
|
#define HAVE_TEST_AND_SET 1 |
254 |
|
static inline int testandset(volatile int *p) |
255 |
|
{ |
256 |
< |
int ret; |
255 |
< |
long int readval; |
256 |
> |
long int ret; |
257 |
|
/* Note: the "xchg" instruction does not need a "lock" prefix */ |
258 |
< |
__asm__ __volatile__("xchgl %0, %1" |
259 |
< |
: "=r" (ret), "=m" (*p), "=a" (readval) |
258 |
> |
__asm__ __volatile__("xchgl %k0, %1" |
259 |
> |
: "=r" (ret), "=m" (*p) |
260 |
|
: "0" (1), "m" (*p) |
261 |
|
: "memory"); |
262 |
|
return ret; |
361 |
|
extern uint64 GetTicks_usec(void); |
362 |
|
extern void Delay_usec(uint32 usec); |
363 |
|
|
364 |
< |
#ifdef HAVE_PTHREADS |
364 |
> |
#if defined(HAVE_PTHREADS) || (defined(__linux__) && defined(__powerpc__)) |
365 |
|
// Setup pthread attributes |
366 |
|
extern void Set_pthread_attr(pthread_attr_t *attr, int priority); |
367 |
|
#endif |