130 |
|
{ i_FBcc, "FBcc" }, |
131 |
|
{ i_FSAVE, "FSAVE" }, |
132 |
|
{ i_FRESTORE, "FRESTORE" }, |
133 |
+ |
|
134 |
+ |
{ i_CINVL, "CINVL" }, |
135 |
+ |
{ i_CINVP, "CINVP" }, |
136 |
+ |
{ i_CINVA, "CINVA" }, |
137 |
+ |
{ i_CPUSHL, "CPUSHL" }, |
138 |
+ |
{ i_CPUSHP, "CPUSHP" }, |
139 |
+ |
{ i_CPUSHA, "CPUSHA" }, |
140 |
+ |
{ i_MOVE16, "MOVE16" }, |
141 |
+ |
|
142 |
|
{ i_MMUOP, "MMUOP" }, |
143 |
|
{ i_ILLG, "" }, |
144 |
|
}; |
339 |
|
case 'A': |
340 |
|
srcmode = Areg; |
341 |
|
switch (opcstr[pos++]) { |
342 |
+ |
case 'l': srcmode = absl; break; |
343 |
|
case 'r': srcreg = bitval[bitr]; srcgather = 1; srcpos = bitpos[bitr]; break; |
344 |
|
case 'R': srcreg = bitval[bitR]; srcgather = 1; srcpos = bitpos[bitR]; break; |
345 |
|
default: abort(); |
394 |
|
srcpos = bitpos[bitK]; |
395 |
|
} |
396 |
|
break; |
397 |
+ |
case 'p': srcmode = immi; srcreg = bitval[bitp]; |
398 |
+ |
if (CPU_EMU_SIZE < 5) { // gb-- what is CPU_EMU_SIZE used for ?? |
399 |
+ |
/* 0..3 */ |
400 |
+ |
srcgather = 1; |
401 |
+ |
srctype = 7; |
402 |
+ |
srcpos = bitpos[bitp]; |
403 |
+ |
} |
404 |
+ |
break; |
405 |
|
default: abort(); |
406 |
|
} |
407 |
|
break; |
530 |
|
case 'A': |
531 |
|
destmode = Areg; |
532 |
|
switch (opcstr[pos++]) { |
533 |
+ |
case 'l': destmode = absl; break; |
534 |
|
case 'r': destreg = bitval[bitr]; dstgather = 1; dstpos = bitpos[bitr]; break; |
535 |
|
case 'R': destreg = bitval[bitR]; dstgather = 1; dstpos = bitpos[bitR]; break; |
536 |
|
default: abort(); |
757 |
|
smsk = 7; sbitdst = 8; break; |
758 |
|
case 5: |
759 |
|
smsk = 63; sbitdst = 64; break; |
760 |
+ |
case 7: |
761 |
+ |
smsk = 3; sbitdst = 4; break; |
762 |
|
default: |
763 |
|
smsk = 0; sbitdst = 0; |
764 |
|
abort(); |