22 |
|
#include "memory.h" |
23 |
|
#include "readcpu.h" |
24 |
|
#include "newcpu.h" |
25 |
< |
#include "compiler.h" |
25 |
> |
|
26 |
> |
#if ENABLE_MON |
27 |
> |
#include "mon.h" |
28 |
> |
#include "mon_disass.h" |
29 |
> |
#endif |
30 |
|
|
31 |
|
int quit_program = 0; |
32 |
|
int debugging = 0; |
52 |
|
|
53 |
|
cpuop_func *cpufunctbl[65536]; |
54 |
|
|
55 |
+ |
#define FLIGHT_RECORDER 0 |
56 |
+ |
|
57 |
+ |
#if FLIGHT_RECORDER |
58 |
+ |
struct rec_step { |
59 |
+ |
uae_u32 d[8]; |
60 |
+ |
uae_u32 a[8]; |
61 |
+ |
uae_u32 pc; |
62 |
+ |
}; |
63 |
+ |
|
64 |
+ |
const int LOG_SIZE = 8192; |
65 |
+ |
static rec_step log[LOG_SIZE]; |
66 |
+ |
static int log_ptr = -1; // First time initialization |
67 |
+ |
|
68 |
+ |
static const char *log_filename(void) |
69 |
+ |
{ |
70 |
+ |
const char *name = getenv("M68K_LOG_FILE"); |
71 |
+ |
return name ? name : "log.68k"; |
72 |
+ |
} |
73 |
+ |
|
74 |
+ |
static void record_step(uaecptr pc) |
75 |
+ |
{ |
76 |
+ |
for (int i = 0; i < 8; i++) { |
77 |
+ |
log[log_ptr].d[i] = m68k_dreg(regs, i); |
78 |
+ |
log[log_ptr].a[i] = m68k_areg(regs, i); |
79 |
+ |
} |
80 |
+ |
log[log_ptr].pc = pc; |
81 |
+ |
log_ptr = (log_ptr + 1) % LOG_SIZE; |
82 |
+ |
} |
83 |
+ |
|
84 |
+ |
static void dump_log(void) |
85 |
+ |
{ |
86 |
+ |
FILE *f = fopen(log_filename(), "w"); |
87 |
+ |
if (f == NULL) |
88 |
+ |
return; |
89 |
+ |
for (int i = 0; i < LOG_SIZE; i++) { |
90 |
+ |
int j = (i + log_ptr) % LOG_SIZE; |
91 |
+ |
fprintf(f, "pc %08x\n", log[j].pc); |
92 |
+ |
fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]); |
93 |
+ |
fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]); |
94 |
+ |
fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]); |
95 |
+ |
fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]); |
96 |
+ |
#if ENABLE_MON |
97 |
+ |
disass_68k(f, log[j].pc); |
98 |
+ |
#endif |
99 |
+ |
} |
100 |
+ |
} |
101 |
+ |
#endif |
102 |
+ |
|
103 |
|
#define COUNT_INSTRS 0 |
104 |
|
|
105 |
|
#if COUNT_INSTRS |
259 |
|
do_merges (); |
260 |
|
|
261 |
|
build_cpufunctbl (); |
262 |
+ |
|
263 |
+ |
fpu_init (); |
264 |
+ |
fpu_set_integral_fpu (CPUType == 4); |
265 |
+ |
} |
266 |
+ |
|
267 |
+ |
void exit_m68k (void) |
268 |
+ |
{ |
269 |
+ |
fpu_exit (); |
270 |
|
} |
271 |
|
|
272 |
|
struct regstruct regs, lastint_regs; |
275 |
|
static long int m68kpc_offset; |
276 |
|
int lastint_no; |
277 |
|
|
278 |
+ |
#if REAL_ADDRESSING || DIRECT_ADDRESSING |
279 |
+ |
#define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1) |
280 |
+ |
#define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o)) |
281 |
+ |
#define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o)) |
282 |
+ |
#else |
283 |
|
#define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1) |
284 |
|
#define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) |
285 |
|
#define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o)) |
286 |
+ |
#endif |
287 |
|
|
288 |
|
uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf) |
289 |
|
{ |
711 |
|
|
712 |
|
void Exception(int nr, uaecptr oldpc) |
713 |
|
{ |
714 |
< |
compiler_flush_jsr_stack(); |
714 |
> |
uae_u32 currpc = m68k_getpc (); |
715 |
|
MakeSR(); |
716 |
|
if (!regs.s) { |
717 |
|
regs.usp = m68k_areg(regs, 7); |
740 |
|
m68k_areg(regs, 7) -= 2; |
741 |
|
put_word (m68k_areg(regs, 7), nr * 4); |
742 |
|
m68k_areg(regs, 7) -= 4; |
743 |
< |
put_long (m68k_areg(regs, 7), m68k_getpc ()); |
743 |
> |
put_long (m68k_areg(regs, 7), currpc); |
744 |
|
m68k_areg(regs, 7) -= 2; |
745 |
|
put_word (m68k_areg(regs, 7), regs.sr); |
746 |
|
regs.sr |= (1 << 13); |
766 |
|
} |
767 |
|
} |
768 |
|
m68k_areg(regs, 7) -= 4; |
769 |
< |
put_long (m68k_areg(regs, 7), m68k_getpc ()); |
769 |
> |
put_long (m68k_areg(regs, 7), currpc); |
770 |
|
kludge_me_do: |
771 |
|
m68k_areg(regs, 7) -= 2; |
772 |
|
put_word (m68k_areg(regs, 7), regs.sr); |
789 |
|
|
790 |
|
static int caar, cacr, tc, itt0, itt1, dtt0, dtt1; |
791 |
|
|
792 |
< |
void m68k_move2c (int regno, uae_u32 *regp) |
792 |
> |
int m68k_move2c (int regno, uae_u32 *regp) |
793 |
|
{ |
794 |
< |
if (CPUType == 1 && (regno & 0x7FF) > 1) |
794 |
> |
if ((CPUType == 1 && (regno & 0x7FF) > 1) |
795 |
> |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
796 |
> |
|| (CPUType == 4 && regno == 0x802)) |
797 |
> |
{ |
798 |
|
op_illg (0x4E7B); |
799 |
< |
else |
799 |
> |
return 0; |
800 |
> |
} else { |
801 |
|
switch (regno) { |
802 |
|
case 0: regs.sfc = *regp & 7; break; |
803 |
|
case 1: regs.dfc = *regp & 7; break; |
804 |
< |
case 2: cacr = *regp & 0x3; break; /* ignore C and CE */ |
804 |
> |
case 2: cacr = *regp & (CPUType < 4 ? 0x3 : 0x80008000); break; |
805 |
|
case 3: tc = *regp & 0xc000; break; |
806 |
|
case 4: itt0 = *regp & 0xffffe364; break; |
807 |
|
case 5: itt1 = *regp & 0xffffe364; break; |
814 |
|
case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break; |
815 |
|
default: |
816 |
|
op_illg (0x4E7B); |
817 |
< |
break; |
817 |
> |
return 0; |
818 |
|
} |
819 |
+ |
} |
820 |
+ |
return 1; |
821 |
|
} |
822 |
|
|
823 |
< |
void m68k_movec2 (int regno, uae_u32 *regp) |
823 |
> |
int m68k_movec2 (int regno, uae_u32 *regp) |
824 |
|
{ |
825 |
< |
if (CPUType == 1 && (regno & 0x7FF) > 1) |
825 |
> |
if ((CPUType == 1 && (regno & 0x7FF) > 1) |
826 |
> |
|| (CPUType < 4 && (regno & 0x7FF) > 2) |
827 |
> |
|| (CPUType == 4 && regno == 0x802)) |
828 |
> |
{ |
829 |
|
op_illg (0x4E7A); |
830 |
< |
else |
830 |
> |
return 0; |
831 |
> |
} else { |
832 |
|
switch (regno) { |
833 |
|
case 0: *regp = regs.sfc; break; |
834 |
|
case 1: *regp = regs.dfc; break; |
845 |
|
case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break; |
846 |
|
default: |
847 |
|
op_illg (0x4E7A); |
848 |
< |
break; |
848 |
> |
return 0; |
849 |
> |
} |
850 |
|
} |
851 |
+ |
return 1; |
852 |
|
} |
853 |
|
|
854 |
|
static __inline__ int |
1125 |
|
regs.spcflags = 0; |
1126 |
|
regs.intmask = 7; |
1127 |
|
regs.vbr = regs.sfc = regs.dfc = 0; |
1128 |
< |
regs.fpcr = regs.fpsr = regs.fpiar = 0; |
1128 |
> |
/* gb-- moved into {fpp,fpu_x86}.cpp::fpu_init() |
1129 |
> |
regs.fpcr = regs.fpsr = regs.fpiar = 0; */ |
1130 |
> |
fpu_reset(); |
1131 |
> |
|
1132 |
> |
#if FLIGHT_RECORDER |
1133 |
> |
#if ENABLE_MON |
1134 |
> |
if (log_ptr == -1) { |
1135 |
> |
// Install "log" command in mon |
1136 |
> |
mon_add_command("log", dump_log, "log Dump m68k emulation log\n"); |
1137 |
> |
} |
1138 |
> |
#endif |
1139 |
> |
log_ptr = 0; |
1140 |
> |
memset(log, 0, sizeof(log)); |
1141 |
> |
#endif |
1142 |
|
} |
1143 |
|
|
1144 |
|
void REGPARAM2 op_illg (uae_u32 opcode) |
1145 |
|
{ |
1146 |
|
uaecptr pc = m68k_getpc (); |
1147 |
|
|
1057 |
– |
compiler_flush_jsr_stack (); |
1058 |
– |
|
1148 |
|
if ((opcode & 0xFF00) == 0x7100) { |
1149 |
|
struct M68kRegisters r; |
1150 |
|
int i; |
1151 |
|
|
1152 |
< |
// Return from Execute68k()? |
1152 |
> |
// Return from Exectue68k()? |
1153 |
|
if (opcode == M68K_EXEC_RETURN) { |
1154 |
|
regs.spcflags |= SPCFLAG_BRK; |
1155 |
|
quit_program = 1; |
1208 |
|
|
1209 |
|
static void do_trace (void) |
1210 |
|
{ |
1211 |
< |
if (regs.t0) { |
1211 |
> |
if (regs.t0 && CPUType >= 2) { |
1212 |
|
uae_u16 opcode; |
1213 |
|
/* should also include TRAP, CHK, SR modification FPcc */ |
1214 |
|
/* probably never used so why bother */ |
1245 |
|
static int do_specialties (void) |
1246 |
|
{ |
1247 |
|
/*n_spcinsns++;*/ |
1159 |
– |
run_compiled_code(); |
1248 |
|
if (regs.spcflags & SPCFLAG_DOTRACE) { |
1249 |
|
Exception (9,last_trace_ad); |
1250 |
|
} |
1285 |
|
{ |
1286 |
|
for (;;) { |
1287 |
|
uae_u32 opcode = GET_OPCODE; |
1288 |
+ |
#if FLIGHT_RECORDER |
1289 |
+ |
record_step(m68k_getpc()); |
1290 |
+ |
#endif |
1291 |
|
(*cpufunctbl[opcode])(opcode); |
1292 |
|
if (regs.spcflags) { |
1293 |
|
if (do_specialties()) |