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root/cebix/BasiliskII/src/uae_cpu/newcpu.cpp

Comparing BasiliskII/src/uae_cpu/newcpu.cpp (file contents):
Revision 1.22 by gbeauche, 2006-01-15T22:42:51Z vs.
Revision 1.23 by gbeauche, 2007-06-15T08:10:48Z

#	Line 811 | Line 811 | static void Interrupt(int nr)
811
812		static int caar, cacr, tc, itt0, itt1, dtt0, dtt1, mmusr, urp, srp;
813
814	+	static int movec_illg (int regno)
815	+	{
816	+	switch (CPUType) {
817	+	case 1:
818	+	if ((regno & 0x7ff) <= 1)
819	+	return 0;
820	+	break;
821	+	case 2:
822	+	case 3:
823	+	if ((regno & 0x7ff) <= 2)
824	+	return 0;
825	+	if (regno == 3 || regno == 4)
826	+	return 0;
827	+	break;
828	+	case 4:
829	+	if ((regno & 0x7ff) <= 7) {
830	+	if (regno != 0x802)
831	+	return 0;
832	+	}
833	+	break;
834	+	}
835	+	return 1;
836	+	}
837	+
838		int m68k_move2c (int regno, uae_u32 *regp)
839		{
840	<	if ((CPUType == 1 && (regno & 0x7FF) > 1)
817	<	|| (CPUType < 4 && (regno & 0x7FF) > 2)
818	<	|| (CPUType == 4 && regno == 0x802))
819	<	{
840	>	if (movec_illg (regno)) {
841		op_illg (0x4E7B);
842		return 0;
843		} else {
#	Line 832 | Line 853 | int m68k_move2c (int regno, uae_u32 *reg
853		flush_icache(1);
854		}
855		else {
856	<	set_cache_state((cacr&0x8000) || 0);
836	<	// FIXME: The User Manual claims bit 3 of CACR is undefined
837	<	if (*regp & 0x08)
838	<	flush_icache(2);
856	>	set_cache_state(cacr&0x8000);
857		}
858		#endif
859		break;
#	Line 862 | Line 880 | int m68k_move2c (int regno, uae_u32 *reg
880
881		int m68k_movec2 (int regno, uae_u32 *regp)
882		{
883	<	if ((CPUType == 1 && (regno & 0x7FF) > 1)
866	<	|| (CPUType < 4 && (regno & 0x7FF) > 2)
867	<	|| (CPUType == 4 && regno == 0x802))
883	>	if (movec_illg (regno))
884		{
885		op_illg (0x4E7A);
886		return 0;

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