[ViewVC] Diff of: cebix/BasiliskII/src/uae

Comparing BasiliskII/src/uae_cpu/newcpu.cpp (file contents):
Revision 1.17 by gbeauche, 2002-10-01T09:39:55Z vs.
Revision 1.23 by gbeauche, 2007-06-15T08:10:48Z

#	Line 55 \| Line 55 \| *cpuop_func cpufunctbl[65536];**
55
56		#if FLIGHT_RECORDER
57		struct rec_step {
58	+	uae_u32 pc;
59	+	#if FLIGHT_RECORDER >= 2
60		uae_u32 d[8];
61		uae_u32 a[8];
62	<	uae_u32 pc;
62	>	#endif
63		};
64
65	<	const int LOG_SIZE = 8192;
65	>	const int LOG_SIZE = 32768;
66		static rec_step log[LOG_SIZE];
67		static int log_ptr = -1; // First time initialization
68
#	Line 72 \| Line 74 \| *static const char log_filename(void)**
74
75		void m68k_record_step(uaecptr pc)
76		{
77	<	for (int i = 0; i < 8; i++) {
78	<	log[log_ptr].d[i] = m68k_dreg(regs, i);
79	<	log[log_ptr].a[i] = m68k_areg(regs, i);
77	>	#if FLIGHT_RECORDER >= 2
78	>	/* XXX: if LSB is set, we are recording from generated code and we
79	>	don't support registers recording yet. */
80	>	if ((pc & 1) == 0) {
81	>	for (int i = 0; i < 8; i++) {
82	>	log[log_ptr].d[i] = m68k_dreg(regs, i);
83	>	log[log_ptr].a[i] = m68k_areg(regs, i);
84	>	}
85		}
86	+	#endif
87		log[log_ptr].pc = pc;
88		log_ptr = (log_ptr + 1) % LOG_SIZE;
89		}
#	Line 87 \| Line 95 \| static void dump_log(void)
95		return;
96		for (int i = 0; i < LOG_SIZE; i++) {
97		int j = (i + log_ptr) % LOG_SIZE;
98	<	fprintf(f, "pc %08x\n", log[j].pc);
99	<	fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]);
100	<	fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]);
101	<	fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]);
102	<	fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]);
98	>	uae_u32 pc = log[j].pc & ~1;
99	>	fprintf(f, "pc %08x", pc);
100	>	#if FLIGHT_RECORDER >= 2
101	>	fprintf(f, "\n");
102	>	if ((log[j].pc & 1) == 0) {
103	>	fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]);
104	>	fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]);
105	>	fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]);
106	>	fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]);
107	>	}
108	>	#else
109	>	fprintf(f, " \| ");
110	>	#endif
111		#if ENABLE_MON
112	<	disass_68k(f, log[j].pc);
112	>	disass_68k(f, pc);
113		#endif
114		}
115		fclose(f);
116		}
117		#endif
118
119	+	#if ENABLE_MON
120	+	static void dump_regs(void)
121	+	{
122	+	m68k_dumpstate(NULL);
123	+	}
124	+	#endif
125	+
126		#define COUNT_INSTRS 0
127
128		#if COUNT_INSTRS
#	Line 163 \| Line 186 \| static __inline__ unsigned int cft_map (
186		#endif
187		}
188
189	<	cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
189	>	void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
190
191	<	cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode)
191	>	void REGPARAM2 op_illg_1 (uae_u32 opcode)
192		{
193	<	cpuop_return( op_illg (cft_map (opcode)) );
193	>	op_illg (cft_map (opcode));
194		}
195
196		static void build_cpufunctbl (void)
#	Line 788 \| Line 811 \| static void Interrupt(int nr)
811
812		static int caar, cacr, tc, itt0, itt1, dtt0, dtt1, mmusr, urp, srp;
813
814	+	static int movec_illg (int regno)
815	+	{
816	+	switch (CPUType) {
817	+	case 1:
818	+	if ((regno & 0x7ff) <= 1)
819	+	return 0;
820	+	break;
821	+	case 2:
822	+	case 3:
823	+	if ((regno & 0x7ff) <= 2)
824	+	return 0;
825	+	if (regno == 3 \|\| regno == 4)
826	+	return 0;
827	+	break;
828	+	case 4:
829	+	if ((regno & 0x7ff) <= 7) {
830	+	if (regno != 0x802)
831	+	return 0;
832	+	}
833	+	break;
834	+	}
835	+	return 1;
836	+	}
837	+
838		int m68k_move2c (int regno, uae_u32 *regp)
839		{
840	<	if ((CPUType == 1 && (regno & 0x7FF) > 1)
794	<	\|\| (CPUType < 4 && (regno & 0x7FF) > 2)
795	<	\|\| (CPUType == 4 && regno == 0x802))
796	<	{
840	>	if (movec_illg (regno)) {
841		op_illg (0x4E7B);
842		return 0;
843		} else {
#	Line 809 \| Line 853 \| *int m68k_move2c (int regno, uae_u32 reg**
853		flush_icache(1);
854		}
855		else {
856	<	set_cache_state((cacr&0x8000) \|\| 0);
813	<	// FIXME: The User Manual claims bit 3 of CACR is undefined
814	<	if (*regp & 0x08)
815	<	flush_icache(2);
856	>	set_cache_state(cacr&0x8000);
857		}
858		#endif
859		break;
#	Line 839 \| Line 880 \| *int m68k_move2c (int regno, uae_u32 reg**
880
881		int m68k_movec2 (int regno, uae_u32 *regp)
882		{
883	<	if ((CPUType == 1 && (regno & 0x7FF) > 1)
843	<	\|\| (CPUType < 4 && (regno & 0x7FF) > 2)
844	<	\|\| (CPUType == 4 && regno == 0x802))
883	>	if (movec_illg (regno))
884		{
885		op_illg (0x4E7A);
886		return 0;
#	Line 1152 \| Line 1191 \| void m68k_reset (void)
1191		fpu_reset();
1192
1193		#if FLIGHT_RECORDER
1194	+	log_ptr = 0;
1195	+	memset(log, 0, sizeof(log));
1196	+	#endif
1197	+
1198		#if ENABLE_MON
1199	<	if (log_ptr == -1) {
1199	>	static bool first_time = true;
1200	>	if (first_time) {
1201	>	first_time = false;
1202	>	mon_add_command("regs", dump_regs, "regs Dump m68k emulator registers\n");
1203	>	#if FLIGHT_RECORDER
1204		// Install "log" command in mon
1205		mon_add_command("log", dump_log, "log Dump m68k emulation log\n");
1159	–	}
1206		#endif
1207	<	log_ptr = 0;
1162	<	memset(log, 0, sizeof(log));
1207	>	}
1208		#endif
1209		}
1210
#	Line 1189 \| Line 1234 \| void m68k_emulop(uae_u32 opcode)
1234		MakeFromSR();
1235		}
1236
1237	<	cpuop_rettype REGPARAM2 op_illg (uae_u32 opcode)
1237	>	void REGPARAM2 op_illg (uae_u32 opcode)
1238		{
1239		uaecptr pc = m68k_getpc ();
1240
1241		if ((opcode & 0xF000) == 0xA000) {
1242		Exception(0xA,0);
1243	<	cpuop_return(CFLOW_TRAP);
1243	>	return;
1244		}
1245
1246		if ((opcode & 0xF000) == 0xF000) {
1247		Exception(0xB,0);
1248	<	cpuop_return(CFLOW_TRAP);
1248	>	return;
1249		}
1250
1251		write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
#	Line 1209 \| Line 1254 \| cpuop_rettype REGPARAM2 op_illg (uae_u32
1254		#endif
1255
1256		Exception (4,0);
1257	<	cpuop_return(CFLOW_TRAP);
1257	>	return;
1258		}
1259
1260		void mmu_op(uae_u32 opcode, uae_u16 extra)
#	Line 1307 \| Line 1352 \| int m68k_do_specialties (void)
1352		}
1353		if (SPCFLAGS_TEST( SPCFLAG_BRK )) {
1354		SPCFLAGS_CLEAR( SPCFLAG_BRK );
1355	<	return CFLOW_EXEC_RETURN;
1355	>	return 1;
1356		}
1357		return 0;
1358		}
#	Line 1320 \| Line 1365 \| void m68k_do_execute (void)
1365		m68k_record_step(m68k_getpc());
1366		#endif
1367		(*cpufunctbl[opcode])(opcode);
1368	+	cpu_check_ticks();
1369		if (SPCFLAGS_TEST(SPCFLAG_ALL_BUT_EXEC_RETURN)) {
1370		if (m68k_do_specialties())
1371		return;
#	Line 1327 \| Line 1373 \| void m68k_do_execute (void)
1373		}
1374		}
1375
1330	–	#if USE_JIT && !defined(X86_ASSEMBLY)
1331	–	void m68k_compile_execute (void)
1332	–	{
1333	–	for (;;) {
1334	–	if (quit_program)
1335	–	break;
1336	–	m68k_do_compile_execute();
1337	–	}
1338	–	}
1339	–	#endif
1340	–
1376		void m68k_execute (void)
1377		{
1378		#if USE_JIT

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Comparing BasiliskII/src/uae_cpu/newcpu.cpp (file contents): Revision 1.17 by gbeauche, 2002-10-01T09:39:55Z vs. Revision 1.23 by gbeauche, 2007-06-15T08:10:48Z

Diff Legend

Comparing BasiliskII/src/uae_cpu/newcpu.cpp (file contents):
Revision 1.17 by gbeauche, 2002-10-01T09:39:55Z vs.
Revision 1.23 by gbeauche, 2007-06-15T08:10:48Z