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root/cebix/BasiliskII/src/uae_cpu/newcpu.cpp
Revision: 1.9
Committed: 2001-07-13T10:13:58Z (23 years, 3 months ago) by gbeauche
Branch: MAIN
CVS Tags: snapshot-15012002
Changes since 1.8: +26 -13 lines
Log Message:
- merged some code from uae-0.8.16

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * UAE - The Un*x Amiga Emulator
3     *
4     * MC68000 emulation
5     *
6     * (c) 1995 Bernd Schmidt
7     */
8    
9     #include <stdio.h>
10     #include <stdlib.h>
11     #include <string.h>
12    
13     #include "sysdeps.h"
14    
15     #include "cpu_emulation.h"
16     #include "main.h"
17     #include "emul_op.h"
18    
19     extern int intlev(void); // From baisilisk_glue.cpp
20    
21     #include "m68k.h"
22     #include "memory.h"
23     #include "readcpu.h"
24     #include "newcpu.h"
25    
26     int quit_program = 0;
27     int debugging = 0;
28     struct flag_struct regflags;
29    
30     /* Opcode of faulting instruction */
31     uae_u16 last_op_for_exception_3;
32     /* PC at fault time */
33     uaecptr last_addr_for_exception_3;
34     /* Address that generated the exception */
35     uaecptr last_fault_for_exception_3;
36    
37     int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
38     int imm8_table[] = { 8,1,2,3,4,5,6,7 };
39    
40     int movem_index1[256];
41     int movem_index2[256];
42     int movem_next[256];
43    
44     int fpp_movem_index1[256];
45     int fpp_movem_index2[256];
46     int fpp_movem_next[256];
47    
48     cpuop_func *cpufunctbl[65536];
49    
50     #define COUNT_INSTRS 0
51    
52     #if COUNT_INSTRS
53     static unsigned long int instrcount[65536];
54     static uae_u16 opcodenums[65536];
55    
56     static int compfn (const void *el1, const void *el2)
57     {
58     return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
59     }
60    
61     static char *icountfilename (void)
62     {
63     char *name = getenv ("INSNCOUNT");
64     if (name)
65     return name;
66     return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
67     }
68    
69     void dump_counts (void)
70     {
71     FILE *f = fopen (icountfilename (), "w");
72     unsigned long int total;
73     int i;
74    
75     write_log ("Writing instruction count file...\n");
76     for (i = 0; i < 65536; i++) {
77     opcodenums[i] = i;
78     total += instrcount[i];
79     }
80     qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
81    
82     fprintf (f, "Total: %lu\n", total);
83     for (i=0; i < 65536; i++) {
84     unsigned long int cnt = instrcount[opcodenums[i]];
85     struct instr *dp;
86     struct mnemolookup *lookup;
87     if (!cnt)
88     break;
89     dp = table68k + opcodenums[i];
90     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
91     ;
92     fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
93     }
94     fclose (f);
95     }
96     #else
97     void dump_counts (void)
98     {
99     }
100     #endif
101    
102     int broken_in;
103    
104     static __inline__ unsigned int cft_map (unsigned int f)
105     {
106     #ifndef HAVE_GET_WORD_UNSWAPPED
107     return f;
108     #else
109     return ((f >> 8) & 255) | ((f & 255) << 8);
110     #endif
111     }
112    
113 cebix 1.4 static void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
114 cebix 1.1
115 cebix 1.4 static void REGPARAM2 op_illg_1 (uae_u32 opcode)
116 cebix 1.1 {
117     op_illg (cft_map (opcode));
118     }
119    
120     static void build_cpufunctbl (void)
121     {
122     int i;
123     unsigned long opcode;
124 cebix 1.2 int cpu_level = 0; // 68000 (default)
125     if (CPUType == 4)
126     cpu_level = 4; // 68040 with FPU
127     else {
128     if (FPUType)
129     cpu_level = 3; // 68020 with FPU
130     else if (CPUType >= 2)
131     cpu_level = 2; // 68020
132     else if (CPUType == 1)
133     cpu_level = 1;
134     }
135     struct cputbl *tbl = (
136     cpu_level == 4 ? op_smalltbl_0
137     : cpu_level == 3 ? op_smalltbl_1
138     : cpu_level == 2 ? op_smalltbl_2
139     : cpu_level == 1 ? op_smalltbl_3
140     : op_smalltbl_4);
141 cebix 1.1
142     for (opcode = 0; opcode < 65536; opcode++)
143     cpufunctbl[cft_map (opcode)] = op_illg_1;
144     for (i = 0; tbl[i].handler != NULL; i++) {
145     if (! tbl[i].specific)
146     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
147     }
148     for (opcode = 0; opcode < 65536; opcode++) {
149     cpuop_func *f;
150    
151     if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
152     continue;
153    
154     if (table68k[opcode].handler != -1) {
155     f = cpufunctbl[cft_map (table68k[opcode].handler)];
156     if (f == op_illg_1)
157     abort();
158     cpufunctbl[cft_map (opcode)] = f;
159     }
160     }
161     for (i = 0; tbl[i].handler != NULL; i++) {
162     if (tbl[i].specific)
163     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
164     }
165     }
166    
167     void init_m68k (void)
168     {
169     int i;
170    
171     for (i = 0 ; i < 256 ; i++) {
172     int j;
173     for (j = 0 ; j < 8 ; j++) {
174     if (i & (1 << j)) break;
175     }
176     movem_index1[i] = j;
177     movem_index2[i] = 7-j;
178     movem_next[i] = i & (~(1 << j));
179     }
180     for (i = 0 ; i < 256 ; i++) {
181     int j;
182     for (j = 7 ; j >= 0 ; j--) {
183     if (i & (1 << j)) break;
184     }
185 cebix 1.5 fpp_movem_index1[i] = 7-j;
186     fpp_movem_index2[i] = j;
187 cebix 1.1 fpp_movem_next[i] = i & (~(1 << j));
188     }
189     #if COUNT_INSTRS
190     {
191     FILE *f = fopen (icountfilename (), "r");
192     memset (instrcount, 0, sizeof instrcount);
193     if (f) {
194     uae_u32 opcode, count, total;
195     char name[20];
196     write_log ("Reading instruction count file...\n");
197     fscanf (f, "Total: %lu\n", &total);
198     while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
199     instrcount[opcode] = count;
200     }
201     fclose(f);
202     }
203     }
204     #endif
205     read_table68k ();
206     do_merges ();
207    
208     build_cpufunctbl ();
209 gbeauche 1.6
210     fpu_init ();
211     fpu_set_integral_fpu (CPUType == 4);
212     }
213    
214     void exit_m68k (void)
215     {
216     fpu_exit ();
217 cebix 1.1 }
218    
219     struct regstruct regs, lastint_regs;
220     static struct regstruct regs_backup[16];
221     static int backup_pointer = 0;
222     static long int m68kpc_offset;
223     int lastint_no;
224    
225 gbeauche 1.7 #if REAL_ADDRESSING || DIRECT_ADDRESSING
226     #define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1)
227     #define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o))
228     #define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o))
229     #else
230 cebix 1.1 #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
231     #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
232     #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
233 gbeauche 1.7 #endif
234 cebix 1.1
235     uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf)
236     {
237     uae_u16 dp;
238     uae_s8 disp8;
239     uae_s16 disp16;
240     int r;
241     uae_u32 dispreg;
242     uaecptr addr;
243     uae_s32 offset = 0;
244     char buffer[80];
245    
246     switch (mode){
247     case Dreg:
248     sprintf (buffer,"D%d", reg);
249     break;
250     case Areg:
251     sprintf (buffer,"A%d", reg);
252     break;
253     case Aind:
254     sprintf (buffer,"(A%d)", reg);
255     break;
256     case Aipi:
257     sprintf (buffer,"(A%d)+", reg);
258     break;
259     case Apdi:
260     sprintf (buffer,"-(A%d)", reg);
261     break;
262     case Ad16:
263     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
264     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
265     sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
266 cebix 1.5 (unsigned long)addr);
267 cebix 1.1 break;
268     case Ad8r:
269     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
270     disp8 = dp & 0xFF;
271     r = (dp & 0x7000) >> 12;
272     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
273     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
274     dispreg <<= (dp >> 9) & 3;
275    
276     if (dp & 0x100) {
277     uae_s32 outer = 0, disp = 0;
278     uae_s32 base = m68k_areg(regs,reg);
279     char name[10];
280     sprintf (name,"A%d, ",reg);
281     if (dp & 0x80) { base = 0; name[0] = 0; }
282     if (dp & 0x40) dispreg = 0;
283     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
284     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
285     base += disp;
286    
287     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
288     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
289    
290     if (!(dp & 4)) base += dispreg;
291     if (dp & 3) base = get_long (base);
292     if (dp & 4) base += dispreg;
293    
294     addr = base + outer;
295     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
296     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
297     1 << ((dp >> 9) & 3),
298     disp,outer,
299 cebix 1.5 (unsigned long)addr);
300 cebix 1.1 } else {
301     addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
302     sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
303     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
304     1 << ((dp >> 9) & 3), disp8,
305 cebix 1.5 (unsigned long)addr);
306 cebix 1.1 }
307     break;
308     case PC16:
309     addr = m68k_getpc () + m68kpc_offset;
310     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
311     addr += (uae_s16)disp16;
312 cebix 1.5 sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
313 cebix 1.1 break;
314     case PC8r:
315     addr = m68k_getpc () + m68kpc_offset;
316     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
317     disp8 = dp & 0xFF;
318     r = (dp & 0x7000) >> 12;
319     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
320     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
321     dispreg <<= (dp >> 9) & 3;
322    
323     if (dp & 0x100) {
324     uae_s32 outer = 0,disp = 0;
325     uae_s32 base = addr;
326     char name[10];
327     sprintf (name,"PC, ");
328     if (dp & 0x80) { base = 0; name[0] = 0; }
329     if (dp & 0x40) dispreg = 0;
330     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
331     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
332     base += disp;
333    
334     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
335     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
336    
337     if (!(dp & 4)) base += dispreg;
338     if (dp & 3) base = get_long (base);
339     if (dp & 4) base += dispreg;
340    
341     addr = base + outer;
342     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
343     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
344     1 << ((dp >> 9) & 3),
345     disp,outer,
346 cebix 1.5 (unsigned long)addr);
347 cebix 1.1 } else {
348     addr += (uae_s32)((uae_s8)disp8) + dispreg;
349     sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
350     (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
351 cebix 1.5 disp8, (unsigned long)addr);
352 cebix 1.1 }
353     break;
354     case absw:
355 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
356 cebix 1.1 m68kpc_offset += 2;
357     break;
358     case absl:
359 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
360 cebix 1.1 m68kpc_offset += 4;
361     break;
362     case imm:
363     switch (size){
364     case sz_byte:
365     sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
366     m68kpc_offset += 2;
367     break;
368     case sz_word:
369     sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
370     m68kpc_offset += 2;
371     break;
372     case sz_long:
373 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
374 cebix 1.1 m68kpc_offset += 4;
375     break;
376     default:
377     break;
378     }
379     break;
380     case imm0:
381     offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
382     m68kpc_offset += 2;
383     sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
384     break;
385     case imm1:
386     offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
387     m68kpc_offset += 2;
388     sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
389     break;
390     case imm2:
391     offset = (uae_s32)get_ilong_1 (m68kpc_offset);
392     m68kpc_offset += 4;
393 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
394 cebix 1.1 break;
395     case immi:
396     offset = (uae_s32)(uae_s8)(reg & 0xff);
397 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
398 cebix 1.1 break;
399     default:
400     break;
401     }
402     if (buf == 0)
403     printf ("%s", buffer);
404     else
405     strcat (buf, buffer);
406     return offset;
407     }
408    
409     /* The plan is that this will take over the job of exception 3 handling -
410     * the CPU emulation functions will just do a longjmp to m68k_go whenever
411     * they hit an odd address. */
412     static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
413     {
414     uae_u16 dp;
415     uae_s8 disp8;
416     uae_s16 disp16;
417     int r;
418     uae_u32 dispreg;
419     uaecptr addr;
420     uae_s32 offset = 0;
421    
422     switch (mode){
423     case Dreg:
424     *val = m68k_dreg (regs, reg);
425     return 1;
426     case Areg:
427     *val = m68k_areg (regs, reg);
428     return 1;
429    
430     case Aind:
431     case Aipi:
432     addr = m68k_areg (regs, reg);
433     break;
434     case Apdi:
435     addr = m68k_areg (regs, reg);
436     break;
437     case Ad16:
438     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
439     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
440     break;
441     case Ad8r:
442     addr = m68k_areg (regs, reg);
443     d8r_common:
444     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
445     disp8 = dp & 0xFF;
446     r = (dp & 0x7000) >> 12;
447     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
448     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
449     dispreg <<= (dp >> 9) & 3;
450    
451     if (dp & 0x100) {
452     uae_s32 outer = 0, disp = 0;
453     uae_s32 base = addr;
454     if (dp & 0x80) base = 0;
455     if (dp & 0x40) dispreg = 0;
456     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
457     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
458     base += disp;
459    
460     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
461     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
462    
463     if (!(dp & 4)) base += dispreg;
464     if (dp & 3) base = get_long (base);
465     if (dp & 4) base += dispreg;
466    
467     addr = base + outer;
468     } else {
469     addr += (uae_s32)((uae_s8)disp8) + dispreg;
470     }
471     break;
472     case PC16:
473     addr = m68k_getpc () + m68kpc_offset;
474     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
475     addr += (uae_s16)disp16;
476     break;
477     case PC8r:
478     addr = m68k_getpc () + m68kpc_offset;
479     goto d8r_common;
480     case absw:
481     addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
482     m68kpc_offset += 2;
483     break;
484     case absl:
485     addr = get_ilong_1 (m68kpc_offset);
486     m68kpc_offset += 4;
487     break;
488     case imm:
489     switch (size){
490     case sz_byte:
491     *val = get_iword_1 (m68kpc_offset) & 0xff;
492     m68kpc_offset += 2;
493     break;
494     case sz_word:
495     *val = get_iword_1 (m68kpc_offset) & 0xffff;
496     m68kpc_offset += 2;
497     break;
498     case sz_long:
499     *val = get_ilong_1 (m68kpc_offset);
500     m68kpc_offset += 4;
501     break;
502     default:
503     break;
504     }
505     return 1;
506     case imm0:
507     *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
508     m68kpc_offset += 2;
509     return 1;
510     case imm1:
511     *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
512     m68kpc_offset += 2;
513     return 1;
514     case imm2:
515     *val = get_ilong_1 (m68kpc_offset);
516     m68kpc_offset += 4;
517     return 1;
518     case immi:
519     *val = (uae_s32)(uae_s8)(reg & 0xff);
520     return 1;
521     default:
522     addr = 0;
523     break;
524     }
525     if ((addr & 1) == 0)
526     return 1;
527    
528     last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
529     last_fault_for_exception_3 = addr;
530     return 0;
531     }
532    
533     uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
534     {
535     int reg = (dp >> 12) & 15;
536     uae_s32 regd = regs.regs[reg];
537     if ((dp & 0x800) == 0)
538     regd = (uae_s32)(uae_s16)regd;
539     regd <<= (dp >> 9) & 3;
540     if (dp & 0x100) {
541     uae_s32 outer = 0;
542     if (dp & 0x80) base = 0;
543     if (dp & 0x40) regd = 0;
544    
545     if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
546     if ((dp & 0x30) == 0x30) base += next_ilong();
547    
548     if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
549     if ((dp & 0x3) == 0x3) outer = next_ilong();
550    
551     if ((dp & 0x4) == 0) base += regd;
552     if (dp & 0x3) base = get_long (base);
553     if (dp & 0x4) base += regd;
554    
555     return base + outer;
556     } else {
557     return base + (uae_s32)((uae_s8)dp) + regd;
558     }
559     }
560    
561     uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
562     {
563     int reg = (dp >> 12) & 15;
564     uae_s32 regd = regs.regs[reg];
565     #if 1
566     if ((dp & 0x800) == 0)
567     regd = (uae_s32)(uae_s16)regd;
568     return base + (uae_s8)dp + regd;
569     #else
570     /* Branch-free code... benchmark this again now that
571     * things are no longer inline. */
572     uae_s32 regd16;
573     uae_u32 mask;
574     mask = ((dp & 0x800) >> 11) - 1;
575     regd16 = (uae_s32)(uae_s16)regd;
576     regd16 &= mask;
577     mask = ~mask;
578     base += (uae_s8)dp;
579     regd &= mask;
580     regd |= regd16;
581     return base + regd;
582     #endif
583     }
584    
585     void MakeSR (void)
586     {
587     #if 0
588     assert((regs.t1 & 1) == regs.t1);
589     assert((regs.t0 & 1) == regs.t0);
590     assert((regs.s & 1) == regs.s);
591     assert((regs.m & 1) == regs.m);
592     assert((XFLG & 1) == XFLG);
593     assert((NFLG & 1) == NFLG);
594     assert((ZFLG & 1) == ZFLG);
595     assert((VFLG & 1) == VFLG);
596     assert((CFLG & 1) == CFLG);
597     #endif
598     regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
599     | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
600     | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
601     | GET_CFLG);
602     }
603    
604     void MakeFromSR (void)
605     {
606     int oldm = regs.m;
607     int olds = regs.s;
608    
609     regs.t1 = (regs.sr >> 15) & 1;
610     regs.t0 = (regs.sr >> 14) & 1;
611     regs.s = (regs.sr >> 13) & 1;
612     regs.m = (regs.sr >> 12) & 1;
613     regs.intmask = (regs.sr >> 8) & 7;
614     SET_XFLG ((regs.sr >> 4) & 1);
615     SET_NFLG ((regs.sr >> 3) & 1);
616     SET_ZFLG ((regs.sr >> 2) & 1);
617     SET_VFLG ((regs.sr >> 1) & 1);
618     SET_CFLG (regs.sr & 1);
619     if (CPUType >= 2) {
620     if (olds != regs.s) {
621     if (olds) {
622     if (oldm)
623     regs.msp = m68k_areg(regs, 7);
624     else
625     regs.isp = m68k_areg(regs, 7);
626     m68k_areg(regs, 7) = regs.usp;
627     } else {
628     regs.usp = m68k_areg(regs, 7);
629     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
630     }
631     } else if (olds && oldm != regs.m) {
632     if (oldm) {
633     regs.msp = m68k_areg(regs, 7);
634     m68k_areg(regs, 7) = regs.isp;
635     } else {
636     regs.isp = m68k_areg(regs, 7);
637     m68k_areg(regs, 7) = regs.msp;
638     }
639     }
640     } else {
641     if (olds != regs.s) {
642     if (olds) {
643     regs.isp = m68k_areg(regs, 7);
644     m68k_areg(regs, 7) = regs.usp;
645     } else {
646     regs.usp = m68k_areg(regs, 7);
647     m68k_areg(regs, 7) = regs.isp;
648     }
649     }
650     }
651    
652     regs.spcflags |= SPCFLAG_INT;
653     if (regs.t1 || regs.t0)
654     regs.spcflags |= SPCFLAG_TRACE;
655     else
656     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
657     }
658    
659     void Exception(int nr, uaecptr oldpc)
660     {
661 gbeauche 1.9 uae_u32 currpc = m68k_getpc ();
662 cebix 1.1 MakeSR();
663     if (!regs.s) {
664     regs.usp = m68k_areg(regs, 7);
665     if (CPUType >= 2)
666     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
667     else
668     m68k_areg(regs, 7) = regs.isp;
669     regs.s = 1;
670     }
671     if (CPUType > 0) {
672     if (nr == 2 || nr == 3) {
673     int i;
674     /* @@@ this is probably wrong (?) */
675     for (i = 0 ; i < 12 ; i++) {
676     m68k_areg(regs, 7) -= 2;
677     put_word (m68k_areg(regs, 7), 0);
678     }
679     m68k_areg(regs, 7) -= 2;
680     put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
681     } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
682     m68k_areg(regs, 7) -= 4;
683     put_long (m68k_areg(regs, 7), oldpc);
684     m68k_areg(regs, 7) -= 2;
685     put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
686     } else if (regs.m && nr >= 24 && nr < 32) {
687     m68k_areg(regs, 7) -= 2;
688     put_word (m68k_areg(regs, 7), nr * 4);
689     m68k_areg(regs, 7) -= 4;
690 gbeauche 1.9 put_long (m68k_areg(regs, 7), currpc);
691 cebix 1.1 m68k_areg(regs, 7) -= 2;
692     put_word (m68k_areg(regs, 7), regs.sr);
693     regs.sr |= (1 << 13);
694     regs.msp = m68k_areg(regs, 7);
695     m68k_areg(regs, 7) = regs.isp;
696     m68k_areg(regs, 7) -= 2;
697     put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
698     } else {
699     m68k_areg(regs, 7) -= 2;
700     put_word (m68k_areg(regs, 7), nr * 4);
701     }
702     } else {
703     if (nr == 2 || nr == 3) {
704     m68k_areg(regs, 7) -= 12;
705     /* ??????? */
706     if (nr == 3) {
707     put_long (m68k_areg(regs, 7), last_fault_for_exception_3);
708     put_word (m68k_areg(regs, 7)+4, last_op_for_exception_3);
709     put_long (m68k_areg(regs, 7)+8, last_addr_for_exception_3);
710     }
711     write_log ("Exception!\n");
712     goto kludge_me_do;
713     }
714     }
715     m68k_areg(regs, 7) -= 4;
716 gbeauche 1.9 put_long (m68k_areg(regs, 7), currpc);
717 cebix 1.1 kludge_me_do:
718     m68k_areg(regs, 7) -= 2;
719     put_word (m68k_areg(regs, 7), regs.sr);
720     m68k_setpc (get_long (regs.vbr + 4*nr));
721     fill_prefetch_0 ();
722     regs.t1 = regs.t0 = regs.m = 0;
723     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
724     }
725    
726     static void Interrupt(int nr)
727     {
728     assert(nr < 8 && nr >= 0);
729     lastint_regs = regs;
730     lastint_no = nr;
731     Exception(nr+24, 0);
732    
733     regs.intmask = nr;
734     regs.spcflags |= SPCFLAG_INT;
735     }
736    
737 cebix 1.2 static int caar, cacr, tc, itt0, itt1, dtt0, dtt1;
738 cebix 1.1
739 gbeauche 1.9 int m68k_move2c (int regno, uae_u32 *regp)
740 cebix 1.1 {
741 gbeauche 1.9 if ((CPUType == 1 && (regno & 0x7FF) > 1)
742     || (CPUType < 4 && (regno & 0x7FF) > 2)
743     || (CPUType == 4 && regno == 0x802))
744     {
745 cebix 1.1 op_illg (0x4E7B);
746 gbeauche 1.9 return 0;
747     } else {
748 cebix 1.1 switch (regno) {
749     case 0: regs.sfc = *regp & 7; break;
750     case 1: regs.dfc = *regp & 7; break;
751 gbeauche 1.9 case 2: cacr = *regp & (CPUType < 4 ? 0x3 : 0x80008000); break;
752 cebix 1.2 case 3: tc = *regp & 0xc000; break;
753     case 4: itt0 = *regp & 0xffffe364; break;
754     case 5: itt1 = *regp & 0xffffe364; break;
755     case 6: dtt0 = *regp & 0xffffe364; break;
756     case 7: dtt1 = *regp & 0xffffe364; break;
757 cebix 1.1 case 0x800: regs.usp = *regp; break;
758     case 0x801: regs.vbr = *regp; break;
759     case 0x802: caar = *regp &0xfc; break;
760     case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
761     case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
762     default:
763     op_illg (0x4E7B);
764 gbeauche 1.9 return 0;
765 cebix 1.1 }
766 gbeauche 1.9 }
767     return 1;
768 cebix 1.1 }
769    
770 gbeauche 1.9 int m68k_movec2 (int regno, uae_u32 *regp)
771 cebix 1.1 {
772 gbeauche 1.9 if ((CPUType == 1 && (regno & 0x7FF) > 1)
773     || (CPUType < 4 && (regno & 0x7FF) > 2)
774     || (CPUType == 4 && regno == 0x802))
775     {
776 cebix 1.1 op_illg (0x4E7A);
777 gbeauche 1.9 return 0;
778     } else {
779 cebix 1.1 switch (regno) {
780     case 0: *regp = regs.sfc; break;
781     case 1: *regp = regs.dfc; break;
782     case 2: *regp = cacr; break;
783 cebix 1.2 case 3: *regp = tc; break;
784     case 4: *regp = itt0; break;
785     case 5: *regp = itt1; break;
786     case 6: *regp = dtt0; break;
787     case 7: *regp = dtt1; break;
788 cebix 1.1 case 0x800: *regp = regs.usp; break;
789     case 0x801: *regp = regs.vbr; break;
790     case 0x802: *regp = caar; break;
791     case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
792     case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
793     default:
794     op_illg (0x4E7A);
795 gbeauche 1.9 return 0;
796     }
797 cebix 1.1 }
798 gbeauche 1.9 return 1;
799 cebix 1.1 }
800    
801     static __inline__ int
802     div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
803     {
804     uae_u32 q = 0, cbit = 0;
805     int i;
806    
807     if (div <= src_hi) {
808     return 1;
809     }
810     for (i = 0 ; i < 32 ; i++) {
811     cbit = src_hi & 0x80000000ul;
812     src_hi <<= 1;
813     if (src_lo & 0x80000000ul) src_hi++;
814     src_lo <<= 1;
815     q = q << 1;
816     if (cbit || div <= src_hi) {
817     q |= 1;
818     src_hi -= div;
819     }
820     }
821     *quot = q;
822     *rem = src_hi;
823     return 0;
824     }
825    
826     void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
827     {
828     #if defined(uae_s64)
829     if (src == 0) {
830     Exception (5, oldpc);
831     return;
832     }
833     if (extra & 0x800) {
834     /* signed variant */
835     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
836     uae_s64 quot, rem;
837    
838     if (extra & 0x400) {
839     a &= 0xffffffffu;
840     a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
841     }
842     rem = a % (uae_s64)(uae_s32)src;
843     quot = a / (uae_s64)(uae_s32)src;
844     if ((quot & UVAL64(0xffffffff80000000)) != 0
845     && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
846     {
847     SET_VFLG (1);
848     SET_NFLG (1);
849     SET_CFLG (0);
850     } else {
851     if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
852     SET_VFLG (0);
853     SET_CFLG (0);
854     SET_ZFLG (((uae_s32)quot) == 0);
855     SET_NFLG (((uae_s32)quot) < 0);
856     m68k_dreg(regs, extra & 7) = rem;
857     m68k_dreg(regs, (extra >> 12) & 7) = quot;
858     }
859     } else {
860     /* unsigned */
861     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
862     uae_u64 quot, rem;
863    
864     if (extra & 0x400) {
865     a &= 0xffffffffu;
866     a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
867     }
868     rem = a % (uae_u64)src;
869     quot = a / (uae_u64)src;
870     if (quot > 0xffffffffu) {
871     SET_VFLG (1);
872     SET_NFLG (1);
873     SET_CFLG (0);
874     } else {
875     SET_VFLG (0);
876     SET_CFLG (0);
877     SET_ZFLG (((uae_s32)quot) == 0);
878     SET_NFLG (((uae_s32)quot) < 0);
879     m68k_dreg(regs, extra & 7) = rem;
880     m68k_dreg(regs, (extra >> 12) & 7) = quot;
881     }
882     }
883     #else
884     if (src == 0) {
885     Exception (5, oldpc);
886     return;
887     }
888     if (extra & 0x800) {
889     /* signed variant */
890     uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
891     uae_s32 hi = lo < 0 ? -1 : 0;
892     uae_s32 save_high;
893     uae_u32 quot, rem;
894     uae_u32 sign;
895    
896     if (extra & 0x400) {
897     hi = (uae_s32)m68k_dreg(regs, extra & 7);
898     }
899     save_high = hi;
900     sign = (hi ^ src);
901     if (hi < 0) {
902     hi = ~hi;
903     lo = -lo;
904     if (lo == 0) hi++;
905     }
906     if ((uae_s32)src < 0) src = -src;
907     if (div_unsigned(hi, lo, src, &quot, &rem) ||
908     (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
909     SET_VFLG (1);
910     SET_NFLG (1);
911     SET_CFLG (0);
912     } else {
913     if (sign & 0x80000000) quot = -quot;
914     if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
915     SET_VFLG (0);
916     SET_CFLG (0);
917     SET_ZFLG (((uae_s32)quot) == 0);
918     SET_NFLG (((uae_s32)quot) < 0);
919     m68k_dreg(regs, extra & 7) = rem;
920     m68k_dreg(regs, (extra >> 12) & 7) = quot;
921     }
922     } else {
923     /* unsigned */
924     uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
925     uae_u32 hi = 0;
926     uae_u32 quot, rem;
927    
928     if (extra & 0x400) {
929     hi = (uae_u32)m68k_dreg(regs, extra & 7);
930     }
931     if (div_unsigned(hi, lo, src, &quot, &rem)) {
932     SET_VFLG (1);
933     SET_NFLG (1);
934     SET_CFLG (0);
935     } else {
936     SET_VFLG (0);
937     SET_CFLG (0);
938     SET_ZFLG (((uae_s32)quot) == 0);
939     SET_NFLG (((uae_s32)quot) < 0);
940     m68k_dreg(regs, extra & 7) = rem;
941     m68k_dreg(regs, (extra >> 12) & 7) = quot;
942     }
943     }
944     #endif
945     }
946    
947     static __inline__ void
948     mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
949     {
950     uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
951     uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
952     uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
953     uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
954     uae_u32 lo;
955    
956     lo = r0 + ((r1 << 16) & 0xffff0000ul);
957     if (lo < r0) r3++;
958     r0 = lo;
959     lo = r0 + ((r2 << 16) & 0xffff0000ul);
960     if (lo < r0) r3++;
961     r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
962     *dst_lo = lo;
963     *dst_hi = r3;
964     }
965    
966     void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
967     {
968     #if defined(uae_s64)
969     if (extra & 0x800) {
970     /* signed variant */
971     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
972    
973     a *= (uae_s64)(uae_s32)src;
974     SET_VFLG (0);
975     SET_CFLG (0);
976     SET_ZFLG (a == 0);
977     SET_NFLG (a < 0);
978     if (extra & 0x400)
979     m68k_dreg(regs, extra & 7) = a >> 32;
980     else if ((a & UVAL64(0xffffffff80000000)) != 0
981     && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
982     {
983     SET_VFLG (1);
984     }
985     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
986     } else {
987     /* unsigned */
988     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
989    
990     a *= (uae_u64)src;
991     SET_VFLG (0);
992     SET_CFLG (0);
993     SET_ZFLG (a == 0);
994     SET_NFLG (((uae_s64)a) < 0);
995     if (extra & 0x400)
996     m68k_dreg(regs, extra & 7) = a >> 32;
997     else if ((a & UVAL64(0xffffffff00000000)) != 0) {
998     SET_VFLG (1);
999     }
1000     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1001     }
1002     #else
1003     if (extra & 0x800) {
1004     /* signed variant */
1005     uae_s32 src1,src2;
1006     uae_u32 dst_lo,dst_hi;
1007     uae_u32 sign;
1008    
1009     src1 = (uae_s32)src;
1010     src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1011     sign = (src1 ^ src2);
1012     if (src1 < 0) src1 = -src1;
1013     if (src2 < 0) src2 = -src2;
1014     mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1015     if (sign & 0x80000000) {
1016     dst_hi = ~dst_hi;
1017     dst_lo = -dst_lo;
1018     if (dst_lo == 0) dst_hi++;
1019     }
1020     SET_VFLG (0);
1021     SET_CFLG (0);
1022     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1023     SET_NFLG (((uae_s32)dst_hi) < 0);
1024     if (extra & 0x400)
1025     m68k_dreg(regs, extra & 7) = dst_hi;
1026     else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1027     && ((dst_hi & 0xffffffff) != 0xffffffff
1028     || (dst_lo & 0x80000000) != 0x80000000))
1029     {
1030     SET_VFLG (1);
1031     }
1032     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1033     } else {
1034     /* unsigned */
1035     uae_u32 dst_lo,dst_hi;
1036    
1037     mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1038    
1039     SET_VFLG (0);
1040     SET_CFLG (0);
1041     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1042     SET_NFLG (((uae_s32)dst_hi) < 0);
1043     if (extra & 0x400)
1044     m68k_dreg(regs, extra & 7) = dst_hi;
1045     else if (dst_hi != 0) {
1046     SET_VFLG (1);
1047     }
1048     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1049     }
1050     #endif
1051     }
1052     static char* ccnames[] =
1053     { "T ","F ","HI","LS","CC","CS","NE","EQ",
1054     "VC","VS","PL","MI","GE","LT","GT","LE" };
1055    
1056     void m68k_reset (void)
1057     {
1058     m68k_areg (regs, 7) = 0x2000;
1059     m68k_setpc (ROMBaseMac + 0x2a);
1060     fill_prefetch_0 ();
1061     regs.kick_mask = 0xF80000;
1062     regs.s = 1;
1063     regs.m = 0;
1064     regs.stopped = 0;
1065     regs.t1 = 0;
1066     regs.t0 = 0;
1067     SET_ZFLG (0);
1068     SET_XFLG (0);
1069     SET_CFLG (0);
1070     SET_VFLG (0);
1071     SET_NFLG (0);
1072     regs.spcflags = 0;
1073     regs.intmask = 7;
1074     regs.vbr = regs.sfc = regs.dfc = 0;
1075 gbeauche 1.6 /* gb-- moved into {fpp,fpu_x86}.cpp::fpu_init()
1076     regs.fpcr = regs.fpsr = regs.fpiar = 0; */
1077     fpu_reset();
1078 cebix 1.1 }
1079    
1080 cebix 1.4 void REGPARAM2 op_illg (uae_u32 opcode)
1081 cebix 1.1 {
1082     uaecptr pc = m68k_getpc ();
1083    
1084     if ((opcode & 0xFF00) == 0x7100) {
1085     struct M68kRegisters r;
1086     int i;
1087    
1088 gbeauche 1.9 // Return from Exectue68k()?
1089 cebix 1.1 if (opcode == M68K_EXEC_RETURN) {
1090     regs.spcflags |= SPCFLAG_BRK;
1091     quit_program = 1;
1092 cebix 1.4 return;
1093 cebix 1.1 }
1094    
1095     // Call EMUL_OP opcode
1096     for (i=0; i<8; i++) {
1097     r.d[i] = m68k_dreg(regs, i);
1098     r.a[i] = m68k_areg(regs, i);
1099     }
1100     MakeSR();
1101     r.sr = regs.sr;
1102     EmulOp(opcode, &r);
1103     for (i=0; i<8; i++) {
1104     m68k_dreg(regs, i) = r.d[i];
1105     m68k_areg(regs, i) = r.a[i];
1106     }
1107     regs.sr = r.sr;
1108     MakeFromSR();
1109     m68k_incpc(2);
1110     fill_prefetch_0 ();
1111 cebix 1.4 return;
1112 cebix 1.1 }
1113    
1114     if ((opcode & 0xF000) == 0xA000) {
1115     Exception(0xA,0);
1116 cebix 1.4 return;
1117 cebix 1.1 }
1118    
1119 cebix 1.4 // write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1120 cebix 1.3
1121 cebix 1.1 if ((opcode & 0xF000) == 0xF000) {
1122     Exception(0xB,0);
1123 cebix 1.4 return;
1124 cebix 1.1 }
1125    
1126 cebix 1.4 write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1127    
1128 cebix 1.1 Exception (4,0);
1129     }
1130    
1131     void mmu_op(uae_u32 opcode, uae_u16 extra)
1132     {
1133     if ((extra & 0xB000) == 0) { /* PMOVE instruction */
1134    
1135     } else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */
1136     } else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */
1137     } else
1138     op_illg (opcode);
1139     }
1140    
1141     static int n_insns = 0, n_spcinsns = 0;
1142    
1143     static uaecptr last_trace_ad = 0;
1144    
1145     static void do_trace (void)
1146     {
1147 gbeauche 1.9 if (regs.t0 && CPUType >= 2) {
1148 cebix 1.1 uae_u16 opcode;
1149     /* should also include TRAP, CHK, SR modification FPcc */
1150     /* probably never used so why bother */
1151     /* We can afford this to be inefficient... */
1152     m68k_setpc (m68k_getpc ());
1153     fill_prefetch_0 ();
1154     opcode = get_word (regs.pc);
1155     if (opcode == 0x4e72 /* RTE */
1156     || opcode == 0x4e74 /* RTD */
1157     || opcode == 0x4e75 /* RTS */
1158     || opcode == 0x4e77 /* RTR */
1159     || opcode == 0x4e76 /* TRAPV */
1160     || (opcode & 0xffc0) == 0x4e80 /* JSR */
1161     || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1162     || (opcode & 0xff00) == 0x6100 /* BSR */
1163     || ((opcode & 0xf000) == 0x6000 /* Bcc */
1164     && cctrue((opcode >> 8) & 0xf))
1165     || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1166     && !cctrue((opcode >> 8) & 0xf)
1167     && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1168     {
1169     last_trace_ad = m68k_getpc ();
1170     regs.spcflags &= ~SPCFLAG_TRACE;
1171     regs.spcflags |= SPCFLAG_DOTRACE;
1172     }
1173     } else if (regs.t1) {
1174     last_trace_ad = m68k_getpc ();
1175     regs.spcflags &= ~SPCFLAG_TRACE;
1176     regs.spcflags |= SPCFLAG_DOTRACE;
1177     }
1178     }
1179    
1180    
1181     static int do_specialties (void)
1182     {
1183     /*n_spcinsns++;*/
1184     if (regs.spcflags & SPCFLAG_DOTRACE) {
1185     Exception (9,last_trace_ad);
1186     }
1187     while (regs.spcflags & SPCFLAG_STOP) {
1188     if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){
1189     int intr = intlev ();
1190     regs.spcflags &= ~(SPCFLAG_INT | SPCFLAG_DOINT);
1191     if (intr != -1 && intr > regs.intmask) {
1192     Interrupt (intr);
1193     regs.stopped = 0;
1194     regs.spcflags &= ~SPCFLAG_STOP;
1195     }
1196     }
1197     }
1198     if (regs.spcflags & SPCFLAG_TRACE)
1199     do_trace ();
1200    
1201     if (regs.spcflags & SPCFLAG_DOINT) {
1202     int intr = intlev ();
1203     regs.spcflags &= ~SPCFLAG_DOINT;
1204     if (intr != -1 && intr > regs.intmask) {
1205     Interrupt (intr);
1206     regs.stopped = 0;
1207     }
1208     }
1209     if (regs.spcflags & SPCFLAG_INT) {
1210     regs.spcflags &= ~SPCFLAG_INT;
1211     regs.spcflags |= SPCFLAG_DOINT;
1212     }
1213     if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1214     regs.spcflags &= ~(SPCFLAG_BRK | SPCFLAG_MODE_CHANGE);
1215     return 1;
1216     }
1217     return 0;
1218     }
1219    
1220     static void m68k_run_1 (void)
1221     {
1222 cebix 1.4 for (;;) {
1223     uae_u32 opcode = GET_OPCODE;
1224     (*cpufunctbl[opcode])(opcode);
1225     if (regs.spcflags) {
1226     if (do_specialties())
1227     return;
1228     }
1229 cebix 1.1 }
1230     }
1231    
1232     #define m68k_run1 m68k_run_1
1233    
1234     int in_m68k_go = 0;
1235    
1236     void m68k_go (int may_quit)
1237     {
1238     // m68k_go() must be reentrant for Execute68k() and Execute68kTrap() to work
1239     /*
1240     if (in_m68k_go || !may_quit) {
1241     write_log("Bug! m68k_go is not reentrant.\n");
1242     abort();
1243     }
1244     */
1245     in_m68k_go++;
1246     for (;;) {
1247     if (quit_program > 0) {
1248     if (quit_program == 1)
1249     break;
1250     quit_program = 0;
1251     m68k_reset ();
1252     }
1253     m68k_run1();
1254     }
1255     if (debugging) {
1256     uaecptr nextpc;
1257     m68k_dumpstate(&nextpc);
1258     exit(1);
1259     }
1260     in_m68k_go--;
1261     }
1262    
1263     static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1264     {
1265     uae_u32 opcode, val;
1266     struct instr *dp;
1267    
1268     opcode = get_iword_1(0);
1269     last_op_for_exception_3 = opcode;
1270     m68kpc_offset = 2;
1271    
1272     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1273     opcode = 0x4AFC;
1274     }
1275     dp = table68k + opcode;
1276    
1277     if (dp->suse) {
1278     if (!verify_ea (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, &val)) {
1279     Exception (3, 0);
1280     return;
1281     }
1282     }
1283     if (dp->duse) {
1284     if (!verify_ea (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, &val)) {
1285     Exception (3, 0);
1286     return;
1287     }
1288     }
1289     }
1290    
1291     void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt)
1292     {
1293     uaecptr newpc = 0;
1294     m68kpc_offset = addr - m68k_getpc ();
1295     while (cnt-- > 0) {
1296     char instrname[20],*ccpt;
1297     int opwords;
1298     uae_u32 opcode;
1299     struct mnemolookup *lookup;
1300     struct instr *dp;
1301     printf ("%08lx: ", m68k_getpc () + m68kpc_offset);
1302     for (opwords = 0; opwords < 5; opwords++){
1303     printf ("%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1304     }
1305     opcode = get_iword_1 (m68kpc_offset);
1306     m68kpc_offset += 2;
1307     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1308     opcode = 0x4AFC;
1309     }
1310     dp = table68k + opcode;
1311     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1312     ;
1313    
1314     strcpy (instrname, lookup->name);
1315     ccpt = strstr (instrname, "cc");
1316     if (ccpt != 0) {
1317     strncpy (ccpt, ccnames[dp->cc], 2);
1318     }
1319     printf ("%s", instrname);
1320     switch (dp->size){
1321     case sz_byte: printf (".B "); break;
1322     case sz_word: printf (".W "); break;
1323     case sz_long: printf (".L "); break;
1324     default: printf (" "); break;
1325     }
1326    
1327     if (dp->suse) {
1328     newpc = m68k_getpc () + m68kpc_offset;
1329     newpc += ShowEA (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, 0);
1330     }
1331     if (dp->suse && dp->duse)
1332     printf (",");
1333     if (dp->duse) {
1334     newpc = m68k_getpc () + m68kpc_offset;
1335     newpc += ShowEA (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, 0);
1336     }
1337     if (ccpt != 0) {
1338     if (cctrue(dp->cc))
1339     printf (" == %08lx (TRUE)", newpc);
1340     else
1341     printf (" == %08lx (FALSE)", newpc);
1342     } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1343     printf (" == %08lx", newpc);
1344     printf ("\n");
1345     }
1346     if (nextpc)
1347     *nextpc = m68k_getpc () + m68kpc_offset;
1348     }
1349    
1350     void m68k_dumpstate (uaecptr *nextpc)
1351     {
1352     int i;
1353     for (i = 0; i < 8; i++){
1354     printf ("D%d: %08lx ", i, m68k_dreg(regs, i));
1355     if ((i & 3) == 3) printf ("\n");
1356     }
1357     for (i = 0; i < 8; i++){
1358     printf ("A%d: %08lx ", i, m68k_areg(regs, i));
1359     if ((i & 3) == 3) printf ("\n");
1360     }
1361     if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1362     if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1363     if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1364     printf ("USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1365     regs.usp,regs.isp,regs.msp,regs.vbr);
1366     printf ("T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1367     regs.t1, regs.t0, regs.s, regs.m,
1368     GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1369     for (i = 0; i < 8; i++){
1370     printf ("FP%d: %g ", i, regs.fp[i]);
1371     if ((i & 3) == 3) printf ("\n");
1372     }
1373     printf ("N=%d Z=%d I=%d NAN=%d\n",
1374     (regs.fpsr & 0x8000000) != 0,
1375     (regs.fpsr & 0x4000000) != 0,
1376     (regs.fpsr & 0x2000000) != 0,
1377     (regs.fpsr & 0x1000000) != 0);
1378    
1379     m68k_disasm(m68k_getpc (), nextpc, 1);
1380     if (nextpc)
1381     printf ("next PC: %08lx\n", *nextpc);
1382     }