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root/cebix/BasiliskII/src/uae_cpu/newcpu.cpp
Revision: 1.7
Committed: 2000-09-22T17:21:25Z (24 years, 1 month ago) by gbeauche
Branch: MAIN
CVS Tags: snapshot-17022001
Changes since 1.6: +6 -0 lines
Log Message:
- changed set/get PC to better reflect direct or real addressing modes

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * UAE - The Un*x Amiga Emulator
3     *
4     * MC68000 emulation
5     *
6     * (c) 1995 Bernd Schmidt
7     */
8    
9     #include <stdio.h>
10     #include <stdlib.h>
11     #include <string.h>
12    
13     #include "sysdeps.h"
14    
15     #include "cpu_emulation.h"
16     #include "main.h"
17     #include "emul_op.h"
18    
19     extern int intlev(void); // From baisilisk_glue.cpp
20    
21     #include "m68k.h"
22     #include "memory.h"
23     #include "readcpu.h"
24     #include "newcpu.h"
25     #include "compiler.h"
26    
27     int quit_program = 0;
28     int debugging = 0;
29     struct flag_struct regflags;
30    
31     /* Opcode of faulting instruction */
32     uae_u16 last_op_for_exception_3;
33     /* PC at fault time */
34     uaecptr last_addr_for_exception_3;
35     /* Address that generated the exception */
36     uaecptr last_fault_for_exception_3;
37    
38     int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
39     int imm8_table[] = { 8,1,2,3,4,5,6,7 };
40    
41     int movem_index1[256];
42     int movem_index2[256];
43     int movem_next[256];
44    
45     int fpp_movem_index1[256];
46     int fpp_movem_index2[256];
47     int fpp_movem_next[256];
48    
49     cpuop_func *cpufunctbl[65536];
50    
51     #define COUNT_INSTRS 0
52    
53     #if COUNT_INSTRS
54     static unsigned long int instrcount[65536];
55     static uae_u16 opcodenums[65536];
56    
57     static int compfn (const void *el1, const void *el2)
58     {
59     return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
60     }
61    
62     static char *icountfilename (void)
63     {
64     char *name = getenv ("INSNCOUNT");
65     if (name)
66     return name;
67     return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
68     }
69    
70     void dump_counts (void)
71     {
72     FILE *f = fopen (icountfilename (), "w");
73     unsigned long int total;
74     int i;
75    
76     write_log ("Writing instruction count file...\n");
77     for (i = 0; i < 65536; i++) {
78     opcodenums[i] = i;
79     total += instrcount[i];
80     }
81     qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
82    
83     fprintf (f, "Total: %lu\n", total);
84     for (i=0; i < 65536; i++) {
85     unsigned long int cnt = instrcount[opcodenums[i]];
86     struct instr *dp;
87     struct mnemolookup *lookup;
88     if (!cnt)
89     break;
90     dp = table68k + opcodenums[i];
91     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
92     ;
93     fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
94     }
95     fclose (f);
96     }
97     #else
98     void dump_counts (void)
99     {
100     }
101     #endif
102    
103     int broken_in;
104    
105     static __inline__ unsigned int cft_map (unsigned int f)
106     {
107     #ifndef HAVE_GET_WORD_UNSWAPPED
108     return f;
109     #else
110     return ((f >> 8) & 255) | ((f & 255) << 8);
111     #endif
112     }
113    
114 cebix 1.4 static void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
115 cebix 1.1
116 cebix 1.4 static void REGPARAM2 op_illg_1 (uae_u32 opcode)
117 cebix 1.1 {
118     op_illg (cft_map (opcode));
119     }
120    
121     static void build_cpufunctbl (void)
122     {
123     int i;
124     unsigned long opcode;
125 cebix 1.2 int cpu_level = 0; // 68000 (default)
126     if (CPUType == 4)
127     cpu_level = 4; // 68040 with FPU
128     else {
129     if (FPUType)
130     cpu_level = 3; // 68020 with FPU
131     else if (CPUType >= 2)
132     cpu_level = 2; // 68020
133     else if (CPUType == 1)
134     cpu_level = 1;
135     }
136     struct cputbl *tbl = (
137     cpu_level == 4 ? op_smalltbl_0
138     : cpu_level == 3 ? op_smalltbl_1
139     : cpu_level == 2 ? op_smalltbl_2
140     : cpu_level == 1 ? op_smalltbl_3
141     : op_smalltbl_4);
142 cebix 1.1
143     for (opcode = 0; opcode < 65536; opcode++)
144     cpufunctbl[cft_map (opcode)] = op_illg_1;
145     for (i = 0; tbl[i].handler != NULL; i++) {
146     if (! tbl[i].specific)
147     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
148     }
149     for (opcode = 0; opcode < 65536; opcode++) {
150     cpuop_func *f;
151    
152     if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
153     continue;
154    
155     if (table68k[opcode].handler != -1) {
156     f = cpufunctbl[cft_map (table68k[opcode].handler)];
157     if (f == op_illg_1)
158     abort();
159     cpufunctbl[cft_map (opcode)] = f;
160     }
161     }
162     for (i = 0; tbl[i].handler != NULL; i++) {
163     if (tbl[i].specific)
164     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
165     }
166     }
167    
168     void init_m68k (void)
169     {
170     int i;
171    
172     for (i = 0 ; i < 256 ; i++) {
173     int j;
174     for (j = 0 ; j < 8 ; j++) {
175     if (i & (1 << j)) break;
176     }
177     movem_index1[i] = j;
178     movem_index2[i] = 7-j;
179     movem_next[i] = i & (~(1 << j));
180     }
181     for (i = 0 ; i < 256 ; i++) {
182     int j;
183     for (j = 7 ; j >= 0 ; j--) {
184     if (i & (1 << j)) break;
185     }
186 cebix 1.5 fpp_movem_index1[i] = 7-j;
187     fpp_movem_index2[i] = j;
188 cebix 1.1 fpp_movem_next[i] = i & (~(1 << j));
189     }
190     #if COUNT_INSTRS
191     {
192     FILE *f = fopen (icountfilename (), "r");
193     memset (instrcount, 0, sizeof instrcount);
194     if (f) {
195     uae_u32 opcode, count, total;
196     char name[20];
197     write_log ("Reading instruction count file...\n");
198     fscanf (f, "Total: %lu\n", &total);
199     while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
200     instrcount[opcode] = count;
201     }
202     fclose(f);
203     }
204     }
205     #endif
206     read_table68k ();
207     do_merges ();
208    
209     build_cpufunctbl ();
210 gbeauche 1.6
211     fpu_init ();
212     fpu_set_integral_fpu (CPUType == 4);
213     }
214    
215     void exit_m68k (void)
216     {
217     fpu_exit ();
218 cebix 1.1 }
219    
220     struct regstruct regs, lastint_regs;
221     static struct regstruct regs_backup[16];
222     static int backup_pointer = 0;
223     static long int m68kpc_offset;
224     int lastint_no;
225    
226 gbeauche 1.7 #if REAL_ADDRESSING || DIRECT_ADDRESSING
227     #define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1)
228     #define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o))
229     #define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o))
230     #else
231 cebix 1.1 #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
232     #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
233     #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
234 gbeauche 1.7 #endif
235 cebix 1.1
236     uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf)
237     {
238     uae_u16 dp;
239     uae_s8 disp8;
240     uae_s16 disp16;
241     int r;
242     uae_u32 dispreg;
243     uaecptr addr;
244     uae_s32 offset = 0;
245     char buffer[80];
246    
247     switch (mode){
248     case Dreg:
249     sprintf (buffer,"D%d", reg);
250     break;
251     case Areg:
252     sprintf (buffer,"A%d", reg);
253     break;
254     case Aind:
255     sprintf (buffer,"(A%d)", reg);
256     break;
257     case Aipi:
258     sprintf (buffer,"(A%d)+", reg);
259     break;
260     case Apdi:
261     sprintf (buffer,"-(A%d)", reg);
262     break;
263     case Ad16:
264     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
265     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
266     sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
267 cebix 1.5 (unsigned long)addr);
268 cebix 1.1 break;
269     case Ad8r:
270     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
271     disp8 = dp & 0xFF;
272     r = (dp & 0x7000) >> 12;
273     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
274     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
275     dispreg <<= (dp >> 9) & 3;
276    
277     if (dp & 0x100) {
278     uae_s32 outer = 0, disp = 0;
279     uae_s32 base = m68k_areg(regs,reg);
280     char name[10];
281     sprintf (name,"A%d, ",reg);
282     if (dp & 0x80) { base = 0; name[0] = 0; }
283     if (dp & 0x40) dispreg = 0;
284     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
285     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
286     base += disp;
287    
288     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
289     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
290    
291     if (!(dp & 4)) base += dispreg;
292     if (dp & 3) base = get_long (base);
293     if (dp & 4) base += dispreg;
294    
295     addr = base + outer;
296     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
297     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
298     1 << ((dp >> 9) & 3),
299     disp,outer,
300 cebix 1.5 (unsigned long)addr);
301 cebix 1.1 } else {
302     addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
303     sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
304     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
305     1 << ((dp >> 9) & 3), disp8,
306 cebix 1.5 (unsigned long)addr);
307 cebix 1.1 }
308     break;
309     case PC16:
310     addr = m68k_getpc () + m68kpc_offset;
311     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
312     addr += (uae_s16)disp16;
313 cebix 1.5 sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
314 cebix 1.1 break;
315     case PC8r:
316     addr = m68k_getpc () + m68kpc_offset;
317     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
318     disp8 = dp & 0xFF;
319     r = (dp & 0x7000) >> 12;
320     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
321     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
322     dispreg <<= (dp >> 9) & 3;
323    
324     if (dp & 0x100) {
325     uae_s32 outer = 0,disp = 0;
326     uae_s32 base = addr;
327     char name[10];
328     sprintf (name,"PC, ");
329     if (dp & 0x80) { base = 0; name[0] = 0; }
330     if (dp & 0x40) dispreg = 0;
331     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
332     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
333     base += disp;
334    
335     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
336     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
337    
338     if (!(dp & 4)) base += dispreg;
339     if (dp & 3) base = get_long (base);
340     if (dp & 4) base += dispreg;
341    
342     addr = base + outer;
343     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
344     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
345     1 << ((dp >> 9) & 3),
346     disp,outer,
347 cebix 1.5 (unsigned long)addr);
348 cebix 1.1 } else {
349     addr += (uae_s32)((uae_s8)disp8) + dispreg;
350     sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
351     (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
352 cebix 1.5 disp8, (unsigned long)addr);
353 cebix 1.1 }
354     break;
355     case absw:
356 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
357 cebix 1.1 m68kpc_offset += 2;
358     break;
359     case absl:
360 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
361 cebix 1.1 m68kpc_offset += 4;
362     break;
363     case imm:
364     switch (size){
365     case sz_byte:
366     sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
367     m68kpc_offset += 2;
368     break;
369     case sz_word:
370     sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
371     m68kpc_offset += 2;
372     break;
373     case sz_long:
374 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
375 cebix 1.1 m68kpc_offset += 4;
376     break;
377     default:
378     break;
379     }
380     break;
381     case imm0:
382     offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
383     m68kpc_offset += 2;
384     sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
385     break;
386     case imm1:
387     offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
388     m68kpc_offset += 2;
389     sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
390     break;
391     case imm2:
392     offset = (uae_s32)get_ilong_1 (m68kpc_offset);
393     m68kpc_offset += 4;
394 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
395 cebix 1.1 break;
396     case immi:
397     offset = (uae_s32)(uae_s8)(reg & 0xff);
398 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
399 cebix 1.1 break;
400     default:
401     break;
402     }
403     if (buf == 0)
404     printf ("%s", buffer);
405     else
406     strcat (buf, buffer);
407     return offset;
408     }
409    
410     /* The plan is that this will take over the job of exception 3 handling -
411     * the CPU emulation functions will just do a longjmp to m68k_go whenever
412     * they hit an odd address. */
413     static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
414     {
415     uae_u16 dp;
416     uae_s8 disp8;
417     uae_s16 disp16;
418     int r;
419     uae_u32 dispreg;
420     uaecptr addr;
421     uae_s32 offset = 0;
422    
423     switch (mode){
424     case Dreg:
425     *val = m68k_dreg (regs, reg);
426     return 1;
427     case Areg:
428     *val = m68k_areg (regs, reg);
429     return 1;
430    
431     case Aind:
432     case Aipi:
433     addr = m68k_areg (regs, reg);
434     break;
435     case Apdi:
436     addr = m68k_areg (regs, reg);
437     break;
438     case Ad16:
439     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
440     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
441     break;
442     case Ad8r:
443     addr = m68k_areg (regs, reg);
444     d8r_common:
445     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
446     disp8 = dp & 0xFF;
447     r = (dp & 0x7000) >> 12;
448     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
449     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
450     dispreg <<= (dp >> 9) & 3;
451    
452     if (dp & 0x100) {
453     uae_s32 outer = 0, disp = 0;
454     uae_s32 base = addr;
455     if (dp & 0x80) base = 0;
456     if (dp & 0x40) dispreg = 0;
457     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
458     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
459     base += disp;
460    
461     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
462     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
463    
464     if (!(dp & 4)) base += dispreg;
465     if (dp & 3) base = get_long (base);
466     if (dp & 4) base += dispreg;
467    
468     addr = base + outer;
469     } else {
470     addr += (uae_s32)((uae_s8)disp8) + dispreg;
471     }
472     break;
473     case PC16:
474     addr = m68k_getpc () + m68kpc_offset;
475     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
476     addr += (uae_s16)disp16;
477     break;
478     case PC8r:
479     addr = m68k_getpc () + m68kpc_offset;
480     goto d8r_common;
481     case absw:
482     addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
483     m68kpc_offset += 2;
484     break;
485     case absl:
486     addr = get_ilong_1 (m68kpc_offset);
487     m68kpc_offset += 4;
488     break;
489     case imm:
490     switch (size){
491     case sz_byte:
492     *val = get_iword_1 (m68kpc_offset) & 0xff;
493     m68kpc_offset += 2;
494     break;
495     case sz_word:
496     *val = get_iword_1 (m68kpc_offset) & 0xffff;
497     m68kpc_offset += 2;
498     break;
499     case sz_long:
500     *val = get_ilong_1 (m68kpc_offset);
501     m68kpc_offset += 4;
502     break;
503     default:
504     break;
505     }
506     return 1;
507     case imm0:
508     *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
509     m68kpc_offset += 2;
510     return 1;
511     case imm1:
512     *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
513     m68kpc_offset += 2;
514     return 1;
515     case imm2:
516     *val = get_ilong_1 (m68kpc_offset);
517     m68kpc_offset += 4;
518     return 1;
519     case immi:
520     *val = (uae_s32)(uae_s8)(reg & 0xff);
521     return 1;
522     default:
523     addr = 0;
524     break;
525     }
526     if ((addr & 1) == 0)
527     return 1;
528    
529     last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
530     last_fault_for_exception_3 = addr;
531     return 0;
532     }
533    
534     uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
535     {
536     int reg = (dp >> 12) & 15;
537     uae_s32 regd = regs.regs[reg];
538     if ((dp & 0x800) == 0)
539     regd = (uae_s32)(uae_s16)regd;
540     regd <<= (dp >> 9) & 3;
541     if (dp & 0x100) {
542     uae_s32 outer = 0;
543     if (dp & 0x80) base = 0;
544     if (dp & 0x40) regd = 0;
545    
546     if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
547     if ((dp & 0x30) == 0x30) base += next_ilong();
548    
549     if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
550     if ((dp & 0x3) == 0x3) outer = next_ilong();
551    
552     if ((dp & 0x4) == 0) base += regd;
553     if (dp & 0x3) base = get_long (base);
554     if (dp & 0x4) base += regd;
555    
556     return base + outer;
557     } else {
558     return base + (uae_s32)((uae_s8)dp) + regd;
559     }
560     }
561    
562     uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
563     {
564     int reg = (dp >> 12) & 15;
565     uae_s32 regd = regs.regs[reg];
566     #if 1
567     if ((dp & 0x800) == 0)
568     regd = (uae_s32)(uae_s16)regd;
569     return base + (uae_s8)dp + regd;
570     #else
571     /* Branch-free code... benchmark this again now that
572     * things are no longer inline. */
573     uae_s32 regd16;
574     uae_u32 mask;
575     mask = ((dp & 0x800) >> 11) - 1;
576     regd16 = (uae_s32)(uae_s16)regd;
577     regd16 &= mask;
578     mask = ~mask;
579     base += (uae_s8)dp;
580     regd &= mask;
581     regd |= regd16;
582     return base + regd;
583     #endif
584     }
585    
586     void MakeSR (void)
587     {
588     #if 0
589     assert((regs.t1 & 1) == regs.t1);
590     assert((regs.t0 & 1) == regs.t0);
591     assert((regs.s & 1) == regs.s);
592     assert((regs.m & 1) == regs.m);
593     assert((XFLG & 1) == XFLG);
594     assert((NFLG & 1) == NFLG);
595     assert((ZFLG & 1) == ZFLG);
596     assert((VFLG & 1) == VFLG);
597     assert((CFLG & 1) == CFLG);
598     #endif
599     regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
600     | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
601     | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
602     | GET_CFLG);
603     }
604    
605     void MakeFromSR (void)
606     {
607     int oldm = regs.m;
608     int olds = regs.s;
609    
610     regs.t1 = (regs.sr >> 15) & 1;
611     regs.t0 = (regs.sr >> 14) & 1;
612     regs.s = (regs.sr >> 13) & 1;
613     regs.m = (regs.sr >> 12) & 1;
614     regs.intmask = (regs.sr >> 8) & 7;
615     SET_XFLG ((regs.sr >> 4) & 1);
616     SET_NFLG ((regs.sr >> 3) & 1);
617     SET_ZFLG ((regs.sr >> 2) & 1);
618     SET_VFLG ((regs.sr >> 1) & 1);
619     SET_CFLG (regs.sr & 1);
620     if (CPUType >= 2) {
621     if (olds != regs.s) {
622     if (olds) {
623     if (oldm)
624     regs.msp = m68k_areg(regs, 7);
625     else
626     regs.isp = m68k_areg(regs, 7);
627     m68k_areg(regs, 7) = regs.usp;
628     } else {
629     regs.usp = m68k_areg(regs, 7);
630     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
631     }
632     } else if (olds && oldm != regs.m) {
633     if (oldm) {
634     regs.msp = m68k_areg(regs, 7);
635     m68k_areg(regs, 7) = regs.isp;
636     } else {
637     regs.isp = m68k_areg(regs, 7);
638     m68k_areg(regs, 7) = regs.msp;
639     }
640     }
641     } else {
642     if (olds != regs.s) {
643     if (olds) {
644     regs.isp = m68k_areg(regs, 7);
645     m68k_areg(regs, 7) = regs.usp;
646     } else {
647     regs.usp = m68k_areg(regs, 7);
648     m68k_areg(regs, 7) = regs.isp;
649     }
650     }
651     }
652    
653     regs.spcflags |= SPCFLAG_INT;
654     if (regs.t1 || regs.t0)
655     regs.spcflags |= SPCFLAG_TRACE;
656     else
657     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
658     }
659    
660     void Exception(int nr, uaecptr oldpc)
661     {
662     compiler_flush_jsr_stack();
663     MakeSR();
664     if (!regs.s) {
665     regs.usp = m68k_areg(regs, 7);
666     if (CPUType >= 2)
667     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
668     else
669     m68k_areg(regs, 7) = regs.isp;
670     regs.s = 1;
671     }
672     if (CPUType > 0) {
673     if (nr == 2 || nr == 3) {
674     int i;
675     /* @@@ this is probably wrong (?) */
676     for (i = 0 ; i < 12 ; i++) {
677     m68k_areg(regs, 7) -= 2;
678     put_word (m68k_areg(regs, 7), 0);
679     }
680     m68k_areg(regs, 7) -= 2;
681     put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
682     } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
683     m68k_areg(regs, 7) -= 4;
684     put_long (m68k_areg(regs, 7), oldpc);
685     m68k_areg(regs, 7) -= 2;
686     put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
687     } else if (regs.m && nr >= 24 && nr < 32) {
688     m68k_areg(regs, 7) -= 2;
689     put_word (m68k_areg(regs, 7), nr * 4);
690     m68k_areg(regs, 7) -= 4;
691     put_long (m68k_areg(regs, 7), m68k_getpc ());
692     m68k_areg(regs, 7) -= 2;
693     put_word (m68k_areg(regs, 7), regs.sr);
694     regs.sr |= (1 << 13);
695     regs.msp = m68k_areg(regs, 7);
696     m68k_areg(regs, 7) = regs.isp;
697     m68k_areg(regs, 7) -= 2;
698     put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
699     } else {
700     m68k_areg(regs, 7) -= 2;
701     put_word (m68k_areg(regs, 7), nr * 4);
702     }
703     } else {
704     if (nr == 2 || nr == 3) {
705     m68k_areg(regs, 7) -= 12;
706     /* ??????? */
707     if (nr == 3) {
708     put_long (m68k_areg(regs, 7), last_fault_for_exception_3);
709     put_word (m68k_areg(regs, 7)+4, last_op_for_exception_3);
710     put_long (m68k_areg(regs, 7)+8, last_addr_for_exception_3);
711     }
712     write_log ("Exception!\n");
713     goto kludge_me_do;
714     }
715     }
716     m68k_areg(regs, 7) -= 4;
717     put_long (m68k_areg(regs, 7), m68k_getpc ());
718     kludge_me_do:
719     m68k_areg(regs, 7) -= 2;
720     put_word (m68k_areg(regs, 7), regs.sr);
721     m68k_setpc (get_long (regs.vbr + 4*nr));
722     fill_prefetch_0 ();
723     regs.t1 = regs.t0 = regs.m = 0;
724     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
725     }
726    
727     static void Interrupt(int nr)
728     {
729     assert(nr < 8 && nr >= 0);
730     lastint_regs = regs;
731     lastint_no = nr;
732     Exception(nr+24, 0);
733    
734     regs.intmask = nr;
735     regs.spcflags |= SPCFLAG_INT;
736     }
737    
738 cebix 1.2 static int caar, cacr, tc, itt0, itt1, dtt0, dtt1;
739 cebix 1.1
740     void m68k_move2c (int regno, uae_u32 *regp)
741     {
742     if (CPUType == 1 && (regno & 0x7FF) > 1)
743     op_illg (0x4E7B);
744     else
745     switch (regno) {
746     case 0: regs.sfc = *regp & 7; break;
747     case 1: regs.dfc = *regp & 7; break;
748     case 2: cacr = *regp & 0x3; break; /* ignore C and CE */
749 cebix 1.2 case 3: tc = *regp & 0xc000; break;
750     case 4: itt0 = *regp & 0xffffe364; break;
751     case 5: itt1 = *regp & 0xffffe364; break;
752     case 6: dtt0 = *regp & 0xffffe364; break;
753     case 7: dtt1 = *regp & 0xffffe364; break;
754 cebix 1.1 case 0x800: regs.usp = *regp; break;
755     case 0x801: regs.vbr = *regp; break;
756     case 0x802: caar = *regp &0xfc; break;
757     case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
758     case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
759     default:
760     op_illg (0x4E7B);
761     break;
762     }
763     }
764    
765     void m68k_movec2 (int regno, uae_u32 *regp)
766     {
767     if (CPUType == 1 && (regno & 0x7FF) > 1)
768     op_illg (0x4E7A);
769     else
770     switch (regno) {
771     case 0: *regp = regs.sfc; break;
772     case 1: *regp = regs.dfc; break;
773     case 2: *regp = cacr; break;
774 cebix 1.2 case 3: *regp = tc; break;
775     case 4: *regp = itt0; break;
776     case 5: *regp = itt1; break;
777     case 6: *regp = dtt0; break;
778     case 7: *regp = dtt1; break;
779 cebix 1.1 case 0x800: *regp = regs.usp; break;
780     case 0x801: *regp = regs.vbr; break;
781     case 0x802: *regp = caar; break;
782     case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
783     case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
784     default:
785     op_illg (0x4E7A);
786     break;
787     }
788     }
789    
790     static __inline__ int
791     div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
792     {
793     uae_u32 q = 0, cbit = 0;
794     int i;
795    
796     if (div <= src_hi) {
797     return 1;
798     }
799     for (i = 0 ; i < 32 ; i++) {
800     cbit = src_hi & 0x80000000ul;
801     src_hi <<= 1;
802     if (src_lo & 0x80000000ul) src_hi++;
803     src_lo <<= 1;
804     q = q << 1;
805     if (cbit || div <= src_hi) {
806     q |= 1;
807     src_hi -= div;
808     }
809     }
810     *quot = q;
811     *rem = src_hi;
812     return 0;
813     }
814    
815     void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
816     {
817     #if defined(uae_s64)
818     if (src == 0) {
819     Exception (5, oldpc);
820     return;
821     }
822     if (extra & 0x800) {
823     /* signed variant */
824     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
825     uae_s64 quot, rem;
826    
827     if (extra & 0x400) {
828     a &= 0xffffffffu;
829     a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
830     }
831     rem = a % (uae_s64)(uae_s32)src;
832     quot = a / (uae_s64)(uae_s32)src;
833     if ((quot & UVAL64(0xffffffff80000000)) != 0
834     && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
835     {
836     SET_VFLG (1);
837     SET_NFLG (1);
838     SET_CFLG (0);
839     } else {
840     if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
841     SET_VFLG (0);
842     SET_CFLG (0);
843     SET_ZFLG (((uae_s32)quot) == 0);
844     SET_NFLG (((uae_s32)quot) < 0);
845     m68k_dreg(regs, extra & 7) = rem;
846     m68k_dreg(regs, (extra >> 12) & 7) = quot;
847     }
848     } else {
849     /* unsigned */
850     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
851     uae_u64 quot, rem;
852    
853     if (extra & 0x400) {
854     a &= 0xffffffffu;
855     a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
856     }
857     rem = a % (uae_u64)src;
858     quot = a / (uae_u64)src;
859     if (quot > 0xffffffffu) {
860     SET_VFLG (1);
861     SET_NFLG (1);
862     SET_CFLG (0);
863     } else {
864     SET_VFLG (0);
865     SET_CFLG (0);
866     SET_ZFLG (((uae_s32)quot) == 0);
867     SET_NFLG (((uae_s32)quot) < 0);
868     m68k_dreg(regs, extra & 7) = rem;
869     m68k_dreg(regs, (extra >> 12) & 7) = quot;
870     }
871     }
872     #else
873     if (src == 0) {
874     Exception (5, oldpc);
875     return;
876     }
877     if (extra & 0x800) {
878     /* signed variant */
879     uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
880     uae_s32 hi = lo < 0 ? -1 : 0;
881     uae_s32 save_high;
882     uae_u32 quot, rem;
883     uae_u32 sign;
884    
885     if (extra & 0x400) {
886     hi = (uae_s32)m68k_dreg(regs, extra & 7);
887     }
888     save_high = hi;
889     sign = (hi ^ src);
890     if (hi < 0) {
891     hi = ~hi;
892     lo = -lo;
893     if (lo == 0) hi++;
894     }
895     if ((uae_s32)src < 0) src = -src;
896     if (div_unsigned(hi, lo, src, &quot, &rem) ||
897     (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
898     SET_VFLG (1);
899     SET_NFLG (1);
900     SET_CFLG (0);
901     } else {
902     if (sign & 0x80000000) quot = -quot;
903     if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
904     SET_VFLG (0);
905     SET_CFLG (0);
906     SET_ZFLG (((uae_s32)quot) == 0);
907     SET_NFLG (((uae_s32)quot) < 0);
908     m68k_dreg(regs, extra & 7) = rem;
909     m68k_dreg(regs, (extra >> 12) & 7) = quot;
910     }
911     } else {
912     /* unsigned */
913     uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
914     uae_u32 hi = 0;
915     uae_u32 quot, rem;
916    
917     if (extra & 0x400) {
918     hi = (uae_u32)m68k_dreg(regs, extra & 7);
919     }
920     if (div_unsigned(hi, lo, src, &quot, &rem)) {
921     SET_VFLG (1);
922     SET_NFLG (1);
923     SET_CFLG (0);
924     } else {
925     SET_VFLG (0);
926     SET_CFLG (0);
927     SET_ZFLG (((uae_s32)quot) == 0);
928     SET_NFLG (((uae_s32)quot) < 0);
929     m68k_dreg(regs, extra & 7) = rem;
930     m68k_dreg(regs, (extra >> 12) & 7) = quot;
931     }
932     }
933     #endif
934     }
935    
936     static __inline__ void
937     mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
938     {
939     uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
940     uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
941     uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
942     uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
943     uae_u32 lo;
944    
945     lo = r0 + ((r1 << 16) & 0xffff0000ul);
946     if (lo < r0) r3++;
947     r0 = lo;
948     lo = r0 + ((r2 << 16) & 0xffff0000ul);
949     if (lo < r0) r3++;
950     r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
951     *dst_lo = lo;
952     *dst_hi = r3;
953     }
954    
955     void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
956     {
957     #if defined(uae_s64)
958     if (extra & 0x800) {
959     /* signed variant */
960     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
961    
962     a *= (uae_s64)(uae_s32)src;
963     SET_VFLG (0);
964     SET_CFLG (0);
965     SET_ZFLG (a == 0);
966     SET_NFLG (a < 0);
967     if (extra & 0x400)
968     m68k_dreg(regs, extra & 7) = a >> 32;
969     else if ((a & UVAL64(0xffffffff80000000)) != 0
970     && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
971     {
972     SET_VFLG (1);
973     }
974     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
975     } else {
976     /* unsigned */
977     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
978    
979     a *= (uae_u64)src;
980     SET_VFLG (0);
981     SET_CFLG (0);
982     SET_ZFLG (a == 0);
983     SET_NFLG (((uae_s64)a) < 0);
984     if (extra & 0x400)
985     m68k_dreg(regs, extra & 7) = a >> 32;
986     else if ((a & UVAL64(0xffffffff00000000)) != 0) {
987     SET_VFLG (1);
988     }
989     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
990     }
991     #else
992     if (extra & 0x800) {
993     /* signed variant */
994     uae_s32 src1,src2;
995     uae_u32 dst_lo,dst_hi;
996     uae_u32 sign;
997    
998     src1 = (uae_s32)src;
999     src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1000     sign = (src1 ^ src2);
1001     if (src1 < 0) src1 = -src1;
1002     if (src2 < 0) src2 = -src2;
1003     mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1004     if (sign & 0x80000000) {
1005     dst_hi = ~dst_hi;
1006     dst_lo = -dst_lo;
1007     if (dst_lo == 0) dst_hi++;
1008     }
1009     SET_VFLG (0);
1010     SET_CFLG (0);
1011     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1012     SET_NFLG (((uae_s32)dst_hi) < 0);
1013     if (extra & 0x400)
1014     m68k_dreg(regs, extra & 7) = dst_hi;
1015     else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1016     && ((dst_hi & 0xffffffff) != 0xffffffff
1017     || (dst_lo & 0x80000000) != 0x80000000))
1018     {
1019     SET_VFLG (1);
1020     }
1021     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1022     } else {
1023     /* unsigned */
1024     uae_u32 dst_lo,dst_hi;
1025    
1026     mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1027    
1028     SET_VFLG (0);
1029     SET_CFLG (0);
1030     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1031     SET_NFLG (((uae_s32)dst_hi) < 0);
1032     if (extra & 0x400)
1033     m68k_dreg(regs, extra & 7) = dst_hi;
1034     else if (dst_hi != 0) {
1035     SET_VFLG (1);
1036     }
1037     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1038     }
1039     #endif
1040     }
1041     static char* ccnames[] =
1042     { "T ","F ","HI","LS","CC","CS","NE","EQ",
1043     "VC","VS","PL","MI","GE","LT","GT","LE" };
1044    
1045     void m68k_reset (void)
1046     {
1047     m68k_areg (regs, 7) = 0x2000;
1048     m68k_setpc (ROMBaseMac + 0x2a);
1049     fill_prefetch_0 ();
1050     regs.kick_mask = 0xF80000;
1051     regs.s = 1;
1052     regs.m = 0;
1053     regs.stopped = 0;
1054     regs.t1 = 0;
1055     regs.t0 = 0;
1056     SET_ZFLG (0);
1057     SET_XFLG (0);
1058     SET_CFLG (0);
1059     SET_VFLG (0);
1060     SET_NFLG (0);
1061     regs.spcflags = 0;
1062     regs.intmask = 7;
1063     regs.vbr = regs.sfc = regs.dfc = 0;
1064 gbeauche 1.6 /* gb-- moved into {fpp,fpu_x86}.cpp::fpu_init()
1065     regs.fpcr = regs.fpsr = regs.fpiar = 0; */
1066     fpu_reset();
1067 cebix 1.1 }
1068    
1069 cebix 1.4 void REGPARAM2 op_illg (uae_u32 opcode)
1070 cebix 1.1 {
1071     uaecptr pc = m68k_getpc ();
1072    
1073     compiler_flush_jsr_stack ();
1074    
1075     if ((opcode & 0xFF00) == 0x7100) {
1076     struct M68kRegisters r;
1077     int i;
1078    
1079     // Return from Execute68k()?
1080     if (opcode == M68K_EXEC_RETURN) {
1081     regs.spcflags |= SPCFLAG_BRK;
1082     quit_program = 1;
1083 cebix 1.4 return;
1084 cebix 1.1 }
1085    
1086     // Call EMUL_OP opcode
1087     for (i=0; i<8; i++) {
1088     r.d[i] = m68k_dreg(regs, i);
1089     r.a[i] = m68k_areg(regs, i);
1090     }
1091     MakeSR();
1092     r.sr = regs.sr;
1093     EmulOp(opcode, &r);
1094     for (i=0; i<8; i++) {
1095     m68k_dreg(regs, i) = r.d[i];
1096     m68k_areg(regs, i) = r.a[i];
1097     }
1098     regs.sr = r.sr;
1099     MakeFromSR();
1100     m68k_incpc(2);
1101     fill_prefetch_0 ();
1102 cebix 1.4 return;
1103 cebix 1.1 }
1104    
1105     if ((opcode & 0xF000) == 0xA000) {
1106     Exception(0xA,0);
1107 cebix 1.4 return;
1108 cebix 1.1 }
1109    
1110 cebix 1.4 // write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1111 cebix 1.3
1112 cebix 1.1 if ((opcode & 0xF000) == 0xF000) {
1113     Exception(0xB,0);
1114 cebix 1.4 return;
1115 cebix 1.1 }
1116    
1117 cebix 1.4 write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1118    
1119 cebix 1.1 Exception (4,0);
1120     }
1121    
1122     void mmu_op(uae_u32 opcode, uae_u16 extra)
1123     {
1124     if ((extra & 0xB000) == 0) { /* PMOVE instruction */
1125    
1126     } else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */
1127     } else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */
1128     } else
1129     op_illg (opcode);
1130     }
1131    
1132     static int n_insns = 0, n_spcinsns = 0;
1133    
1134     static uaecptr last_trace_ad = 0;
1135    
1136     static void do_trace (void)
1137     {
1138     if (regs.t0) {
1139     uae_u16 opcode;
1140     /* should also include TRAP, CHK, SR modification FPcc */
1141     /* probably never used so why bother */
1142     /* We can afford this to be inefficient... */
1143     m68k_setpc (m68k_getpc ());
1144     fill_prefetch_0 ();
1145     opcode = get_word (regs.pc);
1146     if (opcode == 0x4e72 /* RTE */
1147     || opcode == 0x4e74 /* RTD */
1148     || opcode == 0x4e75 /* RTS */
1149     || opcode == 0x4e77 /* RTR */
1150     || opcode == 0x4e76 /* TRAPV */
1151     || (opcode & 0xffc0) == 0x4e80 /* JSR */
1152     || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1153     || (opcode & 0xff00) == 0x6100 /* BSR */
1154     || ((opcode & 0xf000) == 0x6000 /* Bcc */
1155     && cctrue((opcode >> 8) & 0xf))
1156     || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1157     && !cctrue((opcode >> 8) & 0xf)
1158     && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1159     {
1160     last_trace_ad = m68k_getpc ();
1161     regs.spcflags &= ~SPCFLAG_TRACE;
1162     regs.spcflags |= SPCFLAG_DOTRACE;
1163     }
1164     } else if (regs.t1) {
1165     last_trace_ad = m68k_getpc ();
1166     regs.spcflags &= ~SPCFLAG_TRACE;
1167     regs.spcflags |= SPCFLAG_DOTRACE;
1168     }
1169     }
1170    
1171    
1172     static int do_specialties (void)
1173     {
1174     /*n_spcinsns++;*/
1175     run_compiled_code();
1176     if (regs.spcflags & SPCFLAG_DOTRACE) {
1177     Exception (9,last_trace_ad);
1178     }
1179     while (regs.spcflags & SPCFLAG_STOP) {
1180     if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){
1181     int intr = intlev ();
1182     regs.spcflags &= ~(SPCFLAG_INT | SPCFLAG_DOINT);
1183     if (intr != -1 && intr > regs.intmask) {
1184     Interrupt (intr);
1185     regs.stopped = 0;
1186     regs.spcflags &= ~SPCFLAG_STOP;
1187     }
1188     }
1189     }
1190     if (regs.spcflags & SPCFLAG_TRACE)
1191     do_trace ();
1192    
1193     if (regs.spcflags & SPCFLAG_DOINT) {
1194     int intr = intlev ();
1195     regs.spcflags &= ~SPCFLAG_DOINT;
1196     if (intr != -1 && intr > regs.intmask) {
1197     Interrupt (intr);
1198     regs.stopped = 0;
1199     }
1200     }
1201     if (regs.spcflags & SPCFLAG_INT) {
1202     regs.spcflags &= ~SPCFLAG_INT;
1203     regs.spcflags |= SPCFLAG_DOINT;
1204     }
1205     if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1206     regs.spcflags &= ~(SPCFLAG_BRK | SPCFLAG_MODE_CHANGE);
1207     return 1;
1208     }
1209     return 0;
1210     }
1211    
1212     static void m68k_run_1 (void)
1213     {
1214 cebix 1.4 for (;;) {
1215     uae_u32 opcode = GET_OPCODE;
1216     (*cpufunctbl[opcode])(opcode);
1217     if (regs.spcflags) {
1218     if (do_specialties())
1219     return;
1220     }
1221 cebix 1.1 }
1222     }
1223    
1224     #define m68k_run1 m68k_run_1
1225    
1226     int in_m68k_go = 0;
1227    
1228     void m68k_go (int may_quit)
1229     {
1230     // m68k_go() must be reentrant for Execute68k() and Execute68kTrap() to work
1231     /*
1232     if (in_m68k_go || !may_quit) {
1233     write_log("Bug! m68k_go is not reentrant.\n");
1234     abort();
1235     }
1236     */
1237     in_m68k_go++;
1238     for (;;) {
1239     if (quit_program > 0) {
1240     if (quit_program == 1)
1241     break;
1242     quit_program = 0;
1243     m68k_reset ();
1244     }
1245     m68k_run1();
1246     }
1247     if (debugging) {
1248     uaecptr nextpc;
1249     m68k_dumpstate(&nextpc);
1250     exit(1);
1251     }
1252     in_m68k_go--;
1253     }
1254    
1255     static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1256     {
1257     uae_u32 opcode, val;
1258     struct instr *dp;
1259    
1260     opcode = get_iword_1(0);
1261     last_op_for_exception_3 = opcode;
1262     m68kpc_offset = 2;
1263    
1264     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1265     opcode = 0x4AFC;
1266     }
1267     dp = table68k + opcode;
1268    
1269     if (dp->suse) {
1270     if (!verify_ea (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, &val)) {
1271     Exception (3, 0);
1272     return;
1273     }
1274     }
1275     if (dp->duse) {
1276     if (!verify_ea (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, &val)) {
1277     Exception (3, 0);
1278     return;
1279     }
1280     }
1281     }
1282    
1283     void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt)
1284     {
1285     uaecptr newpc = 0;
1286     m68kpc_offset = addr - m68k_getpc ();
1287     while (cnt-- > 0) {
1288     char instrname[20],*ccpt;
1289     int opwords;
1290     uae_u32 opcode;
1291     struct mnemolookup *lookup;
1292     struct instr *dp;
1293     printf ("%08lx: ", m68k_getpc () + m68kpc_offset);
1294     for (opwords = 0; opwords < 5; opwords++){
1295     printf ("%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1296     }
1297     opcode = get_iword_1 (m68kpc_offset);
1298     m68kpc_offset += 2;
1299     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1300     opcode = 0x4AFC;
1301     }
1302     dp = table68k + opcode;
1303     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1304     ;
1305    
1306     strcpy (instrname, lookup->name);
1307     ccpt = strstr (instrname, "cc");
1308     if (ccpt != 0) {
1309     strncpy (ccpt, ccnames[dp->cc], 2);
1310     }
1311     printf ("%s", instrname);
1312     switch (dp->size){
1313     case sz_byte: printf (".B "); break;
1314     case sz_word: printf (".W "); break;
1315     case sz_long: printf (".L "); break;
1316     default: printf (" "); break;
1317     }
1318    
1319     if (dp->suse) {
1320     newpc = m68k_getpc () + m68kpc_offset;
1321     newpc += ShowEA (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, 0);
1322     }
1323     if (dp->suse && dp->duse)
1324     printf (",");
1325     if (dp->duse) {
1326     newpc = m68k_getpc () + m68kpc_offset;
1327     newpc += ShowEA (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, 0);
1328     }
1329     if (ccpt != 0) {
1330     if (cctrue(dp->cc))
1331     printf (" == %08lx (TRUE)", newpc);
1332     else
1333     printf (" == %08lx (FALSE)", newpc);
1334     } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1335     printf (" == %08lx", newpc);
1336     printf ("\n");
1337     }
1338     if (nextpc)
1339     *nextpc = m68k_getpc () + m68kpc_offset;
1340     }
1341    
1342     void m68k_dumpstate (uaecptr *nextpc)
1343     {
1344     int i;
1345     for (i = 0; i < 8; i++){
1346     printf ("D%d: %08lx ", i, m68k_dreg(regs, i));
1347     if ((i & 3) == 3) printf ("\n");
1348     }
1349     for (i = 0; i < 8; i++){
1350     printf ("A%d: %08lx ", i, m68k_areg(regs, i));
1351     if ((i & 3) == 3) printf ("\n");
1352     }
1353     if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1354     if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1355     if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1356     printf ("USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1357     regs.usp,regs.isp,regs.msp,regs.vbr);
1358     printf ("T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1359     regs.t1, regs.t0, regs.s, regs.m,
1360     GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1361     for (i = 0; i < 8; i++){
1362     printf ("FP%d: %g ", i, regs.fp[i]);
1363     if ((i & 3) == 3) printf ("\n");
1364     }
1365     printf ("N=%d Z=%d I=%d NAN=%d\n",
1366     (regs.fpsr & 0x8000000) != 0,
1367     (regs.fpsr & 0x4000000) != 0,
1368     (regs.fpsr & 0x2000000) != 0,
1369     (regs.fpsr & 0x1000000) != 0);
1370    
1371     m68k_disasm(m68k_getpc (), nextpc, 1);
1372     if (nextpc)
1373     printf ("next PC: %08lx\n", *nextpc);
1374     }