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root/cebix/BasiliskII/src/uae_cpu/newcpu.cpp
Revision: 1.3
Committed: 1999-10-28T16:00:28Z (25 years ago) by cebix
Branch: MAIN
Changes since 1.2: +2 -2 lines
Log Message:
- new SPARC optimizations from Gwenole

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * UAE - The Un*x Amiga Emulator
3     *
4     * MC68000 emulation
5     *
6     * (c) 1995 Bernd Schmidt
7     */
8    
9     #include <stdio.h>
10     #include <stdlib.h>
11     #include <string.h>
12    
13     #include "sysdeps.h"
14    
15     #include "cpu_emulation.h"
16     #include "main.h"
17     #include "emul_op.h"
18    
19     extern int intlev(void); // From baisilisk_glue.cpp
20    
21     #include "m68k.h"
22     #include "memory.h"
23     #include "readcpu.h"
24     #include "newcpu.h"
25     #include "compiler.h"
26    
27     int quit_program = 0;
28     int debugging = 0;
29     struct flag_struct regflags;
30    
31     /* Opcode of faulting instruction */
32     uae_u16 last_op_for_exception_3;
33     /* PC at fault time */
34     uaecptr last_addr_for_exception_3;
35     /* Address that generated the exception */
36     uaecptr last_fault_for_exception_3;
37    
38     int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
39     int imm8_table[] = { 8,1,2,3,4,5,6,7 };
40    
41     int movem_index1[256];
42     int movem_index2[256];
43     int movem_next[256];
44    
45     int fpp_movem_index1[256];
46     int fpp_movem_index2[256];
47     int fpp_movem_next[256];
48    
49     cpuop_func *cpufunctbl[65536];
50    
51     #define COUNT_INSTRS 0
52    
53     #if COUNT_INSTRS
54     static unsigned long int instrcount[65536];
55     static uae_u16 opcodenums[65536];
56    
57     static int compfn (const void *el1, const void *el2)
58     {
59     return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
60     }
61    
62     static char *icountfilename (void)
63     {
64     char *name = getenv ("INSNCOUNT");
65     if (name)
66     return name;
67     return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
68     }
69    
70     void dump_counts (void)
71     {
72     FILE *f = fopen (icountfilename (), "w");
73     unsigned long int total;
74     int i;
75    
76     write_log ("Writing instruction count file...\n");
77     for (i = 0; i < 65536; i++) {
78     opcodenums[i] = i;
79     total += instrcount[i];
80     }
81     qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
82    
83     fprintf (f, "Total: %lu\n", total);
84     for (i=0; i < 65536; i++) {
85     unsigned long int cnt = instrcount[opcodenums[i]];
86     struct instr *dp;
87     struct mnemolookup *lookup;
88     if (!cnt)
89     break;
90     dp = table68k + opcodenums[i];
91     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
92     ;
93     fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
94     }
95     fclose (f);
96     }
97     #else
98     void dump_counts (void)
99     {
100     }
101     #endif
102    
103     int broken_in;
104    
105     static __inline__ unsigned int cft_map (unsigned int f)
106     {
107     #ifndef HAVE_GET_WORD_UNSWAPPED
108     return f;
109     #else
110     return ((f >> 8) & 255) | ((f & 255) << 8);
111     #endif
112     }
113    
114     static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
115    
116     static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
117     {
118     op_illg (cft_map (opcode));
119     return 4;
120     }
121    
122     static void build_cpufunctbl (void)
123     {
124     int i;
125     unsigned long opcode;
126 cebix 1.2 int cpu_level = 0; // 68000 (default)
127     if (CPUType == 4)
128     cpu_level = 4; // 68040 with FPU
129     else {
130     if (FPUType)
131     cpu_level = 3; // 68020 with FPU
132     else if (CPUType >= 2)
133     cpu_level = 2; // 68020
134     else if (CPUType == 1)
135     cpu_level = 1;
136     }
137     struct cputbl *tbl = (
138     cpu_level == 4 ? op_smalltbl_0
139     : cpu_level == 3 ? op_smalltbl_1
140     : cpu_level == 2 ? op_smalltbl_2
141     : cpu_level == 1 ? op_smalltbl_3
142     : op_smalltbl_4);
143 cebix 1.1
144     for (opcode = 0; opcode < 65536; opcode++)
145     cpufunctbl[cft_map (opcode)] = op_illg_1;
146     for (i = 0; tbl[i].handler != NULL; i++) {
147     if (! tbl[i].specific)
148     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
149     }
150     for (opcode = 0; opcode < 65536; opcode++) {
151     cpuop_func *f;
152    
153     if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
154     continue;
155    
156     if (table68k[opcode].handler != -1) {
157     f = cpufunctbl[cft_map (table68k[opcode].handler)];
158     if (f == op_illg_1)
159     abort();
160     cpufunctbl[cft_map (opcode)] = f;
161     }
162     }
163     for (i = 0; tbl[i].handler != NULL; i++) {
164     if (tbl[i].specific)
165     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
166     }
167     }
168    
169     void init_m68k (void)
170     {
171     int i;
172    
173     for (i = 0 ; i < 256 ; i++) {
174     int j;
175     for (j = 0 ; j < 8 ; j++) {
176     if (i & (1 << j)) break;
177     }
178     movem_index1[i] = j;
179     movem_index2[i] = 7-j;
180     movem_next[i] = i & (~(1 << j));
181     }
182     for (i = 0 ; i < 256 ; i++) {
183     int j;
184     for (j = 7 ; j >= 0 ; j--) {
185     if (i & (1 << j)) break;
186     }
187     fpp_movem_index1[i] = j;
188     fpp_movem_index2[i] = 7-j;
189     fpp_movem_next[i] = i & (~(1 << j));
190     }
191     #if COUNT_INSTRS
192     {
193     FILE *f = fopen (icountfilename (), "r");
194     memset (instrcount, 0, sizeof instrcount);
195     if (f) {
196     uae_u32 opcode, count, total;
197     char name[20];
198     write_log ("Reading instruction count file...\n");
199     fscanf (f, "Total: %lu\n", &total);
200     while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
201     instrcount[opcode] = count;
202     }
203     fclose(f);
204     }
205     }
206     #endif
207     read_table68k ();
208     do_merges ();
209    
210     build_cpufunctbl ();
211     }
212    
213     struct regstruct regs, lastint_regs;
214     static struct regstruct regs_backup[16];
215     static int backup_pointer = 0;
216     static long int m68kpc_offset;
217     int lastint_no;
218    
219     #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
220     #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
221     #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
222    
223     uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf)
224     {
225     uae_u16 dp;
226     uae_s8 disp8;
227     uae_s16 disp16;
228     int r;
229     uae_u32 dispreg;
230     uaecptr addr;
231     uae_s32 offset = 0;
232     char buffer[80];
233    
234     switch (mode){
235     case Dreg:
236     sprintf (buffer,"D%d", reg);
237     break;
238     case Areg:
239     sprintf (buffer,"A%d", reg);
240     break;
241     case Aind:
242     sprintf (buffer,"(A%d)", reg);
243     break;
244     case Aipi:
245     sprintf (buffer,"(A%d)+", reg);
246     break;
247     case Apdi:
248     sprintf (buffer,"-(A%d)", reg);
249     break;
250     case Ad16:
251     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
252     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
253     sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
254     (long unsigned int)addr);
255     break;
256     case Ad8r:
257     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
258     disp8 = dp & 0xFF;
259     r = (dp & 0x7000) >> 12;
260     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
261     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
262     dispreg <<= (dp >> 9) & 3;
263    
264     if (dp & 0x100) {
265     uae_s32 outer = 0, disp = 0;
266     uae_s32 base = m68k_areg(regs,reg);
267     char name[10];
268     sprintf (name,"A%d, ",reg);
269     if (dp & 0x80) { base = 0; name[0] = 0; }
270     if (dp & 0x40) dispreg = 0;
271     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
272     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
273     base += disp;
274    
275     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
276     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
277    
278     if (!(dp & 4)) base += dispreg;
279     if (dp & 3) base = get_long (base);
280     if (dp & 4) base += dispreg;
281    
282     addr = base + outer;
283     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
284     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
285     1 << ((dp >> 9) & 3),
286     disp,outer,
287     (long unsigned int)addr);
288     } else {
289     addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
290     sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
291     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
292     1 << ((dp >> 9) & 3), disp8,
293     (long unsigned int)addr);
294     }
295     break;
296     case PC16:
297     addr = m68k_getpc () + m68kpc_offset;
298     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
299     addr += (uae_s16)disp16;
300     sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(long unsigned int)addr);
301     break;
302     case PC8r:
303     addr = m68k_getpc () + m68kpc_offset;
304     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
305     disp8 = dp & 0xFF;
306     r = (dp & 0x7000) >> 12;
307     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
308     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
309     dispreg <<= (dp >> 9) & 3;
310    
311     if (dp & 0x100) {
312     uae_s32 outer = 0,disp = 0;
313     uae_s32 base = addr;
314     char name[10];
315     sprintf (name,"PC, ");
316     if (dp & 0x80) { base = 0; name[0] = 0; }
317     if (dp & 0x40) dispreg = 0;
318     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
319     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
320     base += disp;
321    
322     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
323     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
324    
325     if (!(dp & 4)) base += dispreg;
326     if (dp & 3) base = get_long (base);
327     if (dp & 4) base += dispreg;
328    
329     addr = base + outer;
330     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
331     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
332     1 << ((dp >> 9) & 3),
333     disp,outer,
334     (long unsigned int)addr);
335     } else {
336     addr += (uae_s32)((uae_s8)disp8) + dispreg;
337     sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
338     (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
339     disp8, (long unsigned int)addr);
340     }
341     break;
342     case absw:
343     sprintf (buffer,"$%08lx", (long unsigned int)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
344     m68kpc_offset += 2;
345     break;
346     case absl:
347     sprintf (buffer,"$%08lx", (long unsigned int)get_ilong_1 (m68kpc_offset));
348     m68kpc_offset += 4;
349     break;
350     case imm:
351     switch (size){
352     case sz_byte:
353     sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
354     m68kpc_offset += 2;
355     break;
356     case sz_word:
357     sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
358     m68kpc_offset += 2;
359     break;
360     case sz_long:
361     sprintf (buffer,"#$%08lx", (long unsigned int)(get_ilong_1 (m68kpc_offset)));
362     m68kpc_offset += 4;
363     break;
364     default:
365     break;
366     }
367     break;
368     case imm0:
369     offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
370     m68kpc_offset += 2;
371     sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
372     break;
373     case imm1:
374     offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
375     m68kpc_offset += 2;
376     sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
377     break;
378     case imm2:
379     offset = (uae_s32)get_ilong_1 (m68kpc_offset);
380     m68kpc_offset += 4;
381     sprintf (buffer,"#$%08lx", (long unsigned int)offset);
382     break;
383     case immi:
384     offset = (uae_s32)(uae_s8)(reg & 0xff);
385     sprintf (buffer,"#$%08lx", (long unsigned int)offset);
386     break;
387     default:
388     break;
389     }
390     if (buf == 0)
391     printf ("%s", buffer);
392     else
393     strcat (buf, buffer);
394     return offset;
395     }
396    
397     /* The plan is that this will take over the job of exception 3 handling -
398     * the CPU emulation functions will just do a longjmp to m68k_go whenever
399     * they hit an odd address. */
400     static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
401     {
402     uae_u16 dp;
403     uae_s8 disp8;
404     uae_s16 disp16;
405     int r;
406     uae_u32 dispreg;
407     uaecptr addr;
408     uae_s32 offset = 0;
409    
410     switch (mode){
411     case Dreg:
412     *val = m68k_dreg (regs, reg);
413     return 1;
414     case Areg:
415     *val = m68k_areg (regs, reg);
416     return 1;
417    
418     case Aind:
419     case Aipi:
420     addr = m68k_areg (regs, reg);
421     break;
422     case Apdi:
423     addr = m68k_areg (regs, reg);
424     break;
425     case Ad16:
426     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
427     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
428     break;
429     case Ad8r:
430     addr = m68k_areg (regs, reg);
431     d8r_common:
432     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
433     disp8 = dp & 0xFF;
434     r = (dp & 0x7000) >> 12;
435     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
436     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
437     dispreg <<= (dp >> 9) & 3;
438    
439     if (dp & 0x100) {
440     uae_s32 outer = 0, disp = 0;
441     uae_s32 base = addr;
442     if (dp & 0x80) base = 0;
443     if (dp & 0x40) dispreg = 0;
444     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
445     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
446     base += disp;
447    
448     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
449     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
450    
451     if (!(dp & 4)) base += dispreg;
452     if (dp & 3) base = get_long (base);
453     if (dp & 4) base += dispreg;
454    
455     addr = base + outer;
456     } else {
457     addr += (uae_s32)((uae_s8)disp8) + dispreg;
458     }
459     break;
460     case PC16:
461     addr = m68k_getpc () + m68kpc_offset;
462     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
463     addr += (uae_s16)disp16;
464     break;
465     case PC8r:
466     addr = m68k_getpc () + m68kpc_offset;
467     goto d8r_common;
468     case absw:
469     addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
470     m68kpc_offset += 2;
471     break;
472     case absl:
473     addr = get_ilong_1 (m68kpc_offset);
474     m68kpc_offset += 4;
475     break;
476     case imm:
477     switch (size){
478     case sz_byte:
479     *val = get_iword_1 (m68kpc_offset) & 0xff;
480     m68kpc_offset += 2;
481     break;
482     case sz_word:
483     *val = get_iword_1 (m68kpc_offset) & 0xffff;
484     m68kpc_offset += 2;
485     break;
486     case sz_long:
487     *val = get_ilong_1 (m68kpc_offset);
488     m68kpc_offset += 4;
489     break;
490     default:
491     break;
492     }
493     return 1;
494     case imm0:
495     *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
496     m68kpc_offset += 2;
497     return 1;
498     case imm1:
499     *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
500     m68kpc_offset += 2;
501     return 1;
502     case imm2:
503     *val = get_ilong_1 (m68kpc_offset);
504     m68kpc_offset += 4;
505     return 1;
506     case immi:
507     *val = (uae_s32)(uae_s8)(reg & 0xff);
508     return 1;
509     default:
510     addr = 0;
511     break;
512     }
513     if ((addr & 1) == 0)
514     return 1;
515    
516     last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
517     last_fault_for_exception_3 = addr;
518     return 0;
519     }
520    
521     uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
522     {
523     int reg = (dp >> 12) & 15;
524     uae_s32 regd = regs.regs[reg];
525     if ((dp & 0x800) == 0)
526     regd = (uae_s32)(uae_s16)regd;
527     regd <<= (dp >> 9) & 3;
528     if (dp & 0x100) {
529     uae_s32 outer = 0;
530     if (dp & 0x80) base = 0;
531     if (dp & 0x40) regd = 0;
532    
533     if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
534     if ((dp & 0x30) == 0x30) base += next_ilong();
535    
536     if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
537     if ((dp & 0x3) == 0x3) outer = next_ilong();
538    
539     if ((dp & 0x4) == 0) base += regd;
540     if (dp & 0x3) base = get_long (base);
541     if (dp & 0x4) base += regd;
542    
543     return base + outer;
544     } else {
545     return base + (uae_s32)((uae_s8)dp) + regd;
546     }
547     }
548    
549     uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
550     {
551     int reg = (dp >> 12) & 15;
552     uae_s32 regd = regs.regs[reg];
553     #if 1
554     if ((dp & 0x800) == 0)
555     regd = (uae_s32)(uae_s16)regd;
556     return base + (uae_s8)dp + regd;
557     #else
558     /* Branch-free code... benchmark this again now that
559     * things are no longer inline. */
560     uae_s32 regd16;
561     uae_u32 mask;
562     mask = ((dp & 0x800) >> 11) - 1;
563     regd16 = (uae_s32)(uae_s16)regd;
564     regd16 &= mask;
565     mask = ~mask;
566     base += (uae_s8)dp;
567     regd &= mask;
568     regd |= regd16;
569     return base + regd;
570     #endif
571     }
572    
573     void MakeSR (void)
574     {
575     #if 0
576     assert((regs.t1 & 1) == regs.t1);
577     assert((regs.t0 & 1) == regs.t0);
578     assert((regs.s & 1) == regs.s);
579     assert((regs.m & 1) == regs.m);
580     assert((XFLG & 1) == XFLG);
581     assert((NFLG & 1) == NFLG);
582     assert((ZFLG & 1) == ZFLG);
583     assert((VFLG & 1) == VFLG);
584     assert((CFLG & 1) == CFLG);
585     #endif
586     regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
587     | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
588     | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
589     | GET_CFLG);
590     }
591    
592     void MakeFromSR (void)
593     {
594     int oldm = regs.m;
595     int olds = regs.s;
596    
597     regs.t1 = (regs.sr >> 15) & 1;
598     regs.t0 = (regs.sr >> 14) & 1;
599     regs.s = (regs.sr >> 13) & 1;
600     regs.m = (regs.sr >> 12) & 1;
601     regs.intmask = (regs.sr >> 8) & 7;
602     SET_XFLG ((regs.sr >> 4) & 1);
603     SET_NFLG ((regs.sr >> 3) & 1);
604     SET_ZFLG ((regs.sr >> 2) & 1);
605     SET_VFLG ((regs.sr >> 1) & 1);
606     SET_CFLG (regs.sr & 1);
607     if (CPUType >= 2) {
608     if (olds != regs.s) {
609     if (olds) {
610     if (oldm)
611     regs.msp = m68k_areg(regs, 7);
612     else
613     regs.isp = m68k_areg(regs, 7);
614     m68k_areg(regs, 7) = regs.usp;
615     } else {
616     regs.usp = m68k_areg(regs, 7);
617     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
618     }
619     } else if (olds && oldm != regs.m) {
620     if (oldm) {
621     regs.msp = m68k_areg(regs, 7);
622     m68k_areg(regs, 7) = regs.isp;
623     } else {
624     regs.isp = m68k_areg(regs, 7);
625     m68k_areg(regs, 7) = regs.msp;
626     }
627     }
628     } else {
629     if (olds != regs.s) {
630     if (olds) {
631     regs.isp = m68k_areg(regs, 7);
632     m68k_areg(regs, 7) = regs.usp;
633     } else {
634     regs.usp = m68k_areg(regs, 7);
635     m68k_areg(regs, 7) = regs.isp;
636     }
637     }
638     }
639    
640     regs.spcflags |= SPCFLAG_INT;
641     if (regs.t1 || regs.t0)
642     regs.spcflags |= SPCFLAG_TRACE;
643     else
644     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
645     }
646    
647     void Exception(int nr, uaecptr oldpc)
648     {
649     compiler_flush_jsr_stack();
650     MakeSR();
651     if (!regs.s) {
652     regs.usp = m68k_areg(regs, 7);
653     if (CPUType >= 2)
654     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
655     else
656     m68k_areg(regs, 7) = regs.isp;
657     regs.s = 1;
658     }
659     if (CPUType > 0) {
660     if (nr == 2 || nr == 3) {
661     int i;
662     /* @@@ this is probably wrong (?) */
663     for (i = 0 ; i < 12 ; i++) {
664     m68k_areg(regs, 7) -= 2;
665     put_word (m68k_areg(regs, 7), 0);
666     }
667     m68k_areg(regs, 7) -= 2;
668     put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
669     } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
670     m68k_areg(regs, 7) -= 4;
671     put_long (m68k_areg(regs, 7), oldpc);
672     m68k_areg(regs, 7) -= 2;
673     put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
674     } else if (regs.m && nr >= 24 && nr < 32) {
675     m68k_areg(regs, 7) -= 2;
676     put_word (m68k_areg(regs, 7), nr * 4);
677     m68k_areg(regs, 7) -= 4;
678     put_long (m68k_areg(regs, 7), m68k_getpc ());
679     m68k_areg(regs, 7) -= 2;
680     put_word (m68k_areg(regs, 7), regs.sr);
681     regs.sr |= (1 << 13);
682     regs.msp = m68k_areg(regs, 7);
683     m68k_areg(regs, 7) = regs.isp;
684     m68k_areg(regs, 7) -= 2;
685     put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
686     } else {
687     m68k_areg(regs, 7) -= 2;
688     put_word (m68k_areg(regs, 7), nr * 4);
689     }
690     } else {
691     if (nr == 2 || nr == 3) {
692     m68k_areg(regs, 7) -= 12;
693     /* ??????? */
694     if (nr == 3) {
695     put_long (m68k_areg(regs, 7), last_fault_for_exception_3);
696     put_word (m68k_areg(regs, 7)+4, last_op_for_exception_3);
697     put_long (m68k_areg(regs, 7)+8, last_addr_for_exception_3);
698     }
699     write_log ("Exception!\n");
700     goto kludge_me_do;
701     }
702     }
703     m68k_areg(regs, 7) -= 4;
704     put_long (m68k_areg(regs, 7), m68k_getpc ());
705     kludge_me_do:
706     m68k_areg(regs, 7) -= 2;
707     put_word (m68k_areg(regs, 7), regs.sr);
708     m68k_setpc (get_long (regs.vbr + 4*nr));
709     fill_prefetch_0 ();
710     regs.t1 = regs.t0 = regs.m = 0;
711     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
712     }
713    
714     static void Interrupt(int nr)
715     {
716     assert(nr < 8 && nr >= 0);
717     lastint_regs = regs;
718     lastint_no = nr;
719     Exception(nr+24, 0);
720    
721     regs.intmask = nr;
722     regs.spcflags |= SPCFLAG_INT;
723     }
724    
725 cebix 1.2 static int caar, cacr, tc, itt0, itt1, dtt0, dtt1;
726 cebix 1.1
727     void m68k_move2c (int regno, uae_u32 *regp)
728     {
729     if (CPUType == 1 && (regno & 0x7FF) > 1)
730     op_illg (0x4E7B);
731     else
732     switch (regno) {
733     case 0: regs.sfc = *regp & 7; break;
734     case 1: regs.dfc = *regp & 7; break;
735     case 2: cacr = *regp & 0x3; break; /* ignore C and CE */
736 cebix 1.2 case 3: tc = *regp & 0xc000; break;
737     case 4: itt0 = *regp & 0xffffe364; break;
738     case 5: itt1 = *regp & 0xffffe364; break;
739     case 6: dtt0 = *regp & 0xffffe364; break;
740     case 7: dtt1 = *regp & 0xffffe364; break;
741 cebix 1.1 case 0x800: regs.usp = *regp; break;
742     case 0x801: regs.vbr = *regp; break;
743     case 0x802: caar = *regp &0xfc; break;
744     case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
745     case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
746     default:
747     op_illg (0x4E7B);
748     break;
749     }
750     }
751    
752     void m68k_movec2 (int regno, uae_u32 *regp)
753     {
754     if (CPUType == 1 && (regno & 0x7FF) > 1)
755     op_illg (0x4E7A);
756     else
757     switch (regno) {
758     case 0: *regp = regs.sfc; break;
759     case 1: *regp = regs.dfc; break;
760     case 2: *regp = cacr; break;
761 cebix 1.2 case 3: *regp = tc; break;
762     case 4: *regp = itt0; break;
763     case 5: *regp = itt1; break;
764     case 6: *regp = dtt0; break;
765     case 7: *regp = dtt1; break;
766 cebix 1.1 case 0x800: *regp = regs.usp; break;
767     case 0x801: *regp = regs.vbr; break;
768     case 0x802: *regp = caar; break;
769     case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
770     case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
771     default:
772     op_illg (0x4E7A);
773     break;
774     }
775     }
776    
777     static __inline__ int
778     div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
779     {
780     uae_u32 q = 0, cbit = 0;
781     int i;
782    
783     if (div <= src_hi) {
784     return 1;
785     }
786     for (i = 0 ; i < 32 ; i++) {
787     cbit = src_hi & 0x80000000ul;
788     src_hi <<= 1;
789     if (src_lo & 0x80000000ul) src_hi++;
790     src_lo <<= 1;
791     q = q << 1;
792     if (cbit || div <= src_hi) {
793     q |= 1;
794     src_hi -= div;
795     }
796     }
797     *quot = q;
798     *rem = src_hi;
799     return 0;
800     }
801    
802     void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
803     {
804     #if defined(uae_s64)
805     if (src == 0) {
806     Exception (5, oldpc);
807     return;
808     }
809     if (extra & 0x800) {
810     /* signed variant */
811     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
812     uae_s64 quot, rem;
813    
814     if (extra & 0x400) {
815     a &= 0xffffffffu;
816     a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
817     }
818     rem = a % (uae_s64)(uae_s32)src;
819     quot = a / (uae_s64)(uae_s32)src;
820     if ((quot & UVAL64(0xffffffff80000000)) != 0
821     && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
822     {
823     SET_VFLG (1);
824     SET_NFLG (1);
825     SET_CFLG (0);
826     } else {
827     if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
828     SET_VFLG (0);
829     SET_CFLG (0);
830     SET_ZFLG (((uae_s32)quot) == 0);
831     SET_NFLG (((uae_s32)quot) < 0);
832     m68k_dreg(regs, extra & 7) = rem;
833     m68k_dreg(regs, (extra >> 12) & 7) = quot;
834     }
835     } else {
836     /* unsigned */
837     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
838     uae_u64 quot, rem;
839    
840     if (extra & 0x400) {
841     a &= 0xffffffffu;
842     a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
843     }
844     rem = a % (uae_u64)src;
845     quot = a / (uae_u64)src;
846     if (quot > 0xffffffffu) {
847     SET_VFLG (1);
848     SET_NFLG (1);
849     SET_CFLG (0);
850     } else {
851     SET_VFLG (0);
852     SET_CFLG (0);
853     SET_ZFLG (((uae_s32)quot) == 0);
854     SET_NFLG (((uae_s32)quot) < 0);
855     m68k_dreg(regs, extra & 7) = rem;
856     m68k_dreg(regs, (extra >> 12) & 7) = quot;
857     }
858     }
859     #else
860     if (src == 0) {
861     Exception (5, oldpc);
862     return;
863     }
864     if (extra & 0x800) {
865     /* signed variant */
866     uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
867     uae_s32 hi = lo < 0 ? -1 : 0;
868     uae_s32 save_high;
869     uae_u32 quot, rem;
870     uae_u32 sign;
871    
872     if (extra & 0x400) {
873     hi = (uae_s32)m68k_dreg(regs, extra & 7);
874     }
875     save_high = hi;
876     sign = (hi ^ src);
877     if (hi < 0) {
878     hi = ~hi;
879     lo = -lo;
880     if (lo == 0) hi++;
881     }
882     if ((uae_s32)src < 0) src = -src;
883     if (div_unsigned(hi, lo, src, &quot, &rem) ||
884     (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
885     SET_VFLG (1);
886     SET_NFLG (1);
887     SET_CFLG (0);
888     } else {
889     if (sign & 0x80000000) quot = -quot;
890     if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
891     SET_VFLG (0);
892     SET_CFLG (0);
893     SET_ZFLG (((uae_s32)quot) == 0);
894     SET_NFLG (((uae_s32)quot) < 0);
895     m68k_dreg(regs, extra & 7) = rem;
896     m68k_dreg(regs, (extra >> 12) & 7) = quot;
897     }
898     } else {
899     /* unsigned */
900     uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
901     uae_u32 hi = 0;
902     uae_u32 quot, rem;
903    
904     if (extra & 0x400) {
905     hi = (uae_u32)m68k_dreg(regs, extra & 7);
906     }
907     if (div_unsigned(hi, lo, src, &quot, &rem)) {
908     SET_VFLG (1);
909     SET_NFLG (1);
910     SET_CFLG (0);
911     } else {
912     SET_VFLG (0);
913     SET_CFLG (0);
914     SET_ZFLG (((uae_s32)quot) == 0);
915     SET_NFLG (((uae_s32)quot) < 0);
916     m68k_dreg(regs, extra & 7) = rem;
917     m68k_dreg(regs, (extra >> 12) & 7) = quot;
918     }
919     }
920     #endif
921     }
922    
923     static __inline__ void
924     mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
925     {
926     uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
927     uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
928     uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
929     uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
930     uae_u32 lo;
931    
932     lo = r0 + ((r1 << 16) & 0xffff0000ul);
933     if (lo < r0) r3++;
934     r0 = lo;
935     lo = r0 + ((r2 << 16) & 0xffff0000ul);
936     if (lo < r0) r3++;
937     r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
938     *dst_lo = lo;
939     *dst_hi = r3;
940     }
941    
942     void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
943     {
944     #if defined(uae_s64)
945     if (extra & 0x800) {
946     /* signed variant */
947     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
948    
949     a *= (uae_s64)(uae_s32)src;
950     SET_VFLG (0);
951     SET_CFLG (0);
952     SET_ZFLG (a == 0);
953     SET_NFLG (a < 0);
954     if (extra & 0x400)
955     m68k_dreg(regs, extra & 7) = a >> 32;
956     else if ((a & UVAL64(0xffffffff80000000)) != 0
957     && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
958     {
959     SET_VFLG (1);
960     }
961     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
962     } else {
963     /* unsigned */
964     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
965    
966     a *= (uae_u64)src;
967     SET_VFLG (0);
968     SET_CFLG (0);
969     SET_ZFLG (a == 0);
970     SET_NFLG (((uae_s64)a) < 0);
971     if (extra & 0x400)
972     m68k_dreg(regs, extra & 7) = a >> 32;
973     else if ((a & UVAL64(0xffffffff00000000)) != 0) {
974     SET_VFLG (1);
975     }
976     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
977     }
978     #else
979     if (extra & 0x800) {
980     /* signed variant */
981     uae_s32 src1,src2;
982     uae_u32 dst_lo,dst_hi;
983     uae_u32 sign;
984    
985     src1 = (uae_s32)src;
986     src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
987     sign = (src1 ^ src2);
988     if (src1 < 0) src1 = -src1;
989     if (src2 < 0) src2 = -src2;
990     mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
991     if (sign & 0x80000000) {
992     dst_hi = ~dst_hi;
993     dst_lo = -dst_lo;
994     if (dst_lo == 0) dst_hi++;
995     }
996     SET_VFLG (0);
997     SET_CFLG (0);
998     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
999     SET_NFLG (((uae_s32)dst_hi) < 0);
1000     if (extra & 0x400)
1001     m68k_dreg(regs, extra & 7) = dst_hi;
1002     else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1003     && ((dst_hi & 0xffffffff) != 0xffffffff
1004     || (dst_lo & 0x80000000) != 0x80000000))
1005     {
1006     SET_VFLG (1);
1007     }
1008     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1009     } else {
1010     /* unsigned */
1011     uae_u32 dst_lo,dst_hi;
1012    
1013     mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1014    
1015     SET_VFLG (0);
1016     SET_CFLG (0);
1017     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1018     SET_NFLG (((uae_s32)dst_hi) < 0);
1019     if (extra & 0x400)
1020     m68k_dreg(regs, extra & 7) = dst_hi;
1021     else if (dst_hi != 0) {
1022     SET_VFLG (1);
1023     }
1024     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1025     }
1026     #endif
1027     }
1028     static char* ccnames[] =
1029     { "T ","F ","HI","LS","CC","CS","NE","EQ",
1030     "VC","VS","PL","MI","GE","LT","GT","LE" };
1031    
1032     void m68k_reset (void)
1033     {
1034     m68k_areg (regs, 7) = 0x2000;
1035     m68k_setpc (ROMBaseMac + 0x2a);
1036     fill_prefetch_0 ();
1037     regs.kick_mask = 0xF80000;
1038     regs.s = 1;
1039     regs.m = 0;
1040     regs.stopped = 0;
1041     regs.t1 = 0;
1042     regs.t0 = 0;
1043     SET_ZFLG (0);
1044     SET_XFLG (0);
1045     SET_CFLG (0);
1046     SET_VFLG (0);
1047     SET_NFLG (0);
1048     regs.spcflags = 0;
1049     regs.intmask = 7;
1050     regs.vbr = regs.sfc = regs.dfc = 0;
1051     regs.fpcr = regs.fpsr = regs.fpiar = 0;
1052     }
1053    
1054     unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1055     {
1056     uaecptr pc = m68k_getpc ();
1057    
1058     compiler_flush_jsr_stack ();
1059    
1060     if ((opcode & 0xFF00) == 0x7100) {
1061     struct M68kRegisters r;
1062     int i;
1063    
1064     // Return from Execute68k()?
1065     if (opcode == M68K_EXEC_RETURN) {
1066     regs.spcflags |= SPCFLAG_BRK;
1067     quit_program = 1;
1068     return 4;
1069     }
1070    
1071     // Call EMUL_OP opcode
1072     for (i=0; i<8; i++) {
1073     r.d[i] = m68k_dreg(regs, i);
1074     r.a[i] = m68k_areg(regs, i);
1075     }
1076     MakeSR();
1077     r.sr = regs.sr;
1078     EmulOp(opcode, &r);
1079     for (i=0; i<8; i++) {
1080     m68k_dreg(regs, i) = r.d[i];
1081     m68k_areg(regs, i) = r.a[i];
1082     }
1083     regs.sr = r.sr;
1084     MakeFromSR();
1085     m68k_incpc(2);
1086     fill_prefetch_0 ();
1087     return 4;
1088     }
1089    
1090     if ((opcode & 0xF000) == 0xA000) {
1091     Exception(0xA,0);
1092     return 4;
1093     }
1094    
1095 cebix 1.3 write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1096    
1097 cebix 1.1 if ((opcode & 0xF000) == 0xF000) {
1098     Exception(0xB,0);
1099     return 4;
1100     }
1101    
1102     Exception (4,0);
1103     return 4;
1104     }
1105    
1106     void mmu_op(uae_u32 opcode, uae_u16 extra)
1107     {
1108     if ((extra & 0xB000) == 0) { /* PMOVE instruction */
1109    
1110     } else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */
1111     } else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */
1112     } else
1113     op_illg (opcode);
1114     }
1115    
1116     static int n_insns = 0, n_spcinsns = 0;
1117    
1118     static uaecptr last_trace_ad = 0;
1119    
1120     static void do_trace (void)
1121     {
1122     if (regs.t0) {
1123     uae_u16 opcode;
1124     /* should also include TRAP, CHK, SR modification FPcc */
1125     /* probably never used so why bother */
1126     /* We can afford this to be inefficient... */
1127     m68k_setpc (m68k_getpc ());
1128     fill_prefetch_0 ();
1129     opcode = get_word (regs.pc);
1130     if (opcode == 0x4e72 /* RTE */
1131     || opcode == 0x4e74 /* RTD */
1132     || opcode == 0x4e75 /* RTS */
1133     || opcode == 0x4e77 /* RTR */
1134     || opcode == 0x4e76 /* TRAPV */
1135     || (opcode & 0xffc0) == 0x4e80 /* JSR */
1136     || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1137     || (opcode & 0xff00) == 0x6100 /* BSR */
1138     || ((opcode & 0xf000) == 0x6000 /* Bcc */
1139     && cctrue((opcode >> 8) & 0xf))
1140     || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1141     && !cctrue((opcode >> 8) & 0xf)
1142     && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1143     {
1144     last_trace_ad = m68k_getpc ();
1145     regs.spcflags &= ~SPCFLAG_TRACE;
1146     regs.spcflags |= SPCFLAG_DOTRACE;
1147     }
1148     } else if (regs.t1) {
1149     last_trace_ad = m68k_getpc ();
1150     regs.spcflags &= ~SPCFLAG_TRACE;
1151     regs.spcflags |= SPCFLAG_DOTRACE;
1152     }
1153     }
1154    
1155    
1156     static int do_specialties (void)
1157     {
1158     /*n_spcinsns++;*/
1159     run_compiled_code();
1160     if (regs.spcflags & SPCFLAG_DOTRACE) {
1161     Exception (9,last_trace_ad);
1162     }
1163     while (regs.spcflags & SPCFLAG_STOP) {
1164     if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){
1165     int intr = intlev ();
1166     regs.spcflags &= ~(SPCFLAG_INT | SPCFLAG_DOINT);
1167     if (intr != -1 && intr > regs.intmask) {
1168     Interrupt (intr);
1169     regs.stopped = 0;
1170     regs.spcflags &= ~SPCFLAG_STOP;
1171     }
1172     }
1173     }
1174     if (regs.spcflags & SPCFLAG_TRACE)
1175     do_trace ();
1176    
1177     if (regs.spcflags & SPCFLAG_DOINT) {
1178     int intr = intlev ();
1179     regs.spcflags &= ~SPCFLAG_DOINT;
1180     if (intr != -1 && intr > regs.intmask) {
1181     Interrupt (intr);
1182     regs.stopped = 0;
1183     }
1184     }
1185     if (regs.spcflags & SPCFLAG_INT) {
1186     regs.spcflags &= ~SPCFLAG_INT;
1187     regs.spcflags |= SPCFLAG_DOINT;
1188     }
1189     if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1190     regs.spcflags &= ~(SPCFLAG_BRK | SPCFLAG_MODE_CHANGE);
1191     return 1;
1192     }
1193     return 0;
1194     }
1195    
1196     static void m68k_run_1 (void)
1197     {
1198     for (;;) {
1199     int cycles;
1200     uae_u32 opcode = GET_OPCODE;
1201     #if 0
1202     if (get_ilong (0) != do_get_mem_long (&regs.prefetch)) {
1203     debugging = 1;
1204     return;
1205     }
1206     #endif
1207     /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1208     /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1209     #if COUNT_INSTRS == 2
1210     if (table68k[cft_map (opcode)].handler != -1)
1211     instrcount[table68k[cft_map (opcode)].handler]++;
1212     #elif COUNT_INSTRS == 1
1213     instrcount[opcode]++;
1214     #endif
1215     #if defined(X86_ASSEMBLYxxx)
1216     __asm__ __volatile__("\tcall *%%ebx"
1217     : "=&a" (cycles) : "b" (cpufunctbl[opcode]), "0" (opcode)
1218     : "%edx", "%ecx",
1219     "%esi", "%edi", "%ebp", "memory", "cc");
1220     #else
1221     cycles = (*cpufunctbl[opcode])(opcode);
1222     #endif
1223     /*n_insns++;*/
1224     if (regs.spcflags) {
1225     if (do_specialties ())
1226     return;
1227     }
1228     }
1229     }
1230    
1231     #ifdef X86_ASSEMBLYxxx
1232     static __inline__ void m68k_run1 (void)
1233     {
1234     /* Work around compiler bug: GCC doesn't push %ebp in m68k_run_1. */
1235     __asm__ __volatile__ ("pushl %%ebp\n\tcall *%0\n\tpopl %%ebp" : : "r" (m68k_run_1) : "%eax", "%edx", "%ecx", "memory", "cc");
1236     }
1237     #else
1238     #define m68k_run1 m68k_run_1
1239     #endif
1240    
1241     int in_m68k_go = 0;
1242    
1243     void m68k_go (int may_quit)
1244     {
1245     // m68k_go() must be reentrant for Execute68k() and Execute68kTrap() to work
1246     /*
1247     if (in_m68k_go || !may_quit) {
1248     write_log("Bug! m68k_go is not reentrant.\n");
1249     abort();
1250     }
1251     */
1252     in_m68k_go++;
1253     for (;;) {
1254     if (quit_program > 0) {
1255     if (quit_program == 1)
1256     break;
1257     quit_program = 0;
1258     m68k_reset ();
1259     }
1260     m68k_run1();
1261     }
1262     if (debugging) {
1263     uaecptr nextpc;
1264     m68k_dumpstate(&nextpc);
1265     exit(1);
1266     }
1267     in_m68k_go--;
1268     }
1269    
1270     static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1271     {
1272     uae_u32 opcode, val;
1273     struct instr *dp;
1274    
1275     opcode = get_iword_1(0);
1276     last_op_for_exception_3 = opcode;
1277     m68kpc_offset = 2;
1278    
1279     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1280     opcode = 0x4AFC;
1281     }
1282     dp = table68k + opcode;
1283    
1284     if (dp->suse) {
1285     if (!verify_ea (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, &val)) {
1286     Exception (3, 0);
1287     return;
1288     }
1289     }
1290     if (dp->duse) {
1291     if (!verify_ea (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, &val)) {
1292     Exception (3, 0);
1293     return;
1294     }
1295     }
1296     }
1297    
1298     void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt)
1299     {
1300     uaecptr newpc = 0;
1301     m68kpc_offset = addr - m68k_getpc ();
1302     while (cnt-- > 0) {
1303     char instrname[20],*ccpt;
1304     int opwords;
1305     uae_u32 opcode;
1306     struct mnemolookup *lookup;
1307     struct instr *dp;
1308     printf ("%08lx: ", m68k_getpc () + m68kpc_offset);
1309     for (opwords = 0; opwords < 5; opwords++){
1310     printf ("%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1311     }
1312     opcode = get_iword_1 (m68kpc_offset);
1313     m68kpc_offset += 2;
1314     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1315     opcode = 0x4AFC;
1316     }
1317     dp = table68k + opcode;
1318     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1319     ;
1320    
1321     strcpy (instrname, lookup->name);
1322     ccpt = strstr (instrname, "cc");
1323     if (ccpt != 0) {
1324     strncpy (ccpt, ccnames[dp->cc], 2);
1325     }
1326     printf ("%s", instrname);
1327     switch (dp->size){
1328     case sz_byte: printf (".B "); break;
1329     case sz_word: printf (".W "); break;
1330     case sz_long: printf (".L "); break;
1331     default: printf (" "); break;
1332     }
1333    
1334     if (dp->suse) {
1335     newpc = m68k_getpc () + m68kpc_offset;
1336     newpc += ShowEA (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, 0);
1337     }
1338     if (dp->suse && dp->duse)
1339     printf (",");
1340     if (dp->duse) {
1341     newpc = m68k_getpc () + m68kpc_offset;
1342     newpc += ShowEA (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, 0);
1343     }
1344     if (ccpt != 0) {
1345     if (cctrue(dp->cc))
1346     printf (" == %08lx (TRUE)", newpc);
1347     else
1348     printf (" == %08lx (FALSE)", newpc);
1349     } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1350     printf (" == %08lx", newpc);
1351     printf ("\n");
1352     }
1353     if (nextpc)
1354     *nextpc = m68k_getpc () + m68kpc_offset;
1355     }
1356    
1357     void m68k_dumpstate (uaecptr *nextpc)
1358     {
1359     int i;
1360     for (i = 0; i < 8; i++){
1361     printf ("D%d: %08lx ", i, m68k_dreg(regs, i));
1362     if ((i & 3) == 3) printf ("\n");
1363     }
1364     for (i = 0; i < 8; i++){
1365     printf ("A%d: %08lx ", i, m68k_areg(regs, i));
1366     if ((i & 3) == 3) printf ("\n");
1367     }
1368     if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1369     if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1370     if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1371     printf ("USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1372     regs.usp,regs.isp,regs.msp,regs.vbr);
1373     printf ("T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1374     regs.t1, regs.t0, regs.s, regs.m,
1375     GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1376     for (i = 0; i < 8; i++){
1377     printf ("FP%d: %g ", i, regs.fp[i]);
1378     if ((i & 3) == 3) printf ("\n");
1379     }
1380     printf ("N=%d Z=%d I=%d NAN=%d\n",
1381     (regs.fpsr & 0x8000000) != 0,
1382     (regs.fpsr & 0x4000000) != 0,
1383     (regs.fpsr & 0x2000000) != 0,
1384     (regs.fpsr & 0x1000000) != 0);
1385    
1386     m68k_disasm(m68k_getpc (), nextpc, 1);
1387     if (nextpc)
1388     printf ("next PC: %08lx\n", *nextpc);
1389     }