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root/cebix/BasiliskII/src/uae_cpu/newcpu.cpp
Revision: 1.15
Committed: 2002-09-13T12:50:56Z (22 years, 1 month ago) by gbeauche
Branch: MAIN
Changes since 1.14: +6 -26 lines
Log Message:
Updates for new FPU core architecture

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * UAE - The Un*x Amiga Emulator
3     *
4     * MC68000 emulation
5     *
6     * (c) 1995 Bernd Schmidt
7     */
8    
9     #include <stdio.h>
10     #include <stdlib.h>
11     #include <string.h>
12    
13     #include "sysdeps.h"
14    
15     #include "cpu_emulation.h"
16     #include "main.h"
17     #include "emul_op.h"
18    
19     extern int intlev(void); // From baisilisk_glue.cpp
20    
21     #include "m68k.h"
22     #include "memory.h"
23     #include "readcpu.h"
24     #include "newcpu.h"
25 gbeauche 1.15 #include "fpu/fpu.h"
26 cebix 1.1
27 gbeauche 1.14 #if defined(ENABLE_EXCLUSIVE_SPCFLAGS) && !defined(HAVE_HARDWARE_LOCKS)
28     B2_mutex *spcflags_lock = NULL;
29 gbeauche 1.13 #endif
30    
31 gbeauche 1.10 #if ENABLE_MON
32     #include "mon.h"
33     #include "mon_disass.h"
34     #endif
35    
36 cebix 1.1 int quit_program = 0;
37 gbeauche 1.13 const int debugging = 0;
38 cebix 1.1 struct flag_struct regflags;
39    
40     /* Opcode of faulting instruction */
41     uae_u16 last_op_for_exception_3;
42     /* PC at fault time */
43     uaecptr last_addr_for_exception_3;
44     /* Address that generated the exception */
45     uaecptr last_fault_for_exception_3;
46    
47     int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
48     int imm8_table[] = { 8,1,2,3,4,5,6,7 };
49    
50     int movem_index1[256];
51     int movem_index2[256];
52     int movem_next[256];
53    
54     cpuop_func *cpufunctbl[65536];
55    
56 gbeauche 1.10 #define FLIGHT_RECORDER 0
57    
58     #if FLIGHT_RECORDER
59     struct rec_step {
60     uae_u32 d[8];
61     uae_u32 a[8];
62     uae_u32 pc;
63     };
64    
65     const int LOG_SIZE = 8192;
66     static rec_step log[LOG_SIZE];
67     static int log_ptr = -1; // First time initialization
68    
69     static const char *log_filename(void)
70     {
71     const char *name = getenv("M68K_LOG_FILE");
72     return name ? name : "log.68k";
73     }
74    
75     static void record_step(uaecptr pc)
76     {
77     for (int i = 0; i < 8; i++) {
78     log[log_ptr].d[i] = m68k_dreg(regs, i);
79     log[log_ptr].a[i] = m68k_areg(regs, i);
80     }
81     log[log_ptr].pc = pc;
82     log_ptr = (log_ptr + 1) % LOG_SIZE;
83     }
84    
85     static void dump_log(void)
86     {
87     FILE *f = fopen(log_filename(), "w");
88     if (f == NULL)
89     return;
90     for (int i = 0; i < LOG_SIZE; i++) {
91     int j = (i + log_ptr) % LOG_SIZE;
92     fprintf(f, "pc %08x\n", log[j].pc);
93     fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]);
94     fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]);
95     fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]);
96     fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]);
97     #if ENABLE_MON
98     disass_68k(f, log[j].pc);
99     #endif
100     }
101 gbeauche 1.11 fclose(f);
102 gbeauche 1.10 }
103     #endif
104    
105 cebix 1.1 #define COUNT_INSTRS 0
106    
107     #if COUNT_INSTRS
108     static unsigned long int instrcount[65536];
109     static uae_u16 opcodenums[65536];
110    
111     static int compfn (const void *el1, const void *el2)
112     {
113     return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
114     }
115    
116     static char *icountfilename (void)
117     {
118     char *name = getenv ("INSNCOUNT");
119     if (name)
120     return name;
121     return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
122     }
123    
124     void dump_counts (void)
125     {
126     FILE *f = fopen (icountfilename (), "w");
127     unsigned long int total;
128     int i;
129    
130     write_log ("Writing instruction count file...\n");
131     for (i = 0; i < 65536; i++) {
132     opcodenums[i] = i;
133     total += instrcount[i];
134     }
135     qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
136    
137     fprintf (f, "Total: %lu\n", total);
138     for (i=0; i < 65536; i++) {
139     unsigned long int cnt = instrcount[opcodenums[i]];
140     struct instr *dp;
141     struct mnemolookup *lookup;
142     if (!cnt)
143     break;
144     dp = table68k + opcodenums[i];
145     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
146     ;
147     fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
148     }
149     fclose (f);
150     }
151     #else
152     void dump_counts (void)
153     {
154     }
155     #endif
156    
157     int broken_in;
158    
159     static __inline__ unsigned int cft_map (unsigned int f)
160     {
161     #ifndef HAVE_GET_WORD_UNSWAPPED
162     return f;
163     #else
164     return ((f >> 8) & 255) | ((f & 255) << 8);
165     #endif
166     }
167    
168 gbeauche 1.13 cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
169 cebix 1.1
170 gbeauche 1.13 cpuop_rettype REGPARAM2 op_illg_1 (uae_u32 opcode)
171 cebix 1.1 {
172 gbeauche 1.13 cpuop_return( op_illg (cft_map (opcode)) );
173 cebix 1.1 }
174    
175     static void build_cpufunctbl (void)
176     {
177     int i;
178     unsigned long opcode;
179 cebix 1.2 int cpu_level = 0; // 68000 (default)
180     if (CPUType == 4)
181     cpu_level = 4; // 68040 with FPU
182     else {
183     if (FPUType)
184     cpu_level = 3; // 68020 with FPU
185     else if (CPUType >= 2)
186     cpu_level = 2; // 68020
187     else if (CPUType == 1)
188     cpu_level = 1;
189     }
190     struct cputbl *tbl = (
191 gbeauche 1.13 cpu_level == 4 ? op_smalltbl_0_ff
192     : cpu_level == 3 ? op_smalltbl_1_ff
193     : cpu_level == 2 ? op_smalltbl_2_ff
194     : cpu_level == 1 ? op_smalltbl_3_ff
195     : op_smalltbl_4_ff);
196 cebix 1.1
197     for (opcode = 0; opcode < 65536; opcode++)
198     cpufunctbl[cft_map (opcode)] = op_illg_1;
199     for (i = 0; tbl[i].handler != NULL; i++) {
200     if (! tbl[i].specific)
201     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
202     }
203     for (opcode = 0; opcode < 65536; opcode++) {
204     cpuop_func *f;
205    
206     if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
207     continue;
208    
209     if (table68k[opcode].handler != -1) {
210     f = cpufunctbl[cft_map (table68k[opcode].handler)];
211     if (f == op_illg_1)
212     abort();
213     cpufunctbl[cft_map (opcode)] = f;
214     }
215     }
216     for (i = 0; tbl[i].handler != NULL; i++) {
217     if (tbl[i].specific)
218     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
219     }
220     }
221    
222     void init_m68k (void)
223     {
224     int i;
225    
226     for (i = 0 ; i < 256 ; i++) {
227     int j;
228     for (j = 0 ; j < 8 ; j++) {
229     if (i & (1 << j)) break;
230     }
231     movem_index1[i] = j;
232     movem_index2[i] = 7-j;
233     movem_next[i] = i & (~(1 << j));
234     }
235     #if COUNT_INSTRS
236     {
237     FILE *f = fopen (icountfilename (), "r");
238     memset (instrcount, 0, sizeof instrcount);
239     if (f) {
240     uae_u32 opcode, count, total;
241     char name[20];
242     write_log ("Reading instruction count file...\n");
243     fscanf (f, "Total: %lu\n", &total);
244     while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
245     instrcount[opcode] = count;
246     }
247     fclose(f);
248     }
249     }
250     #endif
251     read_table68k ();
252     do_merges ();
253    
254     build_cpufunctbl ();
255 gbeauche 1.14
256     #if defined(ENABLE_EXCLUSIVE_SPCFLAGS) && !defined(HAVE_HARDWARE_LOCKS)
257     spcflags_lock = B2_create_mutex();
258     #endif
259 gbeauche 1.15 fpu_init(CPUType == 4);
260 gbeauche 1.6 }
261    
262     void exit_m68k (void)
263     {
264     fpu_exit ();
265 gbeauche 1.14 #if defined(ENABLE_EXCLUSIVE_SPCFLAGS) && !defined(HAVE_HARDWARE_LOCKS)
266     B2_delete_mutex(spcflags_lock);
267     #endif
268 cebix 1.1 }
269    
270     struct regstruct regs, lastint_regs;
271     static struct regstruct regs_backup[16];
272     static int backup_pointer = 0;
273     static long int m68kpc_offset;
274     int lastint_no;
275    
276 gbeauche 1.7 #if REAL_ADDRESSING || DIRECT_ADDRESSING
277     #define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1)
278     #define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o))
279     #define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o))
280     #else
281 cebix 1.1 #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
282     #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
283     #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
284 gbeauche 1.7 #endif
285 cebix 1.1
286     uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf)
287     {
288     uae_u16 dp;
289     uae_s8 disp8;
290     uae_s16 disp16;
291     int r;
292     uae_u32 dispreg;
293     uaecptr addr;
294     uae_s32 offset = 0;
295     char buffer[80];
296    
297     switch (mode){
298     case Dreg:
299     sprintf (buffer,"D%d", reg);
300     break;
301     case Areg:
302     sprintf (buffer,"A%d", reg);
303     break;
304     case Aind:
305     sprintf (buffer,"(A%d)", reg);
306     break;
307     case Aipi:
308     sprintf (buffer,"(A%d)+", reg);
309     break;
310     case Apdi:
311     sprintf (buffer,"-(A%d)", reg);
312     break;
313     case Ad16:
314     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
315     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
316     sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
317 cebix 1.5 (unsigned long)addr);
318 cebix 1.1 break;
319     case Ad8r:
320     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
321     disp8 = dp & 0xFF;
322     r = (dp & 0x7000) >> 12;
323     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
324     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
325     dispreg <<= (dp >> 9) & 3;
326    
327     if (dp & 0x100) {
328     uae_s32 outer = 0, disp = 0;
329     uae_s32 base = m68k_areg(regs,reg);
330     char name[10];
331     sprintf (name,"A%d, ",reg);
332     if (dp & 0x80) { base = 0; name[0] = 0; }
333     if (dp & 0x40) dispreg = 0;
334     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
335     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
336     base += disp;
337    
338     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
339     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
340    
341     if (!(dp & 4)) base += dispreg;
342     if (dp & 3) base = get_long (base);
343     if (dp & 4) base += dispreg;
344    
345     addr = base + outer;
346     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
347     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
348     1 << ((dp >> 9) & 3),
349     disp,outer,
350 cebix 1.5 (unsigned long)addr);
351 cebix 1.1 } else {
352     addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
353     sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
354     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
355     1 << ((dp >> 9) & 3), disp8,
356 cebix 1.5 (unsigned long)addr);
357 cebix 1.1 }
358     break;
359     case PC16:
360     addr = m68k_getpc () + m68kpc_offset;
361     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
362     addr += (uae_s16)disp16;
363 cebix 1.5 sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
364 cebix 1.1 break;
365     case PC8r:
366     addr = m68k_getpc () + m68kpc_offset;
367     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
368     disp8 = dp & 0xFF;
369     r = (dp & 0x7000) >> 12;
370     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
371     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
372     dispreg <<= (dp >> 9) & 3;
373    
374     if (dp & 0x100) {
375     uae_s32 outer = 0,disp = 0;
376     uae_s32 base = addr;
377     char name[10];
378     sprintf (name,"PC, ");
379     if (dp & 0x80) { base = 0; name[0] = 0; }
380     if (dp & 0x40) dispreg = 0;
381     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
382     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
383     base += disp;
384    
385     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
386     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
387    
388     if (!(dp & 4)) base += dispreg;
389     if (dp & 3) base = get_long (base);
390     if (dp & 4) base += dispreg;
391    
392     addr = base + outer;
393     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
394     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
395     1 << ((dp >> 9) & 3),
396     disp,outer,
397 cebix 1.5 (unsigned long)addr);
398 cebix 1.1 } else {
399     addr += (uae_s32)((uae_s8)disp8) + dispreg;
400     sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
401     (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
402 cebix 1.5 disp8, (unsigned long)addr);
403 cebix 1.1 }
404     break;
405     case absw:
406 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
407 cebix 1.1 m68kpc_offset += 2;
408     break;
409     case absl:
410 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
411 cebix 1.1 m68kpc_offset += 4;
412     break;
413     case imm:
414     switch (size){
415     case sz_byte:
416     sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
417     m68kpc_offset += 2;
418     break;
419     case sz_word:
420     sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
421     m68kpc_offset += 2;
422     break;
423     case sz_long:
424 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
425 cebix 1.1 m68kpc_offset += 4;
426     break;
427     default:
428     break;
429     }
430     break;
431     case imm0:
432     offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
433     m68kpc_offset += 2;
434     sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
435     break;
436     case imm1:
437     offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
438     m68kpc_offset += 2;
439     sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
440     break;
441     case imm2:
442     offset = (uae_s32)get_ilong_1 (m68kpc_offset);
443     m68kpc_offset += 4;
444 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
445 cebix 1.1 break;
446     case immi:
447     offset = (uae_s32)(uae_s8)(reg & 0xff);
448 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
449 cebix 1.1 break;
450     default:
451     break;
452     }
453     if (buf == 0)
454     printf ("%s", buffer);
455     else
456     strcat (buf, buffer);
457     return offset;
458     }
459    
460     /* The plan is that this will take over the job of exception 3 handling -
461     * the CPU emulation functions will just do a longjmp to m68k_go whenever
462     * they hit an odd address. */
463     static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
464     {
465     uae_u16 dp;
466     uae_s8 disp8;
467     uae_s16 disp16;
468     int r;
469     uae_u32 dispreg;
470     uaecptr addr;
471     uae_s32 offset = 0;
472    
473     switch (mode){
474     case Dreg:
475     *val = m68k_dreg (regs, reg);
476     return 1;
477     case Areg:
478     *val = m68k_areg (regs, reg);
479     return 1;
480    
481     case Aind:
482     case Aipi:
483     addr = m68k_areg (regs, reg);
484     break;
485     case Apdi:
486     addr = m68k_areg (regs, reg);
487     break;
488     case Ad16:
489     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
490     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
491     break;
492     case Ad8r:
493     addr = m68k_areg (regs, reg);
494     d8r_common:
495     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
496     disp8 = dp & 0xFF;
497     r = (dp & 0x7000) >> 12;
498     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
499     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
500     dispreg <<= (dp >> 9) & 3;
501    
502     if (dp & 0x100) {
503     uae_s32 outer = 0, disp = 0;
504     uae_s32 base = addr;
505     if (dp & 0x80) base = 0;
506     if (dp & 0x40) dispreg = 0;
507     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
508     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
509     base += disp;
510    
511     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
512     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
513    
514     if (!(dp & 4)) base += dispreg;
515     if (dp & 3) base = get_long (base);
516     if (dp & 4) base += dispreg;
517    
518     addr = base + outer;
519     } else {
520     addr += (uae_s32)((uae_s8)disp8) + dispreg;
521     }
522     break;
523     case PC16:
524     addr = m68k_getpc () + m68kpc_offset;
525     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
526     addr += (uae_s16)disp16;
527     break;
528     case PC8r:
529     addr = m68k_getpc () + m68kpc_offset;
530     goto d8r_common;
531     case absw:
532     addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
533     m68kpc_offset += 2;
534     break;
535     case absl:
536     addr = get_ilong_1 (m68kpc_offset);
537     m68kpc_offset += 4;
538     break;
539     case imm:
540     switch (size){
541     case sz_byte:
542     *val = get_iword_1 (m68kpc_offset) & 0xff;
543     m68kpc_offset += 2;
544     break;
545     case sz_word:
546     *val = get_iword_1 (m68kpc_offset) & 0xffff;
547     m68kpc_offset += 2;
548     break;
549     case sz_long:
550     *val = get_ilong_1 (m68kpc_offset);
551     m68kpc_offset += 4;
552     break;
553     default:
554     break;
555     }
556     return 1;
557     case imm0:
558     *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
559     m68kpc_offset += 2;
560     return 1;
561     case imm1:
562     *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
563     m68kpc_offset += 2;
564     return 1;
565     case imm2:
566     *val = get_ilong_1 (m68kpc_offset);
567     m68kpc_offset += 4;
568     return 1;
569     case immi:
570     *val = (uae_s32)(uae_s8)(reg & 0xff);
571     return 1;
572     default:
573     addr = 0;
574     break;
575     }
576     if ((addr & 1) == 0)
577     return 1;
578    
579     last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
580     last_fault_for_exception_3 = addr;
581     return 0;
582     }
583    
584     uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
585     {
586     int reg = (dp >> 12) & 15;
587     uae_s32 regd = regs.regs[reg];
588     if ((dp & 0x800) == 0)
589     regd = (uae_s32)(uae_s16)regd;
590     regd <<= (dp >> 9) & 3;
591     if (dp & 0x100) {
592     uae_s32 outer = 0;
593     if (dp & 0x80) base = 0;
594     if (dp & 0x40) regd = 0;
595    
596     if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
597     if ((dp & 0x30) == 0x30) base += next_ilong();
598    
599     if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
600     if ((dp & 0x3) == 0x3) outer = next_ilong();
601    
602     if ((dp & 0x4) == 0) base += regd;
603     if (dp & 0x3) base = get_long (base);
604     if (dp & 0x4) base += regd;
605    
606     return base + outer;
607     } else {
608     return base + (uae_s32)((uae_s8)dp) + regd;
609     }
610     }
611    
612     uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
613     {
614     int reg = (dp >> 12) & 15;
615     uae_s32 regd = regs.regs[reg];
616     #if 1
617     if ((dp & 0x800) == 0)
618     regd = (uae_s32)(uae_s16)regd;
619     return base + (uae_s8)dp + regd;
620     #else
621     /* Branch-free code... benchmark this again now that
622     * things are no longer inline. */
623     uae_s32 regd16;
624     uae_u32 mask;
625     mask = ((dp & 0x800) >> 11) - 1;
626     regd16 = (uae_s32)(uae_s16)regd;
627     regd16 &= mask;
628     mask = ~mask;
629     base += (uae_s8)dp;
630     regd &= mask;
631     regd |= regd16;
632     return base + regd;
633     #endif
634     }
635    
636     void MakeSR (void)
637     {
638     #if 0
639     assert((regs.t1 & 1) == regs.t1);
640     assert((regs.t0 & 1) == regs.t0);
641     assert((regs.s & 1) == regs.s);
642     assert((regs.m & 1) == regs.m);
643     assert((XFLG & 1) == XFLG);
644     assert((NFLG & 1) == NFLG);
645     assert((ZFLG & 1) == ZFLG);
646     assert((VFLG & 1) == VFLG);
647     assert((CFLG & 1) == CFLG);
648     #endif
649     regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
650     | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
651     | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
652     | GET_CFLG);
653     }
654    
655     void MakeFromSR (void)
656     {
657     int oldm = regs.m;
658     int olds = regs.s;
659    
660     regs.t1 = (regs.sr >> 15) & 1;
661     regs.t0 = (regs.sr >> 14) & 1;
662     regs.s = (regs.sr >> 13) & 1;
663     regs.m = (regs.sr >> 12) & 1;
664     regs.intmask = (regs.sr >> 8) & 7;
665     SET_XFLG ((regs.sr >> 4) & 1);
666     SET_NFLG ((regs.sr >> 3) & 1);
667     SET_ZFLG ((regs.sr >> 2) & 1);
668     SET_VFLG ((regs.sr >> 1) & 1);
669     SET_CFLG (regs.sr & 1);
670     if (CPUType >= 2) {
671     if (olds != regs.s) {
672     if (olds) {
673     if (oldm)
674     regs.msp = m68k_areg(regs, 7);
675     else
676     regs.isp = m68k_areg(regs, 7);
677     m68k_areg(regs, 7) = regs.usp;
678     } else {
679     regs.usp = m68k_areg(regs, 7);
680     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
681     }
682     } else if (olds && oldm != regs.m) {
683     if (oldm) {
684     regs.msp = m68k_areg(regs, 7);
685     m68k_areg(regs, 7) = regs.isp;
686     } else {
687     regs.isp = m68k_areg(regs, 7);
688     m68k_areg(regs, 7) = regs.msp;
689     }
690     }
691     } else {
692     if (olds != regs.s) {
693     if (olds) {
694     regs.isp = m68k_areg(regs, 7);
695     m68k_areg(regs, 7) = regs.usp;
696     } else {
697     regs.usp = m68k_areg(regs, 7);
698     m68k_areg(regs, 7) = regs.isp;
699     }
700     }
701     }
702    
703 gbeauche 1.13 SPCFLAGS_SET( SPCFLAG_INT );
704 cebix 1.1 if (regs.t1 || regs.t0)
705 gbeauche 1.13 SPCFLAGS_SET( SPCFLAG_TRACE );
706 cebix 1.1 else
707 gbeauche 1.12 /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
708     SR-modifying instructions (including STOP). */
709 gbeauche 1.13 SPCFLAGS_CLEAR( SPCFLAG_TRACE );
710 cebix 1.1 }
711    
712     void Exception(int nr, uaecptr oldpc)
713     {
714 gbeauche 1.9 uae_u32 currpc = m68k_getpc ();
715 cebix 1.1 MakeSR();
716     if (!regs.s) {
717     regs.usp = m68k_areg(regs, 7);
718     if (CPUType >= 2)
719     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
720     else
721     m68k_areg(regs, 7) = regs.isp;
722     regs.s = 1;
723     }
724     if (CPUType > 0) {
725     if (nr == 2 || nr == 3) {
726     int i;
727     /* @@@ this is probably wrong (?) */
728     for (i = 0 ; i < 12 ; i++) {
729     m68k_areg(regs, 7) -= 2;
730     put_word (m68k_areg(regs, 7), 0);
731     }
732     m68k_areg(regs, 7) -= 2;
733     put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
734     } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
735     m68k_areg(regs, 7) -= 4;
736     put_long (m68k_areg(regs, 7), oldpc);
737     m68k_areg(regs, 7) -= 2;
738     put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
739     } else if (regs.m && nr >= 24 && nr < 32) {
740     m68k_areg(regs, 7) -= 2;
741     put_word (m68k_areg(regs, 7), nr * 4);
742     m68k_areg(regs, 7) -= 4;
743 gbeauche 1.9 put_long (m68k_areg(regs, 7), currpc);
744 cebix 1.1 m68k_areg(regs, 7) -= 2;
745     put_word (m68k_areg(regs, 7), regs.sr);
746     regs.sr |= (1 << 13);
747     regs.msp = m68k_areg(regs, 7);
748     m68k_areg(regs, 7) = regs.isp;
749     m68k_areg(regs, 7) -= 2;
750     put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
751     } else {
752     m68k_areg(regs, 7) -= 2;
753     put_word (m68k_areg(regs, 7), nr * 4);
754     }
755     } else {
756     if (nr == 2 || nr == 3) {
757     m68k_areg(regs, 7) -= 12;
758     /* ??????? */
759     if (nr == 3) {
760     put_long (m68k_areg(regs, 7), last_fault_for_exception_3);
761     put_word (m68k_areg(regs, 7)+4, last_op_for_exception_3);
762     put_long (m68k_areg(regs, 7)+8, last_addr_for_exception_3);
763     }
764     write_log ("Exception!\n");
765     goto kludge_me_do;
766     }
767     }
768     m68k_areg(regs, 7) -= 4;
769 gbeauche 1.9 put_long (m68k_areg(regs, 7), currpc);
770 cebix 1.1 kludge_me_do:
771     m68k_areg(regs, 7) -= 2;
772     put_word (m68k_areg(regs, 7), regs.sr);
773     m68k_setpc (get_long (regs.vbr + 4*nr));
774 gbeauche 1.13 SPCFLAGS_SET( SPCFLAG_JIT_END_COMPILE );
775 cebix 1.1 fill_prefetch_0 ();
776     regs.t1 = regs.t0 = regs.m = 0;
777 gbeauche 1.13 SPCFLAGS_CLEAR( SPCFLAG_TRACE | SPCFLAG_DOTRACE );
778 cebix 1.1 }
779    
780     static void Interrupt(int nr)
781     {
782     assert(nr < 8 && nr >= 0);
783     lastint_regs = regs;
784     lastint_no = nr;
785     Exception(nr+24, 0);
786    
787     regs.intmask = nr;
788 gbeauche 1.13 SPCFLAGS_SET( SPCFLAG_INT );
789 cebix 1.1 }
790    
791 gbeauche 1.12 static int caar, cacr, tc, itt0, itt1, dtt0, dtt1, mmusr, urp, srp;
792 cebix 1.1
793 gbeauche 1.9 int m68k_move2c (int regno, uae_u32 *regp)
794 cebix 1.1 {
795 gbeauche 1.9 if ((CPUType == 1 && (regno & 0x7FF) > 1)
796 gbeauche 1.12 || (CPUType < 4 && (regno & 0x7FF) > 2)
797     || (CPUType == 4 && regno == 0x802))
798 gbeauche 1.9 {
799 cebix 1.1 op_illg (0x4E7B);
800 gbeauche 1.9 return 0;
801     } else {
802 cebix 1.1 switch (regno) {
803     case 0: regs.sfc = *regp & 7; break;
804     case 1: regs.dfc = *regp & 7; break;
805 gbeauche 1.9 case 2: cacr = *regp & (CPUType < 4 ? 0x3 : 0x80008000); break;
806 cebix 1.2 case 3: tc = *regp & 0xc000; break;
807     case 4: itt0 = *regp & 0xffffe364; break;
808     case 5: itt1 = *regp & 0xffffe364; break;
809     case 6: dtt0 = *regp & 0xffffe364; break;
810     case 7: dtt1 = *regp & 0xffffe364; break;
811 cebix 1.1 case 0x800: regs.usp = *regp; break;
812     case 0x801: regs.vbr = *regp; break;
813     case 0x802: caar = *regp &0xfc; break;
814     case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
815     case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
816 gbeauche 1.12 case 0x805: mmusr = *regp; break;
817     case 0x806: urp = *regp; break;
818     case 0x807: srp = *regp; break;
819 cebix 1.1 default:
820     op_illg (0x4E7B);
821 gbeauche 1.9 return 0;
822 cebix 1.1 }
823 gbeauche 1.9 }
824     return 1;
825 cebix 1.1 }
826    
827 gbeauche 1.9 int m68k_movec2 (int regno, uae_u32 *regp)
828 cebix 1.1 {
829 gbeauche 1.9 if ((CPUType == 1 && (regno & 0x7FF) > 1)
830 gbeauche 1.12 || (CPUType < 4 && (regno & 0x7FF) > 2)
831     || (CPUType == 4 && regno == 0x802))
832 gbeauche 1.9 {
833 cebix 1.1 op_illg (0x4E7A);
834 gbeauche 1.9 return 0;
835     } else {
836 cebix 1.1 switch (regno) {
837     case 0: *regp = regs.sfc; break;
838     case 1: *regp = regs.dfc; break;
839     case 2: *regp = cacr; break;
840 cebix 1.2 case 3: *regp = tc; break;
841     case 4: *regp = itt0; break;
842     case 5: *regp = itt1; break;
843     case 6: *regp = dtt0; break;
844     case 7: *regp = dtt1; break;
845 cebix 1.1 case 0x800: *regp = regs.usp; break;
846     case 0x801: *regp = regs.vbr; break;
847     case 0x802: *regp = caar; break;
848     case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
849     case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
850 gbeauche 1.12 case 0x805: *regp = mmusr; break;
851     case 0x806: *regp = urp; break;
852     case 0x807: *regp = srp; break;
853 cebix 1.1 default:
854     op_illg (0x4E7A);
855 gbeauche 1.9 return 0;
856     }
857 cebix 1.1 }
858 gbeauche 1.9 return 1;
859 cebix 1.1 }
860    
861     static __inline__ int
862     div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
863     {
864     uae_u32 q = 0, cbit = 0;
865     int i;
866    
867     if (div <= src_hi) {
868     return 1;
869     }
870     for (i = 0 ; i < 32 ; i++) {
871     cbit = src_hi & 0x80000000ul;
872     src_hi <<= 1;
873     if (src_lo & 0x80000000ul) src_hi++;
874     src_lo <<= 1;
875     q = q << 1;
876     if (cbit || div <= src_hi) {
877     q |= 1;
878     src_hi -= div;
879     }
880     }
881     *quot = q;
882     *rem = src_hi;
883     return 0;
884     }
885    
886     void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
887     {
888     #if defined(uae_s64)
889     if (src == 0) {
890     Exception (5, oldpc);
891     return;
892     }
893     if (extra & 0x800) {
894     /* signed variant */
895     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
896     uae_s64 quot, rem;
897    
898     if (extra & 0x400) {
899     a &= 0xffffffffu;
900     a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
901     }
902     rem = a % (uae_s64)(uae_s32)src;
903     quot = a / (uae_s64)(uae_s32)src;
904     if ((quot & UVAL64(0xffffffff80000000)) != 0
905     && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
906     {
907     SET_VFLG (1);
908     SET_NFLG (1);
909     SET_CFLG (0);
910     } else {
911     if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
912     SET_VFLG (0);
913     SET_CFLG (0);
914     SET_ZFLG (((uae_s32)quot) == 0);
915     SET_NFLG (((uae_s32)quot) < 0);
916     m68k_dreg(regs, extra & 7) = rem;
917     m68k_dreg(regs, (extra >> 12) & 7) = quot;
918     }
919     } else {
920     /* unsigned */
921     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
922     uae_u64 quot, rem;
923    
924     if (extra & 0x400) {
925     a &= 0xffffffffu;
926     a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
927     }
928     rem = a % (uae_u64)src;
929     quot = a / (uae_u64)src;
930     if (quot > 0xffffffffu) {
931     SET_VFLG (1);
932     SET_NFLG (1);
933     SET_CFLG (0);
934     } else {
935     SET_VFLG (0);
936     SET_CFLG (0);
937     SET_ZFLG (((uae_s32)quot) == 0);
938     SET_NFLG (((uae_s32)quot) < 0);
939     m68k_dreg(regs, extra & 7) = rem;
940     m68k_dreg(regs, (extra >> 12) & 7) = quot;
941     }
942     }
943     #else
944     if (src == 0) {
945     Exception (5, oldpc);
946     return;
947     }
948     if (extra & 0x800) {
949     /* signed variant */
950     uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
951     uae_s32 hi = lo < 0 ? -1 : 0;
952     uae_s32 save_high;
953     uae_u32 quot, rem;
954     uae_u32 sign;
955    
956     if (extra & 0x400) {
957     hi = (uae_s32)m68k_dreg(regs, extra & 7);
958     }
959     save_high = hi;
960     sign = (hi ^ src);
961     if (hi < 0) {
962     hi = ~hi;
963     lo = -lo;
964     if (lo == 0) hi++;
965     }
966     if ((uae_s32)src < 0) src = -src;
967     if (div_unsigned(hi, lo, src, &quot, &rem) ||
968     (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
969     SET_VFLG (1);
970     SET_NFLG (1);
971     SET_CFLG (0);
972     } else {
973     if (sign & 0x80000000) quot = -quot;
974     if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
975     SET_VFLG (0);
976     SET_CFLG (0);
977     SET_ZFLG (((uae_s32)quot) == 0);
978     SET_NFLG (((uae_s32)quot) < 0);
979     m68k_dreg(regs, extra & 7) = rem;
980     m68k_dreg(regs, (extra >> 12) & 7) = quot;
981     }
982     } else {
983     /* unsigned */
984     uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
985     uae_u32 hi = 0;
986     uae_u32 quot, rem;
987    
988     if (extra & 0x400) {
989     hi = (uae_u32)m68k_dreg(regs, extra & 7);
990     }
991     if (div_unsigned(hi, lo, src, &quot, &rem)) {
992     SET_VFLG (1);
993     SET_NFLG (1);
994     SET_CFLG (0);
995     } else {
996     SET_VFLG (0);
997     SET_CFLG (0);
998     SET_ZFLG (((uae_s32)quot) == 0);
999     SET_NFLG (((uae_s32)quot) < 0);
1000     m68k_dreg(regs, extra & 7) = rem;
1001     m68k_dreg(regs, (extra >> 12) & 7) = quot;
1002     }
1003     }
1004     #endif
1005     }
1006    
1007     static __inline__ void
1008     mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1009     {
1010     uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1011     uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1012     uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1013     uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1014     uae_u32 lo;
1015    
1016     lo = r0 + ((r1 << 16) & 0xffff0000ul);
1017     if (lo < r0) r3++;
1018     r0 = lo;
1019     lo = r0 + ((r2 << 16) & 0xffff0000ul);
1020     if (lo < r0) r3++;
1021     r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1022     *dst_lo = lo;
1023     *dst_hi = r3;
1024     }
1025    
1026     void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1027     {
1028     #if defined(uae_s64)
1029     if (extra & 0x800) {
1030     /* signed variant */
1031     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1032    
1033     a *= (uae_s64)(uae_s32)src;
1034     SET_VFLG (0);
1035     SET_CFLG (0);
1036     SET_ZFLG (a == 0);
1037     SET_NFLG (a < 0);
1038     if (extra & 0x400)
1039     m68k_dreg(regs, extra & 7) = a >> 32;
1040     else if ((a & UVAL64(0xffffffff80000000)) != 0
1041     && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1042     {
1043     SET_VFLG (1);
1044     }
1045     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1046     } else {
1047     /* unsigned */
1048     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1049    
1050     a *= (uae_u64)src;
1051     SET_VFLG (0);
1052     SET_CFLG (0);
1053     SET_ZFLG (a == 0);
1054     SET_NFLG (((uae_s64)a) < 0);
1055     if (extra & 0x400)
1056     m68k_dreg(regs, extra & 7) = a >> 32;
1057     else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1058     SET_VFLG (1);
1059     }
1060     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1061     }
1062     #else
1063     if (extra & 0x800) {
1064     /* signed variant */
1065     uae_s32 src1,src2;
1066     uae_u32 dst_lo,dst_hi;
1067     uae_u32 sign;
1068    
1069     src1 = (uae_s32)src;
1070     src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1071     sign = (src1 ^ src2);
1072     if (src1 < 0) src1 = -src1;
1073     if (src2 < 0) src2 = -src2;
1074     mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1075     if (sign & 0x80000000) {
1076     dst_hi = ~dst_hi;
1077     dst_lo = -dst_lo;
1078     if (dst_lo == 0) dst_hi++;
1079     }
1080     SET_VFLG (0);
1081     SET_CFLG (0);
1082     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1083     SET_NFLG (((uae_s32)dst_hi) < 0);
1084     if (extra & 0x400)
1085     m68k_dreg(regs, extra & 7) = dst_hi;
1086     else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1087     && ((dst_hi & 0xffffffff) != 0xffffffff
1088     || (dst_lo & 0x80000000) != 0x80000000))
1089     {
1090     SET_VFLG (1);
1091     }
1092     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1093     } else {
1094     /* unsigned */
1095     uae_u32 dst_lo,dst_hi;
1096    
1097     mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1098    
1099     SET_VFLG (0);
1100     SET_CFLG (0);
1101     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1102     SET_NFLG (((uae_s32)dst_hi) < 0);
1103     if (extra & 0x400)
1104     m68k_dreg(regs, extra & 7) = dst_hi;
1105     else if (dst_hi != 0) {
1106     SET_VFLG (1);
1107     }
1108     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1109     }
1110     #endif
1111     }
1112     static char* ccnames[] =
1113     { "T ","F ","HI","LS","CC","CS","NE","EQ",
1114     "VC","VS","PL","MI","GE","LT","GT","LE" };
1115    
1116 gbeauche 1.13 // If value is greater than zero, this means we are still processing an EmulOp
1117     // because the counter is incremented only in m68k_execute(), i.e. interpretive
1118     // execution only
1119     static int m68k_execute_depth = 0;
1120    
1121 cebix 1.1 void m68k_reset (void)
1122     {
1123     m68k_areg (regs, 7) = 0x2000;
1124     m68k_setpc (ROMBaseMac + 0x2a);
1125     fill_prefetch_0 ();
1126     regs.s = 1;
1127     regs.m = 0;
1128     regs.stopped = 0;
1129     regs.t1 = 0;
1130     regs.t0 = 0;
1131     SET_ZFLG (0);
1132     SET_XFLG (0);
1133     SET_CFLG (0);
1134     SET_VFLG (0);
1135     SET_NFLG (0);
1136 gbeauche 1.13 SPCFLAGS_INIT( 0 );
1137 cebix 1.1 regs.intmask = 7;
1138     regs.vbr = regs.sfc = regs.dfc = 0;
1139 gbeauche 1.6 fpu_reset();
1140 gbeauche 1.10
1141     #if FLIGHT_RECORDER
1142     #if ENABLE_MON
1143     if (log_ptr == -1) {
1144     // Install "log" command in mon
1145     mon_add_command("log", dump_log, "log Dump m68k emulation log\n");
1146     }
1147     #endif
1148     log_ptr = 0;
1149     memset(log, 0, sizeof(log));
1150     #endif
1151 cebix 1.1 }
1152    
1153 gbeauche 1.13 void m68k_emulop_return(void)
1154 cebix 1.1 {
1155 gbeauche 1.13 SPCFLAGS_SET( SPCFLAG_BRK );
1156     quit_program = 1;
1157     }
1158 cebix 1.1
1159 gbeauche 1.13 void m68k_emulop(uae_u32 opcode)
1160     {
1161 cebix 1.1 struct M68kRegisters r;
1162     int i;
1163    
1164     for (i=0; i<8; i++) {
1165     r.d[i] = m68k_dreg(regs, i);
1166     r.a[i] = m68k_areg(regs, i);
1167     }
1168     MakeSR();
1169     r.sr = regs.sr;
1170     EmulOp(opcode, &r);
1171     for (i=0; i<8; i++) {
1172     m68k_dreg(regs, i) = r.d[i];
1173     m68k_areg(regs, i) = r.a[i];
1174     }
1175     regs.sr = r.sr;
1176     MakeFromSR();
1177 gbeauche 1.13 }
1178    
1179     cpuop_rettype REGPARAM2 op_illg (uae_u32 opcode)
1180     {
1181     uaecptr pc = m68k_getpc ();
1182 cebix 1.1
1183     if ((opcode & 0xF000) == 0xA000) {
1184     Exception(0xA,0);
1185 gbeauche 1.13 cpuop_return(CFLOW_TRAP);
1186 cebix 1.1 }
1187    
1188     if ((opcode & 0xF000) == 0xF000) {
1189     Exception(0xB,0);
1190 gbeauche 1.13 cpuop_return(CFLOW_TRAP);
1191 cebix 1.1 }
1192    
1193 cebix 1.4 write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1194    
1195 cebix 1.1 Exception (4,0);
1196 gbeauche 1.13 cpuop_return(CFLOW_TRAP);
1197 cebix 1.1 }
1198    
1199     void mmu_op(uae_u32 opcode, uae_u16 extra)
1200     {
1201 gbeauche 1.12 if ((opcode & 0xFE0) == 0x0500) {
1202     /* PFLUSH */
1203     mmusr = 0;
1204     } else if ((opcode & 0x0FD8) == 0x548) {
1205     /* PTEST */
1206 cebix 1.1 } else
1207 gbeauche 1.12 op_illg (opcode);
1208 cebix 1.1 }
1209    
1210     static int n_insns = 0, n_spcinsns = 0;
1211    
1212     static uaecptr last_trace_ad = 0;
1213    
1214     static void do_trace (void)
1215     {
1216 gbeauche 1.9 if (regs.t0 && CPUType >= 2) {
1217 cebix 1.1 uae_u16 opcode;
1218     /* should also include TRAP, CHK, SR modification FPcc */
1219     /* probably never used so why bother */
1220     /* We can afford this to be inefficient... */
1221     m68k_setpc (m68k_getpc ());
1222     fill_prefetch_0 ();
1223 gbeauche 1.13 opcode = get_word(m68k_getpc());
1224 cebix 1.1 if (opcode == 0x4e72 /* RTE */
1225     || opcode == 0x4e74 /* RTD */
1226     || opcode == 0x4e75 /* RTS */
1227     || opcode == 0x4e77 /* RTR */
1228     || opcode == 0x4e76 /* TRAPV */
1229     || (opcode & 0xffc0) == 0x4e80 /* JSR */
1230     || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1231     || (opcode & 0xff00) == 0x6100 /* BSR */
1232     || ((opcode & 0xf000) == 0x6000 /* Bcc */
1233     && cctrue((opcode >> 8) & 0xf))
1234     || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1235     && !cctrue((opcode >> 8) & 0xf)
1236     && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1237     {
1238     last_trace_ad = m68k_getpc ();
1239 gbeauche 1.13 SPCFLAGS_CLEAR( SPCFLAG_TRACE );
1240     SPCFLAGS_SET( SPCFLAG_DOTRACE );
1241 cebix 1.1 }
1242     } else if (regs.t1) {
1243     last_trace_ad = m68k_getpc ();
1244 gbeauche 1.13 SPCFLAGS_CLEAR( SPCFLAG_TRACE );
1245     SPCFLAGS_SET( SPCFLAG_DOTRACE );
1246 cebix 1.1 }
1247     }
1248    
1249 gbeauche 1.13 int m68k_do_specialties (void)
1250 cebix 1.1 {
1251 gbeauche 1.13 if (SPCFLAGS_TEST( SPCFLAG_DOTRACE )) {
1252 cebix 1.1 Exception (9,last_trace_ad);
1253     }
1254 gbeauche 1.13 while (SPCFLAGS_TEST( SPCFLAG_STOP )) {
1255     if (SPCFLAGS_TEST( SPCFLAG_INT | SPCFLAG_DOINT )){
1256     SPCFLAGS_CLEAR( SPCFLAG_INT | SPCFLAG_DOINT );
1257 cebix 1.1 int intr = intlev ();
1258     if (intr != -1 && intr > regs.intmask) {
1259     Interrupt (intr);
1260     regs.stopped = 0;
1261 gbeauche 1.13 SPCFLAGS_CLEAR( SPCFLAG_STOP );
1262 cebix 1.1 }
1263     }
1264     }
1265 gbeauche 1.13 if (SPCFLAGS_TEST( SPCFLAG_TRACE ))
1266 cebix 1.1 do_trace ();
1267    
1268 gbeauche 1.13 if (SPCFLAGS_TEST( SPCFLAG_DOINT )) {
1269     SPCFLAGS_CLEAR( SPCFLAG_DOINT );
1270 cebix 1.1 int intr = intlev ();
1271     if (intr != -1 && intr > regs.intmask) {
1272     Interrupt (intr);
1273     regs.stopped = 0;
1274     }
1275     }
1276 gbeauche 1.13 if (SPCFLAGS_TEST( SPCFLAG_INT )) {
1277     SPCFLAGS_CLEAR( SPCFLAG_INT );
1278     SPCFLAGS_SET( SPCFLAG_DOINT );
1279     }
1280     if (SPCFLAGS_TEST( SPCFLAG_BRK )) {
1281     SPCFLAGS_CLEAR( SPCFLAG_BRK );
1282     return CFLOW_EXEC_RETURN;
1283 cebix 1.1 }
1284     return 0;
1285     }
1286    
1287 gbeauche 1.13 void m68k_do_execute (void)
1288 cebix 1.1 {
1289 cebix 1.4 for (;;) {
1290     uae_u32 opcode = GET_OPCODE;
1291 gbeauche 1.10 #if FLIGHT_RECORDER
1292     record_step(m68k_getpc());
1293     #endif
1294 gbeauche 1.12 #ifdef X86_ASSEMBLY
1295     __asm__ __volatile__("\tpushl %%ebp\n\tcall *%%ebx\n\tpopl %%ebp" /* FIXME */
1296     : : "b" (cpufunctbl[opcode]), "a" (opcode)
1297     : "%edx", "%ecx", "%esi", "%edi", "%ebp", "memory", "cc");
1298     #else
1299 cebix 1.4 (*cpufunctbl[opcode])(opcode);
1300 gbeauche 1.12 #endif
1301 gbeauche 1.13 if (SPCFLAGS_TEST(SPCFLAG_ALL_BUT_EXEC_RETURN)) {
1302     if (m68k_do_specialties())
1303 cebix 1.4 return;
1304     }
1305 cebix 1.1 }
1306     }
1307    
1308 gbeauche 1.13 void m68k_execute (void)
1309 cebix 1.1 {
1310     for (;;) {
1311     if (quit_program > 0) {
1312     if (quit_program == 1)
1313     break;
1314     quit_program = 0;
1315     m68k_reset ();
1316     }
1317 gbeauche 1.13 m68k_do_execute();
1318 cebix 1.1 }
1319     if (debugging) {
1320     uaecptr nextpc;
1321     m68k_dumpstate(&nextpc);
1322     exit(1);
1323     }
1324     }
1325    
1326     static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1327     {
1328     uae_u32 opcode, val;
1329     struct instr *dp;
1330    
1331     opcode = get_iword_1(0);
1332     last_op_for_exception_3 = opcode;
1333     m68kpc_offset = 2;
1334    
1335     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1336     opcode = 0x4AFC;
1337     }
1338     dp = table68k + opcode;
1339    
1340     if (dp->suse) {
1341     if (!verify_ea (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, &val)) {
1342     Exception (3, 0);
1343     return;
1344     }
1345     }
1346     if (dp->duse) {
1347     if (!verify_ea (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, &val)) {
1348     Exception (3, 0);
1349     return;
1350     }
1351     }
1352     }
1353    
1354     void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt)
1355     {
1356     uaecptr newpc = 0;
1357     m68kpc_offset = addr - m68k_getpc ();
1358     while (cnt-- > 0) {
1359     char instrname[20],*ccpt;
1360     int opwords;
1361     uae_u32 opcode;
1362     struct mnemolookup *lookup;
1363     struct instr *dp;
1364     printf ("%08lx: ", m68k_getpc () + m68kpc_offset);
1365     for (opwords = 0; opwords < 5; opwords++){
1366     printf ("%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1367     }
1368     opcode = get_iword_1 (m68kpc_offset);
1369     m68kpc_offset += 2;
1370     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1371     opcode = 0x4AFC;
1372     }
1373     dp = table68k + opcode;
1374     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1375     ;
1376    
1377     strcpy (instrname, lookup->name);
1378     ccpt = strstr (instrname, "cc");
1379     if (ccpt != 0) {
1380     strncpy (ccpt, ccnames[dp->cc], 2);
1381     }
1382     printf ("%s", instrname);
1383     switch (dp->size){
1384     case sz_byte: printf (".B "); break;
1385     case sz_word: printf (".W "); break;
1386     case sz_long: printf (".L "); break;
1387     default: printf (" "); break;
1388     }
1389    
1390     if (dp->suse) {
1391     newpc = m68k_getpc () + m68kpc_offset;
1392     newpc += ShowEA (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, 0);
1393     }
1394     if (dp->suse && dp->duse)
1395     printf (",");
1396     if (dp->duse) {
1397     newpc = m68k_getpc () + m68kpc_offset;
1398     newpc += ShowEA (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, 0);
1399     }
1400     if (ccpt != 0) {
1401     if (cctrue(dp->cc))
1402     printf (" == %08lx (TRUE)", newpc);
1403     else
1404     printf (" == %08lx (FALSE)", newpc);
1405     } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1406     printf (" == %08lx", newpc);
1407     printf ("\n");
1408     }
1409     if (nextpc)
1410     *nextpc = m68k_getpc () + m68kpc_offset;
1411     }
1412    
1413     void m68k_dumpstate (uaecptr *nextpc)
1414     {
1415     int i;
1416     for (i = 0; i < 8; i++){
1417     printf ("D%d: %08lx ", i, m68k_dreg(regs, i));
1418     if ((i & 3) == 3) printf ("\n");
1419     }
1420     for (i = 0; i < 8; i++){
1421     printf ("A%d: %08lx ", i, m68k_areg(regs, i));
1422     if ((i & 3) == 3) printf ("\n");
1423     }
1424     if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1425     if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1426     if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1427     printf ("USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1428     regs.usp,regs.isp,regs.msp,regs.vbr);
1429     printf ("T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1430     regs.t1, regs.t0, regs.s, regs.m,
1431     GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1432 gbeauche 1.15
1433     fpu_dump_registers();
1434     fpu_dump_flags();
1435    
1436 cebix 1.1 m68k_disasm(m68k_getpc (), nextpc, 1);
1437     if (nextpc)
1438     printf ("next PC: %08lx\n", *nextpc);
1439     }