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root/cebix/BasiliskII/src/uae_cpu/newcpu.cpp
Revision: 1.11
Committed: 2002-03-18T21:25:07Z (22 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.10: +1 -0 lines
Log Message:
- Close log file

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * UAE - The Un*x Amiga Emulator
3     *
4     * MC68000 emulation
5     *
6     * (c) 1995 Bernd Schmidt
7     */
8    
9     #include <stdio.h>
10     #include <stdlib.h>
11     #include <string.h>
12    
13     #include "sysdeps.h"
14    
15     #include "cpu_emulation.h"
16     #include "main.h"
17     #include "emul_op.h"
18    
19     extern int intlev(void); // From baisilisk_glue.cpp
20    
21     #include "m68k.h"
22     #include "memory.h"
23     #include "readcpu.h"
24     #include "newcpu.h"
25    
26 gbeauche 1.10 #if ENABLE_MON
27     #include "mon.h"
28     #include "mon_disass.h"
29     #endif
30    
31 cebix 1.1 int quit_program = 0;
32     int debugging = 0;
33     struct flag_struct regflags;
34    
35     /* Opcode of faulting instruction */
36     uae_u16 last_op_for_exception_3;
37     /* PC at fault time */
38     uaecptr last_addr_for_exception_3;
39     /* Address that generated the exception */
40     uaecptr last_fault_for_exception_3;
41    
42     int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
43     int imm8_table[] = { 8,1,2,3,4,5,6,7 };
44    
45     int movem_index1[256];
46     int movem_index2[256];
47     int movem_next[256];
48    
49     int fpp_movem_index1[256];
50     int fpp_movem_index2[256];
51     int fpp_movem_next[256];
52    
53     cpuop_func *cpufunctbl[65536];
54    
55 gbeauche 1.10 #define FLIGHT_RECORDER 0
56    
57     #if FLIGHT_RECORDER
58     struct rec_step {
59     uae_u32 d[8];
60     uae_u32 a[8];
61     uae_u32 pc;
62     };
63    
64     const int LOG_SIZE = 8192;
65     static rec_step log[LOG_SIZE];
66     static int log_ptr = -1; // First time initialization
67    
68     static const char *log_filename(void)
69     {
70     const char *name = getenv("M68K_LOG_FILE");
71     return name ? name : "log.68k";
72     }
73    
74     static void record_step(uaecptr pc)
75     {
76     for (int i = 0; i < 8; i++) {
77     log[log_ptr].d[i] = m68k_dreg(regs, i);
78     log[log_ptr].a[i] = m68k_areg(regs, i);
79     }
80     log[log_ptr].pc = pc;
81     log_ptr = (log_ptr + 1) % LOG_SIZE;
82     }
83    
84     static void dump_log(void)
85     {
86     FILE *f = fopen(log_filename(), "w");
87     if (f == NULL)
88     return;
89     for (int i = 0; i < LOG_SIZE; i++) {
90     int j = (i + log_ptr) % LOG_SIZE;
91     fprintf(f, "pc %08x\n", log[j].pc);
92     fprintf(f, "d0 %08x d1 %08x d2 %08x d3 %08x\n", log[j].d[0], log[j].d[1], log[j].d[2], log[j].d[3]);
93     fprintf(f, "d4 %08x d5 %08x d6 %08x d7 %08x\n", log[j].d[4], log[j].d[5], log[j].d[6], log[j].d[7]);
94     fprintf(f, "a0 %08x a1 %08x a2 %08x a3 %08x\n", log[j].a[0], log[j].a[1], log[j].a[2], log[j].a[3]);
95     fprintf(f, "a4 %08x a5 %08x a6 %08x a7 %08x\n", log[j].a[4], log[j].a[5], log[j].a[6], log[j].a[7]);
96     #if ENABLE_MON
97     disass_68k(f, log[j].pc);
98     #endif
99     }
100 gbeauche 1.11 fclose(f);
101 gbeauche 1.10 }
102     #endif
103    
104 cebix 1.1 #define COUNT_INSTRS 0
105    
106     #if COUNT_INSTRS
107     static unsigned long int instrcount[65536];
108     static uae_u16 opcodenums[65536];
109    
110     static int compfn (const void *el1, const void *el2)
111     {
112     return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
113     }
114    
115     static char *icountfilename (void)
116     {
117     char *name = getenv ("INSNCOUNT");
118     if (name)
119     return name;
120     return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
121     }
122    
123     void dump_counts (void)
124     {
125     FILE *f = fopen (icountfilename (), "w");
126     unsigned long int total;
127     int i;
128    
129     write_log ("Writing instruction count file...\n");
130     for (i = 0; i < 65536; i++) {
131     opcodenums[i] = i;
132     total += instrcount[i];
133     }
134     qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
135    
136     fprintf (f, "Total: %lu\n", total);
137     for (i=0; i < 65536; i++) {
138     unsigned long int cnt = instrcount[opcodenums[i]];
139     struct instr *dp;
140     struct mnemolookup *lookup;
141     if (!cnt)
142     break;
143     dp = table68k + opcodenums[i];
144     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
145     ;
146     fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
147     }
148     fclose (f);
149     }
150     #else
151     void dump_counts (void)
152     {
153     }
154     #endif
155    
156     int broken_in;
157    
158     static __inline__ unsigned int cft_map (unsigned int f)
159     {
160     #ifndef HAVE_GET_WORD_UNSWAPPED
161     return f;
162     #else
163     return ((f >> 8) & 255) | ((f & 255) << 8);
164     #endif
165     }
166    
167 cebix 1.4 static void REGPARAM2 op_illg_1 (uae_u32 opcode) REGPARAM;
168 cebix 1.1
169 cebix 1.4 static void REGPARAM2 op_illg_1 (uae_u32 opcode)
170 cebix 1.1 {
171     op_illg (cft_map (opcode));
172     }
173    
174     static void build_cpufunctbl (void)
175     {
176     int i;
177     unsigned long opcode;
178 cebix 1.2 int cpu_level = 0; // 68000 (default)
179     if (CPUType == 4)
180     cpu_level = 4; // 68040 with FPU
181     else {
182     if (FPUType)
183     cpu_level = 3; // 68020 with FPU
184     else if (CPUType >= 2)
185     cpu_level = 2; // 68020
186     else if (CPUType == 1)
187     cpu_level = 1;
188     }
189     struct cputbl *tbl = (
190     cpu_level == 4 ? op_smalltbl_0
191     : cpu_level == 3 ? op_smalltbl_1
192     : cpu_level == 2 ? op_smalltbl_2
193     : cpu_level == 1 ? op_smalltbl_3
194     : op_smalltbl_4);
195 cebix 1.1
196     for (opcode = 0; opcode < 65536; opcode++)
197     cpufunctbl[cft_map (opcode)] = op_illg_1;
198     for (i = 0; tbl[i].handler != NULL; i++) {
199     if (! tbl[i].specific)
200     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
201     }
202     for (opcode = 0; opcode < 65536; opcode++) {
203     cpuop_func *f;
204    
205     if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
206     continue;
207    
208     if (table68k[opcode].handler != -1) {
209     f = cpufunctbl[cft_map (table68k[opcode].handler)];
210     if (f == op_illg_1)
211     abort();
212     cpufunctbl[cft_map (opcode)] = f;
213     }
214     }
215     for (i = 0; tbl[i].handler != NULL; i++) {
216     if (tbl[i].specific)
217     cpufunctbl[cft_map (tbl[i].opcode)] = tbl[i].handler;
218     }
219     }
220    
221     void init_m68k (void)
222     {
223     int i;
224    
225     for (i = 0 ; i < 256 ; i++) {
226     int j;
227     for (j = 0 ; j < 8 ; j++) {
228     if (i & (1 << j)) break;
229     }
230     movem_index1[i] = j;
231     movem_index2[i] = 7-j;
232     movem_next[i] = i & (~(1 << j));
233     }
234     for (i = 0 ; i < 256 ; i++) {
235     int j;
236     for (j = 7 ; j >= 0 ; j--) {
237     if (i & (1 << j)) break;
238     }
239 cebix 1.5 fpp_movem_index1[i] = 7-j;
240     fpp_movem_index2[i] = j;
241 cebix 1.1 fpp_movem_next[i] = i & (~(1 << j));
242     }
243     #if COUNT_INSTRS
244     {
245     FILE *f = fopen (icountfilename (), "r");
246     memset (instrcount, 0, sizeof instrcount);
247     if (f) {
248     uae_u32 opcode, count, total;
249     char name[20];
250     write_log ("Reading instruction count file...\n");
251     fscanf (f, "Total: %lu\n", &total);
252     while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
253     instrcount[opcode] = count;
254     }
255     fclose(f);
256     }
257     }
258     #endif
259     read_table68k ();
260     do_merges ();
261    
262     build_cpufunctbl ();
263 gbeauche 1.6
264     fpu_init ();
265     fpu_set_integral_fpu (CPUType == 4);
266     }
267    
268     void exit_m68k (void)
269     {
270     fpu_exit ();
271 cebix 1.1 }
272    
273     struct regstruct regs, lastint_regs;
274     static struct regstruct regs_backup[16];
275     static int backup_pointer = 0;
276     static long int m68kpc_offset;
277     int lastint_no;
278    
279 gbeauche 1.7 #if REAL_ADDRESSING || DIRECT_ADDRESSING
280     #define get_ibyte_1(o) get_byte(get_virtual_address(regs.pc_p) + (o) + 1)
281     #define get_iword_1(o) get_word(get_virtual_address(regs.pc_p) + (o))
282     #define get_ilong_1(o) get_long(get_virtual_address(regs.pc_p) + (o))
283     #else
284 cebix 1.1 #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
285     #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
286     #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
287 gbeauche 1.7 #endif
288 cebix 1.1
289     uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf)
290     {
291     uae_u16 dp;
292     uae_s8 disp8;
293     uae_s16 disp16;
294     int r;
295     uae_u32 dispreg;
296     uaecptr addr;
297     uae_s32 offset = 0;
298     char buffer[80];
299    
300     switch (mode){
301     case Dreg:
302     sprintf (buffer,"D%d", reg);
303     break;
304     case Areg:
305     sprintf (buffer,"A%d", reg);
306     break;
307     case Aind:
308     sprintf (buffer,"(A%d)", reg);
309     break;
310     case Aipi:
311     sprintf (buffer,"(A%d)+", reg);
312     break;
313     case Apdi:
314     sprintf (buffer,"-(A%d)", reg);
315     break;
316     case Ad16:
317     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
318     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
319     sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
320 cebix 1.5 (unsigned long)addr);
321 cebix 1.1 break;
322     case Ad8r:
323     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
324     disp8 = dp & 0xFF;
325     r = (dp & 0x7000) >> 12;
326     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
327     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
328     dispreg <<= (dp >> 9) & 3;
329    
330     if (dp & 0x100) {
331     uae_s32 outer = 0, disp = 0;
332     uae_s32 base = m68k_areg(regs,reg);
333     char name[10];
334     sprintf (name,"A%d, ",reg);
335     if (dp & 0x80) { base = 0; name[0] = 0; }
336     if (dp & 0x40) dispreg = 0;
337     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
338     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
339     base += disp;
340    
341     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
342     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
343    
344     if (!(dp & 4)) base += dispreg;
345     if (dp & 3) base = get_long (base);
346     if (dp & 4) base += dispreg;
347    
348     addr = base + outer;
349     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
350     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
351     1 << ((dp >> 9) & 3),
352     disp,outer,
353 cebix 1.5 (unsigned long)addr);
354 cebix 1.1 } else {
355     addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
356     sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
357     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
358     1 << ((dp >> 9) & 3), disp8,
359 cebix 1.5 (unsigned long)addr);
360 cebix 1.1 }
361     break;
362     case PC16:
363     addr = m68k_getpc () + m68kpc_offset;
364     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
365     addr += (uae_s16)disp16;
366 cebix 1.5 sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
367 cebix 1.1 break;
368     case PC8r:
369     addr = m68k_getpc () + m68kpc_offset;
370     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
371     disp8 = dp & 0xFF;
372     r = (dp & 0x7000) >> 12;
373     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
374     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
375     dispreg <<= (dp >> 9) & 3;
376    
377     if (dp & 0x100) {
378     uae_s32 outer = 0,disp = 0;
379     uae_s32 base = addr;
380     char name[10];
381     sprintf (name,"PC, ");
382     if (dp & 0x80) { base = 0; name[0] = 0; }
383     if (dp & 0x40) dispreg = 0;
384     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
385     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
386     base += disp;
387    
388     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
389     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
390    
391     if (!(dp & 4)) base += dispreg;
392     if (dp & 3) base = get_long (base);
393     if (dp & 4) base += dispreg;
394    
395     addr = base + outer;
396     sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
397     dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
398     1 << ((dp >> 9) & 3),
399     disp,outer,
400 cebix 1.5 (unsigned long)addr);
401 cebix 1.1 } else {
402     addr += (uae_s32)((uae_s8)disp8) + dispreg;
403     sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
404     (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
405 cebix 1.5 disp8, (unsigned long)addr);
406 cebix 1.1 }
407     break;
408     case absw:
409 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
410 cebix 1.1 m68kpc_offset += 2;
411     break;
412     case absl:
413 cebix 1.5 sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
414 cebix 1.1 m68kpc_offset += 4;
415     break;
416     case imm:
417     switch (size){
418     case sz_byte:
419     sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
420     m68kpc_offset += 2;
421     break;
422     case sz_word:
423     sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
424     m68kpc_offset += 2;
425     break;
426     case sz_long:
427 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
428 cebix 1.1 m68kpc_offset += 4;
429     break;
430     default:
431     break;
432     }
433     break;
434     case imm0:
435     offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
436     m68kpc_offset += 2;
437     sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
438     break;
439     case imm1:
440     offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
441     m68kpc_offset += 2;
442     sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
443     break;
444     case imm2:
445     offset = (uae_s32)get_ilong_1 (m68kpc_offset);
446     m68kpc_offset += 4;
447 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
448 cebix 1.1 break;
449     case immi:
450     offset = (uae_s32)(uae_s8)(reg & 0xff);
451 cebix 1.5 sprintf (buffer,"#$%08lx", (unsigned long)offset);
452 cebix 1.1 break;
453     default:
454     break;
455     }
456     if (buf == 0)
457     printf ("%s", buffer);
458     else
459     strcat (buf, buffer);
460     return offset;
461     }
462    
463     /* The plan is that this will take over the job of exception 3 handling -
464     * the CPU emulation functions will just do a longjmp to m68k_go whenever
465     * they hit an odd address. */
466     static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
467     {
468     uae_u16 dp;
469     uae_s8 disp8;
470     uae_s16 disp16;
471     int r;
472     uae_u32 dispreg;
473     uaecptr addr;
474     uae_s32 offset = 0;
475    
476     switch (mode){
477     case Dreg:
478     *val = m68k_dreg (regs, reg);
479     return 1;
480     case Areg:
481     *val = m68k_areg (regs, reg);
482     return 1;
483    
484     case Aind:
485     case Aipi:
486     addr = m68k_areg (regs, reg);
487     break;
488     case Apdi:
489     addr = m68k_areg (regs, reg);
490     break;
491     case Ad16:
492     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
493     addr = m68k_areg(regs,reg) + (uae_s16)disp16;
494     break;
495     case Ad8r:
496     addr = m68k_areg (regs, reg);
497     d8r_common:
498     dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
499     disp8 = dp & 0xFF;
500     r = (dp & 0x7000) >> 12;
501     dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
502     if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
503     dispreg <<= (dp >> 9) & 3;
504    
505     if (dp & 0x100) {
506     uae_s32 outer = 0, disp = 0;
507     uae_s32 base = addr;
508     if (dp & 0x80) base = 0;
509     if (dp & 0x40) dispreg = 0;
510     if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
511     if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
512     base += disp;
513    
514     if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
515     if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
516    
517     if (!(dp & 4)) base += dispreg;
518     if (dp & 3) base = get_long (base);
519     if (dp & 4) base += dispreg;
520    
521     addr = base + outer;
522     } else {
523     addr += (uae_s32)((uae_s8)disp8) + dispreg;
524     }
525     break;
526     case PC16:
527     addr = m68k_getpc () + m68kpc_offset;
528     disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
529     addr += (uae_s16)disp16;
530     break;
531     case PC8r:
532     addr = m68k_getpc () + m68kpc_offset;
533     goto d8r_common;
534     case absw:
535     addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
536     m68kpc_offset += 2;
537     break;
538     case absl:
539     addr = get_ilong_1 (m68kpc_offset);
540     m68kpc_offset += 4;
541     break;
542     case imm:
543     switch (size){
544     case sz_byte:
545     *val = get_iword_1 (m68kpc_offset) & 0xff;
546     m68kpc_offset += 2;
547     break;
548     case sz_word:
549     *val = get_iword_1 (m68kpc_offset) & 0xffff;
550     m68kpc_offset += 2;
551     break;
552     case sz_long:
553     *val = get_ilong_1 (m68kpc_offset);
554     m68kpc_offset += 4;
555     break;
556     default:
557     break;
558     }
559     return 1;
560     case imm0:
561     *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
562     m68kpc_offset += 2;
563     return 1;
564     case imm1:
565     *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
566     m68kpc_offset += 2;
567     return 1;
568     case imm2:
569     *val = get_ilong_1 (m68kpc_offset);
570     m68kpc_offset += 4;
571     return 1;
572     case immi:
573     *val = (uae_s32)(uae_s8)(reg & 0xff);
574     return 1;
575     default:
576     addr = 0;
577     break;
578     }
579     if ((addr & 1) == 0)
580     return 1;
581    
582     last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
583     last_fault_for_exception_3 = addr;
584     return 0;
585     }
586    
587     uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
588     {
589     int reg = (dp >> 12) & 15;
590     uae_s32 regd = regs.regs[reg];
591     if ((dp & 0x800) == 0)
592     regd = (uae_s32)(uae_s16)regd;
593     regd <<= (dp >> 9) & 3;
594     if (dp & 0x100) {
595     uae_s32 outer = 0;
596     if (dp & 0x80) base = 0;
597     if (dp & 0x40) regd = 0;
598    
599     if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
600     if ((dp & 0x30) == 0x30) base += next_ilong();
601    
602     if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
603     if ((dp & 0x3) == 0x3) outer = next_ilong();
604    
605     if ((dp & 0x4) == 0) base += regd;
606     if (dp & 0x3) base = get_long (base);
607     if (dp & 0x4) base += regd;
608    
609     return base + outer;
610     } else {
611     return base + (uae_s32)((uae_s8)dp) + regd;
612     }
613     }
614    
615     uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
616     {
617     int reg = (dp >> 12) & 15;
618     uae_s32 regd = regs.regs[reg];
619     #if 1
620     if ((dp & 0x800) == 0)
621     regd = (uae_s32)(uae_s16)regd;
622     return base + (uae_s8)dp + regd;
623     #else
624     /* Branch-free code... benchmark this again now that
625     * things are no longer inline. */
626     uae_s32 regd16;
627     uae_u32 mask;
628     mask = ((dp & 0x800) >> 11) - 1;
629     regd16 = (uae_s32)(uae_s16)regd;
630     regd16 &= mask;
631     mask = ~mask;
632     base += (uae_s8)dp;
633     regd &= mask;
634     regd |= regd16;
635     return base + regd;
636     #endif
637     }
638    
639     void MakeSR (void)
640     {
641     #if 0
642     assert((regs.t1 & 1) == regs.t1);
643     assert((regs.t0 & 1) == regs.t0);
644     assert((regs.s & 1) == regs.s);
645     assert((regs.m & 1) == regs.m);
646     assert((XFLG & 1) == XFLG);
647     assert((NFLG & 1) == NFLG);
648     assert((ZFLG & 1) == ZFLG);
649     assert((VFLG & 1) == VFLG);
650     assert((CFLG & 1) == CFLG);
651     #endif
652     regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
653     | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
654     | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
655     | GET_CFLG);
656     }
657    
658     void MakeFromSR (void)
659     {
660     int oldm = regs.m;
661     int olds = regs.s;
662    
663     regs.t1 = (regs.sr >> 15) & 1;
664     regs.t0 = (regs.sr >> 14) & 1;
665     regs.s = (regs.sr >> 13) & 1;
666     regs.m = (regs.sr >> 12) & 1;
667     regs.intmask = (regs.sr >> 8) & 7;
668     SET_XFLG ((regs.sr >> 4) & 1);
669     SET_NFLG ((regs.sr >> 3) & 1);
670     SET_ZFLG ((regs.sr >> 2) & 1);
671     SET_VFLG ((regs.sr >> 1) & 1);
672     SET_CFLG (regs.sr & 1);
673     if (CPUType >= 2) {
674     if (olds != regs.s) {
675     if (olds) {
676     if (oldm)
677     regs.msp = m68k_areg(regs, 7);
678     else
679     regs.isp = m68k_areg(regs, 7);
680     m68k_areg(regs, 7) = regs.usp;
681     } else {
682     regs.usp = m68k_areg(regs, 7);
683     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
684     }
685     } else if (olds && oldm != regs.m) {
686     if (oldm) {
687     regs.msp = m68k_areg(regs, 7);
688     m68k_areg(regs, 7) = regs.isp;
689     } else {
690     regs.isp = m68k_areg(regs, 7);
691     m68k_areg(regs, 7) = regs.msp;
692     }
693     }
694     } else {
695     if (olds != regs.s) {
696     if (olds) {
697     regs.isp = m68k_areg(regs, 7);
698     m68k_areg(regs, 7) = regs.usp;
699     } else {
700     regs.usp = m68k_areg(regs, 7);
701     m68k_areg(regs, 7) = regs.isp;
702     }
703     }
704     }
705    
706     regs.spcflags |= SPCFLAG_INT;
707     if (regs.t1 || regs.t0)
708     regs.spcflags |= SPCFLAG_TRACE;
709     else
710     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
711     }
712    
713     void Exception(int nr, uaecptr oldpc)
714     {
715 gbeauche 1.9 uae_u32 currpc = m68k_getpc ();
716 cebix 1.1 MakeSR();
717     if (!regs.s) {
718     regs.usp = m68k_areg(regs, 7);
719     if (CPUType >= 2)
720     m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
721     else
722     m68k_areg(regs, 7) = regs.isp;
723     regs.s = 1;
724     }
725     if (CPUType > 0) {
726     if (nr == 2 || nr == 3) {
727     int i;
728     /* @@@ this is probably wrong (?) */
729     for (i = 0 ; i < 12 ; i++) {
730     m68k_areg(regs, 7) -= 2;
731     put_word (m68k_areg(regs, 7), 0);
732     }
733     m68k_areg(regs, 7) -= 2;
734     put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
735     } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
736     m68k_areg(regs, 7) -= 4;
737     put_long (m68k_areg(regs, 7), oldpc);
738     m68k_areg(regs, 7) -= 2;
739     put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
740     } else if (regs.m && nr >= 24 && nr < 32) {
741     m68k_areg(regs, 7) -= 2;
742     put_word (m68k_areg(regs, 7), nr * 4);
743     m68k_areg(regs, 7) -= 4;
744 gbeauche 1.9 put_long (m68k_areg(regs, 7), currpc);
745 cebix 1.1 m68k_areg(regs, 7) -= 2;
746     put_word (m68k_areg(regs, 7), regs.sr);
747     regs.sr |= (1 << 13);
748     regs.msp = m68k_areg(regs, 7);
749     m68k_areg(regs, 7) = regs.isp;
750     m68k_areg(regs, 7) -= 2;
751     put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
752     } else {
753     m68k_areg(regs, 7) -= 2;
754     put_word (m68k_areg(regs, 7), nr * 4);
755     }
756     } else {
757     if (nr == 2 || nr == 3) {
758     m68k_areg(regs, 7) -= 12;
759     /* ??????? */
760     if (nr == 3) {
761     put_long (m68k_areg(regs, 7), last_fault_for_exception_3);
762     put_word (m68k_areg(regs, 7)+4, last_op_for_exception_3);
763     put_long (m68k_areg(regs, 7)+8, last_addr_for_exception_3);
764     }
765     write_log ("Exception!\n");
766     goto kludge_me_do;
767     }
768     }
769     m68k_areg(regs, 7) -= 4;
770 gbeauche 1.9 put_long (m68k_areg(regs, 7), currpc);
771 cebix 1.1 kludge_me_do:
772     m68k_areg(regs, 7) -= 2;
773     put_word (m68k_areg(regs, 7), regs.sr);
774     m68k_setpc (get_long (regs.vbr + 4*nr));
775     fill_prefetch_0 ();
776     regs.t1 = regs.t0 = regs.m = 0;
777     regs.spcflags &= ~(SPCFLAG_TRACE | SPCFLAG_DOTRACE);
778     }
779    
780     static void Interrupt(int nr)
781     {
782     assert(nr < 8 && nr >= 0);
783     lastint_regs = regs;
784     lastint_no = nr;
785     Exception(nr+24, 0);
786    
787     regs.intmask = nr;
788     regs.spcflags |= SPCFLAG_INT;
789     }
790    
791 cebix 1.2 static int caar, cacr, tc, itt0, itt1, dtt0, dtt1;
792 cebix 1.1
793 gbeauche 1.9 int m68k_move2c (int regno, uae_u32 *regp)
794 cebix 1.1 {
795 gbeauche 1.9 if ((CPUType == 1 && (regno & 0x7FF) > 1)
796     || (CPUType < 4 && (regno & 0x7FF) > 2)
797     || (CPUType == 4 && regno == 0x802))
798     {
799 cebix 1.1 op_illg (0x4E7B);
800 gbeauche 1.9 return 0;
801     } else {
802 cebix 1.1 switch (regno) {
803     case 0: regs.sfc = *regp & 7; break;
804     case 1: regs.dfc = *regp & 7; break;
805 gbeauche 1.9 case 2: cacr = *regp & (CPUType < 4 ? 0x3 : 0x80008000); break;
806 cebix 1.2 case 3: tc = *regp & 0xc000; break;
807     case 4: itt0 = *regp & 0xffffe364; break;
808     case 5: itt1 = *regp & 0xffffe364; break;
809     case 6: dtt0 = *regp & 0xffffe364; break;
810     case 7: dtt1 = *regp & 0xffffe364; break;
811 cebix 1.1 case 0x800: regs.usp = *regp; break;
812     case 0x801: regs.vbr = *regp; break;
813     case 0x802: caar = *regp &0xfc; break;
814     case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
815     case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
816     default:
817     op_illg (0x4E7B);
818 gbeauche 1.9 return 0;
819 cebix 1.1 }
820 gbeauche 1.9 }
821     return 1;
822 cebix 1.1 }
823    
824 gbeauche 1.9 int m68k_movec2 (int regno, uae_u32 *regp)
825 cebix 1.1 {
826 gbeauche 1.9 if ((CPUType == 1 && (regno & 0x7FF) > 1)
827     || (CPUType < 4 && (regno & 0x7FF) > 2)
828     || (CPUType == 4 && regno == 0x802))
829     {
830 cebix 1.1 op_illg (0x4E7A);
831 gbeauche 1.9 return 0;
832     } else {
833 cebix 1.1 switch (regno) {
834     case 0: *regp = regs.sfc; break;
835     case 1: *regp = regs.dfc; break;
836     case 2: *regp = cacr; break;
837 cebix 1.2 case 3: *regp = tc; break;
838     case 4: *regp = itt0; break;
839     case 5: *regp = itt1; break;
840     case 6: *regp = dtt0; break;
841     case 7: *regp = dtt1; break;
842 cebix 1.1 case 0x800: *regp = regs.usp; break;
843     case 0x801: *regp = regs.vbr; break;
844     case 0x802: *regp = caar; break;
845     case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
846     case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
847     default:
848     op_illg (0x4E7A);
849 gbeauche 1.9 return 0;
850     }
851 cebix 1.1 }
852 gbeauche 1.9 return 1;
853 cebix 1.1 }
854    
855     static __inline__ int
856     div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
857     {
858     uae_u32 q = 0, cbit = 0;
859     int i;
860    
861     if (div <= src_hi) {
862     return 1;
863     }
864     for (i = 0 ; i < 32 ; i++) {
865     cbit = src_hi & 0x80000000ul;
866     src_hi <<= 1;
867     if (src_lo & 0x80000000ul) src_hi++;
868     src_lo <<= 1;
869     q = q << 1;
870     if (cbit || div <= src_hi) {
871     q |= 1;
872     src_hi -= div;
873     }
874     }
875     *quot = q;
876     *rem = src_hi;
877     return 0;
878     }
879    
880     void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
881     {
882     #if defined(uae_s64)
883     if (src == 0) {
884     Exception (5, oldpc);
885     return;
886     }
887     if (extra & 0x800) {
888     /* signed variant */
889     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
890     uae_s64 quot, rem;
891    
892     if (extra & 0x400) {
893     a &= 0xffffffffu;
894     a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
895     }
896     rem = a % (uae_s64)(uae_s32)src;
897     quot = a / (uae_s64)(uae_s32)src;
898     if ((quot & UVAL64(0xffffffff80000000)) != 0
899     && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
900     {
901     SET_VFLG (1);
902     SET_NFLG (1);
903     SET_CFLG (0);
904     } else {
905     if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
906     SET_VFLG (0);
907     SET_CFLG (0);
908     SET_ZFLG (((uae_s32)quot) == 0);
909     SET_NFLG (((uae_s32)quot) < 0);
910     m68k_dreg(regs, extra & 7) = rem;
911     m68k_dreg(regs, (extra >> 12) & 7) = quot;
912     }
913     } else {
914     /* unsigned */
915     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
916     uae_u64 quot, rem;
917    
918     if (extra & 0x400) {
919     a &= 0xffffffffu;
920     a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
921     }
922     rem = a % (uae_u64)src;
923     quot = a / (uae_u64)src;
924     if (quot > 0xffffffffu) {
925     SET_VFLG (1);
926     SET_NFLG (1);
927     SET_CFLG (0);
928     } else {
929     SET_VFLG (0);
930     SET_CFLG (0);
931     SET_ZFLG (((uae_s32)quot) == 0);
932     SET_NFLG (((uae_s32)quot) < 0);
933     m68k_dreg(regs, extra & 7) = rem;
934     m68k_dreg(regs, (extra >> 12) & 7) = quot;
935     }
936     }
937     #else
938     if (src == 0) {
939     Exception (5, oldpc);
940     return;
941     }
942     if (extra & 0x800) {
943     /* signed variant */
944     uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
945     uae_s32 hi = lo < 0 ? -1 : 0;
946     uae_s32 save_high;
947     uae_u32 quot, rem;
948     uae_u32 sign;
949    
950     if (extra & 0x400) {
951     hi = (uae_s32)m68k_dreg(regs, extra & 7);
952     }
953     save_high = hi;
954     sign = (hi ^ src);
955     if (hi < 0) {
956     hi = ~hi;
957     lo = -lo;
958     if (lo == 0) hi++;
959     }
960     if ((uae_s32)src < 0) src = -src;
961     if (div_unsigned(hi, lo, src, &quot, &rem) ||
962     (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
963     SET_VFLG (1);
964     SET_NFLG (1);
965     SET_CFLG (0);
966     } else {
967     if (sign & 0x80000000) quot = -quot;
968     if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
969     SET_VFLG (0);
970     SET_CFLG (0);
971     SET_ZFLG (((uae_s32)quot) == 0);
972     SET_NFLG (((uae_s32)quot) < 0);
973     m68k_dreg(regs, extra & 7) = rem;
974     m68k_dreg(regs, (extra >> 12) & 7) = quot;
975     }
976     } else {
977     /* unsigned */
978     uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
979     uae_u32 hi = 0;
980     uae_u32 quot, rem;
981    
982     if (extra & 0x400) {
983     hi = (uae_u32)m68k_dreg(regs, extra & 7);
984     }
985     if (div_unsigned(hi, lo, src, &quot, &rem)) {
986     SET_VFLG (1);
987     SET_NFLG (1);
988     SET_CFLG (0);
989     } else {
990     SET_VFLG (0);
991     SET_CFLG (0);
992     SET_ZFLG (((uae_s32)quot) == 0);
993     SET_NFLG (((uae_s32)quot) < 0);
994     m68k_dreg(regs, extra & 7) = rem;
995     m68k_dreg(regs, (extra >> 12) & 7) = quot;
996     }
997     }
998     #endif
999     }
1000    
1001     static __inline__ void
1002     mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1003     {
1004     uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1005     uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1006     uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1007     uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1008     uae_u32 lo;
1009    
1010     lo = r0 + ((r1 << 16) & 0xffff0000ul);
1011     if (lo < r0) r3++;
1012     r0 = lo;
1013     lo = r0 + ((r2 << 16) & 0xffff0000ul);
1014     if (lo < r0) r3++;
1015     r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1016     *dst_lo = lo;
1017     *dst_hi = r3;
1018     }
1019    
1020     void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1021     {
1022     #if defined(uae_s64)
1023     if (extra & 0x800) {
1024     /* signed variant */
1025     uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1026    
1027     a *= (uae_s64)(uae_s32)src;
1028     SET_VFLG (0);
1029     SET_CFLG (0);
1030     SET_ZFLG (a == 0);
1031     SET_NFLG (a < 0);
1032     if (extra & 0x400)
1033     m68k_dreg(regs, extra & 7) = a >> 32;
1034     else if ((a & UVAL64(0xffffffff80000000)) != 0
1035     && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1036     {
1037     SET_VFLG (1);
1038     }
1039     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1040     } else {
1041     /* unsigned */
1042     uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1043    
1044     a *= (uae_u64)src;
1045     SET_VFLG (0);
1046     SET_CFLG (0);
1047     SET_ZFLG (a == 0);
1048     SET_NFLG (((uae_s64)a) < 0);
1049     if (extra & 0x400)
1050     m68k_dreg(regs, extra & 7) = a >> 32;
1051     else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1052     SET_VFLG (1);
1053     }
1054     m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1055     }
1056     #else
1057     if (extra & 0x800) {
1058     /* signed variant */
1059     uae_s32 src1,src2;
1060     uae_u32 dst_lo,dst_hi;
1061     uae_u32 sign;
1062    
1063     src1 = (uae_s32)src;
1064     src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1065     sign = (src1 ^ src2);
1066     if (src1 < 0) src1 = -src1;
1067     if (src2 < 0) src2 = -src2;
1068     mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1069     if (sign & 0x80000000) {
1070     dst_hi = ~dst_hi;
1071     dst_lo = -dst_lo;
1072     if (dst_lo == 0) dst_hi++;
1073     }
1074     SET_VFLG (0);
1075     SET_CFLG (0);
1076     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1077     SET_NFLG (((uae_s32)dst_hi) < 0);
1078     if (extra & 0x400)
1079     m68k_dreg(regs, extra & 7) = dst_hi;
1080     else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1081     && ((dst_hi & 0xffffffff) != 0xffffffff
1082     || (dst_lo & 0x80000000) != 0x80000000))
1083     {
1084     SET_VFLG (1);
1085     }
1086     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1087     } else {
1088     /* unsigned */
1089     uae_u32 dst_lo,dst_hi;
1090    
1091     mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1092    
1093     SET_VFLG (0);
1094     SET_CFLG (0);
1095     SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1096     SET_NFLG (((uae_s32)dst_hi) < 0);
1097     if (extra & 0x400)
1098     m68k_dreg(regs, extra & 7) = dst_hi;
1099     else if (dst_hi != 0) {
1100     SET_VFLG (1);
1101     }
1102     m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1103     }
1104     #endif
1105     }
1106     static char* ccnames[] =
1107     { "T ","F ","HI","LS","CC","CS","NE","EQ",
1108     "VC","VS","PL","MI","GE","LT","GT","LE" };
1109    
1110     void m68k_reset (void)
1111     {
1112     m68k_areg (regs, 7) = 0x2000;
1113     m68k_setpc (ROMBaseMac + 0x2a);
1114     fill_prefetch_0 ();
1115     regs.kick_mask = 0xF80000;
1116     regs.s = 1;
1117     regs.m = 0;
1118     regs.stopped = 0;
1119     regs.t1 = 0;
1120     regs.t0 = 0;
1121     SET_ZFLG (0);
1122     SET_XFLG (0);
1123     SET_CFLG (0);
1124     SET_VFLG (0);
1125     SET_NFLG (0);
1126     regs.spcflags = 0;
1127     regs.intmask = 7;
1128     regs.vbr = regs.sfc = regs.dfc = 0;
1129 gbeauche 1.6 /* gb-- moved into {fpp,fpu_x86}.cpp::fpu_init()
1130     regs.fpcr = regs.fpsr = regs.fpiar = 0; */
1131     fpu_reset();
1132 gbeauche 1.10
1133     #if FLIGHT_RECORDER
1134     #if ENABLE_MON
1135     if (log_ptr == -1) {
1136     // Install "log" command in mon
1137     mon_add_command("log", dump_log, "log Dump m68k emulation log\n");
1138     }
1139     #endif
1140     log_ptr = 0;
1141     memset(log, 0, sizeof(log));
1142     #endif
1143 cebix 1.1 }
1144    
1145 cebix 1.4 void REGPARAM2 op_illg (uae_u32 opcode)
1146 cebix 1.1 {
1147     uaecptr pc = m68k_getpc ();
1148    
1149     if ((opcode & 0xFF00) == 0x7100) {
1150     struct M68kRegisters r;
1151     int i;
1152    
1153 gbeauche 1.9 // Return from Exectue68k()?
1154 cebix 1.1 if (opcode == M68K_EXEC_RETURN) {
1155     regs.spcflags |= SPCFLAG_BRK;
1156     quit_program = 1;
1157 cebix 1.4 return;
1158 cebix 1.1 }
1159    
1160     // Call EMUL_OP opcode
1161     for (i=0; i<8; i++) {
1162     r.d[i] = m68k_dreg(regs, i);
1163     r.a[i] = m68k_areg(regs, i);
1164     }
1165     MakeSR();
1166     r.sr = regs.sr;
1167     EmulOp(opcode, &r);
1168     for (i=0; i<8; i++) {
1169     m68k_dreg(regs, i) = r.d[i];
1170     m68k_areg(regs, i) = r.a[i];
1171     }
1172     regs.sr = r.sr;
1173     MakeFromSR();
1174     m68k_incpc(2);
1175     fill_prefetch_0 ();
1176 cebix 1.4 return;
1177 cebix 1.1 }
1178    
1179     if ((opcode & 0xF000) == 0xA000) {
1180     Exception(0xA,0);
1181 cebix 1.4 return;
1182 cebix 1.1 }
1183    
1184 cebix 1.4 // write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1185 cebix 1.3
1186 cebix 1.1 if ((opcode & 0xF000) == 0xF000) {
1187     Exception(0xB,0);
1188 cebix 1.4 return;
1189 cebix 1.1 }
1190    
1191 cebix 1.4 write_log ("Illegal instruction: %04x at %08lx\n", opcode, pc);
1192    
1193 cebix 1.1 Exception (4,0);
1194     }
1195    
1196     void mmu_op(uae_u32 opcode, uae_u16 extra)
1197     {
1198     if ((extra & 0xB000) == 0) { /* PMOVE instruction */
1199    
1200     } else if ((extra & 0xF000) == 0x2000) { /* PLOAD instruction */
1201     } else if ((extra & 0xF000) == 0x8000) { /* PTEST instruction */
1202     } else
1203     op_illg (opcode);
1204     }
1205    
1206     static int n_insns = 0, n_spcinsns = 0;
1207    
1208     static uaecptr last_trace_ad = 0;
1209    
1210     static void do_trace (void)
1211     {
1212 gbeauche 1.9 if (regs.t0 && CPUType >= 2) {
1213 cebix 1.1 uae_u16 opcode;
1214     /* should also include TRAP, CHK, SR modification FPcc */
1215     /* probably never used so why bother */
1216     /* We can afford this to be inefficient... */
1217     m68k_setpc (m68k_getpc ());
1218     fill_prefetch_0 ();
1219     opcode = get_word (regs.pc);
1220     if (opcode == 0x4e72 /* RTE */
1221     || opcode == 0x4e74 /* RTD */
1222     || opcode == 0x4e75 /* RTS */
1223     || opcode == 0x4e77 /* RTR */
1224     || opcode == 0x4e76 /* TRAPV */
1225     || (opcode & 0xffc0) == 0x4e80 /* JSR */
1226     || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1227     || (opcode & 0xff00) == 0x6100 /* BSR */
1228     || ((opcode & 0xf000) == 0x6000 /* Bcc */
1229     && cctrue((opcode >> 8) & 0xf))
1230     || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1231     && !cctrue((opcode >> 8) & 0xf)
1232     && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1233     {
1234     last_trace_ad = m68k_getpc ();
1235     regs.spcflags &= ~SPCFLAG_TRACE;
1236     regs.spcflags |= SPCFLAG_DOTRACE;
1237     }
1238     } else if (regs.t1) {
1239     last_trace_ad = m68k_getpc ();
1240     regs.spcflags &= ~SPCFLAG_TRACE;
1241     regs.spcflags |= SPCFLAG_DOTRACE;
1242     }
1243     }
1244    
1245    
1246     static int do_specialties (void)
1247     {
1248     /*n_spcinsns++;*/
1249     if (regs.spcflags & SPCFLAG_DOTRACE) {
1250     Exception (9,last_trace_ad);
1251     }
1252     while (regs.spcflags & SPCFLAG_STOP) {
1253     if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)){
1254     int intr = intlev ();
1255     regs.spcflags &= ~(SPCFLAG_INT | SPCFLAG_DOINT);
1256     if (intr != -1 && intr > regs.intmask) {
1257     Interrupt (intr);
1258     regs.stopped = 0;
1259     regs.spcflags &= ~SPCFLAG_STOP;
1260     }
1261     }
1262     }
1263     if (regs.spcflags & SPCFLAG_TRACE)
1264     do_trace ();
1265    
1266     if (regs.spcflags & SPCFLAG_DOINT) {
1267     int intr = intlev ();
1268     regs.spcflags &= ~SPCFLAG_DOINT;
1269     if (intr != -1 && intr > regs.intmask) {
1270     Interrupt (intr);
1271     regs.stopped = 0;
1272     }
1273     }
1274     if (regs.spcflags & SPCFLAG_INT) {
1275     regs.spcflags &= ~SPCFLAG_INT;
1276     regs.spcflags |= SPCFLAG_DOINT;
1277     }
1278     if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1279     regs.spcflags &= ~(SPCFLAG_BRK | SPCFLAG_MODE_CHANGE);
1280     return 1;
1281     }
1282     return 0;
1283     }
1284    
1285     static void m68k_run_1 (void)
1286     {
1287 cebix 1.4 for (;;) {
1288     uae_u32 opcode = GET_OPCODE;
1289 gbeauche 1.10 #if FLIGHT_RECORDER
1290     record_step(m68k_getpc());
1291     #endif
1292 cebix 1.4 (*cpufunctbl[opcode])(opcode);
1293     if (regs.spcflags) {
1294     if (do_specialties())
1295     return;
1296     }
1297 cebix 1.1 }
1298     }
1299    
1300     #define m68k_run1 m68k_run_1
1301    
1302     int in_m68k_go = 0;
1303    
1304     void m68k_go (int may_quit)
1305     {
1306     // m68k_go() must be reentrant for Execute68k() and Execute68kTrap() to work
1307     /*
1308     if (in_m68k_go || !may_quit) {
1309     write_log("Bug! m68k_go is not reentrant.\n");
1310     abort();
1311     }
1312     */
1313     in_m68k_go++;
1314     for (;;) {
1315     if (quit_program > 0) {
1316     if (quit_program == 1)
1317     break;
1318     quit_program = 0;
1319     m68k_reset ();
1320     }
1321     m68k_run1();
1322     }
1323     if (debugging) {
1324     uaecptr nextpc;
1325     m68k_dumpstate(&nextpc);
1326     exit(1);
1327     }
1328     in_m68k_go--;
1329     }
1330    
1331     static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1332     {
1333     uae_u32 opcode, val;
1334     struct instr *dp;
1335    
1336     opcode = get_iword_1(0);
1337     last_op_for_exception_3 = opcode;
1338     m68kpc_offset = 2;
1339    
1340     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1341     opcode = 0x4AFC;
1342     }
1343     dp = table68k + opcode;
1344    
1345     if (dp->suse) {
1346     if (!verify_ea (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, &val)) {
1347     Exception (3, 0);
1348     return;
1349     }
1350     }
1351     if (dp->duse) {
1352     if (!verify_ea (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, &val)) {
1353     Exception (3, 0);
1354     return;
1355     }
1356     }
1357     }
1358    
1359     void m68k_disasm (uaecptr addr, uaecptr *nextpc, int cnt)
1360     {
1361     uaecptr newpc = 0;
1362     m68kpc_offset = addr - m68k_getpc ();
1363     while (cnt-- > 0) {
1364     char instrname[20],*ccpt;
1365     int opwords;
1366     uae_u32 opcode;
1367     struct mnemolookup *lookup;
1368     struct instr *dp;
1369     printf ("%08lx: ", m68k_getpc () + m68kpc_offset);
1370     for (opwords = 0; opwords < 5; opwords++){
1371     printf ("%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1372     }
1373     opcode = get_iword_1 (m68kpc_offset);
1374     m68kpc_offset += 2;
1375     if (cpufunctbl[cft_map (opcode)] == op_illg_1) {
1376     opcode = 0x4AFC;
1377     }
1378     dp = table68k + opcode;
1379     for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1380     ;
1381    
1382     strcpy (instrname, lookup->name);
1383     ccpt = strstr (instrname, "cc");
1384     if (ccpt != 0) {
1385     strncpy (ccpt, ccnames[dp->cc], 2);
1386     }
1387     printf ("%s", instrname);
1388     switch (dp->size){
1389     case sz_byte: printf (".B "); break;
1390     case sz_word: printf (".W "); break;
1391     case sz_long: printf (".L "); break;
1392     default: printf (" "); break;
1393     }
1394    
1395     if (dp->suse) {
1396     newpc = m68k_getpc () + m68kpc_offset;
1397     newpc += ShowEA (dp->sreg, (amodes)dp->smode, (wordsizes)dp->size, 0);
1398     }
1399     if (dp->suse && dp->duse)
1400     printf (",");
1401     if (dp->duse) {
1402     newpc = m68k_getpc () + m68kpc_offset;
1403     newpc += ShowEA (dp->dreg, (amodes)dp->dmode, (wordsizes)dp->size, 0);
1404     }
1405     if (ccpt != 0) {
1406     if (cctrue(dp->cc))
1407     printf (" == %08lx (TRUE)", newpc);
1408     else
1409     printf (" == %08lx (FALSE)", newpc);
1410     } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1411     printf (" == %08lx", newpc);
1412     printf ("\n");
1413     }
1414     if (nextpc)
1415     *nextpc = m68k_getpc () + m68kpc_offset;
1416     }
1417    
1418     void m68k_dumpstate (uaecptr *nextpc)
1419     {
1420     int i;
1421     for (i = 0; i < 8; i++){
1422     printf ("D%d: %08lx ", i, m68k_dreg(regs, i));
1423     if ((i & 3) == 3) printf ("\n");
1424     }
1425     for (i = 0; i < 8; i++){
1426     printf ("A%d: %08lx ", i, m68k_areg(regs, i));
1427     if ((i & 3) == 3) printf ("\n");
1428     }
1429     if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1430     if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1431     if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1432     printf ("USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1433     regs.usp,regs.isp,regs.msp,regs.vbr);
1434     printf ("T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1435     regs.t1, regs.t0, regs.s, regs.m,
1436     GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1437     for (i = 0; i < 8; i++){
1438     printf ("FP%d: %g ", i, regs.fp[i]);
1439     if ((i & 3) == 3) printf ("\n");
1440     }
1441     printf ("N=%d Z=%d I=%d NAN=%d\n",
1442     (regs.fpsr & 0x8000000) != 0,
1443     (regs.fpsr & 0x4000000) != 0,
1444     (regs.fpsr & 0x2000000) != 0,
1445     (regs.fpsr & 0x1000000) != 0);
1446    
1447     m68k_disasm(m68k_getpc (), nextpc, 1);
1448     if (nextpc)
1449     printf ("next PC: %08lx\n", *nextpc);
1450     }