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/* |
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* fpu/core.h - base fpu context definition |
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* |
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* Basilisk II (C) 1997-1999 Christian Bauer |
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* |
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* MC68881/68040 fpu emulation |
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* |
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* Original UAE FPU, copyright 1996 Herman ten Brugge |
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* Rewrite for x86, copyright 1999-2000 Lauri Pesonen |
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* New framework, copyright 2000 Gwenole Beauchesne |
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* Adapted for JIT compilation (c) Bernd Meyer, 2000 |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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|
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#ifndef FPU_CORE_H |
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#define FPU_CORE_H |
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|
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#include "sysdeps.h" |
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#include "fpu/types.h" |
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|
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/* ========================================================================== */ |
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/* ========================= FPU CONTEXT DEFINITION ========================= */ |
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/* ========================================================================== */ |
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|
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/* We don't use all features of the C++ language so that we may still |
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* easily backport that code to C. |
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*/ |
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|
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struct fpu_t { |
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|
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/* ---------------------------------------------------------------------- */ |
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/* --- Floating-Point Data Registers --- */ |
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/* ---------------------------------------------------------------------- */ |
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|
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/* The eight %fp0 .. %fp7 registers */ |
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fpu_register registers[8]; |
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|
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/* Used for lazy evalualation of FPU flags */ |
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fpu_register result; |
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|
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/* ---------------------------------------------------------------------- */ |
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/* --- Floating-Point Control Register --- */ |
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/* ---------------------------------------------------------------------- */ |
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|
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struct { |
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|
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/* Exception Enable Byte */ |
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uae_u32 exception_enable; |
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#define FPCR_EXCEPTION_ENABLE 0x0000ff00 |
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#define FPCR_EXCEPTION_BSUN 0x00008000 |
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#define FPCR_EXCEPTION_SNAN 0x00004000 |
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#define FPCR_EXCEPTION_OPERR 0x00002000 |
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#define FPCR_EXCEPTION_OVFL 0x00001000 |
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#define FPCR_EXCEPTION_UNFL 0x00000800 |
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#define FPCR_EXCEPTION_DZ 0x00000400 |
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#define FPCR_EXCEPTION_INEX2 0x00000200 |
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#define FPCR_EXCEPTION_INEX1 0x00000100 |
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|
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/* Mode Control Byte Mask */ |
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#define FPCR_MODE_CONTROL 0x000000ff |
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|
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/* Rounding precision */ |
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uae_u32 rounding_precision; |
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#define FPCR_ROUNDING_PRECISION 0x000000c0 |
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#define FPCR_PRECISION_SINGLE 0x00000040 |
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#define FPCR_PRECISION_DOUBLE 0x00000080 |
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#define FPCR_PRECISION_EXTENDED 0x00000000 |
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|
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/* Rounding mode */ |
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uae_u32 rounding_mode; |
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#define FPCR_ROUNDING_MODE 0x00000030 |
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#define FPCR_ROUND_NEAR 0x00000000 |
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#define FPCR_ROUND_ZERO 0x00000010 |
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#define FPCR_ROUND_MINF 0x00000020 |
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#define FPCR_ROUND_PINF 0x00000030 |
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|
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} fpcr; |
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|
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/* ---------------------------------------------------------------------- */ |
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/* --- Floating-Point Status Register --- */ |
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/* ---------------------------------------------------------------------- */ |
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|
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struct { |
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|
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/* Floating-Point Condition Code Byte */ |
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uae_u32 condition_codes; |
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#define FPSR_CCB 0xff000000 |
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#define FPSR_CCB_NEGATIVE 0x08000000 |
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#define FPSR_CCB_ZERO 0x04000000 |
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#define FPSR_CCB_INFINITY 0x02000000 |
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#define FPSR_CCB_NAN 0x01000000 |
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|
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/* Quotient Byte */ |
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uae_u32 quotient; |
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#define FPSR_QUOTIENT 0x00ff0000 |
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#define FPSR_QUOTIENT_SIGN 0x00800000 |
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#define FPSR_QUOTIENT_VALUE 0x007f0000 |
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|
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/* Exception Status Byte */ |
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uae_u32 exception_status; |
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#define FPSR_EXCEPTION_STATUS FPCR_EXCEPTION_ENABLE |
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#define FPSR_EXCEPTION_BSUN FPCR_EXCEPTION_BSUN |
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#define FPSR_EXCEPTION_SNAN FPCR_EXCEPTION_SNAN |
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#define FPSR_EXCEPTION_OPERR FPCR_EXCEPTION_OPERR |
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#define FPSR_EXCEPTION_OVFL FPCR_EXCEPTION_OVFL |
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#define FPSR_EXCEPTION_UNFL FPCR_EXCEPTION_UNFL |
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#define FPSR_EXCEPTION_DZ FPCR_EXCEPTION_DZ |
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#define FPSR_EXCEPTION_INEX2 FPCR_EXCEPTION_INEX2 |
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#define FPSR_EXCEPTION_INEX1 FPCR_EXCEPTION_INEX1 |
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|
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/* Accrued Exception Byte */ |
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uae_u32 accrued_exception; |
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#define FPSR_ACCRUED_EXCEPTION 0x000000ff |
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#define FPSR_ACCR_IOP 0x00000080 |
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#define FPSR_ACCR_OVFL 0x00000040 |
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#define FPSR_ACCR_UNFL 0x00000020 |
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#define FPSR_ACCR_DZ 0x00000010 |
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#define FPSR_ACCR_INEX 0x00000008 |
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|
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} fpsr; |
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|
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/* ---------------------------------------------------------------------- */ |
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/* --- Floating-Point Instruction Address Register --- */ |
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/* ---------------------------------------------------------------------- */ |
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|
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uae_u32 instruction_address; |
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|
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/* ---------------------------------------------------------------------- */ |
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/* --- Initialization / Finalization --- */ |
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/* ---------------------------------------------------------------------- */ |
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|
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/* Flag set if we emulate an integral 68040 FPU */ |
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bool is_integral; |
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|
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/* ---------------------------------------------------------------------- */ |
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/* --- Extra FPE-dependant defines --- */ |
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/* ---------------------------------------------------------------------- */ |
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|
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#if defined(FPU_X86) \ |
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|| (defined(FPU_UAE) && defined(X86_ASSEMBLY)) \ |
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|| (defined(FPU_IEEE) && defined(X86_ASSEMBLY)) |
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|
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#define CW_RESET 0x0040 // initial CW value after RESET |
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#define CW_FINIT 0x037F // initial CW value after FINIT |
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#define SW_RESET 0x0000 // initial SW value after RESET |
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#define SW_FINIT 0x0000 // initial SW value after FINIT |
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#define TW_RESET 0x5555 // initial TW value after RESET |
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#define TW_FINIT 0x0FFF // initial TW value after FINIT |
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|
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#define CW_X 0x1000 // infinity control |
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#define CW_RC_ZERO 0x0C00 // rounding control toward zero |
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#define CW_RC_UP 0x0800 // rounding control toward + |
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#define CW_RC_DOWN 0x0400 // rounding control toward - |
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#define CW_RC_NEAR 0x0000 // rounding control toward even |
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#define CW_PC_EXTENDED 0x0300 // precision control 64bit |
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#define CW_PC_DOUBLE 0x0200 // precision control 53bit |
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#define CW_PC_RESERVED 0x0100 // precision control reserved |
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#define CW_PC_SINGLE 0x0000 // precision control 24bit |
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#define CW_PM 0x0020 // precision exception mask |
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#define CW_UM 0x0010 // underflow exception mask |
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#define CW_OM 0x0008 // overflow exception mask |
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#define CW_ZM 0x0004 // zero divide exception mask |
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#define CW_DM 0x0002 // denormalized operand exception mask |
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#define CW_IM 0x0001 // invalid operation exception mask |
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|
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#define SW_B 0x8000 // busy flag |
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#define SW_C3 0x4000 // condition code flag 3 |
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#define SW_TOP_7 0x3800 // top of stack = ST(7) |
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#define SW_TOP_6 0x3000 // top of stack = ST(6) |
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#define SW_TOP_5 0x2800 // top of stack = ST(5) |
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#define SW_TOP_4 0x2000 // top of stack = ST(4) |
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#define SW_TOP_3 0x1800 // top of stack = ST(3) |
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#define SW_TOP_2 0x1000 // top of stack = ST(2) |
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#define SW_TOP_1 0x0800 // top of stack = ST(1) |
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#define SW_TOP_0 0x0000 // top of stack = ST(0) |
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#define SW_C2 0x0400 // condition code flag 2 |
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#define SW_C1 0x0200 // condition code flag 1 |
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#define SW_C0 0x0100 // condition code flag 0 |
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#define SW_ES 0x0080 // error summary status flag |
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#define SW_SF 0x0040 // stack fault flag |
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#define SW_PE 0x0020 // precision exception flag |
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#define SW_UE 0x0010 // underflow exception flag |
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#define SW_OE 0x0008 // overflow exception flag |
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#define SW_ZE 0x0004 // zero divide exception flag |
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#define SW_DE 0x0002 // denormalized operand exception flag |
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#define SW_IE 0x0001 // invalid operation exception flag |
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|
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#define X86_ROUNDING_MODE 0x0C00 |
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#define X86_ROUNDING_PRECISION 0x0300 |
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|
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#endif /* FPU_X86 */ |
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|
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}; |
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|
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/* We handle only one global fpu */ |
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extern fpu_t fpu; |
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|
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/* Return the address of a particular register */ |
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inline fpu_register * const fpu_register_address(int i) |
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{ return &fpu.registers[i]; } |
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|
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/* Dump functions for m68k_dumpstate */ |
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extern void fpu_dump_registers(void); |
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extern void fpu_dump_flags(void); |
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|
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/* Accessors to FPU Control Register */ |
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extern inline uae_u32 get_fpcr(void); |
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extern inline void set_fpcr(uae_u32 new_fpcr); |
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|
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/* Accessors to FPU Status Register */ |
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extern inline uae_u32 get_fpsr(void); |
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extern void set_fpsr(uae_u32 new_fpsr); |
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|
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/* Accessors to FPU Instruction Address Register */ |
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extern inline uae_u32 get_fpiar(); |
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extern inline void set_fpiar(uae_u32 new_fpiar); |
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|
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/* Initialization / Finalization */ |
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extern void fpu_init(bool integral_68040); |
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extern void fpu_exit(void); |
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extern void fpu_reset(void); |
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|
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/* Floating-point arithmetic instructions */ |
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void fpuop_arithmetic(uae_u32 opcode, uae_u32 extra) REGPARAM; |
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|
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/* Floating-point program control operations */ |
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void fpuop_bcc(uae_u32 opcode, uaecptr pc, uae_u32 extra) REGPARAM; |
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void fpuop_dbcc(uae_u32 opcode, uae_u32 extra) REGPARAM; |
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void fpuop_scc(uae_u32 opcode, uae_u32 extra) REGPARAM; |
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|
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/* Floating-point system control operations */ |
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void fpuop_save(uae_u32 opcode) REGPARAM; |
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void fpuop_restore(uae_u32 opcode) REGPARAM; |
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void fpuop_trapcc(uae_u32 opcode, uaecptr oldpc) REGPARAM; |
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|
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#endif /* FPU_CORE_H */ |
