icc9.1 & gcc4.1 warning fixes

Revision 1.22 - (view) (annotate) - [select for diffs]
2006-07-17T04:07:41Z (17 years, 11 months ago) by gbeauche
Branch: MAIN
Changes since 1.21: +102 -0 lines
Diff to previous 1.21

Add LEALQmr, EMMS, SSE CMP and a series of new SSE opcodes (auto-generated)

Add more SSE templates for new SheepShaver's code generator -- though it
should be made independent of this file.

Revision 1.20 - (view) (annotate) - [select for diffs]
2006-07-14T09:09:12Z (17 years, 11 months ago) by gbeauche
Branch: MAIN
Changes since 1.19: +13 -12 lines
Diff to previous 1.19

Run-time assembler fixes:
- Check for RIP register only in 64-bit mode
- Add missing macros and arguments (BT*im)
- MOVSWQ/MOVZWQ are 64-bit mode instructions only

Cosmetics, fix %rh cases in !X86_FLAT_REGISTERS mode, lahf/sahf are now
valid instructions in long mode (recent enough CPU revisions: lahf_lm).

Revision 1.18 - (view) (annotate) - [select for diffs]
2005-04-24T23:00:08Z (19 years, 2 months ago) by gbeauche
Branch: MAIN
CVS Tags: nigel-build-17
Changes since 1.17: +4 -4 lines
Diff to previous 1.17

Fix build with gcc4 on x86-64: ignore errors when casting pointers to int
from regs & fpu members + code cache. This is possible because data is
allocated in 32-bit space and we force allocation of translation cache to
those bounds too.

Happy New Year!

Revision 1.16 - (view) (annotate) - [select for diffs]
2004-11-08T20:48:19Z (19 years, 8 months ago) by gbeauche
Branch: MAIN
Changes since 1.15: +8 -2 lines
Diff to previous 1.15

Enable RIP-relative addressing, optimize REX conditions processing in
! X86_FLAT_REGISTERS mode, fix __REX_mem encodings (e.g. POPLm)

- optimize absolute addresses into RIP relative, if possible
- fix MOVQir as the operand is 64-bit
- fix IMULWrr, IMULLrr, IMULQrr, MOVSBWrr, MOVZBWrr

Revision 1.14 - (view) (annotate) - [select for diffs]
2004-10-31T16:02:04Z (19 years, 8 months ago) by gbeauche
Branch: MAIN
Changes since 1.13: +9 -7 lines
Diff to previous 1.13

Reorder SPL, BPL, SIL, DIL IDs so that 8-bit register allocation is simpler
Fix MOVZBL and MOVSBL encodings with those extended 8-bit registers

fix SIB encoding with base=r13
fix PUSH/POP with x86_64 extended registers
fix CALL/JMP REX prefixes

Revision 1.12 - (view) (annotate) - [select for diffs]
2004-01-12T15:29:30Z (20 years, 6 months ago) by cebix
Branch: MAIN
CVS Tags: nigel-build-15, nigel-build-16
Changes since 1.11: +1 -1 lines
Diff to previous 1.11

Happy New Year! :)

- Fix "extended register" predicate to exclude X86_NOREG and X86_RIP
- Really handle requested 32-bit absolute address in AMD64 target
- Fix REX prefixes in 16-bit ALU instructions
- Fix POPF, remove useless? POPFD and PUSHFD

Revision 1.10 - (view) (annotate) - [select for diffs]
2003-03-19T17:06:22Z (21 years, 3 months ago) by gbeauche
Branch: MAIN
CVS Tags: nigel-build-12, nigel-build-13
Changes since 1.9: +17 -6 lines
Diff to previous 1.9

Optimize TEST[BWLQ]ir case where dest register is %rax
Add JCCSii and JCCii which directly takes the displacement value to encode

Fix MOVBrr

Revision 1.8 - (view) (annotate) - [select for diffs]
2003-03-19T11:34:10Z (21 years, 3 months ago) by gbeauche
Branch: MAIN
Changes since 1.7: +1 -1 lines
Diff to previous 1.7

Fix 0(%rbp,<reg>,1) operand encoding

Add sign/zero-extend instructions

Revision 1.6 - (view) (annotate) - [select for diffs]
2003-03-18T16:28:23Z (21 years, 3 months ago) by gbeauche
Branch: MAIN
Changes since 1.5: +26 -23 lines
Diff to previous 1.5

Fix _REXBmr(). Add CPUID. Some C++ compiler fixes. Make x86_emit_failure()
be void, and let x86_emit_failure0() be an int expression instead.

Add CMOV and BSF/BSR instructions

Revision 1.4 - (view) (annotate) - [select for diffs]
2003-03-18T10:08:16Z (21 years, 3 months ago) by gbeauche
Branch: MAIN
Changes since 1.3: +13 -3 lines
Diff to previous 1.3

Handle absolute and RIP addressing modes in x86-64

Add some SSE/SSE2 instructions

Revision 1.2 - (view) (annotate) - [select for diffs]
2003-01-31T23:48:10Z (21 years, 5 months ago) by gbeauche
Branch: MAIN
Changes since 1.1: +119 -22 lines
Diff to previous 1.1

Add some FPU instructions. Minor clean-ups.

Add new run-time assembler derived from GNU lightning. It is suitable for
both i386 and x86-64 architectures. Still needs some work (see TODO) and
an actual glue to the JIT backend.

Original work is LGPL, but per section 3 of this license, I opt for GPL v2
for Basilisk II purposes.