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root/cebix/BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp
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Comparing BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp (file contents):
Revision 1.6 by gbeauche, 2002-10-03T16:13:46Z vs.
Revision 1.37 by gbeauche, 2007-01-14T13:07:22Z

# Line 3 | Line 3
3   *
4   *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
5   *
6 < *  Adaptation for Basilisk II and improvements, copyright 2000-2002
6 > *  Adaptation for Basilisk II and improvements, copyright 2000-2005
7   *    Gwenole Beauchesne
8   *
9 < *  Basilisk II (C) 1997-2002 Christian Bauer
9 > *  Basilisk II (C) 1997-2005 Christian Bauer
10 > *
11 > *  Portions related to CPU detection come from linux/arch/i386/kernel/setup.c
12   *  
13   *  This program is free software; you can redistribute it and/or modify
14   *  it under the terms of the GNU General Public License as published by
# Line 40 | Line 42
42   #define EBP_INDEX 5
43   #define ESI_INDEX 6
44   #define EDI_INDEX 7
45 + #if defined(__x86_64__)
46 + #define R8_INDEX  8
47 + #define R9_INDEX  9
48 + #define R10_INDEX 10
49 + #define R11_INDEX 11
50 + #define R12_INDEX 12
51 + #define R13_INDEX 13
52 + #define R14_INDEX 14
53 + #define R15_INDEX 15
54 + #endif
55 + /* XXX this has to match X86_Reg8H_Base + 4 */
56 + #define AH_INDEX (0x10+4+EAX_INDEX)
57 + #define CH_INDEX (0x10+4+ECX_INDEX)
58 + #define DH_INDEX (0x10+4+EDX_INDEX)
59 + #define BH_INDEX (0x10+4+EBX_INDEX)
60  
61   /* The register in which subroutines return an integer return value */
62 < #define REG_RESULT 0
62 > #define REG_RESULT EAX_INDEX
63  
64   /* The registers subroutines take their first and second argument in */
65   #if defined( _MSC_VER ) && !defined( USE_NORMAL_CALLING_CONVENTION )
66   /* Handle the _fastcall parameters of ECX and EDX */
67 < #define REG_PAR1 1
68 < #define REG_PAR2 2
67 > #define REG_PAR1 ECX_INDEX
68 > #define REG_PAR2 EDX_INDEX
69 > #elif defined(__x86_64__)
70 > #define REG_PAR1 EDI_INDEX
71 > #define REG_PAR2 ESI_INDEX
72   #else
73 < #define REG_PAR1 0
74 < #define REG_PAR2 2
73 > #define REG_PAR1 EAX_INDEX
74 > #define REG_PAR2 EDX_INDEX
75   #endif
76  
77 < /* Three registers that are not used for any of the above */
58 < #define REG_NOPAR1 6
59 < #define REG_NOPAR2 5
60 < #define REG_NOPAR3 3
61 <
62 < #define REG_PC_PRE 0 /* The register we use for preloading regs.pc_p */
77 > #define REG_PC_PRE EAX_INDEX /* The register we use for preloading regs.pc_p */
78   #if defined( _MSC_VER ) && !defined( USE_NORMAL_CALLING_CONVENTION )
79 < #define REG_PC_TMP 0
79 > #define REG_PC_TMP EAX_INDEX
80   #else
81 < #define REG_PC_TMP 1 /* Another register that is not the above */
81 > #define REG_PC_TMP ECX_INDEX /* Another register that is not the above */
82   #endif
83  
84 < #define SHIFTCOUNT_NREG 1  /* Register that can be used for shiftcount.
84 > #define SHIFTCOUNT_NREG ECX_INDEX  /* Register that can be used for shiftcount.
85                                -1 if any reg will do */
86 < #define MUL_NREG1 0 /* %eax will hold the low 32 bits after a 32x32 mul */
87 < #define MUL_NREG2 2 /* %edx will hold the high 32 bits */
86 > #define MUL_NREG1 EAX_INDEX /* %eax will hold the low 32 bits after a 32x32 mul */
87 > #define MUL_NREG2 EDX_INDEX /* %edx will hold the high 32 bits */
88 >
89 > #define STACK_ALIGN             16
90 > #define STACK_OFFSET    sizeof(void *)
91  
92   uae_s8 always_used[]={4,-1};
93 + #if defined(__x86_64__)
94 + uae_s8 can_byte[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
95 + uae_s8 can_word[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
96 + #else
97   uae_s8 can_byte[]={0,1,2,3,-1};
98   uae_s8 can_word[]={0,1,2,3,5,6,7,-1};
99 + #endif
100  
101 + #if USE_OPTIMIZED_CALLS
102 + /* Make sure interpretive core does not use cpuopti */
103 + uae_u8 call_saved[]={0,0,0,1,1,1,1,1};
104 + #error FIXME: code not ready
105 + #else
106   /* cpuopti mutate instruction handlers to assume registers are saved
107     by the caller */
108 < uae_u8 call_saved[]={0,0,0,0,1,0,0,0};
108 > uae_u8 call_saved[]={0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0};
109 > #endif
110  
111   /* This *should* be the same as call_saved. But:
112     - We might not really know which registers are saved, and which aren't,
# Line 86 | Line 115 | uae_u8 call_saved[]={0,0,0,0,1,0,0,0};
115     - Special registers (such like the stack pointer) should not be "preserved"
116       by pushing, even though they are "saved" across function calls
117   */
118 < uae_u8 need_to_preserve[]={1,1,1,1,0,1,1,1};
118 > #if defined(__x86_64__)
119 > /* callee-saved registers as defined by Linux AMD64 ABI: rbx, rbp, rsp, r12 - r15 */
120 > /* preserve r11 because it's generally used to hold pointers to functions */
121 > static const uae_u8 need_to_preserve[]={0,0,0,1,0,1,0,0,0,0,0,1,1,1,1,1};
122 > #else
123 > /* callee-saved registers as defined by System V IA-32 ABI: edi, esi, ebx, ebp */
124 > static const uae_u8 need_to_preserve[]={0,0,0,1,0,1,1,1};
125 > #endif
126  
127   /* Whether classes of instructions do or don't clobber the native flags */
128   #define CLOBBER_MOV
# Line 111 | Line 147 | uae_u8 need_to_preserve[]={1,1,1,1,0,1,1
147   #define CLOBBER_TEST clobber_flags()
148   #define CLOBBER_CL16
149   #define CLOBBER_CL8  
150 + #define CLOBBER_SE32
151   #define CLOBBER_SE16
152   #define CLOBBER_SE8
153 + #define CLOBBER_ZE32
154   #define CLOBBER_ZE16
155   #define CLOBBER_ZE8
156   #define CLOBBER_SW16 clobber_flags()
# Line 122 | Line 160 | uae_u8 need_to_preserve[]={1,1,1,1,0,1,1
160   #define CLOBBER_BT   clobber_flags()
161   #define CLOBBER_BSF  clobber_flags()
162  
163 + /* The older code generator is now deprecated.  */
164 + #define USE_NEW_RTASM 1
165 +
166 + #if USE_NEW_RTASM
167 +
168 + #if defined(__x86_64__)
169 + #define X86_TARGET_64BIT                1
170 + /* The address override prefix causes a 5 cycles penalty on Intel Core
171 +   processors. Another solution would be to decompose the load in an LEA,
172 +   MOV (to zero-extend), MOV (from memory): is it better? */
173 + #define ADDR32                                  x86_emit_byte(0x67),
174 + #else
175 + #define ADDR32                                  /**/
176 + #endif
177 + #define X86_FLAT_REGISTERS              0
178 + #define X86_OPTIMIZE_ALU                1
179 + #define X86_OPTIMIZE_ROTSHI             1
180 + #include "codegen_x86.h"
181 +
182 + #define x86_emit_byte(B)                emit_byte(B)
183 + #define x86_emit_word(W)                emit_word(W)
184 + #define x86_emit_long(L)                emit_long(L)
185 + #define x86_emit_quad(Q)                emit_quad(Q)
186 + #define x86_get_target()                get_target()
187 + #define x86_emit_failure(MSG)   jit_fail(MSG, __FILE__, __LINE__, __FUNCTION__)
188 +
189 + static void jit_fail(const char *msg, const char *file, int line, const char *function)
190 + {
191 +        fprintf(stderr, "JIT failure in function %s from file %s at line %d: %s\n",
192 +                        function, file, line, msg);
193 +        abort();
194 + }
195 +
196 + LOWFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
197 + {
198 + #if defined(__x86_64__)
199 +        PUSHQr(r);
200 + #else
201 +        PUSHLr(r);
202 + #endif
203 + }
204 + LENDFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
205 +
206 + LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
207 + {
208 + #if defined(__x86_64__)
209 +        POPQr(r);
210 + #else
211 +        POPLr(r);
212 + #endif
213 + }
214 + LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
215 +
216 + LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
217 + {
218 + #if defined(__x86_64__)
219 +        POPQm(d, X86_NOREG, X86_NOREG, 1);
220 + #else
221 +        POPLm(d, X86_NOREG, X86_NOREG, 1);
222 + #endif
223 + }
224 + LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
225 +
226 + LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
227 + {
228 +        BTLir(i, r);
229 + }
230 + LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
231 +
232 + LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
233 + {
234 +        BTLrr(b, r);
235 + }
236 + LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
237 +
238 + LOWFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
239 + {
240 +        BTCLir(i, r);
241 + }
242 + LENDFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
243 +
244 + LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
245 + {
246 +        BTCLrr(b, r);
247 + }
248 + LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
249 +
250 + LOWFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
251 + {
252 +        BTRLir(i, r);
253 + }
254 + LENDFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
255 +
256 + LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
257 + {
258 +        BTRLrr(b, r);
259 + }
260 + LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
261 +
262 + LOWFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
263 + {
264 +        BTSLir(i, r);
265 + }
266 + LENDFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
267 +
268 + LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
269 + {
270 +        BTSLrr(b, r);
271 + }
272 + LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
273 +
274 + LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
275 + {
276 +        SUBWir(i, d);
277 + }
278 + LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
279 +
280 + LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
281 + {
282 +        MOVLmr(s, X86_NOREG, X86_NOREG, 1, d);
283 + }
284 + LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
285 +
286 + LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
287 + {
288 +        MOVLim(s, d, X86_NOREG, X86_NOREG, 1);
289 + }
290 + LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
291 +
292 + LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
293 + {
294 +        MOVWim(s, d, X86_NOREG, X86_NOREG, 1);
295 + }
296 + LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
297 +
298 + LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
299 + {
300 +        MOVBim(s, d, X86_NOREG, X86_NOREG, 1);
301 + }
302 + LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
303 +
304 + LOWFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
305 + {
306 +        ROLBim(i, d, X86_NOREG, X86_NOREG, 1);
307 + }
308 + LENDFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
309 +
310 + LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
311 + {
312 +        ROLBir(i, r);
313 + }
314 + LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
315 +
316 + LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
317 + {
318 +        ROLWir(i, r);
319 + }
320 + LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
321 +
322 + LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
323 + {
324 +        ROLLir(i, r);
325 + }
326 + LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
327 +
328 + LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
329 + {
330 +        ROLLrr(r, d);
331 + }
332 + LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
333 +
334 + LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
335 + {
336 +        ROLWrr(r, d);
337 + }
338 + LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
339 +
340 + LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
341 + {
342 +        ROLBrr(r, d);
343 + }
344 + LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
345 +
346 + LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
347 + {
348 +        SHLLrr(r, d);
349 + }
350 + LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
351 +
352 + LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
353 + {
354 +        SHLWrr(r, d);
355 + }
356 + LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
357 +
358 + LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
359 + {
360 +        SHLBrr(r, d);
361 + }
362 + LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
363 +
364 + LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
365 + {
366 +        RORBir(i, r);
367 + }
368 + LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
369 +
370 + LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
371 + {
372 +        RORWir(i, r);
373 + }
374 + LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
375 +
376 + LOWFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
377 + {
378 +        ORLmr(s, X86_NOREG, X86_NOREG, 1, d);
379 + }
380 + LENDFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
381 +
382 + LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
383 + {
384 +        RORLir(i, r);
385 + }
386 + LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
387 +
388 + LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
389 + {
390 +        RORLrr(r, d);
391 + }
392 + LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
393 +
394 + LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
395 + {
396 +        RORWrr(r, d);
397 + }
398 + LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
399 +
400 + LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
401 + {
402 +        RORBrr(r, d);
403 + }
404 + LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
405 +
406 + LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
407 + {
408 +        SHRLrr(r, d);
409 + }
410 + LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
411 +
412 + LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
413 + {
414 +        SHRWrr(r, d);
415 + }
416 + LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
417 +
418 + LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
419 + {
420 +        SHRBrr(r, d);
421 + }
422 + LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
423 +
424 + LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
425 + {
426 +        SARLrr(r, d);
427 + }
428 + LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
429 +
430 + LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
431 + {
432 +        SARWrr(r, d);
433 + }
434 + LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
435 +
436 + LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
437 + {
438 +        SARBrr(r, d);
439 + }
440 + LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
441 +
442 + LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
443 + {
444 +        SHLLir(i, r);
445 + }
446 + LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
447 +
448 + LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
449 + {
450 +        SHLWir(i, r);
451 + }
452 + LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
453 +
454 + LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
455 + {
456 +        SHLBir(i, r);
457 + }
458 + LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
459 +
460 + LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
461 + {
462 +        SHRLir(i, r);
463 + }
464 + LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
465 +
466 + LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
467 + {
468 +        SHRWir(i, r);
469 + }
470 + LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
471 +
472 + LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
473 + {
474 +        SHRBir(i, r);
475 + }
476 + LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
477 +
478 + LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
479 + {
480 +        SARLir(i, r);
481 + }
482 + LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
483 +
484 + LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
485 + {
486 +        SARWir(i, r);
487 + }
488 + LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
489 +
490 + LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
491 + {
492 +        SARBir(i, r);
493 + }
494 + LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
495 +
496 + LOWFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
497 + {
498 +        SAHF();
499 + }
500 + LENDFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
501 +
502 + LOWFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
503 + {
504 +        CPUID();
505 + }
506 + LENDFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
507 +
508 + LOWFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
509 + {
510 +        LAHF();
511 + }
512 + LENDFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
513 +
514 + LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
515 + {
516 +        SETCCir(cc, d);
517 + }
518 + LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
519 +
520 + LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
521 + {
522 +        SETCCim(cc, d, X86_NOREG, X86_NOREG, 1);
523 + }
524 + LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
525 +
526 + LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
527 + {
528 +        if (have_cmov)
529 +                CMOVLrr(cc, s, d);
530 +        else { /* replacement using branch and mov */
531 + #if defined(__x86_64__)
532 +                write_log("x86-64 implementations are bound to have CMOV!\n");
533 +                abort();
534 + #endif
535 +                JCCSii(cc^1, 2);
536 +                MOVLrr(s, d);
537 +        }
538 + }
539 + LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
540 +
541 + LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
542 + {
543 +        BSFLrr(s, d);
544 + }
545 + LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
546 +
547 + LOWFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s))
548 + {
549 +        MOVSLQrr(s, d);
550 + }
551 + LENDFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s))
552 +
553 + LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
554 + {
555 +        MOVSWLrr(s, d);
556 + }
557 + LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
558 +
559 + LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
560 + {
561 +        MOVSBLrr(s, d);
562 + }
563 + LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
564 +
565 + LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
566 + {
567 +        MOVZWLrr(s, d);
568 + }
569 + LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
570 +
571 + LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
572 + {
573 +        MOVZBLrr(s, d);
574 + }
575 + LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
576 +
577 + LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
578 + {
579 +        IMULLrr(s, d);
580 + }
581 + LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
582 +
583 + LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
584 + {
585 +        if (d!=MUL_NREG1 || s!=MUL_NREG2) {
586 +        write_log("Bad register in IMUL: d=%d, s=%d\n",d,s);
587 +        abort();
588 +        }
589 +        IMULLr(s);
590 + }
591 + LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
592 +
593 + LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
594 + {
595 +        if (d!=MUL_NREG1 || s!=MUL_NREG2) {
596 +        write_log("Bad register in MUL: d=%d, s=%d\n",d,s);
597 +        abort();
598 +        }
599 +        MULLr(s);
600 + }
601 + LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
602 +
603 + LOWFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
604 + {
605 +        abort(); /* %^$&%^$%#^ x86! */
606 + }
607 + LENDFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
608 +
609 + LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
610 + {
611 +        MOVBrr(s, d);
612 + }
613 + LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
614 +
615 + LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
616 + {
617 +        MOVWrr(s, d);
618 + }
619 + LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
620 +
621 + LOWFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
622 + {
623 +        ADDR32 MOVLmr(0, baser, index, factor, d);
624 + }
625 + LENDFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
626 +
627 + LOWFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
628 + {
629 +        ADDR32 MOVWmr(0, baser, index, factor, d);
630 + }
631 + LENDFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
632 +
633 + LOWFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
634 + {
635 +        ADDR32 MOVBmr(0, baser, index, factor, d);
636 + }
637 + LENDFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
638 +
639 + LOWFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
640 + {
641 +        ADDR32 MOVLrm(s, 0, baser, index, factor);
642 + }
643 + LENDFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
644 +
645 + LOWFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
646 + {
647 +        ADDR32 MOVWrm(s, 0, baser, index, factor);
648 + }
649 + LENDFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
650 +
651 + LOWFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
652 + {
653 +        ADDR32 MOVBrm(s, 0, baser, index, factor);
654 + }
655 + LENDFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
656 +
657 + LOWFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
658 + {
659 +        ADDR32 MOVLrm(s, base, baser, index, factor);
660 + }
661 + LENDFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
662 +
663 + LOWFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
664 + {
665 +        ADDR32 MOVWrm(s, base, baser, index, factor);
666 + }
667 + LENDFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
668 +
669 + LOWFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
670 + {
671 +        ADDR32 MOVBrm(s, base, baser, index, factor);
672 + }
673 + LENDFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
674 +
675 + LOWFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
676 + {
677 +        ADDR32 MOVLmr(base, baser, index, factor, d);
678 + }
679 + LENDFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
680 +
681 + LOWFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
682 + {
683 +        ADDR32 MOVWmr(base, baser, index, factor, d);
684 + }
685 + LENDFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
686 +
687 + LOWFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
688 + {
689 +        ADDR32 MOVBmr(base, baser, index, factor, d);
690 + }
691 + LENDFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
692 +
693 + LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
694 + {
695 +        ADDR32 MOVLmr(base, X86_NOREG, index, factor, d);
696 + }
697 + LENDFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
698 +
699 + LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
700 + {
701 +        if (have_cmov)
702 +                ADDR32 CMOVLmr(cond, base, X86_NOREG, index, factor, d);
703 +        else { /* replacement using branch and mov */
704 + #if defined(__x86_64__)
705 +                write_log("x86-64 implementations are bound to have CMOV!\n");
706 +                abort();
707 + #endif
708 +                JCCSii(cond^1, 7);
709 +                ADDR32 MOVLmr(base, X86_NOREG, index, factor, d);
710 +        }
711 + }
712 + LENDFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
713 +
714 + LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
715 + {
716 +        if (have_cmov)
717 +                CMOVLmr(cond, mem, X86_NOREG, X86_NOREG, 1, d);
718 +        else { /* replacement using branch and mov */
719 + #if defined(__x86_64__)
720 +                write_log("x86-64 implementations are bound to have CMOV!\n");
721 +                abort();
722 + #endif
723 +                JCCSii(cond^1, 6);
724 +                MOVLmr(mem, X86_NOREG, X86_NOREG, 1, d);
725 +        }
726 + }
727 + LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
728 +
729 + LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
730 + {
731 +        ADDR32 MOVLmr(offset, s, X86_NOREG, 1, d);
732 + }
733 + LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
734 +
735 + LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
736 + {
737 +        ADDR32 MOVWmr(offset, s, X86_NOREG, 1, d);
738 + }
739 + LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
740 +
741 + LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
742 + {
743 +        ADDR32 MOVBmr(offset, s, X86_NOREG, 1, d);
744 + }
745 + LENDFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
746 +
747 + LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
748 + {
749 +        ADDR32 MOVLmr(offset, s, X86_NOREG, 1, d);
750 + }
751 + LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
752 +
753 + LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
754 + {
755 +        ADDR32 MOVWmr(offset, s, X86_NOREG, 1, d);
756 + }
757 + LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
758 +
759 + LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
760 + {
761 +        ADDR32 MOVBmr(offset, s, X86_NOREG, 1, d);
762 + }
763 + LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
764 +
765 + LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
766 + {
767 +        ADDR32 MOVLim(i, offset, d, X86_NOREG, 1);
768 + }
769 + LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
770 +
771 + LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
772 + {
773 +        ADDR32 MOVWim(i, offset, d, X86_NOREG, 1);
774 + }
775 + LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
776 +
777 + LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
778 + {
779 +        ADDR32 MOVBim(i, offset, d, X86_NOREG, 1);
780 + }
781 + LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
782 +
783 + LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
784 + {
785 +        ADDR32 MOVLrm(s, offset, d, X86_NOREG, 1);
786 + }
787 + LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
788 +
789 + LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
790 + {
791 +        ADDR32 MOVWrm(s, offset, d, X86_NOREG, 1);
792 + }
793 + LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
794 +
795 + LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
796 + {
797 +        ADDR32 MOVBrm(s, offset, d, X86_NOREG, 1);
798 + }
799 + LENDFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
800 +
801 + LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
802 + {
803 +        LEALmr(offset, s, X86_NOREG, 1, d);
804 + }
805 + LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
806 +
807 + LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
808 + {
809 +        LEALmr(offset, s, index, factor, d);
810 + }
811 + LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
812 +
813 + LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
814 + {
815 +        LEALmr(0, s, index, factor, d);
816 + }
817 + LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
818 +
819 + LOWFUNC(NONE,NONE,4,raw_lea_l_r_scaled,(W4 d, R4 index, IMM factor))
820 + {
821 +        LEALmr(0, X86_NOREG, index, factor, d);
822 + }
823 + LENDFUNC(NONE,NONE,4,raw_lea_l_r_scaled,(W4 d, R4 index, IMM factor))
824 +
825 + LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
826 + {
827 +        ADDR32 MOVLrm(s, offset, d, X86_NOREG, 1);
828 + }
829 + LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
830 +
831 + LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
832 + {
833 +        ADDR32 MOVWrm(s, offset, d, X86_NOREG, 1);
834 + }
835 + LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
836 +
837 + LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
838 + {
839 +        ADDR32 MOVBrm(s, offset, d, X86_NOREG, 1);
840 + }
841 + LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
842 +
843 + LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
844 + {
845 +        BSWAPLr(r);
846 + }
847 + LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
848 +
849 + LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
850 + {
851 +        ROLWir(8, r);
852 + }
853 + LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
854 +
855 + LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
856 + {
857 +        MOVLrr(s, d);
858 + }
859 + LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
860 +
861 + LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
862 + {
863 +        MOVLrm(s, d, X86_NOREG, X86_NOREG, 1);
864 + }
865 + LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
866 +
867 + LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
868 + {
869 +        MOVWrm(s, d, X86_NOREG, X86_NOREG, 1);
870 + }
871 + LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
872 +
873 + LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
874 + {
875 +        MOVWmr(s, X86_NOREG, X86_NOREG, 1, d);
876 + }
877 + LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
878 +
879 + LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
880 + {
881 +        MOVBrm(s, d, X86_NOREG, X86_NOREG, 1);
882 + }
883 + LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
884 +
885 + LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
886 + {
887 +        MOVBmr(s, X86_NOREG, X86_NOREG, 1, d);
888 + }
889 + LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
890 +
891 + LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
892 + {
893 +        MOVLir(s, d);
894 + }
895 + LENDFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
896 +
897 + LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
898 + {
899 +        MOVWir(s, d);
900 + }
901 + LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
902 +
903 + LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
904 + {
905 +        MOVBir(s, d);
906 + }
907 + LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
908 +
909 + LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
910 + {
911 +        ADCLim(s, d, X86_NOREG, X86_NOREG, 1);
912 + }
913 + LENDFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
914 +
915 + LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s))
916 + {
917 +        ADDLim(s, d, X86_NOREG, X86_NOREG, 1);
918 + }
919 + LENDFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s))
920 +
921 + LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s))
922 + {
923 +        ADDWim(s, d, X86_NOREG, X86_NOREG, 1);
924 + }
925 + LENDFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s))
926 +
927 + LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s))
928 + {
929 +        ADDBim(s, d, X86_NOREG, X86_NOREG, 1);
930 + }
931 + LENDFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s))
932 +
933 + LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
934 + {
935 +        TESTLir(i, d);
936 + }
937 + LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
938 +
939 + LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
940 + {
941 +        TESTLrr(s, d);
942 + }
943 + LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
944 +
945 + LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
946 + {
947 +        TESTWrr(s, d);
948 + }
949 + LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
950 +
951 + LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
952 + {
953 +        TESTBrr(s, d);
954 + }
955 + LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
956 +
957 + LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
958 + {
959 +        XORLir(i, d);
960 + }
961 + LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
962 +
963 + LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
964 + {
965 +        ANDLir(i, d);
966 + }
967 + LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
968 +
969 + LOWFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
970 + {
971 +        ANDWir(i, d);
972 + }
973 + LENDFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
974 +
975 + LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
976 + {
977 +        ANDLrr(s, d);
978 + }
979 + LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
980 +
981 + LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
982 + {
983 +        ANDWrr(s, d);
984 + }
985 + LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
986 +
987 + LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
988 + {
989 +        ANDBrr(s, d);
990 + }
991 + LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
992 +
993 + LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
994 + {
995 +        ORLir(i, d);
996 + }
997 + LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
998 +
999 + LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
1000 + {
1001 +        ORLrr(s, d);
1002 + }
1003 + LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
1004 +
1005 + LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
1006 + {
1007 +        ORWrr(s, d);
1008 + }
1009 + LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
1010 +
1011 + LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
1012 + {
1013 +        ORBrr(s, d);
1014 + }
1015 + LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
1016 +
1017 + LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
1018 + {
1019 +        ADCLrr(s, d);
1020 + }
1021 + LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
1022 +
1023 + LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
1024 + {
1025 +        ADCWrr(s, d);
1026 + }
1027 + LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
1028 +
1029 + LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
1030 + {
1031 +        ADCBrr(s, d);
1032 + }
1033 + LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
1034 +
1035 + LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
1036 + {
1037 +        ADDLrr(s, d);
1038 + }
1039 + LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
1040 +
1041 + LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
1042 + {
1043 +        ADDWrr(s, d);
1044 + }
1045 + LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
1046 +
1047 + LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
1048 + {
1049 +        ADDBrr(s, d);
1050 + }
1051 + LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
1052 +
1053 + LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
1054 + {
1055 +        SUBLir(i, d);
1056 + }
1057 + LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
1058 +
1059 + LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
1060 + {
1061 +        SUBBir(i, d);
1062 + }
1063 + LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
1064 +
1065 + LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
1066 + {
1067 +        ADDLir(i, d);
1068 + }
1069 + LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
1070 +
1071 + LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
1072 + {
1073 +        ADDWir(i, d);
1074 + }
1075 + LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
1076 +
1077 + LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
1078 + {
1079 +        ADDBir(i, d);
1080 + }
1081 + LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
1082 +
1083 + LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
1084 + {
1085 +        SBBLrr(s, d);
1086 + }
1087 + LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
1088 +
1089 + LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
1090 + {
1091 +        SBBWrr(s, d);
1092 + }
1093 + LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
1094 +
1095 + LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
1096 + {
1097 +        SBBBrr(s, d);
1098 + }
1099 + LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
1100 +
1101 + LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
1102 + {
1103 +        SUBLrr(s, d);
1104 + }
1105 + LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
1106 +
1107 + LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
1108 + {
1109 +        SUBWrr(s, d);
1110 + }
1111 + LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
1112 +
1113 + LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
1114 + {
1115 +        SUBBrr(s, d);
1116 + }
1117 + LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
1118 +
1119 + LOWFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
1120 + {
1121 +        CMPLrr(s, d);
1122 + }
1123 + LENDFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
1124 +
1125 + LOWFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
1126 + {
1127 +        CMPLir(i, r);
1128 + }
1129 + LENDFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
1130 +
1131 + LOWFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
1132 + {
1133 +        CMPWrr(s, d);
1134 + }
1135 + LENDFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
1136 +
1137 + LOWFUNC(WRITE,READ,2,raw_cmp_b_mi,(MEMR d, IMM s))
1138 + {
1139 +        CMPBim(s, d, X86_NOREG, X86_NOREG, 1);
1140 + }
1141 + LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
1142 +
1143 + LOWFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
1144 + {
1145 +        CMPBir(i, d);
1146 + }
1147 + LENDFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
1148 +
1149 + LOWFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
1150 + {
1151 +        CMPBrr(s, d);
1152 + }
1153 + LENDFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
1154 +
1155 + LOWFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
1156 + {
1157 +        ADDR32 CMPLmr(offset, X86_NOREG, index, factor, d);
1158 + }
1159 + LENDFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
1160 +
1161 + LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
1162 + {
1163 +        XORLrr(s, d);
1164 + }
1165 + LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
1166 +
1167 + LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
1168 + {
1169 +        XORWrr(s, d);
1170 + }
1171 + LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
1172 +
1173 + LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
1174 + {
1175 +        XORBrr(s, d);
1176 + }
1177 + LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
1178 +
1179 + LOWFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
1180 + {
1181 +        SUBLim(s, d, X86_NOREG, X86_NOREG, 1);
1182 + }
1183 + LENDFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
1184 +
1185 + LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
1186 + {
1187 +        CMPLim(s, d, X86_NOREG, X86_NOREG, 1);
1188 + }
1189 + LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
1190 +
1191 + LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
1192 + {
1193 +        XCHGLrr(r2, r1);
1194 + }
1195 + LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
1196 +
1197 + LOWFUNC(NONE,NONE,2,raw_xchg_b_rr,(RW4 r1, RW4 r2))
1198 + {
1199 +        XCHGBrr(r2, r1);
1200 + }
1201 + LENDFUNC(NONE,NONE,2,raw_xchg_b_rr,(RW4 r1, RW4 r2))
1202 +
1203 + LOWFUNC(READ,WRITE,0,raw_pushfl,(void))
1204 + {
1205 +        PUSHF();
1206 + }
1207 + LENDFUNC(READ,WRITE,0,raw_pushfl,(void))
1208 +
1209 + LOWFUNC(WRITE,READ,0,raw_popfl,(void))
1210 + {
1211 +        POPF();
1212 + }
1213 + LENDFUNC(WRITE,READ,0,raw_popfl,(void))
1214 +
1215 + /* Generate floating-point instructions */
1216 + static inline void x86_fadd_m(MEMR s)
1217 + {
1218 +        FADDLm(s,X86_NOREG,X86_NOREG,1);
1219 + }
1220 +
1221 + #else
1222 +
1223   const bool optimize_accum               = true;
1224   const bool optimize_imm8                = true;
1225   const bool optimize_shift_once  = true;
# Line 157 | Line 1255 | LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
1255   }
1256   LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
1257  
1258 + LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
1259 + {
1260 +        emit_byte(0x8f);
1261 +        emit_byte(0x05);
1262 +        emit_long(d);
1263 + }
1264 + LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
1265 +
1266   LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
1267   {
1268          emit_byte(0x0f);
# Line 1071 | Line 2177 | LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d
2177  
2178   LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
2179   {
2180 +        Dif(!isbyte(offset)) abort();
2181      emit_byte(0x8b);
2182      emit_byte(0x40+8*d+s);
2183      emit_byte(offset);
# Line 1079 | Line 2186 | LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d,
2186  
2187   LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
2188   {
2189 +        Dif(!isbyte(offset)) abort();
2190      emit_byte(0x66);
2191      emit_byte(0x8b);
2192      emit_byte(0x40+8*d+s);
# Line 1088 | Line 2196 | LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d,
2196  
2197   LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
2198   {
2199 +        Dif(!isbyte(offset)) abort();
2200      emit_byte(0x8a);
2201      emit_byte(0x40+8*d+s);
2202      emit_byte(offset);
# Line 1121 | Line 2230 | LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d
2230  
2231   LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
2232   {
2233 +        Dif(!isbyte(offset)) abort();
2234      emit_byte(0xc7);
2235      emit_byte(0x40+d);
2236      emit_byte(offset);
# Line 1130 | Line 2240 | LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d
2240  
2241   LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
2242   {
2243 +        Dif(!isbyte(offset)) abort();
2244      emit_byte(0x66);
2245      emit_byte(0xc7);
2246      emit_byte(0x40+d);
# Line 1140 | Line 2251 | LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d
2251  
2252   LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
2253   {
2254 +        Dif(!isbyte(offset)) abort();
2255      emit_byte(0xc6);
2256      emit_byte(0x40+d);
2257      emit_byte(offset);
# Line 1149 | Line 2261 | LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d
2261  
2262   LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
2263   {
2264 +        Dif(!isbyte(offset)) abort();
2265      emit_byte(0x89);
2266      emit_byte(0x40+8*s+d);
2267      emit_byte(offset);
# Line 1157 | Line 2270 | LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d
2270  
2271   LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
2272   {
2273 +        Dif(!isbyte(offset)) abort();
2274      emit_byte(0x66);
2275      emit_byte(0x89);
2276      emit_byte(0x40+8*s+d);
# Line 1166 | Line 2280 | LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d
2280  
2281   LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
2282   {
2283 +        Dif(!isbyte(offset)) abort();
2284      emit_byte(0x88);
2285      emit_byte(0x40+8*s+d);
2286      emit_byte(offset);
# Line 1326 | Line 2441 | LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d,
2441   LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
2442   {
2443      emit_byte(0x88);
2444 <    emit_byte(0x05+8*s);
2444 >    emit_byte(0x05+8*(s&0xf)); /* XXX this handles %ah case (defined as 0x10+4) and others */
2445      emit_long(d);
2446   }
2447   LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
# Line 1440 | Line 2555 | LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d
2555   }
2556   LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
2557  
2558 + LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
2559 + {
2560 +    emit_byte(0x81);
2561 +    emit_byte(0xf0+d);
2562 +    emit_long(i);
2563 + }
2564 + LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
2565 +
2566   LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
2567   {
2568          if (optimize_imm8 && isbyte(i)) {
# Line 1855 | Line 2978 | LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r
2978   }
2979   LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
2980  
2981 < /*************************************************************************
1859 < * FIXME: string-related instructions                                    *
1860 < *************************************************************************/
1861 <
1862 < LOWFUNC(WRITE,NONE,0,raw_cld,(void))
1863 < {
1864 <        emit_byte(0xfc);
1865 < }
1866 < LENDFUNC(WRITE,NONE,0,raw_cld,(void))
1867 <
1868 < LOWFUNC(WRITE,NONE,0,raw_std,(void))
1869 < {
1870 <        emit_byte(0xfd);
1871 < }
1872 < LENDFUNC(WRITE,NONE,0,raw_std,(void))
1873 <
1874 < LOWFUNC(NONE,RMW,0,raw_movs_b,(void))
1875 < {
1876 <        emit_byte(0xa4);
1877 < }
1878 < LENDFUNC(NONE,RMW,0,raw_movs_b,(void))
1879 <
1880 < LOWFUNC(NONE,RMW,0,raw_movs_l,(void))
1881 < {
1882 <        emit_byte(0xa5);
1883 < }
1884 < LENDFUNC(NONE,RMW,0,raw_movs_l,(void))
1885 <
1886 < LOWFUNC(NONE,RMW,0,raw_rep,(void))
1887 < {
1888 <        emit_byte(0xf3);
1889 < }
1890 < LENDFUNC(NONE,RMW,0,raw_rep,(void))
1891 <
1892 < LOWFUNC(NONE,RMW,0,raw_rep_movsb,(void))
1893 < {
1894 <        raw_rep();
1895 <        raw_movs_b();
1896 < }
1897 < LENDFUNC(NONE,RMW,0,raw_rep_movsb,(void))
1898 <
1899 < LOWFUNC(NONE,RMW,0,raw_rep_movsl,(void))
2981 > LOWFUNC(NONE,NONE,2,raw_xchg_b_rr,(RW4 r1, RW4 r2))
2982   {
2983 <        raw_rep();
2984 <        raw_movs_l();
2983 >  emit_byte(0x86);
2984 >  emit_byte(0xc0+8*(r1&0xf)+(r2&0xf)); /* XXX this handles upper-halves registers (e.g. %ah defined as 0x10+4) */
2985   }
2986 < LENDFUNC(NONE,RMW,0,raw_rep_movsl,(void))
2986 > LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
2987  
2988   /*************************************************************************
2989   * FIXME: mem access modes probably wrong                                *
# Line 1919 | Line 3001 | LOWFUNC(WRITE,READ,0,raw_popfl,(void))
3001   }
3002   LENDFUNC(WRITE,READ,0,raw_popfl,(void))
3003  
3004 + /* Generate floating-point instructions */
3005 + static inline void x86_fadd_m(MEMR s)
3006 + {
3007 +        emit_byte(0xdc);
3008 +        emit_byte(0x05);
3009 +        emit_long(s);
3010 + }
3011 +
3012 + #endif
3013 +
3014   /*************************************************************************
3015   * Unoptimizable stuff --- jump                                          *
3016   *************************************************************************/
3017  
3018   static __inline__ void raw_call_r(R4 r)
3019   {
3020 + #if USE_NEW_RTASM
3021 +    CALLsr(r);
3022 + #else
3023      emit_byte(0xff);
3024      emit_byte(0xd0+r);
3025 + #endif
3026   }
3027  
3028   static __inline__ void raw_call_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
3029   {
3030 + #if USE_NEW_RTASM
3031 +    CALLsm(base, X86_NOREG, r, m);
3032 + #else
3033      int mu;
3034      switch(m) {
3035       case 1: mu=0; break;
# Line 1943 | Line 3042 | static __inline__ void raw_call_m_indexe
3042      emit_byte(0x14);
3043      emit_byte(0x05+8*r+0x40*mu);
3044      emit_long(base);
3045 + #endif
3046   }
3047  
3048   static __inline__ void raw_jmp_r(R4 r)
3049   {
3050 + #if USE_NEW_RTASM
3051 +    JMPsr(r);
3052 + #else
3053      emit_byte(0xff);
3054      emit_byte(0xe0+r);
3055 + #endif
3056   }
3057  
3058   static __inline__ void raw_jmp_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
3059   {
3060 + #if USE_NEW_RTASM
3061 +    JMPsm(base, X86_NOREG, r, m);
3062 + #else
3063      int mu;
3064      switch(m) {
3065       case 1: mu=0; break;
# Line 1965 | Line 3072 | static __inline__ void raw_jmp_m_indexed
3072      emit_byte(0x24);
3073      emit_byte(0x05+8*r+0x40*mu);
3074      emit_long(base);
3075 + #endif
3076   }
3077  
3078   static __inline__ void raw_jmp_m(uae_u32 base)
# Line 1977 | Line 3085 | static __inline__ void raw_jmp_m(uae_u32
3085  
3086   static __inline__ void raw_call(uae_u32 t)
3087   {
3088 + #if USE_NEW_RTASM
3089 +    CALLm(t);
3090 + #else
3091      emit_byte(0xe8);
3092      emit_long(t-(uae_u32)target-4);
3093 + #endif
3094   }
3095  
3096   static __inline__ void raw_jmp(uae_u32 t)
3097   {
3098 + #if USE_NEW_RTASM
3099 +    JMPm(t);
3100 + #else
3101      emit_byte(0xe9);
3102      emit_long(t-(uae_u32)target-4);
3103 + #endif
3104   }
3105  
3106   static __inline__ void raw_jl(uae_u32 t)
3107   {
3108      emit_byte(0x0f);
3109      emit_byte(0x8c);
3110 <    emit_long(t-(uae_u32)target-4);
3110 >    emit_long(t-(uintptr)target-4);
3111   }
3112  
3113   static __inline__ void raw_jz(uae_u32 t)
3114   {
3115      emit_byte(0x0f);
3116      emit_byte(0x84);
3117 <    emit_long(t-(uae_u32)target-4);
3117 >    emit_long(t-(uintptr)target-4);
3118   }
3119  
3120   static __inline__ void raw_jnz(uae_u32 t)
3121   {
3122      emit_byte(0x0f);
3123      emit_byte(0x85);
3124 <    emit_long(t-(uae_u32)target-4);
3124 >    emit_long(t-(uintptr)target-4);
3125   }
3126  
3127   static __inline__ void raw_jnz_l_oponly(void)
# Line 2055 | Line 3171 | static __inline__ void raw_nop(void)
3171      emit_byte(0x90);
3172   }
3173  
3174 + static __inline__ void raw_emit_nop_filler(int nbytes)
3175 + {
3176 +  /* Source: GNU Binutils 2.12.90.0.15 */
3177 +  /* Various efficient no-op patterns for aligning code labels.
3178 +     Note: Don't try to assemble the instructions in the comments.
3179 +     0L and 0w are not legal.  */
3180 +  static const uae_u8 f32_1[] =
3181 +    {0x90};                                                                     /* nop                                  */
3182 +  static const uae_u8 f32_2[] =
3183 +    {0x89,0xf6};                                                        /* movl %esi,%esi               */
3184 +  static const uae_u8 f32_3[] =
3185 +    {0x8d,0x76,0x00};                                           /* leal 0(%esi),%esi    */
3186 +  static const uae_u8 f32_4[] =
3187 +    {0x8d,0x74,0x26,0x00};                                      /* leal 0(%esi,1),%esi  */
3188 +  static const uae_u8 f32_5[] =
3189 +    {0x90,                                                                      /* nop                                  */
3190 +     0x8d,0x74,0x26,0x00};                                      /* leal 0(%esi,1),%esi  */
3191 +  static const uae_u8 f32_6[] =
3192 +    {0x8d,0xb6,0x00,0x00,0x00,0x00};            /* leal 0L(%esi),%esi   */
3193 +  static const uae_u8 f32_7[] =
3194 +    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
3195 +  static const uae_u8 f32_8[] =
3196 +    {0x90,                                                                      /* nop                                  */
3197 +     0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
3198 +  static const uae_u8 f32_9[] =
3199 +    {0x89,0xf6,                                                         /* movl %esi,%esi               */
3200 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3201 +  static const uae_u8 f32_10[] =
3202 +    {0x8d,0x76,0x00,                                            /* leal 0(%esi),%esi    */
3203 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3204 +  static const uae_u8 f32_11[] =
3205 +    {0x8d,0x74,0x26,0x00,                                       /* leal 0(%esi,1),%esi  */
3206 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3207 +  static const uae_u8 f32_12[] =
3208 +    {0x8d,0xb6,0x00,0x00,0x00,0x00,                     /* leal 0L(%esi),%esi   */
3209 +     0x8d,0xbf,0x00,0x00,0x00,0x00};            /* leal 0L(%edi),%edi   */
3210 +  static const uae_u8 f32_13[] =
3211 +    {0x8d,0xb6,0x00,0x00,0x00,0x00,                     /* leal 0L(%esi),%esi   */
3212 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3213 +  static const uae_u8 f32_14[] =
3214 +    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00,        /* leal 0L(%esi,1),%esi */
3215 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3216 +  static const uae_u8 f32_15[] =
3217 +    {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90,        /* jmp .+15; lotsa nops */
3218 +     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
3219 +  static const uae_u8 f32_16[] =
3220 +    {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90,        /* jmp .+15; lotsa nops */
3221 +     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
3222 +  static const uae_u8 *const f32_patt[] = {
3223 +    f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
3224 +    f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
3225 +  };
3226 +  static const uae_u8 prefixes[4] = { 0x66, 0x66, 0x66, 0x66 };
3227 +
3228 + #if defined(__x86_64__)
3229 +  /* The recommended way to pad 64bit code is to use NOPs preceded by
3230 +     maximally four 0x66 prefixes.  Balance the size of nops.  */
3231 +  if (nbytes == 0)
3232 +          return;
3233 +
3234 +  int i;
3235 +  int nnops = (nbytes + 3) / 4;
3236 +  int len = nbytes / nnops;
3237 +  int remains = nbytes - nnops * len;
3238 +
3239 +  for (i = 0; i < remains; i++) {
3240 +          emit_block(prefixes, len);
3241 +          raw_nop();
3242 +  }
3243 +  for (; i < nnops; i++) {
3244 +          emit_block(prefixes, len - 1);
3245 +          raw_nop();
3246 +  }
3247 + #else
3248 +  int nloops = nbytes / 16;
3249 +  while (nloops-- > 0)
3250 +        emit_block(f32_16, sizeof(f32_16));
3251 +
3252 +  nbytes %= 16;
3253 +  if (nbytes)
3254 +        emit_block(f32_patt[nbytes - 1], nbytes);
3255 + #endif
3256 + }
3257 +
3258  
3259   /*************************************************************************
3260   * Flag handling, to and fro UAE flag register                           *
3261   *************************************************************************/
3262  
3263 < #ifdef SAHF_SETO_PROFITABLE
2064 <
2065 < #define FLAG_NREG1 0  /* Set to -1 if any register will do */
2066 <
2067 < static __inline__ void raw_flags_to_reg(int r)
3263 > static __inline__ void raw_flags_evicted(int r)
3264   {
2069 –  raw_lahf(0);  /* Most flags in AH */
2070 –  //raw_setcc(r,0); /* V flag in AL */
2071 –  raw_setcc_m((uae_u32)live.state[FLAGTMP].mem,0);
2072 –  
2073 – #if 1   /* Let's avoid those nasty partial register stalls */
2074 –  //raw_mov_b_mr((uae_u32)live.state[FLAGTMP].mem,r);
2075 –  raw_mov_b_mr(((uae_u32)live.state[FLAGTMP].mem)+1,r+4);
3265    //live.state[FLAGTMP].status=CLEAN;
3266    live.state[FLAGTMP].status=INMEM;
3267    live.state[FLAGTMP].realreg=-1;
# Line 2082 | Line 3271 | static __inline__ void raw_flags_to_reg(
3271        abort();
3272    }
3273    live.nat[r].nholds=0;
3274 + }
3275 +
3276 + #define FLAG_NREG1_FLAGREG 0  /* Set to -1 if any register will do */
3277 + static __inline__ void raw_flags_to_reg_FLAGREG(int r)
3278 + {
3279 +  raw_lahf(0);  /* Most flags in AH */
3280 +  //raw_setcc(r,0); /* V flag in AL */
3281 +  raw_setcc_m((uintptr)live.state[FLAGTMP].mem,0);
3282 +  
3283 + #if 1   /* Let's avoid those nasty partial register stalls */
3284 +  //raw_mov_b_mr((uintptr)live.state[FLAGTMP].mem,r);
3285 +  raw_mov_b_mr(((uintptr)live.state[FLAGTMP].mem)+1,AH_INDEX);
3286 +  raw_flags_evicted(r);
3287   #endif
3288   }
3289  
3290 < #define FLAG_NREG2 0  /* Set to -1 if any register will do */
3291 < static __inline__ void raw_reg_to_flags(int r)
3290 > #define FLAG_NREG2_FLAGREG 0  /* Set to -1 if any register will do */
3291 > static __inline__ void raw_reg_to_flags_FLAGREG(int r)
3292   {
3293    raw_cmp_b_ri(r,-127); /* set V */
3294    raw_sahf(0);
3295   }
3296  
3297 < #else
3297 > #define FLAG_NREG3_FLAGREG 0  /* Set to -1 if any register will do */
3298 > static __inline__ void raw_flags_set_zero_FLAGREG(int s, int tmp)
3299 > {
3300 >    raw_mov_l_rr(tmp,s);
3301 >    raw_lahf(s); /* flags into ah */
3302 >    raw_and_l_ri(s,0xffffbfff);
3303 >    raw_and_l_ri(tmp,0x00004000);
3304 >    raw_xor_l_ri(tmp,0x00004000);
3305 >    raw_or_l(s,tmp);
3306 >    raw_sahf(s);
3307 > }
3308 >
3309 > static __inline__ void raw_flags_init_FLAGREG(void) { }
3310  
3311 < #define FLAG_NREG1 -1  /* Set to -1 if any register will do */
3312 < static __inline__ void raw_flags_to_reg(int r)
3311 > #define FLAG_NREG1_FLAGSTK -1  /* Set to -1 if any register will do */
3312 > static __inline__ void raw_flags_to_reg_FLAGSTK(int r)
3313   {
3314          raw_pushfl();
3315          raw_pop_l_r(r);
3316 <        raw_mov_l_mr((uae_u32)live.state[FLAGTMP].mem,r);
3317 < //      live.state[FLAGTMP].status=CLEAN;
2104 <        live.state[FLAGTMP].status=INMEM;
2105 <        live.state[FLAGTMP].realreg=-1;
2106 <        /* We just "evicted" FLAGTMP. */
2107 <        if (live.nat[r].nholds!=1) {
2108 <          /* Huh? */
2109 <          abort();
2110 <        }
2111 <        live.nat[r].nholds=0;
3316 >        raw_mov_l_mr((uintptr)live.state[FLAGTMP].mem,r);
3317 >        raw_flags_evicted(r);
3318   }
3319  
3320 < #define FLAG_NREG2 -1  /* Set to -1 if any register will do */
3321 < static __inline__ void raw_reg_to_flags(int r)
3320 > #define FLAG_NREG2_FLAGSTK -1  /* Set to -1 if any register will do */
3321 > static __inline__ void raw_reg_to_flags_FLAGSTK(int r)
3322   {
3323          raw_push_l_r(r);
3324          raw_popfl();
3325   }
3326  
3327 + #define FLAG_NREG3_FLAGSTK -1  /* Set to -1 if any register will do */
3328 + static __inline__ void raw_flags_set_zero_FLAGSTK(int s, int tmp)
3329 + {
3330 +    raw_mov_l_rr(tmp,s);
3331 +    raw_pushfl();
3332 +    raw_pop_l_r(s);
3333 +    raw_and_l_ri(s,0xffffffbf);
3334 +    raw_and_l_ri(tmp,0x00000040);
3335 +    raw_xor_l_ri(tmp,0x00000040);
3336 +    raw_or_l(s,tmp);
3337 +    raw_push_l_r(s);
3338 +    raw_popfl();
3339 + }
3340 +
3341 + static __inline__ void raw_flags_init_FLAGSTK(void) { }
3342 +
3343 + #if defined(__x86_64__)
3344 + /* Try to use the LAHF/SETO method on x86_64 since it is faster.
3345 +   This can't be the default because some older CPUs don't support
3346 +   LAHF/SAHF in long mode.  */
3347 + static int FLAG_NREG1_FLAGGEN = 0;
3348 + static __inline__ void raw_flags_to_reg_FLAGGEN(int r)
3349 + {
3350 +        if (have_lahf_lm) {
3351 +                // NOTE: the interpreter uses the normal EFLAGS layout
3352 +                //   pushf/popf CF(0) ZF( 6) SF( 7) OF(11)
3353 +                //   sahf/lahf  CF(8) ZF(14) SF(15) OF( 0)
3354 +                assert(r == 0);
3355 +                raw_setcc(r,0);                                 /* V flag in AL */
3356 +                raw_lea_l_r_scaled(0,0,8);              /* move it to its EFLAGS location */
3357 +                raw_mov_b_mr(((uintptr)live.state[FLAGTMP].mem)+1,0);
3358 +                raw_lahf(0);                                    /* most flags in AH */
3359 +                raw_mov_b_mr((uintptr)live.state[FLAGTMP].mem,AH_INDEX);
3360 +                raw_flags_evicted(r);
3361 +        }
3362 +        else
3363 +                raw_flags_to_reg_FLAGSTK(r);
3364 + }
3365 +
3366 + static int FLAG_NREG2_FLAGGEN = 0;
3367 + static __inline__ void raw_reg_to_flags_FLAGGEN(int r)
3368 + {
3369 +        if (have_lahf_lm) {
3370 +                raw_xchg_b_rr(0,AH_INDEX);
3371 +                raw_cmp_b_ri(r,-120); /* set V */
3372 +                raw_sahf(0);
3373 +        }
3374 +        else
3375 +                raw_reg_to_flags_FLAGSTK(r);
3376 + }
3377 +
3378 + static int FLAG_NREG3_FLAGGEN = 0;
3379 + static __inline__ void raw_flags_set_zero_FLAGGEN(int s, int tmp)
3380 + {
3381 +        if (have_lahf_lm)
3382 +                raw_flags_set_zero_FLAGREG(s, tmp);
3383 +        else
3384 +                raw_flags_set_zero_FLAGSTK(s, tmp);
3385 + }
3386 +
3387 + static __inline__ void raw_flags_init_FLAGGEN(void)
3388 + {
3389 +        if (have_lahf_lm) {
3390 +                FLAG_NREG1_FLAGGEN = FLAG_NREG1_FLAGREG;
3391 +                FLAG_NREG2_FLAGGEN = FLAG_NREG2_FLAGREG;
3392 +                FLAG_NREG1_FLAGGEN = FLAG_NREG3_FLAGREG;
3393 +        }
3394 +        else {
3395 +                FLAG_NREG1_FLAGGEN = FLAG_NREG1_FLAGSTK;
3396 +                FLAG_NREG2_FLAGGEN = FLAG_NREG2_FLAGSTK;
3397 +                FLAG_NREG1_FLAGGEN = FLAG_NREG3_FLAGSTK;
3398 +        }
3399 + }
3400   #endif
3401  
3402 + #ifdef SAHF_SETO_PROFITABLE
3403 + #define FLAG_SUFFIX FLAGREG
3404 + #elif defined __x86_64__
3405 + #define FLAG_SUFFIX FLAGGEN
3406 + #else
3407 + #define FLAG_SUFFIX FLAGSTK
3408 + #endif
3409 +
3410 + #define FLAG_GLUE_2(x, y)               x ## _ ## y
3411 + #define FLAG_GLUE_1(x, y)               FLAG_GLUE_2(x, y)
3412 + #define FLAG_GLUE(x)                    FLAG_GLUE_1(x, FLAG_SUFFIX)
3413 +
3414 + #define raw_flags_init                  FLAG_GLUE(raw_flags_init)
3415 + #define FLAG_NREG1                              FLAG_GLUE(FLAG_NREG1)
3416 + #define raw_flags_to_reg                FLAG_GLUE(raw_flags_to_reg)
3417 + #define FLAG_NREG2                              FLAG_GLUE(FLAG_NREG2)
3418 + #define raw_reg_to_flags                FLAG_GLUE(raw_reg_to_flags)
3419 + #define FLAG_NREG3                              FLAG_GLUE(FLAG_NREG3)
3420 + #define raw_flags_set_zero              FLAG_GLUE(raw_flags_set_zero)
3421 +
3422   /* Apparently, there are enough instructions between flag store and
3423     flag reload to avoid the partial memory stall */
3424   static __inline__ void raw_load_flagreg(uae_u32 target, uae_u32 r)
3425   {
3426   #if 1
3427 <    raw_mov_l_rm(target,(uae_u32)live.state[r].mem);
3427 >    raw_mov_l_rm(target,(uintptr)live.state[r].mem);
3428   #else
3429 <    raw_mov_b_rm(target,(uae_u32)live.state[r].mem);
3430 <    raw_mov_b_rm(target+4,((uae_u32)live.state[r].mem)+1);
3429 >    raw_mov_b_rm(target,(uintptr)live.state[r].mem);
3430 >    raw_mov_b_rm(target+4,((uintptr)live.state[r].mem)+1);
3431   #endif
3432   }
3433  
# Line 2136 | Line 3435 | static __inline__ void raw_load_flagreg(
3435   static __inline__ void raw_load_flagx(uae_u32 target, uae_u32 r)
3436   {
3437      if (live.nat[target].canbyte)
3438 <        raw_mov_b_rm(target,(uae_u32)live.state[r].mem);
3438 >        raw_mov_b_rm(target,(uintptr)live.state[r].mem);
3439      else if (live.nat[target].canword)
3440 <        raw_mov_w_rm(target,(uae_u32)live.state[r].mem);
3440 >        raw_mov_w_rm(target,(uintptr)live.state[r].mem);
3441      else
3442 <        raw_mov_l_rm(target,(uae_u32)live.state[r].mem);
3442 >        raw_mov_l_rm(target,(uintptr)live.state[r].mem);
3443   }
3444  
3445 + static __inline__ void raw_dec_sp(int off)
3446 + {
3447 +    if (off) raw_sub_l_ri(ESP_INDEX,off);
3448 + }
3449  
3450   static __inline__ void raw_inc_sp(int off)
3451   {
3452 <    raw_add_l_ri(ESP_INDEX,off);
3452 >    if (off) raw_add_l_ri(ESP_INDEX,off);
3453   }
3454  
3455   /*************************************************************************
# Line 2305 | Line 3608 | static void vec(int x, struct sigcontext
3608                  for (i=0;i<5;i++)
3609                      vecbuf[i]=target[i];
3610                  emit_byte(0xe9);
3611 <                emit_long((uae_u32)veccode-(uae_u32)target-4);
3611 >                emit_long((uintptr)veccode-(uintptr)target-4);
3612                  write_log("Create jump to %p\n",veccode);
3613              
3614                  write_log("Handled one access!\n");
# Line 2332 | Line 3635 | static void vec(int x, struct sigcontext
3635                  }
3636                  for (i=0;i<5;i++)
3637                      raw_mov_b_mi(sc.eip+i,vecbuf[i]);
3638 <                raw_mov_l_mi((uae_u32)&in_handler,0);
3638 >                raw_mov_l_mi((uintptr)&in_handler,0);
3639                  emit_byte(0xe9);
3640 <                emit_long(sc.eip+len-(uae_u32)target-4);
3640 >                emit_long(sc.eip+len-(uintptr)target-4);
3641                  in_handler=1;
3642                  target=tmp;
3643              }
# Line 2429 | Line 3732 | enum {
3732    X86_PROCESSOR_K6,
3733    X86_PROCESSOR_ATHLON,
3734    X86_PROCESSOR_PENTIUM4,
3735 +  X86_PROCESSOR_X86_64,
3736    X86_PROCESSOR_max
3737   };
3738  
# Line 2439 | Line 3743 | static const char * x86_processor_string
3743    "PentiumPro",
3744    "K6",
3745    "Athlon",
3746 <  "Pentium4"
3746 >  "Pentium4",
3747 >  "x86-64"
3748   };
3749  
3750   static struct ptt {
# Line 2456 | Line 3761 | x86_alignments[X86_PROCESSOR_max] = {
3761    { 16, 15, 16,  7, 16 },
3762    { 32,  7, 32,  7, 32 },
3763    { 16,  7, 16,  7, 16 },
3764 <  {  0,  0,  0,  0,  0 }
3764 >  {  0,  0,  0,  0,  0 },
3765 >  { 16,  7, 16,  7, 16 }
3766   };
3767  
3768   static void
# Line 2490 | Line 3796 | x86_get_cpu_vendor(struct cpuinfo_x86 *c
3796   static void
3797   cpuid(uae_u32 op, uae_u32 *eax, uae_u32 *ebx, uae_u32 *ecx, uae_u32 *edx)
3798   {
3799 <  static uae_u8 cpuid_space[256];  
3799 >  const int CPUID_SPACE = 4096;
3800 >  uae_u8* cpuid_space = (uae_u8 *)vm_acquire(CPUID_SPACE);
3801 >  if (cpuid_space == VM_MAP_FAILED)
3802 >    abort();
3803 >  vm_protect(cpuid_space, CPUID_SPACE, VM_PAGE_READ | VM_PAGE_WRITE | VM_PAGE_EXECUTE);
3804 >
3805 >  static uae_u32 s_op, s_eax, s_ebx, s_ecx, s_edx;
3806    uae_u8* tmp=get_target();
3807  
3808 +  s_op = op;
3809    set_target(cpuid_space);
3810    raw_push_l_r(0); /* eax */
3811    raw_push_l_r(1); /* ecx */
3812    raw_push_l_r(2); /* edx */
3813    raw_push_l_r(3); /* ebx */
3814 <  raw_mov_l_rm(0,(uae_u32)&op);
3814 >  raw_mov_l_rm(0,(uintptr)&s_op);
3815    raw_cpuid(0);
3816 <  if (eax != NULL) raw_mov_l_mr((uae_u32)eax,0);
3817 <  if (ebx != NULL) raw_mov_l_mr((uae_u32)ebx,3);
3818 <  if (ecx != NULL) raw_mov_l_mr((uae_u32)ecx,1);
3819 <  if (edx != NULL) raw_mov_l_mr((uae_u32)edx,2);
3816 >  raw_mov_l_mr((uintptr)&s_eax,0);
3817 >  raw_mov_l_mr((uintptr)&s_ebx,3);
3818 >  raw_mov_l_mr((uintptr)&s_ecx,1);
3819 >  raw_mov_l_mr((uintptr)&s_edx,2);
3820    raw_pop_l_r(3);
3821    raw_pop_l_r(2);
3822    raw_pop_l_r(1);
# Line 2512 | Line 3825 | cpuid(uae_u32 op, uae_u32 *eax, uae_u32
3825    set_target(tmp);
3826  
3827    ((cpuop_func*)cpuid_space)(0);
3828 +  if (eax != NULL) *eax = s_eax;
3829 +  if (ebx != NULL) *ebx = s_ebx;
3830 +  if (ecx != NULL) *ecx = s_ecx;
3831 +  if (edx != NULL) *edx = s_edx;
3832 +
3833 +  vm_release(cpuid_space, CPUID_SPACE);
3834   }
3835  
3836   static void
# Line 2520 | Line 3839 | raw_init_cpu(void)
3839    struct cpuinfo_x86 *c = &cpuinfo;
3840  
3841    /* Defaults */
3842 +  c->x86_processor = X86_PROCESSOR_max;
3843    c->x86_vendor = X86_VENDOR_UNKNOWN;
3844    c->cpuid_level = -1;                          /* CPUID not detected */
3845    c->x86_model = c->x86_mask = 0;       /* So far unknown... */
# Line 2541 | Line 3861 | raw_init_cpu(void)
3861          uae_u32 tfms, brand_id;
3862          cpuid(0x00000001, &tfms, &brand_id, NULL, &c->x86_hwcap);
3863          c->x86 = (tfms >> 8) & 15;
3864 +        if (c->x86 == 0xf)
3865 +                c->x86 += (tfms >> 20) & 0xff; /* extended family */
3866          c->x86_model = (tfms >> 4) & 15;
3867 +        if (c->x86_model == 0xf)
3868 +                c->x86_model |= (tfms >> 12) & 0xf0; /* extended model */
3869          c->x86_brand_id = brand_id & 0xff;
2546 –        if ( (c->x86_vendor == X86_VENDOR_AMD) &&
2547 –                 (c->x86 == 0xf)) {
2548 –          /* AMD Extended Family and Model Values */
2549 –          c->x86 += (tfms >> 20) & 0xff;
2550 –          c->x86_model += (tfms >> 12) & 0xf0;
2551 –        }
3870          c->x86_mask = tfms & 15;
3871    } else {
3872          /* Have CPUID level 0 only - unheard of */
3873          c->x86 = 4;
3874    }
3875  
3876 +  /* AMD-defined flags: level 0x80000001 */
3877 +  uae_u32 xlvl;
3878 +  cpuid(0x80000000, &xlvl, NULL, NULL, NULL);
3879 +  if ( (xlvl & 0xffff0000) == 0x80000000 ) {
3880 +        if ( xlvl >= 0x80000001 ) {
3881 +          uae_u32 features, extra_features;
3882 +          cpuid(0x80000001, NULL, NULL, &extra_features, &features);
3883 +          if (features & (1 << 29)) {
3884 +                /* Assume x86-64 if long mode is supported */
3885 +                c->x86_processor = X86_PROCESSOR_X86_64;
3886 +          }
3887 +          if (extra_features & (1 << 0))
3888 +                  have_lahf_lm = true;
3889 +        }
3890 +  }
3891 +          
3892    /* Canonicalize processor ID */
2559 –  c->x86_processor = X86_PROCESSOR_max;
3893    switch (c->x86) {
3894    case 3:
3895          c->x86_processor = X86_PROCESSOR_I386;
# Line 2577 | Line 3910 | raw_init_cpu(void)
3910            c->x86_processor = X86_PROCESSOR_PENTIUMPRO;
3911          break;
3912    case 15:
3913 <        if (c->x86_vendor == X86_VENDOR_INTEL) {
3914 <          /*  Assume any BranID >= 8 and family == 15 yields a Pentium 4 */
3915 <          if (c->x86_brand_id >= 8)
3916 <                c->x86_processor = X86_PROCESSOR_PENTIUM4;
3917 <        }
3918 <        break;
3913 >          if (c->x86_processor == X86_PROCESSOR_max) {
3914 >                  switch (c->x86_vendor) {
3915 >                  case X86_VENDOR_INTEL:
3916 >                          c->x86_processor = X86_PROCESSOR_PENTIUM4;
3917 >                          break;
3918 >                  case X86_VENDOR_AMD:
3919 >                          /* Assume a 32-bit Athlon processor if not in long mode */
3920 >                          c->x86_processor = X86_PROCESSOR_ATHLON;
3921 >                          break;
3922 >                  }
3923 >          }
3924 >          break;
3925    }
3926    if (c->x86_processor == X86_PROCESSOR_max) {
3927 <        fprintf(stderr, "Error: unknown processor type\n");
3927 >        c->x86_processor = X86_PROCESSOR_I386;
3928 >        fprintf(stderr, "Error: unknown processor type, assuming i386\n");
3929          fprintf(stderr, "  Family  : %d\n", c->x86);
3930          fprintf(stderr, "  Model   : %d\n", c->x86_model);
3931          fprintf(stderr, "  Mask    : %d\n", c->x86_mask);
3932 +        fprintf(stderr, "  Vendor  : %s [%d]\n", c->x86_vendor_id, c->x86_vendor);
3933          if (c->x86_brand_id)
3934            fprintf(stderr, "  BrandID : %02x\n", c->x86_brand_id);
2594 –        abort();
3935    }
3936  
3937    /* Have CMOV support? */
3938 <  have_cmov = (c->x86_hwcap & (1 << 15)) && true;
3938 >  have_cmov = c->x86_hwcap & (1 << 15);
3939  
3940    /* Can the host CPU suffer from partial register stalls? */
3941    have_rat_stall = (c->x86_vendor == X86_VENDOR_INTEL);
# Line 2616 | Line 3956 | raw_init_cpu(void)
3956    write_log("Max CPUID level=%d Processor is %s [%s]\n",
3957                          c->cpuid_level, c->x86_vendor_id,
3958                          x86_processor_string_table[c->x86_processor]);
3959 +
3960 +  raw_flags_init();
3961 + }
3962 +
3963 + static bool target_check_bsf(void)
3964 + {
3965 +        bool mismatch = false;
3966 +        for (int g_ZF = 0; g_ZF <= 1; g_ZF++) {
3967 +        for (int g_CF = 0; g_CF <= 1; g_CF++) {
3968 +        for (int g_OF = 0; g_OF <= 1; g_OF++) {
3969 +        for (int g_SF = 0; g_SF <= 1; g_SF++) {
3970 +                for (int value = -1; value <= 1; value++) {
3971 +                        unsigned long flags = (g_SF << 7) | (g_OF << 11) | (g_ZF << 6) | g_CF;
3972 +                        unsigned long tmp = value;
3973 +                        __asm__ __volatile__ ("push %0; popf; bsf %1,%1; pushf; pop %0"
3974 +                                                                  : "+r" (flags), "+r" (tmp) : : "cc");
3975 +                        int OF = (flags >> 11) & 1;
3976 +                        int SF = (flags >>  7) & 1;
3977 +                        int ZF = (flags >>  6) & 1;
3978 +                        int CF = flags & 1;
3979 +                        tmp = (value == 0);
3980 +                        if (ZF != tmp || SF != g_SF || OF != g_OF || CF != g_CF)
3981 +                                mismatch = true;
3982 +                }
3983 +        }}}}
3984 +        if (mismatch)
3985 +                write_log("Target CPU defines all flags on BSF instruction\n");
3986 +        return !mismatch;
3987   }
3988  
3989  
# Line 2740 | Line 4108 | static __inline__ void tos_make(int r)
4108      emit_byte(0xd8+(live.tos+1)-live.spos[r]);  /* store top of stack in reg,
4109                                           and pop it*/
4110   }
4111 <    
4112 <        
4111 >
4112 > /* FP helper functions */
4113 > #if USE_NEW_RTASM
4114 > #define DEFINE_OP(NAME, GEN)                    \
4115 > static inline void raw_##NAME(uint32 m)         \
4116 > {                                               \
4117 >    GEN(m, X86_NOREG, X86_NOREG, 1);            \
4118 > }
4119 > DEFINE_OP(fstl,  FSTLm);
4120 > DEFINE_OP(fstpl, FSTPLm);
4121 > DEFINE_OP(fldl,  FLDLm);
4122 > DEFINE_OP(fildl, FILDLm);
4123 > DEFINE_OP(fistl, FISTLm);
4124 > DEFINE_OP(flds,  FLDSm);
4125 > DEFINE_OP(fsts,  FSTSm);
4126 > DEFINE_OP(fstpt, FSTPTm);
4127 > DEFINE_OP(fldt,  FLDTm);
4128 > #else
4129 > #define DEFINE_OP(NAME, OP1, OP2)               \
4130 > static inline void raw_##NAME(uint32 m)         \
4131 > {                                               \
4132 >    emit_byte(OP1);                             \
4133 >    emit_byte(OP2);                             \
4134 >    emit_long(m);                               \
4135 > }
4136 > DEFINE_OP(fstl,  0xdd, 0x15);
4137 > DEFINE_OP(fstpl, 0xdd, 0x1d);
4138 > DEFINE_OP(fldl,  0xdd, 0x05);
4139 > DEFINE_OP(fildl, 0xdb, 0x05);
4140 > DEFINE_OP(fistl, 0xdb, 0x15);
4141 > DEFINE_OP(flds,  0xd9, 0x05);
4142 > DEFINE_OP(fsts,  0xd9, 0x15);
4143 > DEFINE_OP(fstpt, 0xdb, 0x3d);
4144 > DEFINE_OP(fldt,  0xdb, 0x2d);
4145 > #endif
4146 > #undef DEFINE_OP
4147 >
4148   LOWFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW m, FR r))
4149   {
4150      make_tos(r);
4151 <    emit_byte(0xdd);
2749 <    emit_byte(0x15);
2750 <    emit_long(m);
4151 >    raw_fstl(m);
4152   }
4153   LENDFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW m, FR r))
4154  
4155   LOWFUNC(NONE,WRITE,2,raw_fmov_mr_drop,(MEMW m, FR r))
4156   {
4157      make_tos(r);
4158 <    emit_byte(0xdd);
2758 <    emit_byte(0x1d);
2759 <    emit_long(m);
4158 >    raw_fstpl(m);
4159      live.onstack[live.tos]=-1;
4160      live.tos--;
4161      live.spos[r]=-2;
# Line 2765 | Line 4164 | LENDFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW
4164  
4165   LOWFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMR m))
4166   {
4167 <    emit_byte(0xdd);
2769 <    emit_byte(0x05);
2770 <    emit_long(m);
4167 >    raw_fldl(m);
4168      tos_make(r);
4169   }
4170   LENDFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMR m))
4171  
4172   LOWFUNC(NONE,READ,2,raw_fmovi_rm,(FW r, MEMR m))
4173   {
4174 <    emit_byte(0xdb);
2778 <    emit_byte(0x05);
2779 <    emit_long(m);
4174 >    raw_fildl(m);
4175      tos_make(r);
4176   }
4177   LENDFUNC(NONE,READ,2,raw_fmovi_rm,(FW r, MEMR m))
# Line 2784 | Line 4179 | LENDFUNC(NONE,READ,2,raw_fmovi_rm,(FW r,
4179   LOWFUNC(NONE,WRITE,2,raw_fmovi_mr,(MEMW m, FR r))
4180   {
4181      make_tos(r);
4182 <    emit_byte(0xdb);
2788 <    emit_byte(0x15);
2789 <    emit_long(m);
4182 >    raw_fistl(m);
4183   }
4184   LENDFUNC(NONE,WRITE,2,raw_fmovi_mr,(MEMW m, FR r))
4185  
4186   LOWFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m))
4187   {
4188 <    emit_byte(0xd9);
2796 <    emit_byte(0x05);
2797 <    emit_long(m);
4188 >    raw_flds(m);
4189      tos_make(r);
4190   }
4191   LENDFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m))
# Line 2802 | Line 4193 | LENDFUNC(NONE,READ,2,raw_fmovs_rm,(FW r,
4193   LOWFUNC(NONE,WRITE,2,raw_fmovs_mr,(MEMW m, FR r))
4194   {
4195      make_tos(r);
4196 <    emit_byte(0xd9);
2806 <    emit_byte(0x15);
2807 <    emit_long(m);
4196 >    raw_fsts(m);
4197   }
4198   LENDFUNC(NONE,WRITE,2,raw_fmovs_mr,(MEMW m, FR r))
4199  
# Line 2819 | Line 4208 | LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(ME
4208      emit_byte(0xd9);     /* Get a copy to the top of stack */
4209      emit_byte(0xc0+rs);
4210  
4211 <    emit_byte(0xdb);  /* store and pop it */
2823 <    emit_byte(0x3d);
2824 <    emit_long(m);
4211 >    raw_fstpt(m);       /* store and pop it */
4212   }
4213   LENDFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(MEMW m, FR r))
4214  
# Line 2830 | Line 4217 | LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr_dro
4217      int rs;
4218  
4219      make_tos(r);
4220 <    emit_byte(0xdb);  /* store and pop it */
2834 <    emit_byte(0x3d);
2835 <    emit_long(m);
4220 >    raw_fstpt(m);       /* store and pop it */
4221      live.onstack[live.tos]=-1;
4222      live.tos--;
4223      live.spos[r]=-2;
# Line 2841 | Line 4226 | LENDFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(M
4226  
4227   LOWFUNC(NONE,READ,2,raw_fmov_ext_rm,(FW r, MEMR m))
4228   {
4229 <    emit_byte(0xdb);
2845 <    emit_byte(0x2d);
2846 <    emit_long(m);
4229 >    raw_fldt(m);
4230      tos_make(r);
4231   }
4232   LENDFUNC(NONE,READ,2,raw_fmov_ext_rm,(FW r, MEMR m))
# Line 3030 | Line 4413 | LOWFUNC(NONE,NONE,2,raw_fsin_rr,(FW d, F
4413   }
4414   LENDFUNC(NONE,NONE,2,raw_fsin_rr,(FW d, FR s))
4415  
4416 < double one=1;
4416 > static const double one=1;
4417   LOWFUNC(NONE,NONE,2,raw_ftwotox_rr,(FW d, FR s))
4418   {
4419      int ds;
# Line 3050 | Line 4433 | LOWFUNC(NONE,NONE,2,raw_ftwotox_rr,(FW d
4433      emit_byte(0xe1);  /* subtract rounded from original */
4434      emit_byte(0xd9);
4435      emit_byte(0xf0);  /* f2xm1 */
4436 <    emit_byte(0xdc);
3054 <    emit_byte(0x05);
3055 <    emit_long((uae_u32)&one);  /* Add '1' without using extra stack space */
4436 >    x86_fadd_m((uintptr)&one);  /* Add '1' without using extra stack space */
4437      emit_byte(0xd9);
4438      emit_byte(0xfd);  /* and scale it */
4439      emit_byte(0xdd);
# Line 3084 | Line 4465 | LOWFUNC(NONE,NONE,2,raw_fetox_rr,(FW d,
4465      emit_byte(0xe1);  /* subtract rounded from original */
4466      emit_byte(0xd9);
4467      emit_byte(0xf0);  /* f2xm1 */
4468 <    emit_byte(0xdc);
3088 <    emit_byte(0x05);
3089 <    emit_long((uae_u32)&one);  /* Add '1' without using extra stack space */
4468 >    x86_fadd_m((uintptr)&one);  /* Add '1' without using extra stack space */
4469      emit_byte(0xd9);
4470      emit_byte(0xfd);  /* and scale it */
4471      emit_byte(0xdd);

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