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root/cebix/BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp
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Comparing BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp (file contents):
Revision 1.6 by gbeauche, 2002-10-03T16:13:46Z vs.
Revision 1.27 by gbeauche, 2005-03-22T16:12:18Z

# Line 3 | Line 3
3   *
4   *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
5   *
6 < *  Adaptation for Basilisk II and improvements, copyright 2000-2002
6 > *  Adaptation for Basilisk II and improvements, copyright 2000-2005
7   *    Gwenole Beauchesne
8   *
9 < *  Basilisk II (C) 1997-2002 Christian Bauer
9 > *  Basilisk II (C) 1997-2005 Christian Bauer
10 > *
11 > *  Portions related to CPU detection come from linux/arch/i386/kernel/setup.c
12   *  
13   *  This program is free software; you can redistribute it and/or modify
14   *  it under the terms of the GNU General Public License as published by
# Line 40 | Line 42
42   #define EBP_INDEX 5
43   #define ESI_INDEX 6
44   #define EDI_INDEX 7
45 + #if defined(__x86_64__)
46 + #define R8_INDEX  8
47 + #define R9_INDEX  9
48 + #define R10_INDEX 10
49 + #define R11_INDEX 11
50 + #define R12_INDEX 12
51 + #define R13_INDEX 13
52 + #define R14_INDEX 14
53 + #define R15_INDEX 15
54 + #endif
55  
56   /* The register in which subroutines return an integer return value */
57 < #define REG_RESULT 0
57 > #define REG_RESULT EAX_INDEX
58  
59   /* The registers subroutines take their first and second argument in */
60   #if defined( _MSC_VER ) && !defined( USE_NORMAL_CALLING_CONVENTION )
61   /* Handle the _fastcall parameters of ECX and EDX */
62 < #define REG_PAR1 1
63 < #define REG_PAR2 2
62 > #define REG_PAR1 ECX_INDEX
63 > #define REG_PAR2 EDX_INDEX
64 > #elif defined(__x86_64__)
65 > #define REG_PAR1 EDI_INDEX
66 > #define REG_PAR2 ESI_INDEX
67   #else
68 < #define REG_PAR1 0
69 < #define REG_PAR2 2
68 > #define REG_PAR1 EAX_INDEX
69 > #define REG_PAR2 EDX_INDEX
70   #endif
71  
72 < /* Three registers that are not used for any of the above */
58 < #define REG_NOPAR1 6
59 < #define REG_NOPAR2 5
60 < #define REG_NOPAR3 3
61 <
62 < #define REG_PC_PRE 0 /* The register we use for preloading regs.pc_p */
72 > #define REG_PC_PRE EAX_INDEX /* The register we use for preloading regs.pc_p */
73   #if defined( _MSC_VER ) && !defined( USE_NORMAL_CALLING_CONVENTION )
74 < #define REG_PC_TMP 0
74 > #define REG_PC_TMP EAX_INDEX
75   #else
76 < #define REG_PC_TMP 1 /* Another register that is not the above */
76 > #define REG_PC_TMP ECX_INDEX /* Another register that is not the above */
77   #endif
78  
79 < #define SHIFTCOUNT_NREG 1  /* Register that can be used for shiftcount.
79 > #define SHIFTCOUNT_NREG ECX_INDEX  /* Register that can be used for shiftcount.
80                                -1 if any reg will do */
81 < #define MUL_NREG1 0 /* %eax will hold the low 32 bits after a 32x32 mul */
82 < #define MUL_NREG2 2 /* %edx will hold the high 32 bits */
81 > #define MUL_NREG1 EAX_INDEX /* %eax will hold the low 32 bits after a 32x32 mul */
82 > #define MUL_NREG2 EDX_INDEX /* %edx will hold the high 32 bits */
83  
84   uae_s8 always_used[]={4,-1};
85 + #if defined(__x86_64__)
86 + uae_s8 can_byte[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
87 + uae_s8 can_word[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
88 + #else
89   uae_s8 can_byte[]={0,1,2,3,-1};
90   uae_s8 can_word[]={0,1,2,3,5,6,7,-1};
91 + #endif
92  
93 + #if USE_OPTIMIZED_CALLS
94 + /* Make sure interpretive core does not use cpuopti */
95 + uae_u8 call_saved[]={0,0,0,1,1,1,1,1};
96 + #error FIXME: code not ready
97 + #else
98   /* cpuopti mutate instruction handlers to assume registers are saved
99     by the caller */
100 < uae_u8 call_saved[]={0,0,0,0,1,0,0,0};
100 > uae_u8 call_saved[]={0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0};
101 > #endif
102  
103   /* This *should* be the same as call_saved. But:
104     - We might not really know which registers are saved, and which aren't,
# Line 86 | Line 107 | uae_u8 call_saved[]={0,0,0,0,1,0,0,0};
107     - Special registers (such like the stack pointer) should not be "preserved"
108       by pushing, even though they are "saved" across function calls
109   */
110 < uae_u8 need_to_preserve[]={1,1,1,1,0,1,1,1};
110 > #if defined(__x86_64__)
111 > /* callee-saved registers as defined by Linux/x86_64 ABI: rbx, rbp, rsp, r12 - r15 */
112 > /* preserve r11 because it's generally used to hold pointers to functions */
113 > static const uae_u8 need_to_preserve[]={0,0,0,1,0,1,0,0,0,0,0,1,1,1,1,1};
114 > #else
115 > static const uae_u8 need_to_preserve[]={1,1,1,1,0,1,1,1};
116 > #endif
117  
118   /* Whether classes of instructions do or don't clobber the native flags */
119   #define CLOBBER_MOV
# Line 111 | Line 138 | uae_u8 need_to_preserve[]={1,1,1,1,0,1,1
138   #define CLOBBER_TEST clobber_flags()
139   #define CLOBBER_CL16
140   #define CLOBBER_CL8  
141 + #define CLOBBER_SE32
142   #define CLOBBER_SE16
143   #define CLOBBER_SE8
144 + #define CLOBBER_ZE32
145   #define CLOBBER_ZE16
146   #define CLOBBER_ZE8
147   #define CLOBBER_SW16 clobber_flags()
# Line 122 | Line 151 | uae_u8 need_to_preserve[]={1,1,1,1,0,1,1
151   #define CLOBBER_BT   clobber_flags()
152   #define CLOBBER_BSF  clobber_flags()
153  
154 + /* FIXME: disabled until that's proofread.  */
155 + #if defined(__x86_64__)
156 + #define USE_NEW_RTASM 1
157 + #endif
158 +
159 + #if USE_NEW_RTASM
160 +
161 + #if defined(__x86_64__)
162 + #define X86_TARGET_64BIT                1
163 + #endif
164 + #define X86_FLAT_REGISTERS              0
165 + #define X86_OPTIMIZE_ALU                1
166 + #define X86_OPTIMIZE_ROTSHI             1
167 + #include "codegen_x86.h"
168 +
169 + #define x86_emit_byte(B)                emit_byte(B)
170 + #define x86_emit_word(W)                emit_word(W)
171 + #define x86_emit_long(L)                emit_long(L)
172 + #define x86_emit_quad(Q)                emit_quad(Q)
173 + #define x86_get_target()                get_target()
174 + #define x86_emit_failure(MSG)   jit_fail(MSG, __FILE__, __LINE__, __FUNCTION__)
175 +
176 + static void jit_fail(const char *msg, const char *file, int line, const char *function)
177 + {
178 +        fprintf(stderr, "JIT failure in function %s from file %s at line %d: %s\n",
179 +                        function, file, line, msg);
180 +        abort();
181 + }
182 +
183 + LOWFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
184 + {
185 + #if defined(__x86_64__)
186 +        PUSHQr(r);
187 + #else
188 +        PUSHLr(r);
189 + #endif
190 + }
191 + LENDFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
192 +
193 + LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
194 + {
195 + #if defined(__x86_64__)
196 +        POPQr(r);
197 + #else
198 +        POPLr(r);
199 + #endif
200 + }
201 + LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
202 +
203 + LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
204 + {
205 + #if defined(__x86_64__)
206 +        POPQm(d, X86_NOREG, X86_NOREG, 1);
207 + #else
208 +        POPLm(d, X86_NOREG, X86_NOREG, 1);
209 + #endif
210 + }
211 + LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
212 +
213 + LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
214 + {
215 +        BTLir(i, r);
216 + }
217 + LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
218 +
219 + LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
220 + {
221 +        BTLrr(b, r);
222 + }
223 + LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
224 +
225 + LOWFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
226 + {
227 +        BTCLir(i, r);
228 + }
229 + LENDFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
230 +
231 + LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
232 + {
233 +        BTCLrr(b, r);
234 + }
235 + LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
236 +
237 + LOWFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
238 + {
239 +        BTRLir(i, r);
240 + }
241 + LENDFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
242 +
243 + LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
244 + {
245 +        BTRLrr(b, r);
246 + }
247 + LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
248 +
249 + LOWFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
250 + {
251 +        BTSLir(i, r);
252 + }
253 + LENDFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
254 +
255 + LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
256 + {
257 +        BTSLrr(b, r);
258 + }
259 + LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
260 +
261 + LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
262 + {
263 +        SUBWir(i, d);
264 + }
265 + LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
266 +
267 + LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
268 + {
269 +        MOVLmr(s, X86_NOREG, X86_NOREG, 1, d);
270 + }
271 + LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
272 +
273 + LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
274 + {
275 +        MOVLim(s, d, X86_NOREG, X86_NOREG, 1);
276 + }
277 + LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
278 +
279 + LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
280 + {
281 +        MOVWim(s, d, X86_NOREG, X86_NOREG, 1);
282 + }
283 + LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
284 +
285 + LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
286 + {
287 +        MOVBim(s, d, X86_NOREG, X86_NOREG, 1);
288 + }
289 + LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
290 +
291 + LOWFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
292 + {
293 +        ROLBim(i, d, X86_NOREG, X86_NOREG, 1);
294 + }
295 + LENDFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
296 +
297 + LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
298 + {
299 +        ROLBir(i, r);
300 + }
301 + LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
302 +
303 + LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
304 + {
305 +        ROLWir(i, r);
306 + }
307 + LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
308 +
309 + LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
310 + {
311 +        ROLLir(i, r);
312 + }
313 + LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
314 +
315 + LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
316 + {
317 +        ROLLrr(r, d);
318 + }
319 + LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
320 +
321 + LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
322 + {
323 +        ROLWrr(r, d);
324 + }
325 + LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
326 +
327 + LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
328 + {
329 +        ROLBrr(r, d);
330 + }
331 + LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
332 +
333 + LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
334 + {
335 +        SHLLrr(r, d);
336 + }
337 + LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
338 +
339 + LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
340 + {
341 +        SHLWrr(r, d);
342 + }
343 + LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
344 +
345 + LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
346 + {
347 +        SHLBrr(r, d);
348 + }
349 + LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
350 +
351 + LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
352 + {
353 +        RORBir(i, r);
354 + }
355 + LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
356 +
357 + LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
358 + {
359 +        RORWir(i, r);
360 + }
361 + LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
362 +
363 + LOWFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
364 + {
365 +        ORLmr(s, X86_NOREG, X86_NOREG, 1, d);
366 + }
367 + LENDFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
368 +
369 + LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
370 + {
371 +        RORLir(i, r);
372 + }
373 + LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
374 +
375 + LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
376 + {
377 +        RORLrr(r, d);
378 + }
379 + LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
380 +
381 + LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
382 + {
383 +        RORWrr(r, d);
384 + }
385 + LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
386 +
387 + LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
388 + {
389 +        RORBrr(r, d);
390 + }
391 + LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
392 +
393 + LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
394 + {
395 +        SHRLrr(r, d);
396 + }
397 + LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
398 +
399 + LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
400 + {
401 +        SHRWrr(r, d);
402 + }
403 + LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
404 +
405 + LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
406 + {
407 +        SHRBrr(r, d);
408 + }
409 + LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
410 +
411 + LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
412 + {
413 +        SARLrr(r, d);
414 + }
415 + LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
416 +
417 + LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
418 + {
419 +        SARWrr(r, d);
420 + }
421 + LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
422 +
423 + LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
424 + {
425 +        SARBrr(r, d);
426 + }
427 + LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
428 +
429 + LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
430 + {
431 +        SHLLir(i, r);
432 + }
433 + LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
434 +
435 + LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
436 + {
437 +        SHLWir(i, r);
438 + }
439 + LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
440 +
441 + LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
442 + {
443 +        SHLBir(i, r);
444 + }
445 + LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
446 +
447 + LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
448 + {
449 +        SHRLir(i, r);
450 + }
451 + LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
452 +
453 + LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
454 + {
455 +        SHRWir(i, r);
456 + }
457 + LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
458 +
459 + LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
460 + {
461 +        SHRBir(i, r);
462 + }
463 + LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
464 +
465 + LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
466 + {
467 +        SARLir(i, r);
468 + }
469 + LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
470 +
471 + LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
472 + {
473 +        SARWir(i, r);
474 + }
475 + LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
476 +
477 + LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
478 + {
479 +        SARBir(i, r);
480 + }
481 + LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
482 +
483 + LOWFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
484 + {
485 +        SAHF();
486 + }
487 + LENDFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
488 +
489 + LOWFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
490 + {
491 +        CPUID();
492 + }
493 + LENDFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
494 +
495 + LOWFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
496 + {
497 +        LAHF();
498 + }
499 + LENDFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
500 +
501 + LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
502 + {
503 +        SETCCir(cc, d);
504 + }
505 + LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
506 +
507 + LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
508 + {
509 +        SETCCim(cc, d, X86_NOREG, X86_NOREG, 1);
510 + }
511 + LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
512 +
513 + LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
514 + {
515 +        if (have_cmov)
516 +                CMOVLrr(cc, s, d);
517 +        else { /* replacement using branch and mov */
518 + #if defined(__x86_64__)
519 +                write_log("x86-64 implementations are bound to have CMOV!\n");
520 +                abort();
521 + #endif
522 +                JCCSii(cc^1, 2);
523 +                MOVLrr(s, d);
524 +        }
525 + }
526 + LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
527 +
528 + LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
529 + {
530 +        BSFLrr(s, d);
531 + }
532 + LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
533 +
534 + LOWFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s))
535 + {
536 +        MOVSLQrr(s, d);
537 + }
538 + LENDFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s))
539 +
540 + LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
541 + {
542 +        MOVSWLrr(s, d);
543 + }
544 + LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
545 +
546 + LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
547 + {
548 +        MOVSBLrr(s, d);
549 + }
550 + LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
551 +
552 + LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
553 + {
554 +        MOVZWLrr(s, d);
555 + }
556 + LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
557 +
558 + LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
559 + {
560 +        MOVZBLrr(s, d);
561 + }
562 + LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
563 +
564 + LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
565 + {
566 +        IMULLrr(s, d);
567 + }
568 + LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
569 +
570 + LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
571 + {
572 +        if (d!=MUL_NREG1 || s!=MUL_NREG2) {
573 +        write_log("Bad register in IMUL: d=%d, s=%d\n",d,s);
574 +        abort();
575 +        }
576 +        IMULLr(s);
577 + }
578 + LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
579 +
580 + LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
581 + {
582 +        if (d!=MUL_NREG1 || s!=MUL_NREG2) {
583 +        write_log("Bad register in MUL: d=%d, s=%d\n",d,s);
584 +        abort();
585 +        }
586 +        MULLr(s);
587 + }
588 + LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
589 +
590 + LOWFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
591 + {
592 +        abort(); /* %^$&%^$%#^ x86! */
593 + }
594 + LENDFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
595 +
596 + LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
597 + {
598 +        MOVBrr(s, d);
599 + }
600 + LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
601 +
602 + LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
603 + {
604 +        MOVWrr(s, d);
605 + }
606 + LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
607 +
608 + LOWFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
609 + {
610 +        MOVLmr(0, baser, index, factor, d);
611 + }
612 + LENDFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
613 +
614 + LOWFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
615 + {
616 +        MOVWmr(0, baser, index, factor, d);
617 + }
618 + LENDFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
619 +
620 + LOWFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
621 + {
622 +        MOVBmr(0, baser, index, factor, d);
623 + }
624 + LENDFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
625 +
626 + LOWFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
627 + {
628 +        MOVLrm(s, 0, baser, index, factor);
629 + }
630 + LENDFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
631 +
632 + LOWFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
633 + {
634 +        MOVWrm(s, 0, baser, index, factor);
635 + }
636 + LENDFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
637 +
638 + LOWFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
639 + {
640 +        MOVBrm(s, 0, baser, index, factor);
641 + }
642 + LENDFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
643 +
644 + LOWFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
645 + {
646 +        MOVLrm(s, base, baser, index, factor);
647 + }
648 + LENDFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
649 +
650 + LOWFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
651 + {
652 +        MOVWrm(s, base, baser, index, factor);
653 + }
654 + LENDFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
655 +
656 + LOWFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
657 + {
658 +        MOVBrm(s, base, baser, index, factor);
659 + }
660 + LENDFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
661 +
662 + LOWFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
663 + {
664 +        MOVLmr(base, baser, index, factor, d);
665 + }
666 + LENDFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
667 +
668 + LOWFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
669 + {
670 +        MOVWmr(base, baser, index, factor, d);
671 + }
672 + LENDFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
673 +
674 + LOWFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
675 + {
676 +        MOVBmr(base, baser, index, factor, d);
677 + }
678 + LENDFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
679 +
680 + LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
681 + {
682 +        MOVLmr(base, X86_NOREG, index, factor, d);
683 + }
684 + LENDFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
685 +
686 + LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
687 + {
688 +        if (have_cmov)
689 +                CMOVLmr(cond, base, X86_NOREG, index, factor, d);
690 +        else { /* replacement using branch and mov */
691 + #if defined(__x86_64__)
692 +                write_log("x86-64 implementations are bound to have CMOV!\n");
693 +                abort();
694 + #endif
695 +                JCCSii(cond^1, 7);
696 +                MOVLmr(base, X86_NOREG, index, factor, d);
697 +        }
698 + }
699 + LENDFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
700 +
701 + LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
702 + {
703 +        if (have_cmov)
704 +                CMOVLmr(cond, mem, X86_NOREG, X86_NOREG, 1, d);
705 +        else { /* replacement using branch and mov */
706 + #if defined(__x86_64__)
707 +                write_log("x86-64 implementations are bound to have CMOV!\n");
708 +                abort();
709 + #endif
710 +                JCCSii(cond^1, 6);
711 +                MOVLmr(mem, X86_NOREG, X86_NOREG, 1, d);
712 +        }
713 + }
714 + LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
715 +
716 + LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
717 + {
718 +        MOVLmr(offset, s, X86_NOREG, 1, d);
719 + }
720 + LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
721 +
722 + LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
723 + {
724 +        MOVWmr(offset, s, X86_NOREG, 1, d);
725 + }
726 + LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
727 +
728 + LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
729 + {
730 +        MOVBmr(offset, s, X86_NOREG, 1, d);
731 + }
732 + LENDFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
733 +
734 + LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
735 + {
736 +        MOVLmr(offset, s, X86_NOREG, 1, d);
737 + }
738 + LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
739 +
740 + LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
741 + {
742 +        MOVWmr(offset, s, X86_NOREG, 1, d);
743 + }
744 + LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
745 +
746 + LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
747 + {
748 +        MOVBmr(offset, s, X86_NOREG, 1, d);
749 + }
750 + LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
751 +
752 + LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
753 + {
754 +        MOVLim(i, offset, d, X86_NOREG, 1);
755 + }
756 + LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
757 +
758 + LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
759 + {
760 +        MOVWim(i, offset, d, X86_NOREG, 1);
761 + }
762 + LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
763 +
764 + LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
765 + {
766 +        MOVBim(i, offset, d, X86_NOREG, 1);
767 + }
768 + LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
769 +
770 + LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
771 + {
772 +        MOVLrm(s, offset, d, X86_NOREG, 1);
773 + }
774 + LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
775 +
776 + LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
777 + {
778 +        MOVWrm(s, offset, d, X86_NOREG, 1);
779 + }
780 + LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
781 +
782 + LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
783 + {
784 +        MOVBrm(s, offset, d, X86_NOREG, 1);
785 + }
786 + LENDFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
787 +
788 + LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
789 + {
790 +        LEALmr(offset, s, X86_NOREG, 1, d);
791 + }
792 + LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
793 +
794 + LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
795 + {
796 +        LEALmr(offset, s, index, factor, d);
797 + }
798 + LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
799 +
800 + LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
801 + {
802 +        LEALmr(0, s, index, factor, d);
803 + }
804 + LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
805 +
806 + LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
807 + {
808 +        MOVLrm(s, offset, d, X86_NOREG, 1);
809 + }
810 + LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
811 +
812 + LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
813 + {
814 +        MOVWrm(s, offset, d, X86_NOREG, 1);
815 + }
816 + LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
817 +
818 + LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
819 + {
820 +        MOVBrm(s, offset, d, X86_NOREG, 1);
821 + }
822 + LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
823 +
824 + LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
825 + {
826 +        BSWAPLr(r);
827 + }
828 + LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
829 +
830 + LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
831 + {
832 +        ROLWir(8, r);
833 + }
834 + LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
835 +
836 + LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
837 + {
838 +        MOVLrr(s, d);
839 + }
840 + LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
841 +
842 + LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
843 + {
844 +        MOVLrm(s, d, X86_NOREG, X86_NOREG, 1);
845 + }
846 + LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
847 +
848 + LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
849 + {
850 +        MOVWrm(s, d, X86_NOREG, X86_NOREG, 1);
851 + }
852 + LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
853 +
854 + LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
855 + {
856 +        MOVWmr(s, X86_NOREG, X86_NOREG, 1, d);
857 + }
858 + LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
859 +
860 + LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
861 + {
862 +        MOVBrm(s, d, X86_NOREG, X86_NOREG, 1);
863 + }
864 + LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
865 +
866 + LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
867 + {
868 +        MOVBmr(s, X86_NOREG, X86_NOREG, 1, d);
869 + }
870 + LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
871 +
872 + LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
873 + {
874 +        MOVLir(s, d);
875 + }
876 + LENDFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
877 +
878 + LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
879 + {
880 +        MOVWir(s, d);
881 + }
882 + LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
883 +
884 + LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
885 + {
886 +        MOVBir(s, d);
887 + }
888 + LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
889 +
890 + LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
891 + {
892 +        ADCLim(s, d, X86_NOREG, X86_NOREG, 1);
893 + }
894 + LENDFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
895 +
896 + LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s))
897 + {
898 +        ADDLim(s, d, X86_NOREG, X86_NOREG, 1);
899 + }
900 + LENDFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s))
901 +
902 + LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s))
903 + {
904 +        ADDWim(s, d, X86_NOREG, X86_NOREG, 1);
905 + }
906 + LENDFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s))
907 +
908 + LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s))
909 + {
910 +        ADDBim(s, d, X86_NOREG, X86_NOREG, 1);
911 + }
912 + LENDFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s))
913 +
914 + LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
915 + {
916 +        TESTLir(i, d);
917 + }
918 + LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
919 +
920 + LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
921 + {
922 +        TESTLrr(s, d);
923 + }
924 + LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
925 +
926 + LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
927 + {
928 +        TESTWrr(s, d);
929 + }
930 + LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
931 +
932 + LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
933 + {
934 +        TESTBrr(s, d);
935 + }
936 + LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
937 +
938 + LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
939 + {
940 +        XORLir(i, d);
941 + }
942 + LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
943 +
944 + LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
945 + {
946 +        ANDLir(i, d);
947 + }
948 + LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
949 +
950 + LOWFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
951 + {
952 +        ANDWir(i, d);
953 + }
954 + LENDFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
955 +
956 + LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
957 + {
958 +        ANDLrr(s, d);
959 + }
960 + LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
961 +
962 + LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
963 + {
964 +        ANDWrr(s, d);
965 + }
966 + LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
967 +
968 + LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
969 + {
970 +        ANDBrr(s, d);
971 + }
972 + LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
973 +
974 + LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
975 + {
976 +        ORLir(i, d);
977 + }
978 + LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
979 +
980 + LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
981 + {
982 +        ORLrr(s, d);
983 + }
984 + LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
985 +
986 + LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
987 + {
988 +        ORWrr(s, d);
989 + }
990 + LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
991 +
992 + LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
993 + {
994 +        ORBrr(s, d);
995 + }
996 + LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
997 +
998 + LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
999 + {
1000 +        ADCLrr(s, d);
1001 + }
1002 + LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
1003 +
1004 + LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
1005 + {
1006 +        ADCWrr(s, d);
1007 + }
1008 + LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
1009 +
1010 + LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
1011 + {
1012 +        ADCBrr(s, d);
1013 + }
1014 + LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
1015 +
1016 + LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
1017 + {
1018 +        ADDLrr(s, d);
1019 + }
1020 + LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
1021 +
1022 + LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
1023 + {
1024 +        ADDWrr(s, d);
1025 + }
1026 + LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
1027 +
1028 + LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
1029 + {
1030 +        ADDBrr(s, d);
1031 + }
1032 + LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
1033 +
1034 + LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
1035 + {
1036 +        SUBLir(i, d);
1037 + }
1038 + LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
1039 +
1040 + LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
1041 + {
1042 +        SUBBir(i, d);
1043 + }
1044 + LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
1045 +
1046 + LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
1047 + {
1048 +        ADDLir(i, d);
1049 + }
1050 + LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
1051 +
1052 + LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
1053 + {
1054 +        ADDWir(i, d);
1055 + }
1056 + LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
1057 +
1058 + LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
1059 + {
1060 +        ADDBir(i, d);
1061 + }
1062 + LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
1063 +
1064 + LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
1065 + {
1066 +        SBBLrr(s, d);
1067 + }
1068 + LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
1069 +
1070 + LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
1071 + {
1072 +        SBBWrr(s, d);
1073 + }
1074 + LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
1075 +
1076 + LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
1077 + {
1078 +        SBBBrr(s, d);
1079 + }
1080 + LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
1081 +
1082 + LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
1083 + {
1084 +        SUBLrr(s, d);
1085 + }
1086 + LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
1087 +
1088 + LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
1089 + {
1090 +        SUBWrr(s, d);
1091 + }
1092 + LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
1093 +
1094 + LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
1095 + {
1096 +        SUBBrr(s, d);
1097 + }
1098 + LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
1099 +
1100 + LOWFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
1101 + {
1102 +        CMPLrr(s, d);
1103 + }
1104 + LENDFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
1105 +
1106 + LOWFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
1107 + {
1108 +        CMPLir(i, r);
1109 + }
1110 + LENDFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
1111 +
1112 + LOWFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
1113 + {
1114 +        CMPWrr(s, d);
1115 + }
1116 + LENDFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
1117 +
1118 + LOWFUNC(WRITE,READ,2,raw_cmp_b_mi,(MEMR d, IMM s))
1119 + {
1120 +        CMPBim(s, d, X86_NOREG, X86_NOREG, 1);
1121 + }
1122 + LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
1123 +
1124 + LOWFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
1125 + {
1126 +        CMPBir(i, d);
1127 + }
1128 + LENDFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
1129 +
1130 + LOWFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
1131 + {
1132 +        CMPBrr(s, d);
1133 + }
1134 + LENDFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
1135 +
1136 + LOWFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
1137 + {
1138 +        CMPLmr(offset, X86_NOREG, index, factor, d);
1139 + }
1140 + LENDFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
1141 +
1142 + LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
1143 + {
1144 +        XORLrr(s, d);
1145 + }
1146 + LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
1147 +
1148 + LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
1149 + {
1150 +        XORWrr(s, d);
1151 + }
1152 + LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
1153 +
1154 + LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
1155 + {
1156 +        XORBrr(s, d);
1157 + }
1158 + LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
1159 +
1160 + LOWFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
1161 + {
1162 +        SUBLim(s, d, X86_NOREG, X86_NOREG, 1);
1163 + }
1164 + LENDFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
1165 +
1166 + LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
1167 + {
1168 +        CMPLim(s, d, X86_NOREG, X86_NOREG, 1);
1169 + }
1170 + LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
1171 +
1172 + LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
1173 + {
1174 +        XCHGLrr(r2, r1);
1175 + }
1176 + LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
1177 +
1178 + LOWFUNC(READ,WRITE,0,raw_pushfl,(void))
1179 + {
1180 +        PUSHF();
1181 + }
1182 + LENDFUNC(READ,WRITE,0,raw_pushfl,(void))
1183 +
1184 + LOWFUNC(WRITE,READ,0,raw_popfl,(void))
1185 + {
1186 +        POPF();
1187 + }
1188 + LENDFUNC(WRITE,READ,0,raw_popfl,(void))
1189 +
1190 + #else
1191 +
1192   const bool optimize_accum               = true;
1193   const bool optimize_imm8                = true;
1194   const bool optimize_shift_once  = true;
# Line 157 | Line 1224 | LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
1224   }
1225   LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
1226  
1227 + LOWFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
1228 + {
1229 +        emit_byte(0x8f);
1230 +        emit_byte(0x05);
1231 +        emit_long(d);
1232 + }
1233 + LENDFUNC(NONE,READ,1,raw_pop_l_m,(MEMW d))
1234 +
1235   LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
1236   {
1237          emit_byte(0x0f);
# Line 1071 | Line 2146 | LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d
2146  
2147   LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
2148   {
2149 +        Dif(!isbyte(offset)) abort();
2150      emit_byte(0x8b);
2151      emit_byte(0x40+8*d+s);
2152      emit_byte(offset);
# Line 1079 | Line 2155 | LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d,
2155  
2156   LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
2157   {
2158 +        Dif(!isbyte(offset)) abort();
2159      emit_byte(0x66);
2160      emit_byte(0x8b);
2161      emit_byte(0x40+8*d+s);
# Line 1088 | Line 2165 | LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d,
2165  
2166   LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
2167   {
2168 +        Dif(!isbyte(offset)) abort();
2169      emit_byte(0x8a);
2170      emit_byte(0x40+8*d+s);
2171      emit_byte(offset);
# Line 1121 | Line 2199 | LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d
2199  
2200   LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
2201   {
2202 +        Dif(!isbyte(offset)) abort();
2203      emit_byte(0xc7);
2204      emit_byte(0x40+d);
2205      emit_byte(offset);
# Line 1130 | Line 2209 | LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d
2209  
2210   LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
2211   {
2212 +        Dif(!isbyte(offset)) abort();
2213      emit_byte(0x66);
2214      emit_byte(0xc7);
2215      emit_byte(0x40+d);
# Line 1140 | Line 2220 | LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d
2220  
2221   LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
2222   {
2223 +        Dif(!isbyte(offset)) abort();
2224      emit_byte(0xc6);
2225      emit_byte(0x40+d);
2226      emit_byte(offset);
# Line 1149 | Line 2230 | LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d
2230  
2231   LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
2232   {
2233 +        Dif(!isbyte(offset)) abort();
2234      emit_byte(0x89);
2235      emit_byte(0x40+8*s+d);
2236      emit_byte(offset);
# Line 1157 | Line 2239 | LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d
2239  
2240   LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
2241   {
2242 +        Dif(!isbyte(offset)) abort();
2243      emit_byte(0x66);
2244      emit_byte(0x89);
2245      emit_byte(0x40+8*s+d);
# Line 1166 | Line 2249 | LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d
2249  
2250   LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
2251   {
2252 +        Dif(!isbyte(offset)) abort();
2253      emit_byte(0x88);
2254      emit_byte(0x40+8*s+d);
2255      emit_byte(offset);
# Line 1440 | Line 2524 | LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d
2524   }
2525   LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
2526  
2527 + LOWFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
2528 + {
2529 +    emit_byte(0x81);
2530 +    emit_byte(0xf0+d);
2531 +    emit_long(i);
2532 + }
2533 + LENDFUNC(WRITE,NONE,2,raw_xor_l_ri,(RW4 d, IMM i))
2534 +
2535   LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
2536   {
2537          if (optimize_imm8 && isbyte(i)) {
# Line 1856 | Line 2948 | LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r
2948   LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
2949  
2950   /*************************************************************************
1859 – * FIXME: string-related instructions                                    *
1860 – *************************************************************************/
1861 –
1862 – LOWFUNC(WRITE,NONE,0,raw_cld,(void))
1863 – {
1864 –        emit_byte(0xfc);
1865 – }
1866 – LENDFUNC(WRITE,NONE,0,raw_cld,(void))
1867 –
1868 – LOWFUNC(WRITE,NONE,0,raw_std,(void))
1869 – {
1870 –        emit_byte(0xfd);
1871 – }
1872 – LENDFUNC(WRITE,NONE,0,raw_std,(void))
1873 –
1874 – LOWFUNC(NONE,RMW,0,raw_movs_b,(void))
1875 – {
1876 –        emit_byte(0xa4);
1877 – }
1878 – LENDFUNC(NONE,RMW,0,raw_movs_b,(void))
1879 –
1880 – LOWFUNC(NONE,RMW,0,raw_movs_l,(void))
1881 – {
1882 –        emit_byte(0xa5);
1883 – }
1884 – LENDFUNC(NONE,RMW,0,raw_movs_l,(void))
1885 –
1886 – LOWFUNC(NONE,RMW,0,raw_rep,(void))
1887 – {
1888 –        emit_byte(0xf3);
1889 – }
1890 – LENDFUNC(NONE,RMW,0,raw_rep,(void))
1891 –
1892 – LOWFUNC(NONE,RMW,0,raw_rep_movsb,(void))
1893 – {
1894 –        raw_rep();
1895 –        raw_movs_b();
1896 – }
1897 – LENDFUNC(NONE,RMW,0,raw_rep_movsb,(void))
1898 –
1899 – LOWFUNC(NONE,RMW,0,raw_rep_movsl,(void))
1900 – {
1901 –        raw_rep();
1902 –        raw_movs_l();
1903 – }
1904 – LENDFUNC(NONE,RMW,0,raw_rep_movsl,(void))
1905 –
1906 – /*************************************************************************
2951   * FIXME: mem access modes probably wrong                                *
2952   *************************************************************************/
2953  
# Line 1919 | Line 2963 | LOWFUNC(WRITE,READ,0,raw_popfl,(void))
2963   }
2964   LENDFUNC(WRITE,READ,0,raw_popfl,(void))
2965  
2966 + #endif
2967 +
2968   /*************************************************************************
2969   * Unoptimizable stuff --- jump                                          *
2970   *************************************************************************/
2971  
2972   static __inline__ void raw_call_r(R4 r)
2973   {
2974 + #if USE_NEW_RTASM
2975 +    CALLsr(r);
2976 + #else
2977      emit_byte(0xff);
2978      emit_byte(0xd0+r);
2979 + #endif
2980   }
2981  
2982   static __inline__ void raw_call_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
2983   {
2984 + #if USE_NEW_RTASM
2985 +    CALLsm(base, X86_NOREG, r, m);
2986 + #else
2987      int mu;
2988      switch(m) {
2989       case 1: mu=0; break;
# Line 1943 | Line 2996 | static __inline__ void raw_call_m_indexe
2996      emit_byte(0x14);
2997      emit_byte(0x05+8*r+0x40*mu);
2998      emit_long(base);
2999 + #endif
3000   }
3001  
3002   static __inline__ void raw_jmp_r(R4 r)
3003   {
3004 + #if USE_NEW_RTASM
3005 +    JMPsr(r);
3006 + #else
3007      emit_byte(0xff);
3008      emit_byte(0xe0+r);
3009 + #endif
3010   }
3011  
3012   static __inline__ void raw_jmp_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
3013   {
3014 + #if USE_NEW_RTASM
3015 +    JMPsm(base, X86_NOREG, r, m);
3016 + #else
3017      int mu;
3018      switch(m) {
3019       case 1: mu=0; break;
# Line 1965 | Line 3026 | static __inline__ void raw_jmp_m_indexed
3026      emit_byte(0x24);
3027      emit_byte(0x05+8*r+0x40*mu);
3028      emit_long(base);
3029 + #endif
3030   }
3031  
3032   static __inline__ void raw_jmp_m(uae_u32 base)
# Line 1977 | Line 3039 | static __inline__ void raw_jmp_m(uae_u32
3039  
3040   static __inline__ void raw_call(uae_u32 t)
3041   {
3042 + #if USE_NEW_RTASM
3043 +    CALLm(t);
3044 + #else
3045      emit_byte(0xe8);
3046      emit_long(t-(uae_u32)target-4);
3047 + #endif
3048   }
3049  
3050   static __inline__ void raw_jmp(uae_u32 t)
3051   {
3052 + #if USE_NEW_RTASM
3053 +    JMPm(t);
3054 + #else
3055      emit_byte(0xe9);
3056      emit_long(t-(uae_u32)target-4);
3057 + #endif
3058   }
3059  
3060   static __inline__ void raw_jl(uae_u32 t)
3061   {
3062      emit_byte(0x0f);
3063      emit_byte(0x8c);
3064 <    emit_long(t-(uae_u32)target-4);
3064 >    emit_long(t-(uintptr)target-4);
3065   }
3066  
3067   static __inline__ void raw_jz(uae_u32 t)
3068   {
3069      emit_byte(0x0f);
3070      emit_byte(0x84);
3071 <    emit_long(t-(uae_u32)target-4);
3071 >    emit_long(t-(uintptr)target-4);
3072   }
3073  
3074   static __inline__ void raw_jnz(uae_u32 t)
3075   {
3076      emit_byte(0x0f);
3077      emit_byte(0x85);
3078 <    emit_long(t-(uae_u32)target-4);
3078 >    emit_long(t-(uintptr)target-4);
3079   }
3080  
3081   static __inline__ void raw_jnz_l_oponly(void)
# Line 2055 | Line 3125 | static __inline__ void raw_nop(void)
3125      emit_byte(0x90);
3126   }
3127  
3128 + static __inline__ void raw_emit_nop_filler(int nbytes)
3129 + {
3130 +  /* Source: GNU Binutils 2.12.90.0.15 */
3131 +  /* Various efficient no-op patterns for aligning code labels.
3132 +     Note: Don't try to assemble the instructions in the comments.
3133 +     0L and 0w are not legal.  */
3134 +  static const uae_u8 f32_1[] =
3135 +    {0x90};                                                                     /* nop                                  */
3136 +  static const uae_u8 f32_2[] =
3137 +    {0x89,0xf6};                                                        /* movl %esi,%esi               */
3138 +  static const uae_u8 f32_3[] =
3139 +    {0x8d,0x76,0x00};                                           /* leal 0(%esi),%esi    */
3140 +  static const uae_u8 f32_4[] =
3141 +    {0x8d,0x74,0x26,0x00};                                      /* leal 0(%esi,1),%esi  */
3142 +  static const uae_u8 f32_5[] =
3143 +    {0x90,                                                                      /* nop                                  */
3144 +     0x8d,0x74,0x26,0x00};                                      /* leal 0(%esi,1),%esi  */
3145 +  static const uae_u8 f32_6[] =
3146 +    {0x8d,0xb6,0x00,0x00,0x00,0x00};            /* leal 0L(%esi),%esi   */
3147 +  static const uae_u8 f32_7[] =
3148 +    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
3149 +  static const uae_u8 f32_8[] =
3150 +    {0x90,                                                                      /* nop                                  */
3151 +     0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
3152 +  static const uae_u8 f32_9[] =
3153 +    {0x89,0xf6,                                                         /* movl %esi,%esi               */
3154 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3155 +  static const uae_u8 f32_10[] =
3156 +    {0x8d,0x76,0x00,                                            /* leal 0(%esi),%esi    */
3157 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3158 +  static const uae_u8 f32_11[] =
3159 +    {0x8d,0x74,0x26,0x00,                                       /* leal 0(%esi,1),%esi  */
3160 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3161 +  static const uae_u8 f32_12[] =
3162 +    {0x8d,0xb6,0x00,0x00,0x00,0x00,                     /* leal 0L(%esi),%esi   */
3163 +     0x8d,0xbf,0x00,0x00,0x00,0x00};            /* leal 0L(%edi),%edi   */
3164 +  static const uae_u8 f32_13[] =
3165 +    {0x8d,0xb6,0x00,0x00,0x00,0x00,                     /* leal 0L(%esi),%esi   */
3166 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3167 +  static const uae_u8 f32_14[] =
3168 +    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00,        /* leal 0L(%esi,1),%esi */
3169 +     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
3170 +  static const uae_u8 f32_15[] =
3171 +    {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90,        /* jmp .+15; lotsa nops */
3172 +     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
3173 +  static const uae_u8 f32_16[] =
3174 +    {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90,        /* jmp .+15; lotsa nops */
3175 +     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
3176 +  static const uae_u8 *const f32_patt[] = {
3177 +    f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
3178 +    f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
3179 +  };
3180 +  static const uae_u8 prefixes[4] = { 0x66, 0x66, 0x66, 0x66 };
3181 +
3182 + #if defined(__x86_64__)
3183 +  /* The recommended way to pad 64bit code is to use NOPs preceded by
3184 +     maximally four 0x66 prefixes.  Balance the size of nops.  */
3185 +  if (nbytes == 0)
3186 +          return;
3187 +
3188 +  int i;
3189 +  int nnops = (nbytes + 3) / 4;
3190 +  int len = nbytes / nnops;
3191 +  int remains = nbytes - nnops * len;
3192 +
3193 +  for (i = 0; i < remains; i++) {
3194 +          emit_block(prefixes, len);
3195 +          raw_nop();
3196 +  }
3197 +  for (; i < nnops; i++) {
3198 +          emit_block(prefixes, len - 1);
3199 +          raw_nop();
3200 +  }
3201 + #else
3202 +  int nloops = nbytes / 16;
3203 +  while (nloops-- > 0)
3204 +        emit_block(f32_16, sizeof(f32_16));
3205 +
3206 +  nbytes %= 16;
3207 +  if (nbytes)
3208 +        emit_block(f32_patt[nbytes - 1], nbytes);
3209 + #endif
3210 + }
3211 +
3212  
3213   /*************************************************************************
3214   * Flag handling, to and fro UAE flag register                           *
# Line 2068 | Line 3222 | static __inline__ void raw_flags_to_reg(
3222   {
3223    raw_lahf(0);  /* Most flags in AH */
3224    //raw_setcc(r,0); /* V flag in AL */
3225 <  raw_setcc_m((uae_u32)live.state[FLAGTMP].mem,0);
3225 >  raw_setcc_m((uintptr)live.state[FLAGTMP].mem,0);
3226    
3227   #if 1   /* Let's avoid those nasty partial register stalls */
3228 <  //raw_mov_b_mr((uae_u32)live.state[FLAGTMP].mem,r);
3229 <  raw_mov_b_mr(((uae_u32)live.state[FLAGTMP].mem)+1,r+4);
3228 >  //raw_mov_b_mr((uintptr)live.state[FLAGTMP].mem,r);
3229 >  raw_mov_b_mr(((uintptr)live.state[FLAGTMP].mem)+1,r+4);
3230    //live.state[FLAGTMP].status=CLEAN;
3231    live.state[FLAGTMP].status=INMEM;
3232    live.state[FLAGTMP].realreg=-1;
# Line 2092 | Line 3246 | static __inline__ void raw_reg_to_flags(
3246    raw_sahf(0);
3247   }
3248  
3249 + #define FLAG_NREG3 0  /* Set to -1 if any register will do */
3250 + static __inline__ void raw_flags_set_zero(int s, int tmp)
3251 + {
3252 +    raw_mov_l_rr(tmp,s);
3253 +    raw_lahf(s); /* flags into ah */
3254 +    raw_and_l_ri(s,0xffffbfff);
3255 +    raw_and_l_ri(tmp,0x00004000);
3256 +    raw_xor_l_ri(tmp,0x00004000);
3257 +    raw_or_l(s,tmp);
3258 +    raw_sahf(s);
3259 + }
3260 +
3261   #else
3262  
3263   #define FLAG_NREG1 -1  /* Set to -1 if any register will do */
# Line 2099 | Line 3265 | static __inline__ void raw_flags_to_reg(
3265   {
3266          raw_pushfl();
3267          raw_pop_l_r(r);
3268 <        raw_mov_l_mr((uae_u32)live.state[FLAGTMP].mem,r);
3268 >        raw_mov_l_mr((uintptr)live.state[FLAGTMP].mem,r);
3269   //      live.state[FLAGTMP].status=CLEAN;
3270          live.state[FLAGTMP].status=INMEM;
3271          live.state[FLAGTMP].realreg=-1;
# Line 2118 | Line 3284 | static __inline__ void raw_reg_to_flags(
3284          raw_popfl();
3285   }
3286  
3287 + #define FLAG_NREG3 -1  /* Set to -1 if any register will do */
3288 + static __inline__ void raw_flags_set_zero(int s, int tmp)
3289 + {
3290 +    raw_mov_l_rr(tmp,s);
3291 +    raw_pushfl();
3292 +    raw_pop_l_r(s);
3293 +    raw_and_l_ri(s,0xffffffbf);
3294 +    raw_and_l_ri(tmp,0x00000040);
3295 +    raw_xor_l_ri(tmp,0x00000040);
3296 +    raw_or_l(s,tmp);
3297 +    raw_push_l_r(s);
3298 +    raw_popfl();
3299 + }
3300   #endif
3301  
3302   /* Apparently, there are enough instructions between flag store and
# Line 2125 | Line 3304 | static __inline__ void raw_reg_to_flags(
3304   static __inline__ void raw_load_flagreg(uae_u32 target, uae_u32 r)
3305   {
3306   #if 1
3307 <    raw_mov_l_rm(target,(uae_u32)live.state[r].mem);
3307 >    raw_mov_l_rm(target,(uintptr)live.state[r].mem);
3308   #else
3309 <    raw_mov_b_rm(target,(uae_u32)live.state[r].mem);
3310 <    raw_mov_b_rm(target+4,((uae_u32)live.state[r].mem)+1);
3309 >    raw_mov_b_rm(target,(uintptr)live.state[r].mem);
3310 >    raw_mov_b_rm(target+4,((uintptr)live.state[r].mem)+1);
3311   #endif
3312   }
3313  
# Line 2136 | Line 3315 | static __inline__ void raw_load_flagreg(
3315   static __inline__ void raw_load_flagx(uae_u32 target, uae_u32 r)
3316   {
3317      if (live.nat[target].canbyte)
3318 <        raw_mov_b_rm(target,(uae_u32)live.state[r].mem);
3318 >        raw_mov_b_rm(target,(uintptr)live.state[r].mem);
3319      else if (live.nat[target].canword)
3320 <        raw_mov_w_rm(target,(uae_u32)live.state[r].mem);
3320 >        raw_mov_w_rm(target,(uintptr)live.state[r].mem);
3321      else
3322 <        raw_mov_l_rm(target,(uae_u32)live.state[r].mem);
3322 >        raw_mov_l_rm(target,(uintptr)live.state[r].mem);
3323   }
3324  
2146 –
3325   static __inline__ void raw_inc_sp(int off)
3326   {
3327      raw_add_l_ri(ESP_INDEX,off);
# Line 2305 | Line 3483 | static void vec(int x, struct sigcontext
3483                  for (i=0;i<5;i++)
3484                      vecbuf[i]=target[i];
3485                  emit_byte(0xe9);
3486 <                emit_long((uae_u32)veccode-(uae_u32)target-4);
3486 >                emit_long((uintptr)veccode-(uintptr)target-4);
3487                  write_log("Create jump to %p\n",veccode);
3488              
3489                  write_log("Handled one access!\n");
# Line 2332 | Line 3510 | static void vec(int x, struct sigcontext
3510                  }
3511                  for (i=0;i<5;i++)
3512                      raw_mov_b_mi(sc.eip+i,vecbuf[i]);
3513 <                raw_mov_l_mi((uae_u32)&in_handler,0);
3513 >                raw_mov_l_mi((uintptr)&in_handler,0);
3514                  emit_byte(0xe9);
3515 <                emit_long(sc.eip+len-(uae_u32)target-4);
3515 >                emit_long(sc.eip+len-(uintptr)target-4);
3516                  in_handler=1;
3517                  target=tmp;
3518              }
# Line 2429 | Line 3607 | enum {
3607    X86_PROCESSOR_K6,
3608    X86_PROCESSOR_ATHLON,
3609    X86_PROCESSOR_PENTIUM4,
3610 +  X86_PROCESSOR_K8,
3611    X86_PROCESSOR_max
3612   };
3613  
# Line 2439 | Line 3618 | static const char * x86_processor_string
3618    "PentiumPro",
3619    "K6",
3620    "Athlon",
3621 <  "Pentium4"
3621 >  "Pentium4",
3622 >  "K8"
3623   };
3624  
3625   static struct ptt {
# Line 2456 | Line 3636 | x86_alignments[X86_PROCESSOR_max] = {
3636    { 16, 15, 16,  7, 16 },
3637    { 32,  7, 32,  7, 32 },
3638    { 16,  7, 16,  7, 16 },
3639 <  {  0,  0,  0,  0,  0 }
3639 >  {  0,  0,  0,  0,  0 },
3640 >  { 16,  7, 16,  7, 16 }
3641   };
3642  
3643   static void
# Line 2490 | Line 3671 | x86_get_cpu_vendor(struct cpuinfo_x86 *c
3671   static void
3672   cpuid(uae_u32 op, uae_u32 *eax, uae_u32 *ebx, uae_u32 *ecx, uae_u32 *edx)
3673   {
3674 <  static uae_u8 cpuid_space[256];  
3674 >  const int CPUID_SPACE = 4096;
3675 >  uae_u8* cpuid_space = (uae_u8 *)vm_acquire(CPUID_SPACE);
3676 >  if (cpuid_space == VM_MAP_FAILED)
3677 >    abort();
3678 >  vm_protect(cpuid_space, CPUID_SPACE, VM_PAGE_READ | VM_PAGE_WRITE | VM_PAGE_EXECUTE);
3679 >
3680 >  static uae_u32 s_op, s_eax, s_ebx, s_ecx, s_edx;
3681    uae_u8* tmp=get_target();
3682  
3683 +  s_op = op;
3684    set_target(cpuid_space);
3685    raw_push_l_r(0); /* eax */
3686    raw_push_l_r(1); /* ecx */
3687    raw_push_l_r(2); /* edx */
3688    raw_push_l_r(3); /* ebx */
3689 <  raw_mov_l_rm(0,(uae_u32)&op);
3689 >  raw_mov_l_rm(0,(uintptr)&s_op);
3690    raw_cpuid(0);
3691 <  if (eax != NULL) raw_mov_l_mr((uae_u32)eax,0);
3692 <  if (ebx != NULL) raw_mov_l_mr((uae_u32)ebx,3);
3693 <  if (ecx != NULL) raw_mov_l_mr((uae_u32)ecx,1);
3694 <  if (edx != NULL) raw_mov_l_mr((uae_u32)edx,2);
3691 >  raw_mov_l_mr((uintptr)&s_eax,0);
3692 >  raw_mov_l_mr((uintptr)&s_ebx,3);
3693 >  raw_mov_l_mr((uintptr)&s_ecx,1);
3694 >  raw_mov_l_mr((uintptr)&s_edx,2);
3695    raw_pop_l_r(3);
3696    raw_pop_l_r(2);
3697    raw_pop_l_r(1);
# Line 2512 | Line 3700 | cpuid(uae_u32 op, uae_u32 *eax, uae_u32
3700    set_target(tmp);
3701  
3702    ((cpuop_func*)cpuid_space)(0);
3703 +  if (eax != NULL) *eax = s_eax;
3704 +  if (ebx != NULL) *ebx = s_ebx;
3705 +  if (ecx != NULL) *ecx = s_ecx;
3706 +  if (edx != NULL) *edx = s_edx;
3707 +
3708 +  vm_release(cpuid_space, CPUID_SPACE);
3709   }
3710  
3711   static void
# Line 2520 | Line 3714 | raw_init_cpu(void)
3714    struct cpuinfo_x86 *c = &cpuinfo;
3715  
3716    /* Defaults */
3717 +  c->x86_processor = X86_PROCESSOR_max;
3718    c->x86_vendor = X86_VENDOR_UNKNOWN;
3719    c->cpuid_level = -1;                          /* CPUID not detected */
3720    c->x86_model = c->x86_mask = 0;       /* So far unknown... */
# Line 2555 | Line 3750 | raw_init_cpu(void)
3750          c->x86 = 4;
3751    }
3752  
3753 +  /* AMD-defined flags: level 0x80000001 */
3754 +  uae_u32 xlvl;
3755 +  cpuid(0x80000000, &xlvl, NULL, NULL, NULL);
3756 +  if ( (xlvl & 0xffff0000) == 0x80000000 ) {
3757 +        if ( xlvl >= 0x80000001 ) {
3758 +          uae_u32 features;
3759 +          cpuid(0x80000001, NULL, NULL, NULL, &features);
3760 +          if (features & (1 << 29)) {
3761 +                /* Assume x86-64 if long mode is supported */
3762 +                c->x86_processor = X86_PROCESSOR_K8;
3763 +          }
3764 +        }
3765 +  }
3766 +          
3767    /* Canonicalize processor ID */
2559 –  c->x86_processor = X86_PROCESSOR_max;
3768    switch (c->x86) {
3769    case 3:
3770          c->x86_processor = X86_PROCESSOR_I386;
# Line 2578 | Line 3786 | raw_init_cpu(void)
3786          break;
3787    case 15:
3788          if (c->x86_vendor == X86_VENDOR_INTEL) {
3789 <          /*  Assume any BranID >= 8 and family == 15 yields a Pentium 4 */
3789 >          /* Assume any BrandID >= 8 and family == 15 yields a Pentium 4 */
3790            if (c->x86_brand_id >= 8)
3791                  c->x86_processor = X86_PROCESSOR_PENTIUM4;
3792          }
3793 +        if (c->x86_vendor == X86_VENDOR_AMD) {
3794 +          /* Assume an Athlon processor if family == 15 and it was not
3795 +             detected as an x86-64 so far */
3796 +          if (c->x86_processor == X86_PROCESSOR_max)
3797 +                c->x86_processor = X86_PROCESSOR_ATHLON;
3798 +        }
3799          break;
3800    }
3801    if (c->x86_processor == X86_PROCESSOR_max) {
# Line 2589 | Line 3803 | raw_init_cpu(void)
3803          fprintf(stderr, "  Family  : %d\n", c->x86);
3804          fprintf(stderr, "  Model   : %d\n", c->x86_model);
3805          fprintf(stderr, "  Mask    : %d\n", c->x86_mask);
3806 +        fprintf(stderr, "  Vendor  : %s [%d]\n", c->x86_vendor_id, c->x86_vendor);
3807          if (c->x86_brand_id)
3808            fprintf(stderr, "  BrandID : %02x\n", c->x86_brand_id);
3809          abort();
3810    }
3811  
3812    /* Have CMOV support? */
3813 <  have_cmov = (c->x86_hwcap & (1 << 15)) && true;
3813 >  have_cmov = c->x86_hwcap & (1 << 15);
3814  
3815    /* Can the host CPU suffer from partial register stalls? */
3816    have_rat_stall = (c->x86_vendor == X86_VENDOR_INTEL);
# Line 2618 | Line 3833 | raw_init_cpu(void)
3833                          x86_processor_string_table[c->x86_processor]);
3834   }
3835  
3836 + static bool target_check_bsf(void)
3837 + {
3838 +        bool mismatch = false;
3839 +        for (int g_ZF = 0; g_ZF <= 1; g_ZF++) {
3840 +        for (int g_CF = 0; g_CF <= 1; g_CF++) {
3841 +        for (int g_OF = 0; g_OF <= 1; g_OF++) {
3842 +        for (int g_SF = 0; g_SF <= 1; g_SF++) {
3843 +                for (int value = -1; value <= 1; value++) {
3844 +                        unsigned long flags = (g_SF << 7) | (g_OF << 11) | (g_ZF << 6) | g_CF;
3845 +                        unsigned long tmp = value;
3846 +                        __asm__ __volatile__ ("push %0; popf; bsf %1,%1; pushf; pop %0"
3847 +                                                                  : "+r" (flags), "+r" (tmp) : : "cc");
3848 +                        int OF = (flags >> 11) & 1;
3849 +                        int SF = (flags >>  7) & 1;
3850 +                        int ZF = (flags >>  6) & 1;
3851 +                        int CF = flags & 1;
3852 +                        tmp = (value == 0);
3853 +                        if (ZF != tmp || SF != g_SF || OF != g_OF || CF != g_CF)
3854 +                                mismatch = true;
3855 +                }
3856 +        }}}}
3857 +        if (mismatch)
3858 +                write_log("Target CPU defines all flags on BSF instruction\n");
3859 +        return !mismatch;
3860 + }
3861 +
3862  
3863   /*************************************************************************
3864   * FPU stuff                                                             *
# Line 2740 | Line 3981 | static __inline__ void tos_make(int r)
3981      emit_byte(0xd8+(live.tos+1)-live.spos[r]);  /* store top of stack in reg,
3982                                           and pop it*/
3983   }
3984 <    
3985 <        
3984 >
3985 > /* FP helper functions */
3986 > #if USE_NEW_RTASM
3987 > #define DEFINE_OP(NAME, GEN)                    \
3988 > static inline void raw_##NAME(uint32 m)         \
3989 > {                                               \
3990 >    GEN(m, X86_NOREG, X86_NOREG, 1);            \
3991 > }
3992 > DEFINE_OP(fstl,  FSTLm);
3993 > DEFINE_OP(fstpl, FSTPLm);
3994 > DEFINE_OP(fldl,  FLDLm);
3995 > DEFINE_OP(fildl, FILDLm);
3996 > DEFINE_OP(fistl, FISTLm);
3997 > DEFINE_OP(flds,  FLDSm);
3998 > DEFINE_OP(fsts,  FSTSm);
3999 > DEFINE_OP(fstpt, FSTPTm);
4000 > DEFINE_OP(fldt,  FLDTm);
4001 > #else
4002 > #define DEFINE_OP(NAME, OP1, OP2)               \
4003 > static inline void raw_##NAME(uint32 m)         \
4004 > {                                               \
4005 >    emit_byte(OP1);                             \
4006 >    emit_byte(OP2);                             \
4007 >    emit_long(m);                               \
4008 > }
4009 > DEFINE_OP(fstl,  0xdd, 0x15);
4010 > DEFINE_OP(fstpl, 0xdd, 0x1d);
4011 > DEFINE_OP(fldl,  0xdd, 0x05);
4012 > DEFINE_OP(fildl, 0xdb, 0x05);
4013 > DEFINE_OP(fistl, 0xdb, 0x15);
4014 > DEFINE_OP(flds,  0xd9, 0x05);
4015 > DEFINE_OP(fsts,  0xd9, 0x15);
4016 > DEFINE_OP(fstpt, 0xdb, 0x3d);
4017 > DEFINE_OP(fldt,  0xdb, 0x2d);
4018 > #endif
4019 > #undef DEFINE_OP
4020 >
4021   LOWFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW m, FR r))
4022   {
4023      make_tos(r);
4024 <    emit_byte(0xdd);
2749 <    emit_byte(0x15);
2750 <    emit_long(m);
4024 >    raw_fstl(m);
4025   }
4026   LENDFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW m, FR r))
4027  
4028   LOWFUNC(NONE,WRITE,2,raw_fmov_mr_drop,(MEMW m, FR r))
4029   {
4030      make_tos(r);
4031 <    emit_byte(0xdd);
2758 <    emit_byte(0x1d);
2759 <    emit_long(m);
4031 >    raw_fstpl(m);
4032      live.onstack[live.tos]=-1;
4033      live.tos--;
4034      live.spos[r]=-2;
# Line 2765 | Line 4037 | LENDFUNC(NONE,WRITE,2,raw_fmov_mr,(MEMW
4037  
4038   LOWFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMR m))
4039   {
4040 <    emit_byte(0xdd);
2769 <    emit_byte(0x05);
2770 <    emit_long(m);
4040 >    raw_fldl(m);
4041      tos_make(r);
4042   }
4043   LENDFUNC(NONE,READ,2,raw_fmov_rm,(FW r, MEMR m))
4044  
4045   LOWFUNC(NONE,READ,2,raw_fmovi_rm,(FW r, MEMR m))
4046   {
4047 <    emit_byte(0xdb);
2778 <    emit_byte(0x05);
2779 <    emit_long(m);
4047 >    raw_fildl(m);
4048      tos_make(r);
4049   }
4050   LENDFUNC(NONE,READ,2,raw_fmovi_rm,(FW r, MEMR m))
# Line 2784 | Line 4052 | LENDFUNC(NONE,READ,2,raw_fmovi_rm,(FW r,
4052   LOWFUNC(NONE,WRITE,2,raw_fmovi_mr,(MEMW m, FR r))
4053   {
4054      make_tos(r);
4055 <    emit_byte(0xdb);
2788 <    emit_byte(0x15);
2789 <    emit_long(m);
4055 >    raw_fistl(m);
4056   }
4057   LENDFUNC(NONE,WRITE,2,raw_fmovi_mr,(MEMW m, FR r))
4058  
4059   LOWFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m))
4060   {
4061 <    emit_byte(0xd9);
2796 <    emit_byte(0x05);
2797 <    emit_long(m);
4061 >    raw_flds(m);
4062      tos_make(r);
4063   }
4064   LENDFUNC(NONE,READ,2,raw_fmovs_rm,(FW r, MEMR m))
# Line 2802 | Line 4066 | LENDFUNC(NONE,READ,2,raw_fmovs_rm,(FW r,
4066   LOWFUNC(NONE,WRITE,2,raw_fmovs_mr,(MEMW m, FR r))
4067   {
4068      make_tos(r);
4069 <    emit_byte(0xd9);
2806 <    emit_byte(0x15);
2807 <    emit_long(m);
4069 >    raw_fsts(m);
4070   }
4071   LENDFUNC(NONE,WRITE,2,raw_fmovs_mr,(MEMW m, FR r))
4072  
# Line 2819 | Line 4081 | LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(ME
4081      emit_byte(0xd9);     /* Get a copy to the top of stack */
4082      emit_byte(0xc0+rs);
4083  
4084 <    emit_byte(0xdb);  /* store and pop it */
2823 <    emit_byte(0x3d);
2824 <    emit_long(m);
4084 >    raw_fstpt(m);       /* store and pop it */
4085   }
4086   LENDFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(MEMW m, FR r))
4087  
# Line 2830 | Line 4090 | LOWFUNC(NONE,WRITE,2,raw_fmov_ext_mr_dro
4090      int rs;
4091  
4092      make_tos(r);
4093 <    emit_byte(0xdb);  /* store and pop it */
2834 <    emit_byte(0x3d);
2835 <    emit_long(m);
4093 >    raw_fstpt(m);       /* store and pop it */
4094      live.onstack[live.tos]=-1;
4095      live.tos--;
4096      live.spos[r]=-2;
# Line 2841 | Line 4099 | LENDFUNC(NONE,WRITE,2,raw_fmov_ext_mr,(M
4099  
4100   LOWFUNC(NONE,READ,2,raw_fmov_ext_rm,(FW r, MEMR m))
4101   {
4102 <    emit_byte(0xdb);
2845 <    emit_byte(0x2d);
2846 <    emit_long(m);
4102 >    raw_fldt(m);
4103      tos_make(r);
4104   }
4105   LENDFUNC(NONE,READ,2,raw_fmov_ext_rm,(FW r, MEMR m))
# Line 3052 | Line 4308 | LOWFUNC(NONE,NONE,2,raw_ftwotox_rr,(FW d
4308      emit_byte(0xf0);  /* f2xm1 */
4309      emit_byte(0xdc);
4310      emit_byte(0x05);
4311 <    emit_long((uae_u32)&one);  /* Add '1' without using extra stack space */
4311 >    emit_long((uintptr)&one);  /* Add '1' without using extra stack space */
4312      emit_byte(0xd9);
4313      emit_byte(0xfd);  /* and scale it */
4314      emit_byte(0xdd);
# Line 3086 | Line 4342 | LOWFUNC(NONE,NONE,2,raw_fetox_rr,(FW d,
4342      emit_byte(0xf0);  /* f2xm1 */
4343      emit_byte(0xdc);
4344      emit_byte(0x05);
4345 <    emit_long((uae_u32)&one);  /* Add '1' without using extra stack space */
4345 >    emit_long((uintptr)&one);  /* Add '1' without using extra stack space */
4346      emit_byte(0xd9);
4347      emit_byte(0xfd);  /* and scale it */
4348      emit_byte(0xdd);

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