[ViewVC] Diff of: cebix/BasiliskII/src/uae_cpu/compiler/codegen

Comparing BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp (file contents):
Revision 1.6 by gbeauche, 2002-10-03T16:13:46Z vs.
Revision 1.22 by gbeauche, 2004-11-01T18:40:30Z

+ *  Original 68040 JIT compiler for UAE, copyright 2000-2002 Bernd Meyer
-<
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2002
->
+ *  Adaptation for Basilisk II and improvements, copyright 2000-2004
+ *    Gwenole Beauchesne
-<
+ *  Basilisk II (C) 1997-2002 Christian Bauer
->
+ *  Basilisk II (C) 1997-2004 Christian Bauer
->
+ *
->
+ *  Portions related to CPU detection come from linux/arch/i386/kernel/setup.c
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+#define EBP_INDEX 5
+#define ESI_INDEX 6
+#define EDI_INDEX 7
-+
+#if defined(__x86_64__)
-+
+#define R8_INDEX  8
-+
+#define R9_INDEX  9
-+
+#define R10_INDEX 10
-+
+#define R11_INDEX 11
-+
+#define R12_INDEX 12
-+
+#define R13_INDEX 13
-+
+#define R14_INDEX 14
-+
+#define R15_INDEX 15
-+
+#endif
+/* The register in which subroutines return an integer return value */
-<
+#define REG_RESULT 0
->
+#define REG_RESULT EAX_INDEX
+/* The registers subroutines take their first and second argument in */
+#if defined( _MSC_VER ) && !defined( USE_NORMAL_CALLING_CONVENTION )
+/* Handle the _fastcall parameters of ECX and EDX */
-<
+#define REG_PAR1 1
-<
+#define REG_PAR2 2
->
+#define REG_PAR1 ECX_INDEX
->
+#define REG_PAR2 EDX_INDEX
->
+#elif defined(__x86_64__)
->
+#define REG_PAR1 EDI_INDEX
->
+#define REG_PAR2 ESI_INDEX
+#else
-<
+#define REG_PAR1 0
-<
+#define REG_PAR2 2
->
+#define REG_PAR1 EAX_INDEX
->
+#define REG_PAR2 EDX_INDEX
+#endif
-<
+/* Three registers that are not used for any of the above */
-<
+#define REG_NOPAR1 6
-<
+#define REG_NOPAR2 5
-<
+#define REG_NOPAR3 3
-<
-<
+#define REG_PC_PRE 0 /* The register we use for preloading regs.pc_p */
->
+#define REG_PC_PRE EAX_INDEX /* The register we use for preloading regs.pc_p */
+#if defined( _MSC_VER ) && !defined( USE_NORMAL_CALLING_CONVENTION )
-<
+#define REG_PC_TMP 0
->
+#define REG_PC_TMP EAX_INDEX
+#else
-<
+#define REG_PC_TMP 1 /* Another register that is not the above */
->
+#define REG_PC_TMP ECX_INDEX /* Another register that is not the above */
+#endif
-<
+#define SHIFTCOUNT_NREG 1  /* Register that can be used for shiftcount.
->
+#define SHIFTCOUNT_NREG ECX_INDEX  /* Register that can be used for shiftcount.
+                              -1 if any reg will do */
-<
+#define MUL_NREG1 0 /* %eax will hold the low 32 bits after a 32x32 mul */
-<
+#define MUL_NREG2 2 /* %edx will hold the high 32 bits */
->
+#define MUL_NREG1 EAX_INDEX /* %eax will hold the low 32 bits after a 32x32 mul */
->
+#define MUL_NREG2 EDX_INDEX /* %edx will hold the high 32 bits */
+uae_s8 always_used[]={4,-1};
-+
+#if defined(__x86_64__)
-+
+uae_s8 can_byte[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
-+
+uae_s8 can_word[]={0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,-1};
-+
+#else
+uae_s8 can_byte[]={0,1,2,3,-1};
+uae_s8 can_word[]={0,1,2,3,5,6,7,-1};
-+
+#endif
-+
+#if USE_OPTIMIZED_CALLS
-+
+/* Make sure interpretive core does not use cpuopti */
-+
+uae_u8 call_saved[]={0,0,0,1,1,1,1,1};
-+
+#error FIXME: code not ready
-+
+#else
+/* cpuopti mutate instruction handlers to assume registers are saved
+   by the caller */
-<
+uae_u8 call_saved[]={0,0,0,0,1,0,0,0};
->
+uae_u8 call_saved[]={0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0};
->
+#endif
+/* This *should* be the same as call_saved. But:
+   - We might not really know which registers are saved, and which aren't,
+   - Special registers (such like the stack pointer) should not be "preserved"
+     by pushing, even though they are "saved" across function calls
+*/
-<
+uae_u8 need_to_preserve[]={1,1,1,1,0,1,1,1};
->
+#if defined(__x86_64__)
->
+/* callee-saved registers as defined by Linux/x86_64 ABI: rbx, rbp, rsp, r12 - r15 */
->
+/* preserve r11 because it's generally used to hold pointers to functions */
->
+static const uae_u8 need_to_preserve[]={0,0,0,1,0,1,0,0,0,0,0,1,1,1,1,1};
->
+#else
->
+static const uae_u8 need_to_preserve[]={1,1,1,1,0,1,1,1};
->
+#endif
+/* Whether classes of instructions do or don't clobber the native flags */
+#define CLOBBER_MOV
+#define CLOBBER_TEST clobber_flags()
+#define CLOBBER_CL16
+#define CLOBBER_CL8
-+
+#define CLOBBER_SE32
+#define CLOBBER_SE16
+#define CLOBBER_SE8
-+
+#define CLOBBER_ZE32
+#define CLOBBER_ZE16
+#define CLOBBER_ZE8
+#define CLOBBER_SW16 clobber_flags()
+#define CLOBBER_BT   clobber_flags()
+#define CLOBBER_BSF  clobber_flags()
-+
+/* FIXME: disabled until that's proofread.  */
-+
+#if defined(__x86_64__)
-+
+#define USE_NEW_RTASM 1
-+
+#endif
-+
-+
+#if USE_NEW_RTASM
-+
-+
+#if defined(__x86_64__)
-+
+#define X86_TARGET_64BIT                1
-+
+#endif
-+
+#define X86_FLAT_REGISTERS              0
-+
+#define X86_OPTIMIZE_ALU                1
-+
+#define X86_OPTIMIZE_ROTSHI             1
-+
+#include "codegen_x86.h"
-+
-+
+#define x86_emit_byte(B)                emit_byte(B)
-+
+#define x86_emit_word(W)                emit_word(W)
-+
+#define x86_emit_long(L)                emit_long(L)
-+
+#define x86_emit_quad(Q)                emit_quad(Q)
-+
+#define x86_get_target()                get_target()
-+
+#define x86_emit_failure(MSG)   jit_fail(MSG, __FILE__, __LINE__, __FUNCTION__)
-+
-+
+static void jit_fail(const char *msg, const char *file, int line, const char *function)
-+
+{
-+
+        fprintf(stderr, "JIT failure in function %s from file %s at line %d: %s\n",
-+
+                        function, file, line, msg);
-+
+        abort();
-+
+}
-+
-+
+LOWFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
-+
+{
-+
+#if defined(__x86_64__)
-+
+        PUSHQr(r);
-+
+#else
-+
+        PUSHLr(r);
-+
+#endif
-+
+}
-+
+LENDFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r))
-+
-+
+LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
-+
+{
-+
+#if defined(__x86_64__)
-+
+        POPQr(r);
-+
+#else
-+
+        POPLr(r);
-+
+#endif
-+
+}
-+
+LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
-+
+{
-+
+        BTLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
-+
+{
-+
+        BTLrr(b, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
-+
+{
-+
+        BTCLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
-+
+{
-+
+        BTCLrr(b, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
-+
+{
-+
+        BTRLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
-+
+{
-+
+        BTRLrr(b, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
-+
+{
-+
+        BTSLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
-+
+{
-+
+        BTSLrr(b, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
-+
+{
-+
+        SUBWir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i))
-+
-+
+LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
-+
+{
-+
+        MOVLmr(s, X86_NOREG, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s))
-+
-+
+LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
-+
+{
-+
+        MOVLim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s))
-+
-+
+LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
-+
+{
-+
+        MOVWim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s))
-+
-+
+LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
-+
+{
-+
+        MOVBim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s))
-+
-+
+LOWFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
-+
+{
-+
+        ROLBim(i, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
-+
+{
-+
+        ROLBir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
-+
+{
-+
+        ROLWir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
-+
+{
-+
+        ROLLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
-+
+{
-+
+        ROLLrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
-+
+{
-+
+        ROLWrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
-+
+{
-+
+        ROLBrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
-+
+{
-+
+        SHLLrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
-+
+{
-+
+        SHLWrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
-+
+{
-+
+        SHLBrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
-+
+{
-+
+        RORBir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
-+
+{
-+
+        RORWir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i))
-+
-+
+LOWFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
-+
+{
-+
+        ORLmr(s, X86_NOREG, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
-+
+{
-+
+        RORLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
-+
+{
-+
+        RORLrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
-+
+{
-+
+        RORWrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
-+
+{
-+
+        RORBrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
-+
+{
-+
+        SHRLrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
-+
+{
-+
+        SHRWrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
-+
+{
-+
+        SHRBrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
-+
+{
-+
+        SARLrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
-+
+{
-+
+        SARWrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
-+
+{
-+
+        SARBrr(r, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
-+
+{
-+
+        SHLLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
-+
+{
-+
+        SHLWir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
-+
+{
-+
+        SHLBir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
-+
+{
-+
+        SHRLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
-+
+{
-+
+        SHRWir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
-+
+{
-+
+        SHRBir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
-+
+{
-+
+        SARLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
-+
+{
-+
+        SARWir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
-+
+{
-+
+        SARBir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
-+
+{
-+
+        SAHF();
-+
+}
-+
+LENDFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah))
-+
-+
+LOWFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
-+
+{
-+
+        CPUID();
-+
+}
-+
+LENDFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax))
-+
-+
+LOWFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
-+
+{
-+
+        LAHF();
-+
+}
-+
+LENDFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah))
-+
-+
+LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
-+
+{
-+
+        SETCCir(cc, d);
-+
+}
-+
+LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc))
-+
-+
+LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
-+
+{
-+
+        SETCCim(cc, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc))
-+
-+
+LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
-+
+{
-+
+        if (have_cmov)
-+
+                CMOVLrr(cc, s, d);
-+
+        else { /* replacement using branch and mov */
-+
+#if defined(__x86_64__)
-+
+                write_log("x86-64 implementations are bound to have CMOV!\n");
-+
+                abort();
-+
+#endif
-+
+                JCCSii(cc^1, 2);
-+
+                MOVLrr(s, d);
-+
+        }
-+
+}
-+
+LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
-+
+{
-+
+        BSFLrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s))
-+
+{
-+
+        MOVSLQrr(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_sign_extend_32_rr,(W4 d, R4 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
-+
+{
-+
+        MOVSWLrr(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
-+
+{
-+
+        MOVSBLrr(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
-+
+{
-+
+        MOVZWLrr(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
-+
+{
-+
+        MOVZBLrr(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
-+
+{
-+
+        IMULLrr(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
-+
+{
-+
+        if (d!=MUL_NREG1 || s!=MUL_NREG2) {
-+
+        write_log("Bad register in IMUL: d=%d, s=%d\n",d,s);
-+
+        abort();
-+
+        }
-+
+        IMULLr(s);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
-+
+{
-+
+        if (d!=MUL_NREG1 || s!=MUL_NREG2) {
-+
+        write_log("Bad register in MUL: d=%d, s=%d\n",d,s);
-+
+        abort();
-+
+        }
-+
+        MULLr(s);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
-+
+{
-+
+        abort(); /* %^$&%^$%#^ x86! */
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
-+
+{
-+
+        MOVBrr(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
-+
+{
-+
+        MOVWrr(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s))
-+
-+
+LOWFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
-+
+{
-+
+        MOVLmr(0, baser, index, factor, d);
-+
+}
-+
+LENDFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor))
-+
-+
+LOWFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
-+
+{
-+
+        MOVWmr(0, baser, index, factor, d);
-+
+}
-+
+LENDFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor))
-+
-+
+LOWFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
-+
+{
-+
+        MOVBmr(0, baser, index, factor, d);
-+
+}
-+
+LENDFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor))
-+
-+
+LOWFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
-+
+{
-+
+        MOVLrm(s, 0, baser, index, factor);
-+
+}
-+
+LENDFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s))
-+
-+
+LOWFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
-+
+{
-+
+        MOVWrm(s, 0, baser, index, factor);
-+
+}
-+
+LENDFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s))
-+
-+
+LOWFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
-+
+{
-+
+        MOVBrm(s, 0, baser, index, factor);
-+
+}
-+
+LENDFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s))
-+
-+
+LOWFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
-+
+{
-+
+        MOVLrm(s, base, baser, index, factor);
-+
+}
-+
+LENDFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s))
-+
-+
+LOWFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
-+
+{
-+
+        MOVWrm(s, base, baser, index, factor);
-+
+}
-+
+LENDFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s))
-+
-+
+LOWFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
-+
+{
-+
+        MOVBrm(s, base, baser, index, factor);
-+
+}
-+
+LENDFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s))
-+
-+
+LOWFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
-+
+{
-+
+        MOVLmr(base, baser, index, factor, d);
-+
+}
-+
+LENDFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor))
-+
-+
+LOWFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
-+
+{
-+
+        MOVWmr(base, baser, index, factor, d);
-+
+}
-+
+LENDFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor))
-+
-+
+LOWFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
-+
+{
-+
+        MOVBmr(base, baser, index, factor, d);
-+
+}
-+
+LENDFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor))
-+
-+
+LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
-+
+{
-+
+        MOVLmr(base, X86_NOREG, index, factor, d);
-+
+}
-+
+LENDFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor))
-+
-+
+LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
-+
+{
-+
+        if (have_cmov)
-+
+                CMOVLmr(cond, base, X86_NOREG, index, factor, d);
-+
+        else { /* replacement using branch and mov */
-+
+#if defined(__x86_64__)
-+
+                write_log("x86-64 implementations are bound to have CMOV!\n");
-+
+                abort();
-+
+#endif
-+
+                JCCSii(cond^1, 7);
-+
+                MOVLmr(base, X86_NOREG, index, factor, d);
-+
+        }
-+
+}
-+
+LENDFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond))
-+
-+
+LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
-+
+{
-+
+        if (have_cmov)
-+
+                CMOVLmr(cond, mem, X86_NOREG, X86_NOREG, 1, d);
-+
+        else { /* replacement using branch and mov */
-+
+#if defined(__x86_64__)
-+
+                write_log("x86-64 implementations are bound to have CMOV!\n");
-+
+                abort();
-+
+#endif
-+
+                JCCSii(cond^1, 6);
-+
+                MOVLmr(mem, X86_NOREG, X86_NOREG, 1, d);
-+
+        }
-+
+}
-+
+LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond))
-+
-+
+LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
-+
+{
-+
+        MOVLmr(offset, s, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
-+
-+
+LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
-+
+{
-+
+        MOVWmr(offset, s, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
-+
-+
+LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
-+
+{
-+
+        MOVBmr(offset, s, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
-+
-+
+LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
-+
+{
-+
+        MOVLmr(offset, s, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset))
-+
-+
+LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
-+
+{
-+
+        MOVWmr(offset, s, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset))
-+
-+
+LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
-+
+{
-+
+        MOVBmr(offset, s, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset))
-+
-+
+LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
-+
+{
-+
+        MOVLim(i, offset, d, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
-+
-+
+LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
-+
+{
-+
+        MOVWim(i, offset, d, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
-+
-+
+LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
-+
+{
-+
+        MOVBim(i, offset, d, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
-+
-+
+LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
-+
+{
-+
+        MOVLrm(s, offset, d, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
-+
-+
+LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
-+
+{
-+
+        MOVWrm(s, offset, d, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
-+
-+
+LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
-+
+{
-+
+        MOVBrm(s, offset, d, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
-+
-+
+LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
-+
+{
-+
+        LEALmr(offset, s, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset))
-+
-+
+LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
-+
+{
-+
+        LEALmr(offset, s, index, factor, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset))
-+
-+
+LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
-+
+{
-+
+        LEALmr(0, s, index, factor, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor))
-+
-+
+LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
-+
+{
-+
+        MOVLrm(s, offset, d, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset))
-+
-+
+LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
-+
+{
-+
+        MOVWrm(s, offset, d, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset))
-+
-+
+LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
-+
+{
-+
+        MOVBrm(s, offset, d, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset))
-+
-+
+LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
-+
+{
-+
+        BSWAPLr(r);
-+
+}
-+
+LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r))
-+
-+
+LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
-+
+{
-+
+        ROLWir(8, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
-+
+{
-+
+        MOVLrr(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s))
-+
-+
+LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
-+
+{
-+
+        MOVLrm(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s))
-+
-+
+LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
-+
+{
-+
+        MOVWrm(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s))
-+
-+
+LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
-+
+{
-+
+        MOVWmr(s, X86_NOREG, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s))
-+
-+
+LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
-+
+{
-+
+        MOVBrm(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s))
-+
-+
+LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
-+
+{
-+
+        MOVBmr(s, X86_NOREG, X86_NOREG, 1, d);
-+
+}
-+
+LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
-+
+{
-+
+        MOVLir(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
-+
+{
-+
+        MOVWir(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
-+
+{
-+
+        MOVBir(s, d);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s))
-+
-+
+LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
-+
+{
-+
+        ADCLim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s))
-+
-+
+LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s))
-+
+{
-+
+        ADDLim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s))
-+
-+
+LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s))
-+
+{
-+
+        ADDWim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s))
-+
-+
+LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s))
-+
+{
-+
+        ADDBim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
-+
+{
-+
+        TESTLir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
-+
+{
-+
+        TESTLrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
-+
+{
-+
+        TESTWrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
-+
+{
-+
+        TESTBrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
-+
+{
-+
+        ANDLir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
-+
+{
-+
+        ANDWir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
-+
+{
-+
+        ANDLrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
-+
+{
-+
+        ANDWrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
-+
+{
-+
+        ANDBrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
-+
+{
-+
+        ORLir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
-+
+{
-+
+        ORLrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
-+
+{
-+
+        ORWrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
-+
+{
-+
+        ORBrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s))
-+
-+
+LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
-+
+{
-+
+        ADCLrr(s, d);
-+
+}
-+
+LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s))
-+
-+
+LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
-+
+{
-+
+        ADCWrr(s, d);
-+
+}
-+
+LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s))
-+
-+
+LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
-+
+{
-+
+        ADCBrr(s, d);
-+
+}
-+
+LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
-+
+{
-+
+        ADDLrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
-+
+{
-+
+        ADDWrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
-+
+{
-+
+        ADDBrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
-+
+{
-+
+        SUBLir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
-+
+{
-+
+        SUBBir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
-+
+{
-+
+        ADDLir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
-+
+{
-+
+        ADDWir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
-+
+{
-+
+        ADDBir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i))
-+
-+
+LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
-+
+{
-+
+        SBBLrr(s, d);
-+
+}
-+
+LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s))
-+
-+
+LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
-+
+{
-+
+        SBBWrr(s, d);
-+
+}
-+
+LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s))
-+
-+
+LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
-+
+{
-+
+        SBBBrr(s, d);
-+
+}
-+
+LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
-+
+{
-+
+        SUBLrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
-+
+{
-+
+        SUBWrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
-+
+{
-+
+        SUBBrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
-+
+{
-+
+        CMPLrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
-+
+{
-+
+        CMPLir(i, r);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
-+
+{
-+
+        CMPWrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s))
-+
-+
+LOWFUNC(WRITE,READ,2,raw_cmp_b_mi,(MEMR d, IMM s))
-+
+{
-+
+        CMPBim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
-+
+{
-+
+        CMPBir(i, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
-+
+{
-+
+        CMPBrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s))
-+
-+
+LOWFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
-+
+{
-+
+        CMPLmr(offset, X86_NOREG, index, factor, d);
-+
+}
-+
+LENDFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
-+
+{
-+
+        XORLrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
-+
+{
-+
+        XORWrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s))
-+
-+
+LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
-+
+{
-+
+        XORBrr(s, d);
-+
+}
-+
+LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s))
-+
-+
+LOWFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
-+
+{
-+
+        SUBLim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s))
-+
-+
+LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
-+
+{
-+
+        CMPLim(s, d, X86_NOREG, X86_NOREG, 1);
-+
+}
-+
+LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s))
-+
-+
+LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
-+
+{
-+
+        XCHGLrr(r2, r1);
-+
+}
-+
+LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
-+
-+
+LOWFUNC(READ,WRITE,0,raw_pushfl,(void))
-+
+{
-+
+        PUSHF();
-+
+}
-+
+LENDFUNC(READ,WRITE,0,raw_pushfl,(void))
-+
-+
+LOWFUNC(WRITE,READ,0,raw_popfl,(void))
-+
+{
-+
+        POPF();
-+
+}
-+
+LENDFUNC(WRITE,READ,0,raw_popfl,(void))
-+
-+
+#else
-+
+const bool optimize_accum               = true;
+const bool optimize_imm8                = true;
+const bool optimize_shift_once  = true;
+LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset))
-+
+        Dif(!isbyte(offset)) abort();
+    emit_byte(0x8b);
+    emit_byte(0x40+8*d+s);
+    emit_byte(offset);
+LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset))
-+
+        Dif(!isbyte(offset)) abort();
+    emit_byte(0x66);
+    emit_byte(0x8b);
+    emit_byte(0x40+8*d+s);
+LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset))
-+
+        Dif(!isbyte(offset)) abort();
+    emit_byte(0x8a);
+    emit_byte(0x40+8*d+s);
+    emit_byte(offset);
+LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset))
-+
+        Dif(!isbyte(offset)) abort();
+    emit_byte(0xc7);
+    emit_byte(0x40+d);
+    emit_byte(offset);
+LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset))
-+
+        Dif(!isbyte(offset)) abort();
+    emit_byte(0x66);
+    emit_byte(0xc7);
+    emit_byte(0x40+d);
+LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset))
-+
+        Dif(!isbyte(offset)) abort();
+    emit_byte(0xc6);
+    emit_byte(0x40+d);
+    emit_byte(offset);
+LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset))
-+
+        Dif(!isbyte(offset)) abort();
+    emit_byte(0x89);
+    emit_byte(0x40+8*s+d);
+    emit_byte(offset);
+LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset))
-+
+        Dif(!isbyte(offset)) abort();
+    emit_byte(0x66);
+    emit_byte(0x89);
+    emit_byte(0x40+8*s+d);
+LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset))
-+
+        Dif(!isbyte(offset)) abort();
+    emit_byte(0x88);
+    emit_byte(0x40+8*s+d);
+    emit_byte(offset);
+LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2))
+/*************************************************************************
-–
+ * FIXME: string-related instructions                                    *
-–
+ *************************************************************************/
-–
-–
+LOWFUNC(WRITE,NONE,0,raw_cld,(void))
-–
+{
-–
+        emit_byte(0xfc);
-–
+}
-–
+LENDFUNC(WRITE,NONE,0,raw_cld,(void))
-–
-–
+LOWFUNC(WRITE,NONE,0,raw_std,(void))
-–
+{
-–
+        emit_byte(0xfd);
-–
+}
-–
+LENDFUNC(WRITE,NONE,0,raw_std,(void))
-–
-–
+LOWFUNC(NONE,RMW,0,raw_movs_b,(void))
-–
+{
-–
+        emit_byte(0xa4);
-–
+}
-–
+LENDFUNC(NONE,RMW,0,raw_movs_b,(void))
-–
-–
+LOWFUNC(NONE,RMW,0,raw_movs_l,(void))
-–
+{
-–
+        emit_byte(0xa5);
-–
+}
-–
+LENDFUNC(NONE,RMW,0,raw_movs_l,(void))
-–
-–
+LOWFUNC(NONE,RMW,0,raw_rep,(void))
-–
+{
-–
+        emit_byte(0xf3);
-–
+}
-–
+LENDFUNC(NONE,RMW,0,raw_rep,(void))
-–
-–
+LOWFUNC(NONE,RMW,0,raw_rep_movsb,(void))
-–
+{
-–
+        raw_rep();
-–
+        raw_movs_b();
-–
+}
-–
+LENDFUNC(NONE,RMW,0,raw_rep_movsb,(void))
-–
-–
+LOWFUNC(NONE,RMW,0,raw_rep_movsl,(void))
-–
+{
-–
+        raw_rep();
-–
+        raw_movs_l();
-–
+}
-–
+LENDFUNC(NONE,RMW,0,raw_rep_movsl,(void))
-–
-–
+/*************************************************************************
+ * FIXME: mem access modes probably wrong                                *
+ *************************************************************************/
+LENDFUNC(WRITE,READ,0,raw_popfl,(void))
-+
+#endif
-+
+/*************************************************************************
+ * Unoptimizable stuff --- jump                                          *
+ *************************************************************************/
+static __inline__ void raw_call_r(R4 r)
-+
+#if USE_NEW_RTASM
-+
+    CALLsr(r);
-+
+#else
+    emit_byte(0xff);
+    emit_byte(0xd0+r);
-+
+#endif
+static __inline__ void raw_call_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
-+
+#if USE_NEW_RTASM
-+
+    CALLsm(base, X86_NOREG, r, m);
-+
+#else
+    int mu;
+    switch(m) {
+     case 1: mu=0; break;
+    emit_byte(0x14);
+    emit_byte(0x05+8*r+0x40*mu);
+    emit_long(base);
-+
+#endif
+static __inline__ void raw_jmp_r(R4 r)
-+
+#if USE_NEW_RTASM
-+
+    JMPsr(r);
-+
+#else
+    emit_byte(0xff);
+    emit_byte(0xe0+r);
-+
+#endif
+static __inline__ void raw_jmp_m_indexed(uae_u32 base, uae_u32 r, uae_u32 m)
-+
+#if USE_NEW_RTASM
-+
+    JMPsm(base, X86_NOREG, r, m);
-+
+#else
+    int mu;
+    switch(m) {
+     case 1: mu=0; break;
+    emit_byte(0x24);
+    emit_byte(0x05+8*r+0x40*mu);
+    emit_long(base);
-+
+#endif
+static __inline__ void raw_jmp_m(uae_u32 base)
+static __inline__ void raw_call(uae_u32 t)
-+
+#if USE_NEW_RTASM
-+
+    CALLm(t);
-+
+#else
+    emit_byte(0xe8);
+    emit_long(t-(uae_u32)target-4);
-+
+#endif
+static __inline__ void raw_jmp(uae_u32 t)
-+
+#if USE_NEW_RTASM
-+
+    JMPm(t);
-+
+#else
+    emit_byte(0xe9);
+    emit_long(t-(uae_u32)target-4);
-+
+#endif
+static __inline__ void raw_jl(uae_u32 t)
+    emit_byte(0x0f);
+    emit_byte(0x8c);
-<
+    emit_long(t-(uae_u32)target-4);
->
+    emit_long(t-(uintptr)target-4);
+static __inline__ void raw_jz(uae_u32 t)
+    emit_byte(0x0f);
+    emit_byte(0x84);
-<
+    emit_long(t-(uae_u32)target-4);
->
+    emit_long(t-(uintptr)target-4);
+static __inline__ void raw_jnz(uae_u32 t)
+    emit_byte(0x0f);
+    emit_byte(0x85);
-<
+    emit_long(t-(uae_u32)target-4);
->
+    emit_long(t-(uintptr)target-4);
+static __inline__ void raw_jnz_l_oponly(void)
+    emit_byte(0x90);
-+
+static __inline__ void raw_emit_nop_filler(int nbytes)
-+
+{
-+
+  /* Source: GNU Binutils 2.12.90.0.15 */
-+
+  /* Various efficient no-op patterns for aligning code labels.
-+
+     Note: Don't try to assemble the instructions in the comments.
-+
+L and 0w are not legal.  */
-+
+  static const uae_u8 f32_1[] =
-+
+    {0x90};                                                                     /* nop                                  */
-+
+  static const uae_u8 f32_2[] =
-+
+    {0x89,0xf6};                                                        /* movl %esi,%esi               */
-+
+  static const uae_u8 f32_3[] =
-+
+    {0x8d,0x76,0x00};                                           /* leal 0(%esi),%esi    */
-+
+  static const uae_u8 f32_4[] =
-+
+    {0x8d,0x74,0x26,0x00};                                      /* leal 0(%esi,1),%esi  */
-+
+  static const uae_u8 f32_5[] =
-+
+    {0x90,                                                                      /* nop                                  */
-+
+x8d,0x74,0x26,0x00};                                      /* leal 0(%esi,1),%esi  */
-+
+  static const uae_u8 f32_6[] =
-+
+    {0x8d,0xb6,0x00,0x00,0x00,0x00};            /* leal 0L(%esi),%esi   */
-+
+  static const uae_u8 f32_7[] =
-+
+    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
-+
+  static const uae_u8 f32_8[] =
-+
+    {0x90,                                                                      /* nop                                  */
-+
+x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
-+
+  static const uae_u8 f32_9[] =
-+
+    {0x89,0xf6,                                                         /* movl %esi,%esi               */
-+
+x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
-+
+  static const uae_u8 f32_10[] =
-+
+    {0x8d,0x76,0x00,                                            /* leal 0(%esi),%esi    */
-+
+x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
-+
+  static const uae_u8 f32_11[] =
-+
+    {0x8d,0x74,0x26,0x00,                                       /* leal 0(%esi,1),%esi  */
-+
+x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
-+
+  static const uae_u8 f32_12[] =
-+
+    {0x8d,0xb6,0x00,0x00,0x00,0x00,                     /* leal 0L(%esi),%esi   */
-+
+x8d,0xbf,0x00,0x00,0x00,0x00};            /* leal 0L(%edi),%edi   */
-+
+  static const uae_u8 f32_13[] =
-+
+    {0x8d,0xb6,0x00,0x00,0x00,0x00,                     /* leal 0L(%esi),%esi   */
-+
+x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
-+
+  static const uae_u8 f32_14[] =
-+
+    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00,        /* leal 0L(%esi,1),%esi */
-+
+x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
-+
+  static const uae_u8 f32_15[] =
-+
+    {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90,        /* jmp .+15; lotsa nops */
-+
+x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
-+
+  static const uae_u8 f32_16[] =
-+
+    {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90,        /* jmp .+15; lotsa nops */
-+
+x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
-+
+  static const uae_u8 *const f32_patt[] = {
-+
+    f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
-+
+    f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
-+
+  };
-+
+  static const uae_u8 prefixes[4] = { 0x66, 0x66, 0x66, 0x66 };
-+
-+
+#if defined(__x86_64__)
-+
+  /* The recommended way to pad 64bit code is to use NOPs preceded by
-+
+     maximally four 0x66 prefixes.  Balance the size of nops.  */
-+
+  if (nbytes == 0)
-+
+          return;
-+
-+
+  int i;
-+
+  int nnops = (nbytes + 3) / 4;
-+
+  int len = nbytes / nnops;
-+
+  int remains = nbytes - nnops * len;
-+
-+
+  for (i = 0; i < remains; i++) {
-+
+          emit_block(prefixes, len);
-+
+          raw_nop();
-+
+  }
-+
+  for (; i < nnops; i++) {
-+
+          emit_block(prefixes, len - 1);
-+
+          raw_nop();
-+
+  }
-+
+#else
-+
+  int nloops = nbytes / 16;
-+
+  while (nloops-- > 0)
-+
+        emit_block(f32_16, sizeof(f32_16));
-+
-+
+  nbytes %= 16;
-+
+  if (nbytes)
-+
+        emit_block(f32_patt[nbytes - 1], nbytes);
-+
+#endif
-+
+}
-+
+/*************************************************************************
+ * Flag handling, to and fro UAE flag register                           *
+  raw_lahf(0);  /* Most flags in AH */
+  //raw_setcc(r,0); /* V flag in AL */
-<
+  raw_setcc_m((uae_u32)live.state[FLAGTMP].mem,0);
->
+  raw_setcc_m((uintptr)live.state[FLAGTMP].mem,0);
+#if 1   /* Let's avoid those nasty partial register stalls */
-<
+  //raw_mov_b_mr((uae_u32)live.state[FLAGTMP].mem,r);
-<
+  raw_mov_b_mr(((uae_u32)live.state[FLAGTMP].mem)+1,r+4);
->
+  //raw_mov_b_mr((uintptr)live.state[FLAGTMP].mem,r);
->
+  raw_mov_b_mr(((uintptr)live.state[FLAGTMP].mem)+1,r+4);
+  //live.state[FLAGTMP].status=CLEAN;
+  live.state[FLAGTMP].status=INMEM;
+  live.state[FLAGTMP].realreg=-1;
+        raw_pushfl();
+        raw_pop_l_r(r);
-<
+        raw_mov_l_mr((uae_u32)live.state[FLAGTMP].mem,r);
->
+        raw_mov_l_mr((uintptr)live.state[FLAGTMP].mem,r);
+//      live.state[FLAGTMP].status=CLEAN;
+        live.state[FLAGTMP].status=INMEM;
+        live.state[FLAGTMP].realreg=-1;
+static __inline__ void raw_load_flagreg(uae_u32 target, uae_u32 r)
+#if 1
-<
+    raw_mov_l_rm(target,(uae_u32)live.state[r].mem);
->
+    raw_mov_l_rm(target,(uintptr)live.state[r].mem);
+#else
-<
+    raw_mov_b_rm(target,(uae_u32)live.state[r].mem);
-<
+    raw_mov_b_rm(target+4,((uae_u32)live.state[r].mem)+1);
->
+    raw_mov_b_rm(target,(uintptr)live.state[r].mem);
->
+    raw_mov_b_rm(target+4,((uintptr)live.state[r].mem)+1);
+#endif
+static __inline__ void raw_load_flagx(uae_u32 target, uae_u32 r)
+    if (live.nat[target].canbyte)
-<
+        raw_mov_b_rm(target,(uae_u32)live.state[r].mem);
->
+        raw_mov_b_rm(target,(uintptr)live.state[r].mem);
+    else if (live.nat[target].canword)
-<
+        raw_mov_w_rm(target,(uae_u32)live.state[r].mem);
->
+        raw_mov_w_rm(target,(uintptr)live.state[r].mem);
+    else
-<
+        raw_mov_l_rm(target,(uae_u32)live.state[r].mem);
->
+        raw_mov_l_rm(target,(uintptr)live.state[r].mem);
-+
+#define NATIVE_FLAG_Z 0x40
-+
+static __inline__ void raw_flags_set_zero(int f, int r, int t)
-+
+{
-+
+        // FIXME: this is really suboptimal
-+
+        raw_pushfl();
-+
+        raw_pop_l_r(f);
-+
+        raw_and_l_ri(f,~NATIVE_FLAG_Z);
-+
+        raw_test_l_rr(r,r);
-+
+        raw_mov_l_ri(r,0);
-+
+        raw_mov_l_ri(t,NATIVE_FLAG_Z);
-+
+        raw_cmov_l_rr(r,t,NATIVE_CC_EQ);
-+
+        raw_or_l(f,r);
-+
+        raw_push_l_r(f);
-+
+        raw_popfl();
-+
+}
+static __inline__ void raw_inc_sp(int off)
+                for (i=0;i<5;i++)
+                    vecbuf[i]=target[i];
+                emit_byte(0xe9);
-<
+                emit_long((uae_u32)veccode-(uae_u32)target-4);
->
+                emit_long((uintptr)veccode-(uintptr)target-4);
+                write_log("Create jump to %p\n",veccode);
+                write_log("Handled one access!\n");
+                for (i=0;i<5;i++)
+                    raw_mov_b_mi(sc.eip+i,vecbuf[i]);
-<
+                raw_mov_l_mi((uae_u32)&in_handler,0);
->
+                raw_mov_l_mi((uintptr)&in_handler,0);
+                emit_byte(0xe9);
-<
+                emit_long(sc.eip+len-(uae_u32)target-4);
->
+                emit_long(sc.eip+len-(uintptr)target-4);
+                in_handler=1;
+                target=tmp;
+  X86_PROCESSOR_K6,
+  X86_PROCESSOR_ATHLON,
+  X86_PROCESSOR_PENTIUM4,
-+
+  X86_PROCESSOR_K8,
+  X86_PROCESSOR_max
+};
+  "PentiumPro",
+  "K6",
+  "Athlon",
-<
+  "Pentium4"
->
+  "Pentium4",
->
+  "K8"
+};
+static struct ptt {
+  { 16, 15, 16,  7, 16 },
+  { 32,  7, 32,  7, 32 },
+  { 16,  7, 16,  7, 16 },
-<
+  {  0,  0,  0,  0,  0 }
->
+  {  0,  0,  0,  0,  0 },
->
+  { 16,  7, 16,  7, 16 }
+};
+static void
+cpuid(uae_u32 op, uae_u32 *eax, uae_u32 *ebx, uae_u32 *ecx, uae_u32 *edx)
+  static uae_u8 cpuid_space[256];
-+
+  static uae_u32 s_op, s_eax, s_ebx, s_ecx, s_edx;
+  uae_u8* tmp=get_target();
-+
+  s_op = op;
+  set_target(cpuid_space);
+  raw_push_l_r(0); /* eax */
+  raw_push_l_r(1); /* ecx */
+  raw_push_l_r(2); /* edx */
+  raw_push_l_r(3); /* ebx */
-<
+  raw_mov_l_rm(0,(uae_u32)&op);
->
+  raw_mov_l_rm(0,(uintptr)&s_op);
+  raw_cpuid(0);
-<
+  if (eax != NULL) raw_mov_l_mr((uae_u32)eax,0);
-<
+  if (ebx != NULL) raw_mov_l_mr((uae_u32)ebx,3);
-<
+  if (ecx != NULL) raw_mov_l_mr((uae_u32)ecx,1);
-<
+  if (edx != NULL) raw_mov_l_mr((uae_u32)edx,2);
->
+  raw_mov_l_mr((uintptr)&s_eax,0);
->
+  raw_mov_l_mr((uintptr)&s_ebx,3);
->
+  raw_mov_l_mr((uintptr)&s_ecx,1);
->
+  raw_mov_l_mr((uintptr)&s_edx,2);
+  raw_pop_l_r(3);
+  raw_pop_l_r(2);
+  raw_pop_l_r(1);
+  set_target(tmp);
+  ((cpuop_func*)cpuid_space)(0);
-+
+  if (eax != NULL) *eax = s_eax;
-+
+  if (ebx != NULL) *ebx = s_ebx;
-+
+  if (ecx != NULL) *ecx = s_ecx;
-+
+  if (edx != NULL) *edx = s_edx;
+static void
+  struct cpuinfo_x86 *c = &cpuinfo;
+  /* Defaults */
-+
+  c->x86_processor = X86_PROCESSOR_max;
+  c->x86_vendor = X86_VENDOR_UNKNOWN;
+  c->cpuid_level = -1;                          /* CPUID not detected */
+  c->x86_model = c->x86_mask = 0;       /* So far unknown... */
+        c->x86 = 4;
-+
+  /* AMD-defined flags: level 0x80000001 */
-+
+  uae_u32 xlvl;
-+
+  cpuid(0x80000000, &xlvl, NULL, NULL, NULL);
-+
+  if ( (xlvl & 0xffff0000) == 0x80000000 ) {
-+
+        if ( xlvl >= 0x80000001 ) {
-+
+          uae_u32 features;
-+
+          cpuid(0x80000001, NULL, NULL, NULL, &features);
-+
+          if (features & (1 << 29)) {
-+
+                /* Assume x86-64 if long mode is supported */
-+
+                c->x86_processor = X86_PROCESSOR_K8;
-+
+          }
-+
+        }
-+
+  }
-+
+  /* Canonicalize processor ID */
-–
+  c->x86_processor = X86_PROCESSOR_max;
+  switch (c->x86) {
+  case 3:
+        c->x86_processor = X86_PROCESSOR_I386;
+        break;
+  case 15:
+        if (c->x86_vendor == X86_VENDOR_INTEL) {
-<
+          /*  Assume any BranID >= 8 and family == 15 yields a Pentium 4 */
->
+          /* Assume any BrandID >= 8 and family == 15 yields a Pentium 4 */
+          if (c->x86_brand_id >= 8)
+                c->x86_processor = X86_PROCESSOR_PENTIUM4;
-+
+        if (c->x86_vendor == X86_VENDOR_AMD) {
-+
+          /* Assume an Athlon processor if family == 15 and it was not
-+
+             detected as an x86-64 so far */
-+
+          if (c->x86_processor == X86_PROCESSOR_max)
-+
+                c->x86_processor = X86_PROCESSOR_ATHLON;
-+
+        }
+        break;
+  if (c->x86_processor == X86_PROCESSOR_max) {
+        fprintf(stderr, "  Family  : %d\n", c->x86);
+        fprintf(stderr, "  Model   : %d\n", c->x86_model);
+        fprintf(stderr, "  Mask    : %d\n", c->x86_mask);
-+
+        fprintf(stderr, "  Vendor  : %s [%d]\n", c->x86_vendor_id, c->x86_vendor);
+        if (c->x86_brand_id)
+          fprintf(stderr, "  BrandID : %02x\n", c->x86_brand_id);
+        abort();
+  /* Have CMOV support? */
-<
+  have_cmov = (c->x86_hwcap & (1 << 15)) && true;
->
+  have_cmov = c->x86_hwcap & (1 << 15);
+  /* Can the host CPU suffer from partial register stalls? */
+  have_rat_stall = (c->x86_vendor == X86_VENDOR_INTEL);
+                        x86_processor_string_table[c->x86_processor]);
-+
+static bool target_check_bsf(void)
-+
+{
-+
+        bool mismatch = false;
-+
+        for (int g_ZF = 0; g_ZF <= 1; g_ZF++) {
-+
+        for (int g_CF = 0; g_CF <= 1; g_CF++) {
-+
+        for (int g_OF = 0; g_OF <= 1; g_OF++) {
-+
+        for (int g_SF = 0; g_SF <= 1; g_SF++) {
-+
+                for (int value = -1; value <= 1; value++) {
-+
+                        int flags = (g_SF << 7) | (g_OF << 11) | (g_ZF << 6) | g_CF;
-+
+                        int tmp = value;
-+
+                        __asm__ __volatile__ ("push %0; popf; bsf %1,%1; pushf; pop %0"
-+
+                                                                  : "+r" (flags), "+r" (tmp) : : "cc");
-+
+                        int OF = (flags >> 11) & 1;
-+
+                        int SF = (flags >>  7) & 1;
-+
+                        int ZF = (flags >>  6) & 1;
-+
+                        int CF = flags & 1;
-+
+                        tmp = (value == 0);
-+
+                        if (ZF != tmp || SF != g_SF || OF != g_OF || CF != g_CF)
-+
+                                mismatch = true;
-+
+                }
-+
+        }}}}
-+
+        if (mismatch)
-+
+                write_log("Target CPU defines all flags on BSF instruction\n");
-+
+        return !mismatch;
-+
+}
-+
+/*************************************************************************
+ * FPU stuff                                                             *
+    emit_byte(0xf0);  /* f2xm1 */
+    emit_byte(0xdc);
+    emit_byte(0x05);
-<
+    emit_long((uae_u32)&one);  /* Add '1' without using extra stack space */
->
+    emit_long((uintptr)&one);  /* Add '1' without using extra stack space */
+    emit_byte(0xd9);
+    emit_byte(0xfd);  /* and scale it */
+    emit_byte(0xdd);
+    emit_byte(0xf0);  /* f2xm1 */
+    emit_byte(0xdc);
+    emit_byte(0x05);
-<
+    emit_long((uae_u32)&one);  /* Add '1' without using extra stack space */
->
+    emit_long((uintptr)&one);  /* Add '1' without using extra stack space */
+    emit_byte(0xd9);
+    emit_byte(0xfd);  /* and scale it */
+    emit_byte(0xdd);

Diff Legend

-–
+Removed lines
-+
+Added lines
-<
+Changed lines
->
+Changed lines

Comparing BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp (file contents): Revision 1.6 by gbeauche, 2002-10-03T16:13:46Z vs. Revision 1.22 by gbeauche, 2004-11-01T18:40:30Z

Diff Legend

Comparing BasiliskII/src/uae_cpu/compiler/codegen_x86.cpp (file contents):
Revision 1.6 by gbeauche, 2002-10-03T16:13:46Z vs.
Revision 1.22 by gbeauche, 2004-11-01T18:40:30Z