7 |
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* Gwenole Beauchesne |
8 |
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* |
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* Basilisk II (C) 1997-2002 Christian Bauer |
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* |
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+ |
* Portions related to CPU detection come from linux/arch/i386/kernel/setup.c |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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#define CLOBBER_BT clobber_flags() |
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#define CLOBBER_BSF clobber_flags() |
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|
127 |
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/* FIXME: disabled until that's proofread. */ |
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#if 0 |
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|
130 |
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#if defined(__x86_64__) |
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#define X86_TARGET_64BIT 1 |
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#endif |
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#define X86_FLAT_REGISTERS 0 |
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#define X86_OPTIMIZE_ALU 1 |
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+ |
#define X86_OPTIMIZE_ROTSHI 1 |
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+ |
#include "codegen_x86.h" |
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|
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#define x86_emit_byte(B) emit_byte(B) |
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#define x86_emit_word(W) emit_word(W) |
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#define x86_emit_long(L) emit_long(L) |
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#define x86_get_target() get_target() |
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#define x86_emit_failure(MSG) jit_fail(MSG, __FILE__, __LINE__, __FUNCTION__) |
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|
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static void jit_fail(const char *msg, const char *file, int line, const char *function) |
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{ |
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fprintf(stderr, "JIT failure in function %s from file %s at line %d: %s\n", |
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function, file, line, msg); |
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abort(); |
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} |
150 |
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|
151 |
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LOWFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r)) |
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{ |
153 |
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PUSHLr(r); |
154 |
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} |
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LENDFUNC(NONE,WRITE,1,raw_push_l_r,(R4 r)) |
156 |
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|
157 |
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LOWFUNC(NONE,READ,1,raw_pop_l_r,(R4 r)) |
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{ |
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POPLr(r); |
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} |
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LENDFUNC(NONE,READ,1,raw_pop_l_r,(R4 r)) |
162 |
+ |
|
163 |
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LOWFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i)) |
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{ |
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BTLir(i, r); |
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} |
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LENDFUNC(WRITE,NONE,2,raw_bt_l_ri,(R4 r, IMM i)) |
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|
169 |
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LOWFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b)) |
170 |
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{ |
171 |
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BTLrr(b, r); |
172 |
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} |
173 |
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LENDFUNC(WRITE,NONE,2,raw_bt_l_rr,(R4 r, R4 b)) |
174 |
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|
175 |
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LOWFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i)) |
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{ |
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BTCLir(i, r); |
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} |
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LENDFUNC(WRITE,NONE,2,raw_btc_l_ri,(RW4 r, IMM i)) |
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|
181 |
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LOWFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b)) |
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{ |
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BTCLrr(b, r); |
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} |
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LENDFUNC(WRITE,NONE,2,raw_btc_l_rr,(RW4 r, R4 b)) |
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|
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LOWFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i)) |
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{ |
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BTRLir(i, r); |
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} |
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LENDFUNC(WRITE,NONE,2,raw_btr_l_ri,(RW4 r, IMM i)) |
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|
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LOWFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b)) |
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{ |
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BTRLrr(b, r); |
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} |
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LENDFUNC(WRITE,NONE,2,raw_btr_l_rr,(RW4 r, R4 b)) |
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|
199 |
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LOWFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i)) |
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{ |
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BTSLir(i, r); |
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} |
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LENDFUNC(WRITE,NONE,2,raw_bts_l_ri,(RW4 r, IMM i)) |
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|
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LOWFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b)) |
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{ |
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BTSLrr(b, r); |
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} |
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LENDFUNC(WRITE,NONE,2,raw_bts_l_rr,(RW4 r, R4 b)) |
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|
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LOWFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i)) |
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{ |
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SUBWir(i, d); |
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} |
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LENDFUNC(WRITE,NONE,2,raw_sub_w_ri,(RW2 d, IMM i)) |
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|
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LOWFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s)) |
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{ |
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MOVLmr(s, X86_NOREG, X86_NOREG, 1, d); |
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} |
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LENDFUNC(NONE,READ,2,raw_mov_l_rm,(W4 d, MEMR s)) |
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|
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LOWFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s)) |
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{ |
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MOVLim(s, d, X86_NOREG, X86_NOREG, 1); |
226 |
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} |
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LENDFUNC(NONE,WRITE,2,raw_mov_l_mi,(MEMW d, IMM s)) |
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|
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LOWFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s)) |
230 |
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{ |
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MOVWim(s, d, X86_NOREG, X86_NOREG, 1); |
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} |
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LENDFUNC(NONE,WRITE,2,raw_mov_w_mi,(MEMW d, IMM s)) |
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|
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LOWFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s)) |
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{ |
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MOVBim(s, d, X86_NOREG, X86_NOREG, 1); |
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} |
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LENDFUNC(NONE,WRITE,2,raw_mov_b_mi,(MEMW d, IMM s)) |
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|
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LOWFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i)) |
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{ |
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ROLBim(i, d, X86_NOREG, X86_NOREG, 1); |
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} |
245 |
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LENDFUNC(WRITE,RMW,2,raw_rol_b_mi,(MEMRW d, IMM i)) |
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|
247 |
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LOWFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i)) |
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{ |
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ROLBir(i, r); |
250 |
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} |
251 |
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LENDFUNC(WRITE,NONE,2,raw_rol_b_ri,(RW1 r, IMM i)) |
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|
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LOWFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i)) |
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{ |
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ROLWir(i, r); |
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} |
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LENDFUNC(WRITE,NONE,2,raw_rol_w_ri,(RW2 r, IMM i)) |
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|
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LOWFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i)) |
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{ |
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ROLLir(i, r); |
262 |
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} |
263 |
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LENDFUNC(WRITE,NONE,2,raw_rol_l_ri,(RW4 r, IMM i)) |
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|
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LOWFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r)) |
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{ |
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ROLLrr(r, d); |
268 |
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} |
269 |
+ |
LENDFUNC(WRITE,NONE,2,raw_rol_l_rr,(RW4 d, R1 r)) |
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|
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LOWFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r)) |
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{ |
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ROLWrr(r, d); |
274 |
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} |
275 |
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LENDFUNC(WRITE,NONE,2,raw_rol_w_rr,(RW2 d, R1 r)) |
276 |
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|
277 |
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LOWFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r)) |
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{ |
279 |
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ROLBrr(r, d); |
280 |
+ |
} |
281 |
+ |
LENDFUNC(WRITE,NONE,2,raw_rol_b_rr,(RW1 d, R1 r)) |
282 |
+ |
|
283 |
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LOWFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r)) |
284 |
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{ |
285 |
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SHLLrr(r, d); |
286 |
+ |
} |
287 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shll_l_rr,(RW4 d, R1 r)) |
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|
289 |
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LOWFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r)) |
290 |
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{ |
291 |
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SHLWrr(r, d); |
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} |
293 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shll_w_rr,(RW2 d, R1 r)) |
294 |
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|
295 |
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LOWFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r)) |
296 |
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{ |
297 |
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SHLBrr(r, d); |
298 |
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} |
299 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shll_b_rr,(RW1 d, R1 r)) |
300 |
+ |
|
301 |
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LOWFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i)) |
302 |
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{ |
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RORBir(i, r); |
304 |
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} |
305 |
+ |
LENDFUNC(WRITE,NONE,2,raw_ror_b_ri,(RW1 r, IMM i)) |
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|
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LOWFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i)) |
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{ |
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RORWir(i, r); |
310 |
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} |
311 |
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LENDFUNC(WRITE,NONE,2,raw_ror_w_ri,(RW2 r, IMM i)) |
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|
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LOWFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s)) |
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{ |
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ORLmr(s, X86_NOREG, X86_NOREG, 1, d); |
316 |
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} |
317 |
+ |
LENDFUNC(WRITE,READ,2,raw_or_l_rm,(RW4 d, MEMR s)) |
318 |
+ |
|
319 |
+ |
LOWFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i)) |
320 |
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{ |
321 |
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RORLir(i, r); |
322 |
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} |
323 |
+ |
LENDFUNC(WRITE,NONE,2,raw_ror_l_ri,(RW4 r, IMM i)) |
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|
325 |
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LOWFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r)) |
326 |
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{ |
327 |
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RORLrr(r, d); |
328 |
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} |
329 |
+ |
LENDFUNC(WRITE,NONE,2,raw_ror_l_rr,(RW4 d, R1 r)) |
330 |
+ |
|
331 |
+ |
LOWFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r)) |
332 |
+ |
{ |
333 |
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RORWrr(r, d); |
334 |
+ |
} |
335 |
+ |
LENDFUNC(WRITE,NONE,2,raw_ror_w_rr,(RW2 d, R1 r)) |
336 |
+ |
|
337 |
+ |
LOWFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r)) |
338 |
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{ |
339 |
+ |
RORBrr(r, d); |
340 |
+ |
} |
341 |
+ |
LENDFUNC(WRITE,NONE,2,raw_ror_b_rr,(RW1 d, R1 r)) |
342 |
+ |
|
343 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r)) |
344 |
+ |
{ |
345 |
+ |
SHRLrr(r, d); |
346 |
+ |
} |
347 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shrl_l_rr,(RW4 d, R1 r)) |
348 |
+ |
|
349 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r)) |
350 |
+ |
{ |
351 |
+ |
SHRWrr(r, d); |
352 |
+ |
} |
353 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shrl_w_rr,(RW2 d, R1 r)) |
354 |
+ |
|
355 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r)) |
356 |
+ |
{ |
357 |
+ |
SHRBrr(r, d); |
358 |
+ |
} |
359 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shrl_b_rr,(RW1 d, R1 r)) |
360 |
+ |
|
361 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r)) |
362 |
+ |
{ |
363 |
+ |
SARLrr(r, d); |
364 |
+ |
} |
365 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shra_l_rr,(RW4 d, R1 r)) |
366 |
+ |
|
367 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r)) |
368 |
+ |
{ |
369 |
+ |
SARWrr(r, d); |
370 |
+ |
} |
371 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shra_w_rr,(RW2 d, R1 r)) |
372 |
+ |
|
373 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r)) |
374 |
+ |
{ |
375 |
+ |
SARBrr(r, d); |
376 |
+ |
} |
377 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shra_b_rr,(RW1 d, R1 r)) |
378 |
+ |
|
379 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i)) |
380 |
+ |
{ |
381 |
+ |
SHLLir(i, r); |
382 |
+ |
} |
383 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shll_l_ri,(RW4 r, IMM i)) |
384 |
+ |
|
385 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i)) |
386 |
+ |
{ |
387 |
+ |
SHLWir(i, r); |
388 |
+ |
} |
389 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shll_w_ri,(RW2 r, IMM i)) |
390 |
+ |
|
391 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i)) |
392 |
+ |
{ |
393 |
+ |
SHLBir(i, r); |
394 |
+ |
} |
395 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shll_b_ri,(RW1 r, IMM i)) |
396 |
+ |
|
397 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i)) |
398 |
+ |
{ |
399 |
+ |
SHRLir(i, r); |
400 |
+ |
} |
401 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shrl_l_ri,(RW4 r, IMM i)) |
402 |
+ |
|
403 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i)) |
404 |
+ |
{ |
405 |
+ |
SHRWir(i, r); |
406 |
+ |
} |
407 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shrl_w_ri,(RW2 r, IMM i)) |
408 |
+ |
|
409 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i)) |
410 |
+ |
{ |
411 |
+ |
SHRBir(i, r); |
412 |
+ |
} |
413 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shrl_b_ri,(RW1 r, IMM i)) |
414 |
+ |
|
415 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i)) |
416 |
+ |
{ |
417 |
+ |
SARLir(i, r); |
418 |
+ |
} |
419 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shra_l_ri,(RW4 r, IMM i)) |
420 |
+ |
|
421 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i)) |
422 |
+ |
{ |
423 |
+ |
SARWir(i, r); |
424 |
+ |
} |
425 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shra_w_ri,(RW2 r, IMM i)) |
426 |
+ |
|
427 |
+ |
LOWFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i)) |
428 |
+ |
{ |
429 |
+ |
SARBir(i, r); |
430 |
+ |
} |
431 |
+ |
LENDFUNC(WRITE,NONE,2,raw_shra_b_ri,(RW1 r, IMM i)) |
432 |
+ |
|
433 |
+ |
LOWFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah)) |
434 |
+ |
{ |
435 |
+ |
SAHF(); |
436 |
+ |
} |
437 |
+ |
LENDFUNC(WRITE,NONE,1,raw_sahf,(R2 dummy_ah)) |
438 |
+ |
|
439 |
+ |
LOWFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax)) |
440 |
+ |
{ |
441 |
+ |
CPUID(); |
442 |
+ |
} |
443 |
+ |
LENDFUNC(NONE,NONE,1,raw_cpuid,(R4 dummy_eax)) |
444 |
+ |
|
445 |
+ |
LOWFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah)) |
446 |
+ |
{ |
447 |
+ |
LAHF(); |
448 |
+ |
} |
449 |
+ |
LENDFUNC(READ,NONE,1,raw_lahf,(W2 dummy_ah)) |
450 |
+ |
|
451 |
+ |
LOWFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc)) |
452 |
+ |
{ |
453 |
+ |
SETCCir(cc, d); |
454 |
+ |
} |
455 |
+ |
LENDFUNC(READ,NONE,2,raw_setcc,(W1 d, IMM cc)) |
456 |
+ |
|
457 |
+ |
LOWFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc)) |
458 |
+ |
{ |
459 |
+ |
SETCCim(cc, d, X86_NOREG, X86_NOREG, 1); |
460 |
+ |
} |
461 |
+ |
LENDFUNC(READ,WRITE,2,raw_setcc_m,(MEMW d, IMM cc)) |
462 |
+ |
|
463 |
+ |
LOWFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc)) |
464 |
+ |
{ |
465 |
+ |
if (have_cmov) |
466 |
+ |
CMOVLrr(cc, s, d); |
467 |
+ |
else { /* replacement using branch and mov */ |
468 |
+ |
#if defined(__x86_64__) |
469 |
+ |
write_log("x86-64 implementations are bound to have CMOV!\n"); |
470 |
+ |
abort(); |
471 |
+ |
#endif |
472 |
+ |
JCCSii(cc^1, 2); |
473 |
+ |
MOVLrr(s, d); |
474 |
+ |
} |
475 |
+ |
} |
476 |
+ |
LENDFUNC(READ,NONE,3,raw_cmov_l_rr,(RW4 d, R4 s, IMM cc)) |
477 |
+ |
|
478 |
+ |
LOWFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s)) |
479 |
+ |
{ |
480 |
+ |
BSFLrr(s, d); |
481 |
+ |
} |
482 |
+ |
LENDFUNC(WRITE,NONE,2,raw_bsf_l_rr,(W4 d, R4 s)) |
483 |
+ |
|
484 |
+ |
LOWFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s)) |
485 |
+ |
{ |
486 |
+ |
MOVSWLrr(s, d); |
487 |
+ |
} |
488 |
+ |
LENDFUNC(NONE,NONE,2,raw_sign_extend_16_rr,(W4 d, R2 s)) |
489 |
+ |
|
490 |
+ |
LOWFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s)) |
491 |
+ |
{ |
492 |
+ |
MOVSBLrr(s, d); |
493 |
+ |
} |
494 |
+ |
LENDFUNC(NONE,NONE,2,raw_sign_extend_8_rr,(W4 d, R1 s)) |
495 |
+ |
|
496 |
+ |
LOWFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s)) |
497 |
+ |
{ |
498 |
+ |
MOVZWLrr(s, d); |
499 |
+ |
} |
500 |
+ |
LENDFUNC(NONE,NONE,2,raw_zero_extend_16_rr,(W4 d, R2 s)) |
501 |
+ |
|
502 |
+ |
LOWFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s)) |
503 |
+ |
{ |
504 |
+ |
MOVZBLrr(s, d); |
505 |
+ |
} |
506 |
+ |
LENDFUNC(NONE,NONE,2,raw_zero_extend_8_rr,(W4 d, R1 s)) |
507 |
+ |
|
508 |
+ |
LOWFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s)) |
509 |
+ |
{ |
510 |
+ |
IMULLrr(s, d); |
511 |
+ |
} |
512 |
+ |
LENDFUNC(NONE,NONE,2,raw_imul_32_32,(RW4 d, R4 s)) |
513 |
+ |
|
514 |
+ |
LOWFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) |
515 |
+ |
{ |
516 |
+ |
if (d!=MUL_NREG1 || s!=MUL_NREG2) { |
517 |
+ |
write_log("Bad register in IMUL: d=%d, s=%d\n",d,s); |
518 |
+ |
abort(); |
519 |
+ |
} |
520 |
+ |
IMULLr(s); |
521 |
+ |
} |
522 |
+ |
LENDFUNC(NONE,NONE,2,raw_imul_64_32,(RW4 d, RW4 s)) |
523 |
+ |
|
524 |
+ |
LOWFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) |
525 |
+ |
{ |
526 |
+ |
if (d!=MUL_NREG1 || s!=MUL_NREG2) { |
527 |
+ |
write_log("Bad register in MUL: d=%d, s=%d\n",d,s); |
528 |
+ |
abort(); |
529 |
+ |
} |
530 |
+ |
MULLr(s); |
531 |
+ |
} |
532 |
+ |
LENDFUNC(NONE,NONE,2,raw_mul_64_32,(RW4 d, RW4 s)) |
533 |
+ |
|
534 |
+ |
LOWFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s)) |
535 |
+ |
{ |
536 |
+ |
abort(); /* %^$&%^$%#^ x86! */ |
537 |
+ |
} |
538 |
+ |
LENDFUNC(NONE,NONE,2,raw_mul_32_32,(RW4 d, R4 s)) |
539 |
+ |
|
540 |
+ |
LOWFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s)) |
541 |
+ |
{ |
542 |
+ |
MOVBrr(s, d); |
543 |
+ |
} |
544 |
+ |
LENDFUNC(NONE,NONE,2,raw_mov_b_rr,(W1 d, R1 s)) |
545 |
+ |
|
546 |
+ |
LOWFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s)) |
547 |
+ |
{ |
548 |
+ |
MOVWrr(s, d); |
549 |
+ |
} |
550 |
+ |
LENDFUNC(NONE,NONE,2,raw_mov_w_rr,(W2 d, R2 s)) |
551 |
+ |
|
552 |
+ |
LOWFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor)) |
553 |
+ |
{ |
554 |
+ |
MOVLmr(0, baser, index, factor, d); |
555 |
+ |
} |
556 |
+ |
LENDFUNC(NONE,READ,4,raw_mov_l_rrm_indexed,(W4 d,R4 baser, R4 index, IMM factor)) |
557 |
+ |
|
558 |
+ |
LOWFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor)) |
559 |
+ |
{ |
560 |
+ |
MOVWmr(0, baser, index, factor, d); |
561 |
+ |
} |
562 |
+ |
LENDFUNC(NONE,READ,4,raw_mov_w_rrm_indexed,(W2 d, R4 baser, R4 index, IMM factor)) |
563 |
+ |
|
564 |
+ |
LOWFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor)) |
565 |
+ |
{ |
566 |
+ |
MOVBmr(0, baser, index, factor, d); |
567 |
+ |
} |
568 |
+ |
LENDFUNC(NONE,READ,4,raw_mov_b_rrm_indexed,(W1 d, R4 baser, R4 index, IMM factor)) |
569 |
+ |
|
570 |
+ |
LOWFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s)) |
571 |
+ |
{ |
572 |
+ |
MOVLrm(s, 0, baser, index, factor); |
573 |
+ |
} |
574 |
+ |
LENDFUNC(NONE,WRITE,4,raw_mov_l_mrr_indexed,(R4 baser, R4 index, IMM factor, R4 s)) |
575 |
+ |
|
576 |
+ |
LOWFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s)) |
577 |
+ |
{ |
578 |
+ |
MOVWrm(s, 0, baser, index, factor); |
579 |
+ |
} |
580 |
+ |
LENDFUNC(NONE,WRITE,4,raw_mov_w_mrr_indexed,(R4 baser, R4 index, IMM factor, R2 s)) |
581 |
+ |
|
582 |
+ |
LOWFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s)) |
583 |
+ |
{ |
584 |
+ |
MOVBrm(s, 0, baser, index, factor); |
585 |
+ |
} |
586 |
+ |
LENDFUNC(NONE,WRITE,4,raw_mov_b_mrr_indexed,(R4 baser, R4 index, IMM factor, R1 s)) |
587 |
+ |
|
588 |
+ |
LOWFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s)) |
589 |
+ |
{ |
590 |
+ |
MOVLrm(s, base, baser, index, factor); |
591 |
+ |
} |
592 |
+ |
LENDFUNC(NONE,WRITE,5,raw_mov_l_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R4 s)) |
593 |
+ |
|
594 |
+ |
LOWFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s)) |
595 |
+ |
{ |
596 |
+ |
MOVWrm(s, base, baser, index, factor); |
597 |
+ |
} |
598 |
+ |
LENDFUNC(NONE,WRITE,5,raw_mov_w_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R2 s)) |
599 |
+ |
|
600 |
+ |
LOWFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s)) |
601 |
+ |
{ |
602 |
+ |
MOVBrm(s, base, baser, index, factor); |
603 |
+ |
} |
604 |
+ |
LENDFUNC(NONE,WRITE,5,raw_mov_b_bmrr_indexed,(IMM base, R4 baser, R4 index, IMM factor, R1 s)) |
605 |
+ |
|
606 |
+ |
LOWFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor)) |
607 |
+ |
{ |
608 |
+ |
MOVLmr(base, baser, index, factor, d); |
609 |
+ |
} |
610 |
+ |
LENDFUNC(NONE,READ,5,raw_mov_l_brrm_indexed,(W4 d, IMM base, R4 baser, R4 index, IMM factor)) |
611 |
+ |
|
612 |
+ |
LOWFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor)) |
613 |
+ |
{ |
614 |
+ |
MOVWmr(base, baser, index, factor, d); |
615 |
+ |
} |
616 |
+ |
LENDFUNC(NONE,READ,5,raw_mov_w_brrm_indexed,(W2 d, IMM base, R4 baser, R4 index, IMM factor)) |
617 |
+ |
|
618 |
+ |
LOWFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor)) |
619 |
+ |
{ |
620 |
+ |
MOVBmr(base, baser, index, factor, d); |
621 |
+ |
} |
622 |
+ |
LENDFUNC(NONE,READ,5,raw_mov_b_brrm_indexed,(W1 d, IMM base, R4 baser, R4 index, IMM factor)) |
623 |
+ |
|
624 |
+ |
LOWFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor)) |
625 |
+ |
{ |
626 |
+ |
MOVLmr(base, X86_NOREG, index, factor, d); |
627 |
+ |
} |
628 |
+ |
LENDFUNC(NONE,READ,4,raw_mov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor)) |
629 |
+ |
|
630 |
+ |
LOWFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond)) |
631 |
+ |
{ |
632 |
+ |
if (have_cmov) |
633 |
+ |
CMOVLmr(cond, base, X86_NOREG, index, factor, d); |
634 |
+ |
else { /* replacement using branch and mov */ |
635 |
+ |
#if defined(__x86_64__) |
636 |
+ |
write_log("x86-64 implementations are bound to have CMOV!\n"); |
637 |
+ |
abort(); |
638 |
+ |
#endif |
639 |
+ |
JCCSii(cond^1, 7); |
640 |
+ |
MOVLmr(base, X86_NOREG, index, factor, d); |
641 |
+ |
} |
642 |
+ |
} |
643 |
+ |
LENDFUNC(NONE,READ,5,raw_cmov_l_rm_indexed,(W4 d, IMM base, R4 index, IMM factor, IMM cond)) |
644 |
+ |
|
645 |
+ |
LOWFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond)) |
646 |
+ |
{ |
647 |
+ |
if (have_cmov) |
648 |
+ |
CMOVLmr(cond, mem, X86_NOREG, X86_NOREG, 1, d); |
649 |
+ |
else { /* replacement using branch and mov */ |
650 |
+ |
#if defined(__x86_64__) |
651 |
+ |
write_log("x86-64 implementations are bound to have CMOV!\n"); |
652 |
+ |
abort(); |
653 |
+ |
#endif |
654 |
+ |
JCCSii(cond^1, 6); |
655 |
+ |
MOVLmr(mem, X86_NOREG, X86_NOREG, 1, d); |
656 |
+ |
} |
657 |
+ |
} |
658 |
+ |
LENDFUNC(NONE,READ,3,raw_cmov_l_rm,(W4 d, IMM mem, IMM cond)) |
659 |
+ |
|
660 |
+ |
LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset)) |
661 |
+ |
{ |
662 |
+ |
MOVLmr(offset, s, X86_NOREG, 1, d); |
663 |
+ |
} |
664 |
+ |
LENDFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset)) |
665 |
+ |
|
666 |
+ |
LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset)) |
667 |
+ |
{ |
668 |
+ |
MOVWmr(offset, s, X86_NOREG, 1, d); |
669 |
+ |
} |
670 |
+ |
LENDFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset)) |
671 |
+ |
|
672 |
+ |
LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset)) |
673 |
+ |
{ |
674 |
+ |
MOVBmr(offset, s, X86_NOREG, 1, d); |
675 |
+ |
} |
676 |
+ |
LENDFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset)) |
677 |
+ |
|
678 |
+ |
LOWFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset)) |
679 |
+ |
{ |
680 |
+ |
MOVLmr(offset, s, X86_NOREG, 1, d); |
681 |
+ |
} |
682 |
+ |
LENDFUNC(NONE,READ,3,raw_mov_l_brR,(W4 d, R4 s, IMM offset)) |
683 |
+ |
|
684 |
+ |
LOWFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset)) |
685 |
+ |
{ |
686 |
+ |
MOVWmr(offset, s, X86_NOREG, 1, d); |
687 |
+ |
} |
688 |
+ |
LENDFUNC(NONE,READ,3,raw_mov_w_brR,(W2 d, R4 s, IMM offset)) |
689 |
+ |
|
690 |
+ |
LOWFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset)) |
691 |
+ |
{ |
692 |
+ |
MOVBmr(offset, s, X86_NOREG, 1, d); |
693 |
+ |
} |
694 |
+ |
LENDFUNC(NONE,READ,3,raw_mov_b_brR,(W1 d, R4 s, IMM offset)) |
695 |
+ |
|
696 |
+ |
LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset)) |
697 |
+ |
{ |
698 |
+ |
MOVLim(i, offset, d, X86_NOREG, 1); |
699 |
+ |
} |
700 |
+ |
LENDFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset)) |
701 |
+ |
|
702 |
+ |
LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset)) |
703 |
+ |
{ |
704 |
+ |
MOVWim(i, offset, d, X86_NOREG, 1); |
705 |
+ |
} |
706 |
+ |
LENDFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset)) |
707 |
+ |
|
708 |
+ |
LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset)) |
709 |
+ |
{ |
710 |
+ |
MOVBim(i, offset, d, X86_NOREG, 1); |
711 |
+ |
} |
712 |
+ |
LENDFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset)) |
713 |
+ |
|
714 |
+ |
LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset)) |
715 |
+ |
{ |
716 |
+ |
MOVLrm(s, offset, d, X86_NOREG, 1); |
717 |
+ |
} |
718 |
+ |
LENDFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset)) |
719 |
+ |
|
720 |
+ |
LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset)) |
721 |
+ |
{ |
722 |
+ |
MOVWrm(s, offset, d, X86_NOREG, 1); |
723 |
+ |
} |
724 |
+ |
LENDFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset)) |
725 |
+ |
|
726 |
+ |
LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset)) |
727 |
+ |
{ |
728 |
+ |
MOVBrm(s, offset, d, X86_NOREG, 1); |
729 |
+ |
} |
730 |
+ |
LENDFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset)) |
731 |
+ |
|
732 |
+ |
LOWFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset)) |
733 |
+ |
{ |
734 |
+ |
LEALmr(offset, s, X86_NOREG, 1, d); |
735 |
+ |
} |
736 |
+ |
LENDFUNC(NONE,NONE,3,raw_lea_l_brr,(W4 d, R4 s, IMM offset)) |
737 |
+ |
|
738 |
+ |
LOWFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset)) |
739 |
+ |
{ |
740 |
+ |
LEALmr(offset, s, index, factor, d); |
741 |
+ |
} |
742 |
+ |
LENDFUNC(NONE,NONE,5,raw_lea_l_brr_indexed,(W4 d, R4 s, R4 index, IMM factor, IMM offset)) |
743 |
+ |
|
744 |
+ |
LOWFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor)) |
745 |
+ |
{ |
746 |
+ |
LEALmr(0, s, index, factor, d); |
747 |
+ |
} |
748 |
+ |
LENDFUNC(NONE,NONE,4,raw_lea_l_rr_indexed,(W4 d, R4 s, R4 index, IMM factor)) |
749 |
+ |
|
750 |
+ |
LOWFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset)) |
751 |
+ |
{ |
752 |
+ |
MOVLrm(s, offset, d, X86_NOREG, 1); |
753 |
+ |
} |
754 |
+ |
LENDFUNC(NONE,WRITE,3,raw_mov_l_bRr,(R4 d, R4 s, IMM offset)) |
755 |
+ |
|
756 |
+ |
LOWFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset)) |
757 |
+ |
{ |
758 |
+ |
MOVWrm(s, offset, d, X86_NOREG, 1); |
759 |
+ |
} |
760 |
+ |
LENDFUNC(NONE,WRITE,3,raw_mov_w_bRr,(R4 d, R2 s, IMM offset)) |
761 |
+ |
|
762 |
+ |
LOWFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset)) |
763 |
+ |
{ |
764 |
+ |
MOVBrm(s, offset, d, X86_NOREG, 1); |
765 |
+ |
} |
766 |
+ |
LENDFUNC(NONE,WRITE,3,raw_mov_b_bRr,(R4 d, R1 s, IMM offset)) |
767 |
+ |
|
768 |
+ |
LOWFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r)) |
769 |
+ |
{ |
770 |
+ |
BSWAPLr(r); |
771 |
+ |
} |
772 |
+ |
LENDFUNC(NONE,NONE,1,raw_bswap_32,(RW4 r)) |
773 |
+ |
|
774 |
+ |
LOWFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r)) |
775 |
+ |
{ |
776 |
+ |
ROLWir(8, r); |
777 |
+ |
} |
778 |
+ |
LENDFUNC(WRITE,NONE,1,raw_bswap_16,(RW2 r)) |
779 |
+ |
|
780 |
+ |
LOWFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s)) |
781 |
+ |
{ |
782 |
+ |
MOVLrr(s, d); |
783 |
+ |
} |
784 |
+ |
LENDFUNC(NONE,NONE,2,raw_mov_l_rr,(W4 d, R4 s)) |
785 |
+ |
|
786 |
+ |
LOWFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s)) |
787 |
+ |
{ |
788 |
+ |
MOVLrm(s, d, X86_NOREG, X86_NOREG, 1); |
789 |
+ |
} |
790 |
+ |
LENDFUNC(NONE,WRITE,2,raw_mov_l_mr,(IMM d, R4 s)) |
791 |
+ |
|
792 |
+ |
LOWFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s)) |
793 |
+ |
{ |
794 |
+ |
MOVWrm(s, d, X86_NOREG, X86_NOREG, 1); |
795 |
+ |
} |
796 |
+ |
LENDFUNC(NONE,WRITE,2,raw_mov_w_mr,(IMM d, R2 s)) |
797 |
+ |
|
798 |
+ |
LOWFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s)) |
799 |
+ |
{ |
800 |
+ |
MOVWmr(s, X86_NOREG, X86_NOREG, 1, d); |
801 |
+ |
} |
802 |
+ |
LENDFUNC(NONE,READ,2,raw_mov_w_rm,(W2 d, IMM s)) |
803 |
+ |
|
804 |
+ |
LOWFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s)) |
805 |
+ |
{ |
806 |
+ |
MOVBrm(s, d, X86_NOREG, X86_NOREG, 1); |
807 |
+ |
} |
808 |
+ |
LENDFUNC(NONE,WRITE,2,raw_mov_b_mr,(IMM d, R1 s)) |
809 |
+ |
|
810 |
+ |
LOWFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s)) |
811 |
+ |
{ |
812 |
+ |
MOVBmr(s, X86_NOREG, X86_NOREG, 1, d); |
813 |
+ |
} |
814 |
+ |
LENDFUNC(NONE,READ,2,raw_mov_b_rm,(W1 d, IMM s)) |
815 |
+ |
|
816 |
+ |
LOWFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s)) |
817 |
+ |
{ |
818 |
+ |
MOVLir(s, d); |
819 |
+ |
} |
820 |
+ |
LENDFUNC(NONE,NONE,2,raw_mov_l_ri,(W4 d, IMM s)) |
821 |
+ |
|
822 |
+ |
LOWFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s)) |
823 |
+ |
{ |
824 |
+ |
MOVWir(s, d); |
825 |
+ |
} |
826 |
+ |
LENDFUNC(NONE,NONE,2,raw_mov_w_ri,(W2 d, IMM s)) |
827 |
+ |
|
828 |
+ |
LOWFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s)) |
829 |
+ |
{ |
830 |
+ |
MOVBir(s, d); |
831 |
+ |
} |
832 |
+ |
LENDFUNC(NONE,NONE,2,raw_mov_b_ri,(W1 d, IMM s)) |
833 |
+ |
|
834 |
+ |
LOWFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s)) |
835 |
+ |
{ |
836 |
+ |
ADCLim(s, d, X86_NOREG, X86_NOREG, 1); |
837 |
+ |
} |
838 |
+ |
LENDFUNC(RMW,RMW,2,raw_adc_l_mi,(MEMRW d, IMM s)) |
839 |
+ |
|
840 |
+ |
LOWFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) |
841 |
+ |
{ |
842 |
+ |
ADDLim(s, d, X86_NOREG, X86_NOREG, 1); |
843 |
+ |
} |
844 |
+ |
LENDFUNC(WRITE,RMW,2,raw_add_l_mi,(IMM d, IMM s)) |
845 |
+ |
|
846 |
+ |
LOWFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) |
847 |
+ |
{ |
848 |
+ |
ADDWim(s, d, X86_NOREG, X86_NOREG, 1); |
849 |
+ |
} |
850 |
+ |
LENDFUNC(WRITE,RMW,2,raw_add_w_mi,(IMM d, IMM s)) |
851 |
+ |
|
852 |
+ |
LOWFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) |
853 |
+ |
{ |
854 |
+ |
ADDBim(s, d, X86_NOREG, X86_NOREG, 1); |
855 |
+ |
} |
856 |
+ |
LENDFUNC(WRITE,RMW,2,raw_add_b_mi,(IMM d, IMM s)) |
857 |
+ |
|
858 |
+ |
LOWFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i)) |
859 |
+ |
{ |
860 |
+ |
TESTLir(i, d); |
861 |
+ |
} |
862 |
+ |
LENDFUNC(WRITE,NONE,2,raw_test_l_ri,(R4 d, IMM i)) |
863 |
+ |
|
864 |
+ |
LOWFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s)) |
865 |
+ |
{ |
866 |
+ |
TESTLrr(s, d); |
867 |
+ |
} |
868 |
+ |
LENDFUNC(WRITE,NONE,2,raw_test_l_rr,(R4 d, R4 s)) |
869 |
+ |
|
870 |
+ |
LOWFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s)) |
871 |
+ |
{ |
872 |
+ |
TESTWrr(s, d); |
873 |
+ |
} |
874 |
+ |
LENDFUNC(WRITE,NONE,2,raw_test_w_rr,(R2 d, R2 s)) |
875 |
+ |
|
876 |
+ |
LOWFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s)) |
877 |
+ |
{ |
878 |
+ |
TESTBrr(s, d); |
879 |
+ |
} |
880 |
+ |
LENDFUNC(WRITE,NONE,2,raw_test_b_rr,(R1 d, R1 s)) |
881 |
+ |
|
882 |
+ |
LOWFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i)) |
883 |
+ |
{ |
884 |
+ |
ANDLir(i, d); |
885 |
+ |
} |
886 |
+ |
LENDFUNC(WRITE,NONE,2,raw_and_l_ri,(RW4 d, IMM i)) |
887 |
+ |
|
888 |
+ |
LOWFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i)) |
889 |
+ |
{ |
890 |
+ |
ANDWir(i, d); |
891 |
+ |
} |
892 |
+ |
LENDFUNC(WRITE,NONE,2,raw_and_w_ri,(RW2 d, IMM i)) |
893 |
+ |
|
894 |
+ |
LOWFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s)) |
895 |
+ |
{ |
896 |
+ |
ANDLrr(s, d); |
897 |
+ |
} |
898 |
+ |
LENDFUNC(WRITE,NONE,2,raw_and_l,(RW4 d, R4 s)) |
899 |
+ |
|
900 |
+ |
LOWFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s)) |
901 |
+ |
{ |
902 |
+ |
ANDWrr(s, d); |
903 |
+ |
} |
904 |
+ |
LENDFUNC(WRITE,NONE,2,raw_and_w,(RW2 d, R2 s)) |
905 |
+ |
|
906 |
+ |
LOWFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s)) |
907 |
+ |
{ |
908 |
+ |
ANDBrr(s, d); |
909 |
+ |
} |
910 |
+ |
LENDFUNC(WRITE,NONE,2,raw_and_b,(RW1 d, R1 s)) |
911 |
+ |
|
912 |
+ |
LOWFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i)) |
913 |
+ |
{ |
914 |
+ |
ORLir(i, d); |
915 |
+ |
} |
916 |
+ |
LENDFUNC(WRITE,NONE,2,raw_or_l_ri,(RW4 d, IMM i)) |
917 |
+ |
|
918 |
+ |
LOWFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s)) |
919 |
+ |
{ |
920 |
+ |
ORLrr(s, d); |
921 |
+ |
} |
922 |
+ |
LENDFUNC(WRITE,NONE,2,raw_or_l,(RW4 d, R4 s)) |
923 |
+ |
|
924 |
+ |
LOWFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s)) |
925 |
+ |
{ |
926 |
+ |
ORWrr(s, d); |
927 |
+ |
} |
928 |
+ |
LENDFUNC(WRITE,NONE,2,raw_or_w,(RW2 d, R2 s)) |
929 |
+ |
|
930 |
+ |
LOWFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s)) |
931 |
+ |
{ |
932 |
+ |
ORBrr(s, d); |
933 |
+ |
} |
934 |
+ |
LENDFUNC(WRITE,NONE,2,raw_or_b,(RW1 d, R1 s)) |
935 |
+ |
|
936 |
+ |
LOWFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s)) |
937 |
+ |
{ |
938 |
+ |
ADCLrr(s, d); |
939 |
+ |
} |
940 |
+ |
LENDFUNC(RMW,NONE,2,raw_adc_l,(RW4 d, R4 s)) |
941 |
+ |
|
942 |
+ |
LOWFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s)) |
943 |
+ |
{ |
944 |
+ |
ADCWrr(s, d); |
945 |
+ |
} |
946 |
+ |
LENDFUNC(RMW,NONE,2,raw_adc_w,(RW2 d, R2 s)) |
947 |
+ |
|
948 |
+ |
LOWFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s)) |
949 |
+ |
{ |
950 |
+ |
ADCBrr(s, d); |
951 |
+ |
} |
952 |
+ |
LENDFUNC(RMW,NONE,2,raw_adc_b,(RW1 d, R1 s)) |
953 |
+ |
|
954 |
+ |
LOWFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s)) |
955 |
+ |
{ |
956 |
+ |
ADDLrr(s, d); |
957 |
+ |
} |
958 |
+ |
LENDFUNC(WRITE,NONE,2,raw_add_l,(RW4 d, R4 s)) |
959 |
+ |
|
960 |
+ |
LOWFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s)) |
961 |
+ |
{ |
962 |
+ |
ADDWrr(s, d); |
963 |
+ |
} |
964 |
+ |
LENDFUNC(WRITE,NONE,2,raw_add_w,(RW2 d, R2 s)) |
965 |
+ |
|
966 |
+ |
LOWFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s)) |
967 |
+ |
{ |
968 |
+ |
ADDBrr(s, d); |
969 |
+ |
} |
970 |
+ |
LENDFUNC(WRITE,NONE,2,raw_add_b,(RW1 d, R1 s)) |
971 |
+ |
|
972 |
+ |
LOWFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i)) |
973 |
+ |
{ |
974 |
+ |
SUBLir(i, d); |
975 |
+ |
} |
976 |
+ |
LENDFUNC(WRITE,NONE,2,raw_sub_l_ri,(RW4 d, IMM i)) |
977 |
+ |
|
978 |
+ |
LOWFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i)) |
979 |
+ |
{ |
980 |
+ |
SUBBir(i, d); |
981 |
+ |
} |
982 |
+ |
LENDFUNC(WRITE,NONE,2,raw_sub_b_ri,(RW1 d, IMM i)) |
983 |
+ |
|
984 |
+ |
LOWFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i)) |
985 |
+ |
{ |
986 |
+ |
ADDLir(i, d); |
987 |
+ |
} |
988 |
+ |
LENDFUNC(WRITE,NONE,2,raw_add_l_ri,(RW4 d, IMM i)) |
989 |
+ |
|
990 |
+ |
LOWFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i)) |
991 |
+ |
{ |
992 |
+ |
ADDWir(i, d); |
993 |
+ |
} |
994 |
+ |
LENDFUNC(WRITE,NONE,2,raw_add_w_ri,(RW2 d, IMM i)) |
995 |
+ |
|
996 |
+ |
LOWFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i)) |
997 |
+ |
{ |
998 |
+ |
ADDBir(i, d); |
999 |
+ |
} |
1000 |
+ |
LENDFUNC(WRITE,NONE,2,raw_add_b_ri,(RW1 d, IMM i)) |
1001 |
+ |
|
1002 |
+ |
LOWFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s)) |
1003 |
+ |
{ |
1004 |
+ |
SBBLrr(s, d); |
1005 |
+ |
} |
1006 |
+ |
LENDFUNC(RMW,NONE,2,raw_sbb_l,(RW4 d, R4 s)) |
1007 |
+ |
|
1008 |
+ |
LOWFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s)) |
1009 |
+ |
{ |
1010 |
+ |
SBBWrr(s, d); |
1011 |
+ |
} |
1012 |
+ |
LENDFUNC(RMW,NONE,2,raw_sbb_w,(RW2 d, R2 s)) |
1013 |
+ |
|
1014 |
+ |
LOWFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s)) |
1015 |
+ |
{ |
1016 |
+ |
SBBBrr(s, d); |
1017 |
+ |
} |
1018 |
+ |
LENDFUNC(RMW,NONE,2,raw_sbb_b,(RW1 d, R1 s)) |
1019 |
+ |
|
1020 |
+ |
LOWFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s)) |
1021 |
+ |
{ |
1022 |
+ |
SUBLrr(s, d); |
1023 |
+ |
} |
1024 |
+ |
LENDFUNC(WRITE,NONE,2,raw_sub_l,(RW4 d, R4 s)) |
1025 |
+ |
|
1026 |
+ |
LOWFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s)) |
1027 |
+ |
{ |
1028 |
+ |
SUBWrr(s, d); |
1029 |
+ |
} |
1030 |
+ |
LENDFUNC(WRITE,NONE,2,raw_sub_w,(RW2 d, R2 s)) |
1031 |
+ |
|
1032 |
+ |
LOWFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s)) |
1033 |
+ |
{ |
1034 |
+ |
SUBBrr(s, d); |
1035 |
+ |
} |
1036 |
+ |
LENDFUNC(WRITE,NONE,2,raw_sub_b,(RW1 d, R1 s)) |
1037 |
+ |
|
1038 |
+ |
LOWFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s)) |
1039 |
+ |
{ |
1040 |
+ |
CMPLrr(s, d); |
1041 |
+ |
} |
1042 |
+ |
LENDFUNC(WRITE,NONE,2,raw_cmp_l,(R4 d, R4 s)) |
1043 |
+ |
|
1044 |
+ |
LOWFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i)) |
1045 |
+ |
{ |
1046 |
+ |
CMPLir(i, r); |
1047 |
+ |
} |
1048 |
+ |
LENDFUNC(WRITE,NONE,2,raw_cmp_l_ri,(R4 r, IMM i)) |
1049 |
+ |
|
1050 |
+ |
LOWFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s)) |
1051 |
+ |
{ |
1052 |
+ |
CMPWrr(s, d); |
1053 |
+ |
} |
1054 |
+ |
LENDFUNC(WRITE,NONE,2,raw_cmp_w,(R2 d, R2 s)) |
1055 |
+ |
|
1056 |
+ |
LOWFUNC(WRITE,READ,2,raw_cmp_b_mi,(MEMR d, IMM s)) |
1057 |
+ |
{ |
1058 |
+ |
CMPBim(s, d, X86_NOREG, X86_NOREG, 1); |
1059 |
+ |
} |
1060 |
+ |
LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s)) |
1061 |
+ |
|
1062 |
+ |
LOWFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i)) |
1063 |
+ |
{ |
1064 |
+ |
CMPBir(i, d); |
1065 |
+ |
} |
1066 |
+ |
LENDFUNC(WRITE,NONE,2,raw_cmp_b_ri,(R1 d, IMM i)) |
1067 |
+ |
|
1068 |
+ |
LOWFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s)) |
1069 |
+ |
{ |
1070 |
+ |
CMPBrr(s, d); |
1071 |
+ |
} |
1072 |
+ |
LENDFUNC(WRITE,NONE,2,raw_cmp_b,(R1 d, R1 s)) |
1073 |
+ |
|
1074 |
+ |
LOWFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor)) |
1075 |
+ |
{ |
1076 |
+ |
CMPLmr(offset, X86_NOREG, index, factor, d); |
1077 |
+ |
} |
1078 |
+ |
LENDFUNC(WRITE,READ,4,raw_cmp_l_rm_indexed,(R4 d, IMM offset, R4 index, IMM factor)) |
1079 |
+ |
|
1080 |
+ |
LOWFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s)) |
1081 |
+ |
{ |
1082 |
+ |
XORLrr(s, d); |
1083 |
+ |
} |
1084 |
+ |
LENDFUNC(WRITE,NONE,2,raw_xor_l,(RW4 d, R4 s)) |
1085 |
+ |
|
1086 |
+ |
LOWFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s)) |
1087 |
+ |
{ |
1088 |
+ |
XORWrr(s, d); |
1089 |
+ |
} |
1090 |
+ |
LENDFUNC(WRITE,NONE,2,raw_xor_w,(RW2 d, R2 s)) |
1091 |
+ |
|
1092 |
+ |
LOWFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s)) |
1093 |
+ |
{ |
1094 |
+ |
XORBrr(s, d); |
1095 |
+ |
} |
1096 |
+ |
LENDFUNC(WRITE,NONE,2,raw_xor_b,(RW1 d, R1 s)) |
1097 |
+ |
|
1098 |
+ |
LOWFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s)) |
1099 |
+ |
{ |
1100 |
+ |
SUBLim(s, d, X86_NOREG, X86_NOREG, 1); |
1101 |
+ |
} |
1102 |
+ |
LENDFUNC(WRITE,RMW,2,raw_sub_l_mi,(MEMRW d, IMM s)) |
1103 |
+ |
|
1104 |
+ |
LOWFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s)) |
1105 |
+ |
{ |
1106 |
+ |
CMPLim(s, d, X86_NOREG, X86_NOREG, 1); |
1107 |
+ |
} |
1108 |
+ |
LENDFUNC(WRITE,READ,2,raw_cmp_l_mi,(MEMR d, IMM s)) |
1109 |
+ |
|
1110 |
+ |
LOWFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2)) |
1111 |
+ |
{ |
1112 |
+ |
XCHGLrr(r2, r1); |
1113 |
+ |
} |
1114 |
+ |
LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2)) |
1115 |
+ |
|
1116 |
+ |
LOWFUNC(READ,WRITE,0,raw_pushfl,(void)) |
1117 |
+ |
{ |
1118 |
+ |
PUSHFD(); |
1119 |
+ |
} |
1120 |
+ |
LENDFUNC(READ,WRITE,0,raw_pushfl,(void)) |
1121 |
+ |
|
1122 |
+ |
LOWFUNC(WRITE,READ,0,raw_popfl,(void)) |
1123 |
+ |
{ |
1124 |
+ |
POPFD(); |
1125 |
+ |
} |
1126 |
+ |
LENDFUNC(WRITE,READ,0,raw_popfl,(void)) |
1127 |
+ |
|
1128 |
+ |
#else |
1129 |
+ |
|
1130 |
|
const bool optimize_accum = true; |
1131 |
|
const bool optimize_imm8 = true; |
1132 |
|
const bool optimize_shift_once = true; |
2076 |
|
|
2077 |
|
LOWFUNC(NONE,READ,3,raw_mov_l_rR,(W4 d, R4 s, IMM offset)) |
2078 |
|
{ |
2079 |
+ |
Dif(!isbyte(offset)) abort(); |
2080 |
|
emit_byte(0x8b); |
2081 |
|
emit_byte(0x40+8*d+s); |
2082 |
|
emit_byte(offset); |
2085 |
|
|
2086 |
|
LOWFUNC(NONE,READ,3,raw_mov_w_rR,(W2 d, R4 s, IMM offset)) |
2087 |
|
{ |
2088 |
+ |
Dif(!isbyte(offset)) abort(); |
2089 |
|
emit_byte(0x66); |
2090 |
|
emit_byte(0x8b); |
2091 |
|
emit_byte(0x40+8*d+s); |
2095 |
|
|
2096 |
|
LOWFUNC(NONE,READ,3,raw_mov_b_rR,(W1 d, R4 s, IMM offset)) |
2097 |
|
{ |
2098 |
+ |
Dif(!isbyte(offset)) abort(); |
2099 |
|
emit_byte(0x8a); |
2100 |
|
emit_byte(0x40+8*d+s); |
2101 |
|
emit_byte(offset); |
2129 |
|
|
2130 |
|
LOWFUNC(NONE,WRITE,3,raw_mov_l_Ri,(R4 d, IMM i, IMM offset)) |
2131 |
|
{ |
2132 |
+ |
Dif(!isbyte(offset)) abort(); |
2133 |
|
emit_byte(0xc7); |
2134 |
|
emit_byte(0x40+d); |
2135 |
|
emit_byte(offset); |
2139 |
|
|
2140 |
|
LOWFUNC(NONE,WRITE,3,raw_mov_w_Ri,(R4 d, IMM i, IMM offset)) |
2141 |
|
{ |
2142 |
+ |
Dif(!isbyte(offset)) abort(); |
2143 |
|
emit_byte(0x66); |
2144 |
|
emit_byte(0xc7); |
2145 |
|
emit_byte(0x40+d); |
2150 |
|
|
2151 |
|
LOWFUNC(NONE,WRITE,3,raw_mov_b_Ri,(R4 d, IMM i, IMM offset)) |
2152 |
|
{ |
2153 |
+ |
Dif(!isbyte(offset)) abort(); |
2154 |
|
emit_byte(0xc6); |
2155 |
|
emit_byte(0x40+d); |
2156 |
|
emit_byte(offset); |
2160 |
|
|
2161 |
|
LOWFUNC(NONE,WRITE,3,raw_mov_l_Rr,(R4 d, R4 s, IMM offset)) |
2162 |
|
{ |
2163 |
+ |
Dif(!isbyte(offset)) abort(); |
2164 |
|
emit_byte(0x89); |
2165 |
|
emit_byte(0x40+8*s+d); |
2166 |
|
emit_byte(offset); |
2169 |
|
|
2170 |
|
LOWFUNC(NONE,WRITE,3,raw_mov_w_Rr,(R4 d, R2 s, IMM offset)) |
2171 |
|
{ |
2172 |
+ |
Dif(!isbyte(offset)) abort(); |
2173 |
|
emit_byte(0x66); |
2174 |
|
emit_byte(0x89); |
2175 |
|
emit_byte(0x40+8*s+d); |
2179 |
|
|
2180 |
|
LOWFUNC(NONE,WRITE,3,raw_mov_b_Rr,(R4 d, R1 s, IMM offset)) |
2181 |
|
{ |
2182 |
+ |
Dif(!isbyte(offset)) abort(); |
2183 |
|
emit_byte(0x88); |
2184 |
|
emit_byte(0x40+8*s+d); |
2185 |
|
emit_byte(offset); |
2870 |
|
LENDFUNC(NONE,NONE,2,raw_xchg_l_rr,(RW4 r1, RW4 r2)) |
2871 |
|
|
2872 |
|
/************************************************************************* |
1859 |
– |
* FIXME: string-related instructions * |
1860 |
– |
*************************************************************************/ |
1861 |
– |
|
1862 |
– |
LOWFUNC(WRITE,NONE,0,raw_cld,(void)) |
1863 |
– |
{ |
1864 |
– |
emit_byte(0xfc); |
1865 |
– |
} |
1866 |
– |
LENDFUNC(WRITE,NONE,0,raw_cld,(void)) |
1867 |
– |
|
1868 |
– |
LOWFUNC(WRITE,NONE,0,raw_std,(void)) |
1869 |
– |
{ |
1870 |
– |
emit_byte(0xfd); |
1871 |
– |
} |
1872 |
– |
LENDFUNC(WRITE,NONE,0,raw_std,(void)) |
1873 |
– |
|
1874 |
– |
LOWFUNC(NONE,RMW,0,raw_movs_b,(void)) |
1875 |
– |
{ |
1876 |
– |
emit_byte(0xa4); |
1877 |
– |
} |
1878 |
– |
LENDFUNC(NONE,RMW,0,raw_movs_b,(void)) |
1879 |
– |
|
1880 |
– |
LOWFUNC(NONE,RMW,0,raw_movs_l,(void)) |
1881 |
– |
{ |
1882 |
– |
emit_byte(0xa5); |
1883 |
– |
} |
1884 |
– |
LENDFUNC(NONE,RMW,0,raw_movs_l,(void)) |
1885 |
– |
|
1886 |
– |
LOWFUNC(NONE,RMW,0,raw_rep,(void)) |
1887 |
– |
{ |
1888 |
– |
emit_byte(0xf3); |
1889 |
– |
} |
1890 |
– |
LENDFUNC(NONE,RMW,0,raw_rep,(void)) |
1891 |
– |
|
1892 |
– |
LOWFUNC(NONE,RMW,0,raw_rep_movsb,(void)) |
1893 |
– |
{ |
1894 |
– |
raw_rep(); |
1895 |
– |
raw_movs_b(); |
1896 |
– |
} |
1897 |
– |
LENDFUNC(NONE,RMW,0,raw_rep_movsb,(void)) |
1898 |
– |
|
1899 |
– |
LOWFUNC(NONE,RMW,0,raw_rep_movsl,(void)) |
1900 |
– |
{ |
1901 |
– |
raw_rep(); |
1902 |
– |
raw_movs_l(); |
1903 |
– |
} |
1904 |
– |
LENDFUNC(NONE,RMW,0,raw_rep_movsl,(void)) |
1905 |
– |
|
1906 |
– |
/************************************************************************* |
2873 |
|
* FIXME: mem access modes probably wrong * |
2874 |
|
*************************************************************************/ |
2875 |
|
|
2885 |
|
} |
2886 |
|
LENDFUNC(WRITE,READ,0,raw_popfl,(void)) |
2887 |
|
|
2888 |
+ |
#endif |
2889 |
+ |
|
2890 |
|
/************************************************************************* |
2891 |
|
* Unoptimizable stuff --- jump * |
2892 |
|
*************************************************************************/ |
3023 |
|
emit_byte(0x90); |
3024 |
|
} |
3025 |
|
|
3026 |
+ |
static __inline__ void raw_emit_nop_filler(int nbytes) |
3027 |
+ |
{ |
3028 |
+ |
/* Source: GNU Binutils 2.12.90.0.15 */ |
3029 |
+ |
/* Various efficient no-op patterns for aligning code labels. |
3030 |
+ |
Note: Don't try to assemble the instructions in the comments. |
3031 |
+ |
0L and 0w are not legal. */ |
3032 |
+ |
static const uae_u8 f32_1[] = |
3033 |
+ |
{0x90}; /* nop */ |
3034 |
+ |
static const uae_u8 f32_2[] = |
3035 |
+ |
{0x89,0xf6}; /* movl %esi,%esi */ |
3036 |
+ |
static const uae_u8 f32_3[] = |
3037 |
+ |
{0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ |
3038 |
+ |
static const uae_u8 f32_4[] = |
3039 |
+ |
{0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
3040 |
+ |
static const uae_u8 f32_5[] = |
3041 |
+ |
{0x90, /* nop */ |
3042 |
+ |
0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
3043 |
+ |
static const uae_u8 f32_6[] = |
3044 |
+ |
{0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ |
3045 |
+ |
static const uae_u8 f32_7[] = |
3046 |
+ |
{0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
3047 |
+ |
static const uae_u8 f32_8[] = |
3048 |
+ |
{0x90, /* nop */ |
3049 |
+ |
0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
3050 |
+ |
static const uae_u8 f32_9[] = |
3051 |
+ |
{0x89,0xf6, /* movl %esi,%esi */ |
3052 |
+ |
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
3053 |
+ |
static const uae_u8 f32_10[] = |
3054 |
+ |
{0x8d,0x76,0x00, /* leal 0(%esi),%esi */ |
3055 |
+ |
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
3056 |
+ |
static const uae_u8 f32_11[] = |
3057 |
+ |
{0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ |
3058 |
+ |
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
3059 |
+ |
static const uae_u8 f32_12[] = |
3060 |
+ |
{0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
3061 |
+ |
0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ |
3062 |
+ |
static const uae_u8 f32_13[] = |
3063 |
+ |
{0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
3064 |
+ |
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
3065 |
+ |
static const uae_u8 f32_14[] = |
3066 |
+ |
{0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ |
3067 |
+ |
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
3068 |
+ |
static const uae_u8 f32_15[] = |
3069 |
+ |
{0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ |
3070 |
+ |
0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; |
3071 |
+ |
static const uae_u8 f32_16[] = |
3072 |
+ |
{0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ |
3073 |
+ |
0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; |
3074 |
+ |
static const uae_u8 *const f32_patt[] = { |
3075 |
+ |
f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, |
3076 |
+ |
f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 |
3077 |
+ |
}; |
3078 |
+ |
|
3079 |
+ |
int nloops = nbytes / 16; |
3080 |
+ |
while (nloops-- > 0) |
3081 |
+ |
emit_block(f32_16, sizeof(f32_16)); |
3082 |
+ |
|
3083 |
+ |
nbytes %= 16; |
3084 |
+ |
if (nbytes) |
3085 |
+ |
emit_block(f32_patt[nbytes - 1], nbytes); |
3086 |
+ |
} |
3087 |
+ |
|
3088 |
|
|
3089 |
|
/************************************************************************* |
3090 |
|
* Flag handling, to and fro UAE flag register * |
3173 |
|
raw_mov_l_rm(target,(uae_u32)live.state[r].mem); |
3174 |
|
} |
3175 |
|
|
3176 |
+ |
#define NATIVE_FLAG_Z 0x40 |
3177 |
+ |
static __inline__ void raw_flags_set_zero(int f, int r, int t) |
3178 |
+ |
{ |
3179 |
+ |
// FIXME: this is really suboptimal |
3180 |
+ |
raw_pushfl(); |
3181 |
+ |
raw_pop_l_r(f); |
3182 |
+ |
raw_and_l_ri(f,~NATIVE_FLAG_Z); |
3183 |
+ |
raw_test_l_rr(r,r); |
3184 |
+ |
raw_mov_l_ri(r,0); |
3185 |
+ |
raw_mov_l_ri(t,NATIVE_FLAG_Z); |
3186 |
+ |
raw_cmov_l_rr(r,t,NATIVE_CC_EQ); |
3187 |
+ |
raw_or_l(f,r); |
3188 |
+ |
raw_push_l_r(f); |
3189 |
+ |
raw_popfl(); |
3190 |
+ |
} |
3191 |
|
|
3192 |
|
static __inline__ void raw_inc_sp(int off) |
3193 |
|
{ |
3663 |
|
x86_processor_string_table[c->x86_processor]); |
3664 |
|
} |
3665 |
|
|
3666 |
+ |
static bool target_check_bsf(void) |
3667 |
+ |
{ |
3668 |
+ |
bool mismatch = false; |
3669 |
+ |
for (int g_ZF = 0; g_ZF <= 1; g_ZF++) { |
3670 |
+ |
for (int g_CF = 0; g_CF <= 1; g_CF++) { |
3671 |
+ |
for (int g_OF = 0; g_OF <= 1; g_OF++) { |
3672 |
+ |
for (int g_SF = 0; g_SF <= 1; g_SF++) { |
3673 |
+ |
for (int value = -1; value <= 1; value++) { |
3674 |
+ |
int flags = (g_SF << 7) | (g_OF << 11) | (g_ZF << 6) | g_CF; |
3675 |
+ |
int tmp = value; |
3676 |
+ |
__asm__ __volatile__ ("push %0; popf; bsf %1,%1; pushf; pop %0" |
3677 |
+ |
: "+r" (flags), "+r" (tmp) : : "cc"); |
3678 |
+ |
int OF = (flags >> 11) & 1; |
3679 |
+ |
int SF = (flags >> 7) & 1; |
3680 |
+ |
int ZF = (flags >> 6) & 1; |
3681 |
+ |
int CF = flags & 1; |
3682 |
+ |
tmp = (value == 0); |
3683 |
+ |
if (ZF != tmp || SF != g_SF || OF != g_OF || CF != g_CF) |
3684 |
+ |
mismatch = true; |
3685 |
+ |
} |
3686 |
+ |
}}}} |
3687 |
+ |
if (mismatch) |
3688 |
+ |
write_log("Target CPU defines all flags on BSF instruction\n"); |
3689 |
+ |
return !mismatch; |
3690 |
+ |
} |
3691 |
+ |
|
3692 |
|
|
3693 |
|
/************************************************************************* |
3694 |
|
* FPU stuff * |